Photoelectric conversion device and electronic device

Abstract

To provide a photoelectric conversion device and an electronic device capable of operating in accordance with the amplitude of a signal read out on a vertical signal line.SOLUTION: The photoelectric conversion device includes pixels for generating signals by photoelectric conversion and a determination circuit for determining the amplitudes of the signals read out from pixels on the vertical signal lines. The determination circuit determines a plurality or plurality of types of determination while the plurality of pixels are selected for reading out signals.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an electronic device. [Background technology]

[0002] Patent Document 1 shows a solid-state imaging device that includes a sample and hold section having two sample and hold circuits in parallel for one vertical signal line, and an analog-to-digital section that converts pixel signals output from the sample and hold section into digital signals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] The configuration disclosed in Patent Document 1 does not take into consideration the operation according to the amplitude of the signal read out to the vertical signal line.

[0005] An object of the present invention is to provide a photoelectric conversion device and an electronic device that can operate in accordance with the amplitude of a signal read out to a vertical signal line. [Means for solving the problem]

[0006] The object of the present invention is to provide a pixel circuit including a reset signal, a pixel circuit for generating a data signal by photoelectric conversion, a determination circuit for determining the amplitude of a signal read out from the pixel to a vertical signal line, an A / D conversion circuit that converts a signal based on one or both of the reset signal and the data signal into a corresponding digital signal; The decision circuit makes a first decision on the data signal while the pixel is selected for signal readout, and makes a second decision on the reset signal. and setting an analog gain to be applied to the signal and a digital gain to be applied to the digital signal based on the result of the first determination. The object is achieved by a photoelectric conversion device characterized by the above. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a photoelectric conversion device and an electronic device that can operate in accordance with the amplitude of a signal read out to a vertical signal line. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 3] 2 is a circuit diagram showing an example of the configuration of a sample-and-hold unit and a conversion unit of the photoelectric conversion device of FIG. 1. [Figure 4] 2 is a circuit diagram showing an example of the configuration of a determination circuit of the photoelectric conversion device of FIG. 1; [Figure 5] 2 is a timing chart showing an example of the operation of the photoelectric conversion device shown in FIG. 1; [Figure 6] 1. FIG. 4 is a timing chart showing an example of the operation of the first modification of the photoelectric conversion device of FIG. [Figure 7] 1. FIG. 4 is a timing chart showing an example of the operation of the second modification of the photoelectric conversion device of FIG. [Figure 8] 1. FIG. 4 is a timing chart showing an example of the operation of the third modification of the photoelectric conversion device of FIG. [Figure 9] 1. FIG. 6 is a timing chart showing an example of the operation of the fourth modification of the photoelectric conversion device of FIG. [Figure 10] 10 is a timing chart showing an example of the operation of the fifth modification of the photoelectric conversion device of FIG. [Figure 11] 1. FIG. 4 is a circuit diagram showing another example of the configuration of the determination circuit of the photoelectric conversion device of FIG. [Figure 12] 1. FIG. 4 is a circuit diagram showing yet another example of the configuration of the determination circuit of the photoelectric conversion device of FIG. [Figure 13] 1. FIG. 4 is a circuit diagram showing yet another example of the configuration of the determination circuit of the photoelectric conversion device of FIG. [Figure 14] FIG. 1 is a diagram showing an example of the configuration of a camera incorporating a photoelectric conversion device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] 1 is a block diagram showing an example of the configuration of a photoelectric conversion device 1000 according to an embodiment of the present invention. The photoelectric conversion device 1000 has a structure in which a first substrate 1 and a second substrate 2 are electrically connected. 1 The second substrate has a pixel section 5. 2 The photoelectric conversion device 1000 includes a current source 40, a decision circuit 20, a sample-and-hold unit (SH) 50, a conversion unit (AD) 60, a data processing unit 90, and an output unit 100. The photoelectric conversion device 1000 may be, for example, a CMOS image sensor.

[0011] In the pixel section 5, pixels 10, each having a photoelectric conversion element such as a photodiode, are arranged in a matrix. In the following description, the left-right direction in FIG. 1 is referred to as the row direction or horizontal direction, and the up-down direction in FIG. 1 is referred to as the column direction or vertical direction. In addition, a group of pixels arranged along the row direction in the pixel section 5 is referred to as a pixel row, and a group of pixels arranged along the column direction is referred to as a pixel column. In addition, with respect to the signal transmission direction, the direction toward the pixels 10 is referred to as the upstream or previous stage, and the direction toward the output section 100 is referred to as the downstream or subsequent stage.

[0012] Each pixel 10 generates a signal having a voltage value corresponding to the amount of light incident thereon during an exposure time. The pixel unit 5 is provided with vertical signal lines 30 corresponding to pixel columns. While FIG. 1 shows an example in which one vertical signal line 30 is provided for each pixel column, multiple vertical signal lines 30 may be provided for each pixel column. The vertical signal line 30 transmits signals from pixels 10 that belong to a pixel row selected by an external vertical scanning circuit among the connected pixels 10 to the decision circuit 20 and the sample-and-hold unit 50.

[0013] The current sources 40 are provided corresponding to the respective vertical signal lines 30. The current sources 40 supply bias currents via the vertical signal lines 30 to the pixels 10 selected to read out signals.

[0014] The determination circuit 20 determines the amplitude of a signal supplied via the vertical signal line 30 and outputs the determination result. The amplitude represents the amount of change from a certain reference potential. The amplitude determination may be, for example, a determination of the magnitude relationship with a reference value. FIG. 1 shows an example in which two reference values, a first reference value REF1 and a second reference value REF2, are used for the amplitude determination. Therefore, the determination circuit 20 can perform a first determination using the first reference value REF1 and a second determination using the second reference value REF2. The determination result can be used for subsequent processing in the photoelectric conversion device 1000 or for processing in a circuit external to the photoelectric conversion device 1000. The determination result can be used depending on the circuit and purpose that uses the determination result, and the use of the determination result is not limited.

[0015] The sample and hold unit 50 samples and holds the signals generated by the photoelectric conversion elements of each pixel 10 from the pixel unit 5 via the vertical signal lines 30. The sample and hold unit 50 has a sample and hold circuit that samples and holds a reset signal and a sample and hold circuit that samples and holds a data signal, each connected to the vertical signal lines 30. The reset signal is a signal generated when the charge accumulated in the pixel is reset. The data signal is a signal based on the charge generated by the photoelectric conversion elements during the exposure period.

[0016] The conversion unit 60 is an A / D conversion circuit that is provided for each sample-and-hold unit 50 and performs analog-to-digital (A / D) conversion on the signal output from the corresponding sample-and-hold unit 50 and outputs it as a digital signal. Specific examples of the A / D conversion circuit include, but are not limited to, a slope-type analog-to-digital conversion circuit, a successive approximation type analog-to-digital conversion circuit, and a delta-sigma (ΔΣ) type analog-to-digital conversion circuit.

[0017] The data processing unit 90 applies predetermined processing to the digital signal output from the conversion unit 60 and outputs the result. For example, the data processing unit 90 can apply digital gain to the digital signal, or apply correction processing or interpolation processing. The output unit 100 outputs the digital signal processed by the data processing unit 90 to the outside of the photoelectric conversion device 1000.

[0018] FIG. 2 is a circuit diagram showing an example configuration of a pixel 10. The pixel 10 includes a photoelectric conversion element 400 such as a photodiode, a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. One of the main electrodes of the photoelectric conversion element 400 is connected to a ground potential 450, and the photoelectric conversion element 400 generates a signal charge (e.g., photoelectrons) in an amount corresponding to the amount of received light. The other of the main electrodes of the photoelectric conversion element 400 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 410. A node 420 electrically connected to the gate electrode of the amplification transistor 430 functions as a floating diffusion (FD). The floating diffusion is a charge-voltage converter that converts the charge generated by the photoelectric conversion element 400 into a voltage.

[0019] A transfer signal TX is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 becomes conductive in response to the transfer signal TX, the charge generated in the photoelectric conversion element 400 and stored in the photoelectric conversion element 400 is transferred to a node 420, which is a floating diffusion. The potential of the node 420 in the state in which the charge has been transferred corresponds to the data signal described above.

[0020] The reset transistor 455 is connected between a power supply potential 460 and a node 420. In this specification, when a transistor is connected between A and B, it means that one of the main electrodes of the transistor is connected to A and the other is connected to B, and the gate electrode of the transistor is not connected to A or B.

[0021] A reset signal RES is supplied to the gate electrode of the reset transistor 455. When the reset transistor 455 becomes conductive in response to the reset signal RES, the potential of the node 420 (floating diffusion) is reset to the power supply potential 460. The potential of the node 420 when the reset transistor 455 is in the conductive state corresponds to the above-mentioned reset signal.

[0022] The amplifier transistor 430 has a gate electrode connected to the node 420, one main electrode connected to a power supply potential 460, and the other main electrode connected to the selection transistor 440. The amplifier transistor 430 is an input section of a source follower that outputs a signal generated by photoelectric conversion of the photoelectric conversion element 400 in the pixel 10 to the vertical signal line 30. Therefore, the other main electrode of the amplifier transistor 430 is electrically connected to the vertical signal line 30 via the selection transistor 440. The amplifier transistor 430 and the current source 40 connected to the vertical signal line 30 configure a source follower that converts the voltage of the node 420 into the potential of the vertical signal line 30.

[0023] The selection transistor 440 is connected between the amplification transistor 430 and the vertical signal line 30. A selection signal SEL is supplied to the gate electrode of the selection transistor 440. When the selection transistor 440 becomes conductive in response to the selection signal SEL, the pixel 10 is placed in a selected state. Therefore, a signal is read out to the vertical signal line 30 from the pixel 10 in the selected state.

[0024] The circuit configuration of the pixel 10 is not limited to the configuration shown in FIG. 2 . For example, the selection transistor 440 may be connected between the power supply potential 460 and the amplification transistor 430. Although the configuration shown in FIG. 2 illustrates a four-transistor (4Tr.) configuration of the pixel 10 including the transfer transistor 410, the reset transistor 455, the amplification transistor 430, and the selection transistor 440, the configuration is not limited to this. For example, the selection transistor 440 may be omitted, and a three-transistor configuration in which the amplification transistor 430 also functions as the selection transistor may be employed. Furthermore, a five-transistor or more configuration with an increased number of transistors may be employed depending on the specifications required for the photoelectric conversion device 1000. The pixel 10 may sequentially output a reset signal generated when the reset transistor 455 resets the potential of the node 420 and resets the photoelectric conversion element 400, and a data signal representing the signal level when photoelectric conversion is performed by the photoelectric conversion element 400.

[0025] 3 is a diagram showing a configuration example of the photoelectric conversion device 1000, focusing on the circuits included in the second substrate 2. A sample-and-hold circuit 210 that samples and holds a reset signal and a sample-and-hold circuit 211 that samples and holds a data signal are connected to one vertical signal line 30. The sample-and-hold circuits 210 and 211 constitute a sample-and-hold unit 50. The output of the sample-and-hold unit 50 is supplied from the sample-and-hold circuit 211 to an analog-to-digital conversion circuit 390 that constitutes a conversion unit 60.

[0026] The determination circuit 20, sample-and-hold circuits 210 and 211, and analog-to-digital conversion circuit 390 are provided for each vertical signal line 30. Therefore, if the number of vertical signal lines 30 increases due to an increase in the number of pixels, the space required to arrange these circuits also increases. In this embodiment, these circuits are arranged on a second substrate 2 that is different from the first substrate 1 on which the pixel section 5 is provided, and the first substrate 1 and the second substrate 2 are stacked, thereby reducing restrictions on circuit arrangement and making it possible to reduce the chip area.

[0027] The determination circuit 20 determines the amplitude of the signal read out from the pixel 10 to the vertical signal line 30 using a reference value. The reference value is supplied to the determination circuit 20 from, for example, a reference value circuit included in the photoelectric conversion device 1000 or an external circuit. Here, a first reference value REF1 and a second reference value REF2 are supplied to the determination circuit 20. Therefore, the determination circuit 20 can perform a first determination using the first reference value REF1 and a second determination using the second reference value REF2.

[0028] Here, as an example, the result of the first determination is used for automatic gain control (AGC) of the signal, and the result of the second determination is used for detecting dark spots. Therefore, the result of the first determination is used in the photoelectric conversion device 1000 to control the analog gain (the resistance value of the variable resistor 240) and the digital gain (the magnification or coefficient applied by the data processing unit 90). It is also used, for example, to replace the signal of a pixel where dark spots are occurring with a saturation level signal. This correction may be performed inside the photoelectric conversion device 1000 (e.g., in the data processing unit 90) or outside the photoelectric conversion device 1000. When the correction is performed externally, the result of the second determination can be output to the outside of the photoelectric conversion device 1000 via the output unit 100. However, the uses of the amplitude determination result are not limited to these, and the output destination of the amplitude determination result can also be changed depending on the application.

[0029] The circuit configurations of the sample-and-hold unit 50 and the conversion unit 60 will be described. The sample-and-hold circuit 210 for the reset signal includes a capacitive element 120 and an inverting amplifier 220. The switch 110 switches between a connected state and a disconnected state between the vertical signal line 30 and the capacitive element 120 in accordance with a control signal Smp_n. The inverting amplifier 220 can be configured by combining a source-grounded circuit and a source-follower circuit. The inverting amplifier 220 includes transistors 130, 140, 150, and 160, switches 170, 180, and 190, and a current source 200. The switch 170 is connected between the inverting input terminal and the output terminal of the inverting amplifier 220 and is controlled by a control signal Smpa_n. A reset signal is output from the inverting amplifier 220 in accordance with a control signal Hold_n.

[0030] The sample-and-hold circuit 211 for the data signal may have a configuration similar to that of the sample-and-hold circuit 210 for the reset signal. Specifically, the sample-and-hold circuit 211 includes a capacitive element 121 and an inverting amplifier 221. The switch 111 switches between a connected state and a disconnected state between the vertical signal line 30 and the capacitive element 121 in accordance with a control signal Smp_s. The inverting amplifier 221 may be configured by combining a common-source circuit and a source follower circuit. The inverting amplifier 221 includes transistors 131, 141, 151, and 161, switches 171, 181, and 191, and a current source 201. The switch 171 is connected between the inverting input terminal and the output terminal of the inverting amplifier 221, and is connected to the inverting input terminal of the inverting amplifier 221 in accordance with a control signal Smp_s. s The data signal is output from the inverting amplifier 221 in accordance with the control signal Hold_s.

[0031] A variable resistance element 240 is provided between the output terminal of the sample and hold circuit 210 for the reset signal and the output terminal of the sample and hold circuit 211 for the data signal. The resistance value of the variable resistance element 240 is controlled in accordance with the result of a first determination by the determination circuit 20. For example, when the amplitude of the signal is small (smaller than the first reference value REF1), the determination circuit 20 reduces the resistance value of the variable resistance element 240 more than when the amplitude is not small. This increases the gain for signals with small amplitudes, making it possible to reduce dark noise in captured images.

[0032] The resistance value of the variable resistance element 240 is called the analog gain because it is the gain applied to the analog signal. When the analog gain is changed, data A gain is applied in processing unit 90 to offset the modification. data The gain applied by the processing unit 90 is called a digital gain because it applies to the digital signal after A / D conversion. The values ​​of the analog gain and the digital gain are determined so that their product is 1. Therefore, if the analog gain is made greater than 1, the digital gain will be less than 1.

[0033] The current I flowing through the variable resistance element 240 is expressed as follows, where Vn is the potential of the output terminal of the sample and hold circuit 210, i.e., the potential of the reset signal, Vs is the potential of the output terminal of the sample and hold circuit 211, i.e., the potential of the data signal, and R is the resistance value of the variable resistance element 240: I=(Vn-Vs) / R is.

[0034] The current I is input to the analog-to-digital conversion circuit 390. The current I flowing through the variable resistance element 240 is proportional to the difference between the potential Vn of the pixel's reset signal and the potential Vs of the data signal. Therefore, the current I after correlated double sampling (CDS) is input to the analog-to-digital conversion circuit 390 of the conversion unit 60. Furthermore, by reducing the resistance value R of the variable resistance element 240 below the reference value, a positive gain can be applied to the data signal (Vn-Vs) after CDS.

[0035] Unlike the circuit configuration described here, a configuration may be adopted in which the outputs of the sample-and-hold circuits 210 and 211 are input, and a CDS circuit that obtains the difference between the data signal and the reset signal is used to obtain the data signal after CDS.

[0036] 3 shows a delta-sigma (ΔΣ) analog-to-digital conversion circuit 390 as an example of the analog-to-digital conversion circuit 390 included in the conversion unit 60. The ΔΣ analog-to-digital conversion circuit 390 includes a first integrator, a second integrator, a quantizer 370, and a decimation filter 380. In the analog-to-digital conversion circuit 390, the first integrator is configured with an integral capacitor 320. The second integrator is configured with a Gm cell 330 that converts voltage into current and an integral capacitor 360.

[0037] A digital-to-analog converter 305 including a current source 300 and a switch 310 is connected to the input node of the first integrator. The digital-to-analog converter 305 controls the current to the first integrator in accordance with the digital signal transmitted through the second integrator and the quantizer 370. A digital-to-analog converter 345 including a current source 340 and a switch 350 is connected to the input node of the second integrator. The digital-to-analog converter 345 controls the current to the second integrator in accordance with the result of quantizing the output of the second integrator by the quantizer 370.

[0038] In the ΔΣ analog-to-digital conversion circuit 390, the previous quantized value in the quantizer 370 is fed back to the second integrator and the first integrator via the digital-to-analog converters 305 and 345. In this way, second-order noise shaping characteristics can be obtained by passing the previous quantized value twice through the integrators while feeding it back to the digital-to-analog converters 304 and 345. Furthermore, high-frequency noise can be removed by the decimation filter 380 arranged downstream of the quantizer 370, thereby obtaining a highly accurate analog-to-digital conversion output.

[0039] The digital signal output from the decimation filter 380 is input to the data processing unit 90. The data processing unit 90 applies predetermined processing, including application of digital gain, to the digital signal and outputs the result to the output unit 100. The data processing unit 90 controls the magnitude of the digital gain to be applied to the digital signal based on the result of the first determination notified by the determination circuit 20. The application of the digital gain may be multiplication of the value of the digital signal by a gain coefficient.

[0040] FIG. 4 is a circuit diagram showing an example of the configuration of the decision circuit 20. Each decision circuit 20 shown in FIG. 4 has a configuration compatible with multiple types of reference values. The decision circuit 20 shown in FIG. 4(a) has the same number of deciders and latches as the number of reference values ​​used for decision. This shows a configuration in which two types of reference values ​​are used, and includes a comparator 80 as a first decider that makes a first decision using a first reference value REF1, and a comparator 81 as a second decider that makes a second decision using a second reference value REF2. The result of the first decision is stored in the latch 70, and the result of the second decision is stored in the latch 71. The comparators 80 and 81 output a high level or a low level depending on the magnitude relationship between the potential of the vertical signal line 30 and the reference value.

[0041] 4(b) shows a configuration in which a reference value is selectively input to the comparators, and the number of comparators can be reduced compared to the configuration in FIG. 4(a). The decision circuit 20 has one comparator 80 and one latch 70. The decision circuit 20 also has switches SW1 and SW2 for selectively inputting a first reference value REF1 and a second reference value REF2 to the single comparator 80. Control signals for the switches SW1 and SW2 are supplied as one of the control signals for controlling the operation of reading out a signal from a pixel, for example.

[0042] Fig. 4(c) shows a configuration with a single reference value input line, which allows the number of switches SW1 and SW2 in the configuration of Fig. 4(b) to be reduced. When using the determination circuit 20 of Fig. 4(c), the value of the reference value REF input to the comparator 80 is made variable. Specifically, a first reference value REF1 is input to the comparator 80 during the period when the first determination is made, and a second reference value REF2 is input to the comparator 80 during the period when the second determination is made.

[0043] The reference value used by the determination circuit 20 can be supplied from a reference value circuit 21 provided inside the photoelectric conversion device 1000 or from outside the photoelectric conversion device 1000 .

[0044] 5 is a diagram showing an example of the potential change of the vertical signal line 30 according to the amount of incident light on the selected pixel, and the operation timing of each switch of the sample-and-hold circuits 210 and 211. The diagram also shows the first reference value REF1 and the second reference value REF2 used in the determination circuit 20. The determination circuit 20 is assumed to have the configuration shown in FIG. 4(a).

[0045] Here, examples of potential changes of the vertical signal line 30 are shown for three cases: when the amount of incident light on the pixel 10 is low (low luminance), when it is high (high luminance), and when it is extremely high (ultra-high luminance). Note that ultra-high luminance corresponds to a condition where charges generated in the pixel's photoelectric conversion element leak into the floating diffusion (also known as blooming). Low luminance and high luminance are typical examples of low and high incident light amounts within a range where blooming does not occur. In this embodiment, the pixel 10 accumulates electrons through photoelectric conversion. Therefore, the potential of the vertical signal line 30 decreases from the reference potential as the amount of incident light on the pixel 10 increases.

[0046] The control signals Smp_n and Smpa_n,H in FIG. ol d_n,smp_s,smpa_s, Hol d_s is a control signal for the switch having the same name in Fig. 3. Here, while the control signal is at a high level, the corresponding switch is in an on state (conducting state), and while the control signal is at a low level, the corresponding switch is in an off state (non-conducting state).

[0047] First, at time t1, the control signals Smp_n and Smpa_n go to high level, and the switches 110 and 170 turn on in the reset signal sample-and-hold circuit 210. Next, at time t2 when the control signal Smpa_n transitions from high level to low level, the potential Vn of the reset signal is sampled and stored in the capacitive element 120.

[0048] Next, at time t3, the control signal Smp_n transitions from high to low. Furthermore, the control signal Hold_n goes high, turning on the switches 180 and 190, causing the capacitance element 120 in the sample-and-hold circuit 210 to hold the potential Vn of the reset signal. The charge sampled and held in the capacitance element 120 is output from the sample-and-hold circuit 210 for the reset signal.

[0049] At time t4, a signal generated by the photoelectric conversion element 400 from the pixel 10 is output to the vertical signal line 30. Next, at time t5, the control signals Smp_s and Smpa_s go high, and the switches 111 and 171 in the data signal sample-and-hold circuit 211 are turned on. Next, at time t6 when the control signal Smpa_s transitions from high to low, the potential Vs of the data signal is sampled and stored in the capacitive element 121. The determination circuit 20 performs amplitude determination during the period from time t5 to t6.

[0050] Next, at time t7, the control signal Smpa_s transitions from high to low. s becomes high level, and the switches 181 and 191 are turned on, causing the capacitor 121 to hold the potential Vs of the data signal in the sample and hold circuit 211. The charge sampled and held in this capacitor 121 is output from the sample and hold circuit 211 for the data signal.

[0051] As described above, a current corresponding to the difference between the potential Vn of the reset signal at the output terminal of the sample and hold circuit 210 and the potential Vs of the data signal at the output terminal of the sample and hold circuit 211 is input to the analog-to-digital conversion circuit 390. Next, at time t9, the control signals Hold_n and Hold_s go low, and sampling of the reset signal and data signal of the next pixel 10 begins.

[0052] Next, the relationship between the amount of incident light on a pixel and the amplitude determination result in the determination circuit 20 will be described. Here, a first reference value REF1 for AGC control and a second reference value REF2 for detecting blackouts are provided. Therefore, the first reference value REF1 has a value for detecting a signal with a luminance level within a predetermined range for increasing the analog gain. The second reference value REF2 has a value for detecting the potential of the vertical signal line 30 that exceeds the saturation level.

[0053] When the amount of light incident on the pixel is small and a signal corresponding to low brightness is output, the potential drop of the vertical signal line 30 at time t4 is small and does not fall below the first reference value REF1. As a result, the comparator 80 of the decision circuit 20 outputs a high level as the first decision result. This means that the read data signal is a signal within a brightness range that increases the analog gain. Furthermore, because the potential of the vertical signal line 30 does not fall below the second reference value REF2, the comparator 81 of the decision circuit 20 outputs a high level as the second decision result. This means that no darkening occurs in the data signal.

[0054] When the amount of incident light is large enough to prevent charge leakage from the pixel and a signal corresponding to high brightness is output, the potential drop of the vertical signal line 30 at time t4 becomes large and falls below the first reference value REF1. As a result, the comparator 80 of the decision circuit 20 outputs a low level as the first decision result. This means that the read data signal is not within the brightness range that requires an increase in analog gain. Furthermore, because the potential of the vertical signal line 30 does not fall below the second reference value REF2, the comparator 81 of the decision circuit 20 outputs a high level as the second decision result. This means that no darkening occurs in the data signal.

[0055] In the case of an extremely high brightness that causes blooming, the photoelectric conversion element is saturated. Therefore, the potential of the vertical signal line 30 detected by the decision circuit 20 during the data signal sampling period from time t5 to t6 is lower than the first reference value REF1. As a result, the comparator 80 of the decision circuit 20 outputs a low level as the first decision result.

[0056] Furthermore, at time t4, when the data signal is output to the vertical signal line 30, the potential of the floating diffusion is lower than normal due to charge leaking from the photoelectric conversion element. From this state, charge at a saturation level is further transferred to the floating diffusion, so the potential of the vertical signal line 30 detected by the decision circuit 20 during the period from time t5 to t6 becomes an oversaturation level and falls below the second reference value REF2. Therefore, the comparator 81 of the decision circuit 20 outputs a low level as the second decision result. This means that a darkening phenomenon has occurred in the data signal.

[0057] The determination circuit 20 performs a first determination using a first reference value REF1 and a second determination using a second reference value REF2 while the pixel 10 is selected for signal readout. The determination results are then held in latches 70 and 71, respectively, and can be used for at least one of subsequent processing within the photoelectric conversion device 1000 and processing outside the photoelectric conversion device 1000.

[0058] Here, the result of the first determination is used in the photoelectric conversion device 1000 to adjust the resistance value (analog gain) of the variable resistance element 240 by the determination circuit 20 and to adjust the digital gain applied by the data processing unit 90. Furthermore, the result of the second determination can be used, for example, to correct a data signal in which darkening occurs. This correction may be performed inside the photoelectric conversion device 1000 (for example, in the data processing unit 90) or outside the photoelectric conversion device 1000. In either case, the result of the second determination can be stored in a memory or the like. The correction may be, for example, a process of replacing a data signal in which darkening has been detected by the second determination with a data signal at a saturation level.

[0059] Examples of judgment results and operations based on the judgment results are shown below. The gains applied to low-luminance data signals in the table are merely examples. As mentioned above, the purpose of the judgment is not limited to the AGC control and black sun detection exemplified here. Three or more types of judgment may also be performed. For example, the low-luminance range may be divided into multiple areas, and the number of types of judgment may be increased to perform more detailed AGC control. [Table 1]

[0060] By including a determination circuit that determines the amplitude of a signal read from a pixel to a vertical signal line, the photoelectric conversion device of this embodiment can perform appropriate processing based on the determination result, either inside or outside the photoelectric conversion device. In particular, by performing multiple types of amplitude determination in the determination circuit while a pixel is selected for signal readout, it is possible to realize processing that contributes to improving image quality, such as detecting black suns and adjusting the gain applied to a data signal.

[0061] (Variation 1) 6 is a diagram showing an example of potential changes on the vertical signal line 30 and operation timings of the switches in the sample-and-hold circuits 210 and 211 and the switches in the decision circuit 20, in the first modification in which the decision circuit 20 has the configuration shown in FIG. 4(b). In this modification as well, the first decision and the second decision are made during the sampling period of the data signal.

[0062] 6, the sampling period of the data signal is the period from time t5 to t7. Here, an example is shown in which the second determination is made in the period from time t5 to t6, and the first determination is made in the period from time t6 to t7. Time t6 is the time that divides times t5 and t7 into two equal parts.

[0063] Between time t1 and time t5, the control signals of switches SW1 and SW2 are both low. Therefore, switches SW1 and SW2 are off, and amplitude determination processing is not performed. At time t5, the control signal of switch SW2 becomes high, turning switch SW2 on. Switch SW1 remains off. As a result, the second reference value REF2 is input to the inverting input of comparator 80. Because a data signal is input to the non-inverting input of comparator 80 via vertical signal line 30, the output of comparator 80 is held in latch 70 as the result of the second determination, and then output from output section 100 to outside of photoelectric conversion device 1000. If there is a circuit within photoelectric conversion device 1000 that uses the result of the second determination, that circuit will refer to the state of latch 70 during the period from time t5 to time t6.

[0064] At time t6, the control signal for switch SW2 goes low, turning switch SW2 off. Furthermore, the control signal for switch SW1 goes high, turning switch SW1 on. This causes the first reference value REF1 to be input to the inverting input of comparator 80. Because the data signal continues to be input to the non-inverting input of comparator 80 via vertical signal line 30, the output of comparator 80 is held in latch 70 as the result of the first decision.

[0065] The determination circuit 20 adjusts the resistance value of the variable resistance element 240 based on the result of the first determination, thereby adjusting the analog gain for the post-CDS data signal that is input to the analog-to-digital conversion circuit 390. Furthermore, the data processing unit 90 adjusts the digital gain to be applied to the digital signal that is output from the analog-to-digital conversion circuit 390 based on the result of the first determination held in the latch 70.

[0066] The other operations are the same as those described with reference to Fig. 5, and therefore will not be described again. Note that the order of the first determination and the second determination may be reversed.

[0067] In this modification, in addition to the above-mentioned effects, the configuration of the determination circuit 20 can be simplified, and therefore the circuit scale can be reduced.

[0068] (Variation 2) In the first modification, the first determination and the second determination are sequentially performed during the sampling period of the data signal. In this modification, one of the first determination and the second determination is performed outside the sampling period of the data signal. Specifically, the second determination is performed during a period before the start of output of the data signal (for example, during the sampling period of the reset signal).

[0069] 7 is a diagram showing an example of potential changes on the vertical signal line 30 and operation timings of the switches in the sample-and-hold circuits 210 and 211 and the switches in the decision circuit 20 in Modification 2. Here, it is assumed that the decision circuit 20 has the configuration shown in FIG. 4(b). Since there is no need to perform the first decision and the second decision in parallel, this is suitable for implementation in a decision circuit 20 having a single comparator.

[0070] The reset signal readout period begins at time t1. The control signal of switch SW2 goes high at time t1 to allow the determination circuit 20 to determine the amplitude of the reset signal. The control signal of switch SW1 remains low. This causes a second reference value REF2 to be input to the inverting input of comparator 80. Because the reset signal is read out onto vertical signal line 30, the output of comparator 80 corresponds to the result of the second determination. Note that in this modification, the second determination is performed on the reset signal rather than the data signal, so the value of the second reference value REF2 differs from that of the embodiment and modification 1. A value for detecting the amplitude of the reset signal, which would not occur if blooming were not occurring, is used as the second reference value REF2. For example, the second reference value REF2 may be a value equivalent to 1 / 8 of the full-scale amplitude.

[0071] When blooming occurs, charge overflows from the photoelectric conversion element during the reset signal readout period and leaks into the floating diffusion, causing the reset signal level to change over time. In the example of Figure 7, the reset signal level is not below the second reference value REF2 at time t1, but falls below the second reference value REF2 by time t2, when the reset signal is maintained. As a result, the output of comparator 80 becomes low at time t2, indicating the occurrence of black sun phenomenon.

[0072] At time t2, the control signal of switch SW2 goes low, and the second determination ends. Then, at time t4, the data signal readout period begins, and at time t5, when the data signal is sampled, the control signal of switch SW1 goes high. The control signal of switch SW2 remains low. This causes the first reference value REF1 to be input to the inverting input of comparator 80. Because the data signal is being read out onto vertical signal line 30, the output of comparator 80 corresponds to the result of the first determination.

[0073] Thereafter, at time t6 when the data signal is sampled, the control signal of the switch SW1 goes low, and the first determination ends.

[0074] In this modification, in addition to the same effects as those of the first modification, the time constraints on the determination process can be relaxed more than in the first modification.

[0075] (Variation 3) 8 is a diagram showing an example of potential changes on the vertical signal line 30, operation timings of the switches in the reference value sample-and-hold circuits 210 and 211, and control of the reference value used in the determination circuit 20, for Modification 3 in which the determination circuit 20 has the configuration shown in FIG. 4(c). In this modification, the first determination and the second determination are performed at the same timing as in Modification 2.

[0076] In this modification, the reference value supplied to the inverting input of comparator 80 is variable, and a second reference value REF2 is supplied during the period when the second determination is made, and a first reference value REF1 is supplied during the period when the first determination is made. For example, reference value circuit 21 supplies, as the reference value REF, the second reference value REF2 to the inverting input of comparator 80 from time t1 to t2, and the first reference value REF1 from time t5 to t6. Other than the method of supplying the reference value, this modification is the same as modification 2.

[0077] In this modification, in addition to the same effects as those of the second modification, the number of signal lines for supplying the reference value can be reduced.

[0078] (Variation 4) So far, we have described a configuration in which separate reference values ​​are used for the first and second judgments. However, the same reference value can also be used for the first and second judgments. Figure 9 shows an example of potential changes on the vertical signal line 30, the operation timing of each switch in the reference value sample-and-hold circuits 210 and 211, and control of the reference value used in the judgment circuit 20 in Modification 4.

[0079] 9 corresponds to the case in which the reference value REF in FIG. 8 does not change. In this modification, it is not possible to use an optimum reference value for each determination, but since there is no need to make the reference value variable, the configuration for supplying the reference value (for example, reference value circuit 21) can be simplified. Other effects of this modification are the same as those of modification 3.

[0080] Here, the second reference value REF2 suitable for the second determination is also used for the first determination. However, the first reference value REF1 suitable for the first determination may also be used for the second determination, or a third reference value REF3 different from the first reference value REF1 and the second reference value REF2 may be used for the first determination and the second determination. The result of the first determination is used in the photoelectric conversion device 1000. The result of the second determination is output, for example, to the outside of the photoelectric conversion device 1000. The result of the second determination can be stored in a memory or the like for output to the outside, for example.

[0081] (Variation 5) The above example illustrates the case where multiple types of amplitude determinations are performed for different purposes. However, the present invention can also be applied to cases where amplitude determinations for the same purpose are performed multiple times. For example, if the capacitance of the floating diffusion (node ​​420) of a pixel is variable, the capacitance of the floating diffusion may be changed and the data signal may be read multiple times.

[0082] 10 is a diagram showing an example of the potential change of the vertical signal line 30, the operation timing of each switch of the reference value sample-and-hold circuits 210 and 211, and the reference value used in the decision circuit 20 when the capacitance of the floating diffusion is changed and a data signal is read out multiple times. In this modification, the decision circuit 20 having the configuration shown in FIG. 4(c) is used.

[0083] Here, it is assumed that the first determination is performed for each of the data signals that are read twice. Therefore, the first reference value REF1 is continuously supplied to the determination circuit 20. The first first determination is performed during the first sampling period of the data signal (from time t5 to t6).

[0084] After the data signal is held, at time t10, the capacitance of the floating diffusion is increased, for example, to expand the dynamic range of the pixel. Then, at time t11, the second sampling period of the data signal begins. The change in the capacitance of the floating diffusion changes the amplitude of the data signal. Therefore, during the second sampling period of the data signal (from time t11 to t12), a second first determination is performed. The first determination result held in the latch 70 is overwritten with the second determination result.

[0085] According to this modification, when the capacitance of the floating diffusion is changed, the amplitude of the signal corresponding to the changed capacitance can be determined again. Therefore, when determining the amplitude for the purpose of AGC, for example, it is possible to perform appropriate gain adjustment according to the amplitude of the final data signal.

[0086] Here, as an example of performing the same determination multiple times, an example has been described in which the amplitude of the data signal is determined each time the capacitance of the floating diffusion of a pixel is changed. However, the same determination may also be performed multiple times on the reset signal level. For example, when A / D converting the reset signal level, the capacitance of the floating diffusion may be changed depending on the result of the second determination on the reset signal. By performing the second determination a second time on the reset signal read after the capacitance change, it is possible to appropriately detect dark spots even when the capacitance of the floating diffusion is changed.

[0087] According to this modification, if the capacitance of the floating diffusion is changed after the amplitude has been determined, the amplitude of the signal read after the capacitance has been changed is determined again, thereby enabling appropriate amplitude determination to be performed on the signal read from a pixel with a variable floating diffusion capacitance.

[0088] (Variation 6) When comparators 80 and 81 used in decision circuit 20 are implemented using differential amplifiers, input offsets can cause a decrease in accuracy. Therefore, by using comparator 80 configured to correct the input offset, decision accuracy can be improved.

[0089] FIG. 11 is a diagram showing an example of the configuration of a comparator capable of correcting input offset, which can be used as the comparators 80 and 81 of the decision circuit 20. In FIG.

[0090] 11(a), comparator 80 has two input capacitance elements 500 and 510 and feedback switches 520 and 530. Feedback switch 520 has one end connected to the inverting input terminal and the other end connected to the non-inverting output terminal. Feedback switch 530 has one end connected to the non-inverting input terminal and the other end connected to the inverting output terminal.

[0091] The output of the comparator 80 is a non-inverting output terminal, which is connected to the input terminal of the latch 70. A capacitive element 500 is connected to the inverting input terminal, and a capacitive element 510 is connected to the non-inverting input terminal. A reference value is supplied to the inverting input terminal via the capacitive element 500, and the vertical signal line 30 is connected to the non-inverting input terminal via the capacitive element 500.

[0092] With a reset signal supplied to the non-inverting input and a reference value REF supplied to the inverting input, when switches 520 and 530 are turned on (conducting) and then turned off, the capacitive elements 500 and 510 have the same potential difference, respectively. This allows the input offset voltage of comparator 80 to be canceled.

[0093] 11(b) is the same as FIG. 11(a) except that the differential amplifier constituting the comparator 80 is single-ended. With this configuration as well, the input offset voltage of the comparator 80 can be canceled by turning on (conducting) the switches 520 and 530 and then turning them off while a reset signal is supplied to the non-inverting input and a reference value REF is supplied to the inverting input.

[0094] The comparator 80 may have any known configuration as a so-called auto-zero differential amplifier. The configuration shown in FIG.

[0095] (Variation 7) 12 shows a configuration in which the decision circuit 20 is driven by a current source 40 of a vertical signal line 30 that supplies current to a selection transistor 440 and an amplification transistor 430 of a pixel 10. This makes it possible to reduce power consumption compared to when the decision circuit 20 is driven by a separate power supply.

[0096] The comparator has an N-type MOS transistor 540, P-type MOS transistors 550 and 560, and a reset switch 570. The vertical signal line 30 is connected to the source of the transistor 540, and a reference value REF is input to the gate. The transistor 550 is connected to the power supply voltage and the transistor 540, and a bias voltage is applied to the gate. The transistor 560 is connected to the power supply voltage and the latch 70, and the voltages of the transistors 540 and 550 are applied to the gate. 0 The voltage at the connection point of the transistor 560 is applied. The output of the transistor 560 is input to the latch 70. The reset switch 570 is a switch that resets the latch 70 when turned on.

[0097] When the potential of the vertical signal line 30 drops below (reference voltage REF-threshold voltage Vth of transistor 540), the transistor 540 turns on. When the transistor 540 turns on, a current flows toward the current source 40. This causes the gate voltage of the transistor 560 to drop, turning the transistor 560 on. This causes the latch 70 to hold a high level. The reference voltage REF may be a first reference value REF1 or a second reference value REF2. When making multiple determinations, the reset switch 570 is turned on to reset the previous determination result before making a new determination.

[0098] According to this modification, the determination circuit 20 is driven by the current source 40 of the vertical signal line 30, so that power consumption can be reduced.

[0099] (Variation 8) 13 is a diagram showing another embodiment in which the determination circuit 20 is driven by a current source 40 of the vertical signal line 30. The same components as those in Modification 7 are given the same reference numerals as in FIG. 12 and their description will be omitted. The determination circuit 20 according to this modification adds a configuration for maintaining the potential of the vertical signal line 30 to the configuration of Modification 7.

[0100] Specifically, a switch 590 that connects and disconnects the source and gate of the transistor 540, and a capacitance element 600 that is provided between the gate of the transistor 540 and the input terminal for the reference value are added.

[0101] When the switch 590 is turned on while the reset signal is being read out to the vertical signal line 30, the vertical signal line 30 is connected to the capacitive element 600. When the switch 590 is turned off, the potential of the reset signal is held in the capacitive element 600. The capacitive element 600 functions as a circuit for holding the potential of the reset signal.

[0102] In this state, when the reference value REF is decreased by ΔV and this decreased amount is applied to the capacitive element 600, a potential of (reset signal - ΔV) is applied to the gate of the transistor 540. By adjusting ΔV so that the transistor 540 turns on when the potential of the vertical signal line 30 decreases from the reset signal by, for example, 1 / 8 of the full scale, it is possible to perform a first determination on the data signal. In this way, in this modification, the reference reset signal of the vertical signal line 30 is used as the reference for the gate potential of the transistor 540.

[0103] As a result, according to this modification, the amplitude can be determined while suppressing variations in the threshold voltage Vth of the source follower transistor in the output stage of the pixel that reads out the signal, thereby improving the determination accuracy.

[0104] As described above, the photoelectric conversion device according to this embodiment includes a determination circuit that determines the amplitude of a signal read from a pixel or the amplitude of a signal based on the read signal. While a pixel is selected for signal readout, the determination circuit performs amplitude determinations at various types or timings, allowing appropriate processing to be performed inside or outside the photoelectric conversion device based on the determination results. Using the determination results, for example, it is possible to detect black suns and adjust the gain applied to the data signal, thereby improving image quality.

[0105] (Other embodiments) An application example of the photoelectric conversion device 1000 according to the above embodiment will be described below. FIG. 14 is a schematic diagram of an electronic device EQP equipped with the photoelectric conversion device 1000. FIG. 14 shows a camera as an example of the electronic device EQP. Here, the concept of a camera includes not only a device whose main purpose is to take pictures, but also a device that has an auxiliary photography function (for example, a personal computer or a mobile terminal such as a smartphone).

[0106] The photoelectric conversion device 1000 may be a semiconductor chip with a stacked structure provided with a pixel section 5. As shown in FIG. 14, the photoelectric conversion device 1000 is housed in a semiconductor package PKG. The package PKG may include a base to which the photoelectric conversion device 1000 is fixed, a lid facing the photoelectric conversion device 1000, and a conductive connecting member that connects terminals provided on the base with terminals provided on the photoelectric conversion device 1000. The lid may be made of glass, for example. The connecting member may be a bonding wire, a bump, or the like. The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a memory device MMRY.

[0107] The optical system OPT forms an image on the photoelectric conversion device 1000 and may be, for example, a lens, shutter, or mirror. The control device CTRL controls the operation of the photoelectric conversion device 1000 and may be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device 1000 and may be, for example, a semiconductor device such as a CPU or ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays image data obtained by the photoelectric conversion device 1000. The memory device MMRY is a magnetic device or a semiconductor device that stores image data obtained by the photoelectric conversion device 1000. The memory device MMRY may be a volatile memory such as an SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving or propulsive part such as a motor or engine. In a camera, the mechanical device MCHN can drive components of the optical system OPT for zooming, focusing, and shutter operation. The device EQP displays the image data output from the photoelectric conversion device 1000 on the display device DSPL, or transmits it to the outside via a communication device (not shown) included in the device EQP. For this reason, the device EQP may include a memory device MMRY and a processing device PRCS.

[0108] A camera incorporating the photoelectric conversion device 1000 can be used as a surveillance camera or an on-board camera mounted on transportation equipment such as automobiles, railroad cars, ships, aircraft, or industrial robots. In addition, a camera incorporating the photoelectric conversion device 1000 can be used not only in transportation equipment but also in a wide range of equipment that uses object recognition, such as an intelligent transport system (ITS).

[0109] The present invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Therefore, the following claims are appended to clarify the scope of the invention. [Explanation of symbols]

[0110] 5: pixel unit, 10: pixel, 30: vertical signal line, 50: sample and hold unit, 60: conversion unit, 210, 211: sample and hold circuit, 1000: photoelectric conversion device

Claims

1. a reset signal; and a pixel that generates a data signal by photoelectric conversion; a determination circuit for determining the amplitude of a signal read out from the pixel to a vertical signal line; an A / D conversion circuit that converts a signal based on one or both of the reset signal and the data signal into a corresponding digital signal; the determination circuit performs a first determination on the data signal while the pixel is selected for signal readout, and a second determination on the reset signal; a photoelectric conversion device that sets an analog gain to be applied to the signal and a digital gain to be applied to the digital signal based on a result of the first determination;

2. The determination circuit 2. The photoelectric conversion device according to claim 1, further comprising a determiner that performs the first determination and the second determination.

3. 2. The photoelectric conversion device according to claim 1, wherein the determination circuit performs the first determination during a first period and the second determination during a second period.

4. 4. The photoelectric conversion device according to claim 2, wherein the determination circuit uses a first reference value for the first determination and a second reference value for the second determination.

5. 2. The photoelectric conversion device according to claim 1, wherein the determination circuit uses the same reference value for the first determination and the second determination.

6. 6. The photoelectric conversion device according to claim 5, wherein the result of the first determination is used in the photoelectric conversion device, and the result of the second determination is output to an external device of the photoelectric conversion device.

7. A pixel that generates a reset signal and a data signal by photoelectric conversion; a determination circuit that determines the amplitude of a signal read out from the pixel to a vertical signal line, the determination circuit performs a first determination on the data signal using a reference value while the pixel is selected for signal readout, and performs a second determination on the reset signal using the reference value; A photoelectric conversion device, characterized in that the result of the first determination is used in the photoelectric conversion device, and the result of the second determination is output to an external device of the photoelectric conversion device.

8. The photoelectric conversion device according to any one of claims 1 to 7, characterized in that the judgment circuit is an auto-zero type differential amplifier that receives the signal and a reference value used for the judgment as input and has the function of canceling input offset.

9. 9. The photoelectric conversion device according to claim 1, wherein the determination circuit is driven by a current source connected to a vertical signal line of the pixel.

10. The determination circuit a holding circuit for holding the potential of the reset signal read out to the vertical signal line; the determination is made using a potential generated by lowering the potential of the reset signal held in the holding circuit by a predetermined potential.

10. The photoelectric conversion device according to claim 9.

11. 11. The photoelectric conversion device according to claim 1, wherein the determination circuit holds the result of the determination so that the result can be read out from outside the determination circuit.

12. 12. The photoelectric conversion device according to claim 1, wherein the second determination is a determination as to whether or not a darkening phenomenon occurs in the pixel.

13. The photoelectric conversion device according to any one of claims 1 to 12, a control device that controls the operation of the photoelectric conversion device; An electronic device comprising:

14. A substrate laminated on a substrate on which a pixel that generates a reset signal and a data signal by photoelectric conversion is provided, a determination circuit for determining the amplitude of a signal read out from the pixel to a vertical signal line; an A / D conversion circuit that converts a signal based on one or both of the reset signal and the data signal into a corresponding digital signal; the determination circuit performs a first determination on the data signal while the pixel is selected for signal readout, and a second determination on the reset signal; A substrate, characterized in that an analog gain to be applied to the signal and a digital gain to be applied to the digital signal are set based on the result of the first determination.

15. A substrate as described in Claim 14, characterized in that the second judgment is a judgment of whether or not blackening has occurred in the pixel.

16. A substrate as described in Claim 14 or 15, characterized in that the judgment circuit uses the same reference value for the first judgment and the second judgment.

17. The substrate according to claim 16, wherein the result of the first determination is used to set an analog gain that the A / D conversion circuit applies to the signal, and the result of the second determination is output to the outside of the substrate that is stacked on the substrate on which the pixel is provided.

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