Image sensor control method, image sensor, and program

Abstract

To provide a control method of an image pick-up device, that reduces a fixed pattern noise caused by a quantization error of an AD conversion circuit in a CMOS image sensor.SOLUTION: An image pick-up device is an image pick-up device that includes a plurality of pixels including at least: a photoelectric conversion part; a floating diffusion; a first reset switch that resets a voltage of the floating diffusion, respectively, and is arranged in a matrix shape. The image pick-up device comprises a column circuit including: a vertical signal line, clamp capacity connected to the vertical signal line, and a second reset switch that resets the clamp capacity, which are arranged in each pixel column, respectively. A time between a reset cancellation timing by the first reset switch and a reset cancellation timing by a second reset switch can be changed in accordance with a setting value.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a control method for an image sensor, an image sensor, and a program, and more particularly to a signal readout drive control method for an image sensor. [Background technology]

[0002] Conventionally, CMOS image sensors using a column AD conversion method have been known as imaging elements used in digital cameras and the like. In a column AD conversion CMOS image sensor, an AD conversion circuit arranged for each column of pixels arranged in a matrix is ​​used to AD convert analog signals from the pixels and sequentially read them out. For example, Patent Document 1 discloses the configuration of a column AD conversion CMOS image sensor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-54424 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology disclosed in the above-mentioned Patent Document 1, quantization errors in the AD conversion circuit may become fixed pattern noise, which may deteriorate the image quality.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a control method for an imaging element that reduces fixed pattern noise caused by quantization errors in an AD conversion circuit in a CMOS image sensor. [Means for solving the problem]

[0006] In order to achieve the above object, a control method for an image sensor according to the present invention includes: a plurality of pixels arranged in a matrix, each having a photoelectric conversion unit, a floating diffusion capable of holding charge generated by the photoelectric conversion unit, a first reset switch that resets the voltage of the floating diffusion, and a source follower that outputs a pixel signal according to the voltage of the floating diffusion; vertical signal lines arranged for each pixel column and connected to the source followers of the plurality of pixels; clamp capacitors connected to the vertical signal lines; and a second reset switch that resets the clamp capacitor. an inverting amplifier that, together with the clamp capacitor, constitutes a gain amplifier that amplifies an input voltage signal by a predetermined gain; and an AD conversion circuit that AD converts the voltage signal output from the gain amplifier by a predetermined number of bits; and a column circuit each having a first reset switch and a second reset switch, Any one of the set gain of the gain amplifier, the number of bits of the AD conversion circuit, and ISO sensitivity It is characterized by being changed according to a set value. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a method for controlling an image sensor that reduces fixed pattern noise caused by quantization errors in an AD conversion circuit in a CMOS image sensor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing the configuration of an imaging element according to a first embodiment. [Figure 2] FIG. 2 is an equivalent circuit diagram of the imaging element according to the first embodiment. [Figure 3] 4 is a driving timing chart of the imaging element according to the first embodiment. [Figure 4] 4 is a control table for the imaging element according to the first embodiment. [Figure 5] FIG. 10 is an equivalent circuit diagram of an image sensor according to a second embodiment. [Figure 6] 10 is a driving timing chart of an image sensor according to a second embodiment. [Figure 7] 10 is a control table for an imaging element according to the second embodiment. [Figure 8]FIG. 11 is an equivalent circuit diagram of an image sensor according to a third embodiment. [Figure 9] 10 is a driving timing chart of an image sensor according to a third embodiment. [Figure 10] 10 is a control table for an imaging element according to the third embodiment. [Figure 11] FIG. 10 is an equivalent circuit diagram of an image sensor according to a fourth embodiment. [Figure 12] 10 is a driving timing chart of an image sensor according to a fourth embodiment. [Figure 13] 10 is a control table for an imaging element according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the present invention as defined in the claims, and not all of the combinations of features described in the embodiments are necessarily essential to the solution of the present invention.

[0010] [First embodiment] Fig. 1 is a block diagram showing the configuration of an image sensor according to a first embodiment. As shown in Fig. 1, the image sensor 100 of this embodiment has a configuration known as a column AD conversion type CMOS image sensor. The image sensor 100 includes a pixel unit 101, a vertical scanning unit 102, a column amplifier unit 103, an AD conversion unit 104, pixels 105, vertical signal lines 106, and an output unit 107. The image sensor 100 of this embodiment includes a column readout circuit (column circuit) configured with the vertical signal lines 106, column amplifier unit 103, AD conversion unit 104, etc., provided for each pixel column.

[0011] The pixel section 101 has a plurality of pixels 105 that receive an optical image formed by an optical system, and the plurality of pixels 105 are arranged in a matrix. For the sake of explanation, the pixel section 101 is shown with only six vertical rows and eight horizontal columns, but in reality, the pixel section 101 is made up of many more pixels 105.

[0012] The vertical scanning unit 102 sequentially selects multiple rows of the pixel unit 101 in the vertical direction and applies multiple drive pulse signals to each pixel. In this way, the voltage signal of each pixel is output to the column amplifier unit 103 via a vertical signal line 106. The column amplifier unit 103 amplifies the input voltage signal of each pixel with a predetermined gain and outputs it.

[0013] The AD conversion unit 104 converts the input voltage signal from the column amplifier unit 103 into a digital signal value by AD conversion using a predetermined number of bits. A single-slope AD conversion method is generally used here. In the single-slope AD conversion method, a ramp signal, whose voltage changes at a constant rate over time, is compared with the pixel voltage signal, and the count value at the timing when the signal magnitude relationship is reversed is recorded in memory, thereby obtaining a digital signal value. The AD conversion unit 104 in this embodiment also has a CDS processing unit that includes multiple digital memories and a differential processing circuit for performing so-called CDS operations.

[0014] Note that CDS operation is a correlated double sampling operation. In CDS operation, the AD conversion unit 104 AD converts a pixel signal corresponding to the reset voltage level in the floating diffusion into an N signal. The AD conversion unit 104 also AD converts a pixel signal corresponding to a voltage level obtained by adding the reset voltage level in the floating diffusion to the accumulated charge of the photoelectric conversion unit 201 (described later) into an S signal. The AD conversion unit 104 sequentially AD converts the pixel signal into an N signal and then into an S signal.

[0015] The output unit 107 converts the digital signal value of each pixel into a predetermined signal format and outputs it to the outside of the image sensor 100 via a transmission path.

[0016] FIG. 2 is an equivalent circuit diagram of the image sensor according to the first embodiment. For the sake of explanation, only one pixel and the signal output path of that pixel are shown. As shown in FIG. 2, the pixel 105 includes a photoelectric conversion unit 201, a transfer switch 202, a floating diffusion 203, a reset switch 204, a source follower transistor 205, and a selection switch 206. Hereinafter, the floating diffusion will be referred to as FD, and the source follower transistor will be referred to as SF. This configuration is known as a pixel of a four-transistor CMOS image sensor.

[0017] The column amplifier unit 103 includes an inverting amplifier 208 , a clamp capacitor 209 , a clamp switch 210 , a feedback capacitor 211 , and a gain changeover switch 212 .

[0018] Next, we will explain the detailed configuration of the pixel 105. The photoelectric conversion unit 201 functions as a photodiode that generates and accumulates signal charges according to the amount of light received. The transfer switch 202 is driven by a signal pulse PTX and transfers the signal charges accumulated in the photoelectric conversion unit 201 to the FD 203.

[0019] The FD 203 functions as a charge holding unit, capable of holding signal charges generated in and transferred from the photoelectric conversion unit 201. The FD 203 also functions as a charge-voltage conversion unit that converts the held charges into a voltage signal.

[0020] The reset switch 204 (first reset switch) is driven by a signal pulse PRES, and is configured to be able to discharge the charge of the FD 203 to a power supply node VDD and reset the voltage of the FD 203. The reset switch 204 resets the voltage of the FD 203.

[0021] The SF 205 outputs a signal according to the voltage of the FD 203 as a pixel voltage signal (pixel signal) to the vertical signal line 106. The SF 205 configures a source follower circuit together with a constant current source 207 connected to the vertical signal line.

[0022] The selection switch 206 is driven by a signal pulse PSEL to connect the SF 205 to the vertical signal line 106. The pixel voltage signal output to the vertical signal line 106 is amplified by the column amplifier unit 103 and then output to the AD conversion unit 104 at the subsequent stage.

[0023] The inverting amplifier 208, together with the clamp capacitor 209 and a plurality of feedback capacitors 211, constitutes a gain amplifier that amplifies an input voltage signal by a predetermined gain. This gain is determined by the ratio between the clamp capacitor 209 and the feedback capacitor 211, and therefore the set gain can be changed by switching the operating state of the gain changeover switch 212. That is, the column circuit of this embodiment includes the inverting amplifier 208 connected to the clamp capacitor 209, and is configured to be able to change the set value of the set gain in the inverting amplifier 208.

[0024] 2, for the sake of explanation, two feedback capacitors 211a and 211b are shown as the feedback capacitor 211, and only two gain changeover switches 212a and 212b are shown as the gain changeover switch 212. However, by further using the feedback capacitor 211 and the gain changeover switch 212, it becomes possible to change the set gain in multiple stages.

[0025] FIG. 3 is a drive timing chart for the image sensor according to the first embodiment. For the sake of explanation, only the drive signal pulses related to FIG. 2 during a unit row readout period are shown. The signal pulse HD is a horizontal synchronization signal. The signal pulses HD, PSEL, PRES, PCOR, and PTX in FIG. 3 are digital signal waveforms. Each of these pulses indicates a high-level state (hereinafter referred to as H state) or a low-level state (hereinafter referred to as L state) of each signal waveform. The voltage of the vertical signal line 106 in FIG. 3 is an analog signal waveform, and illustrates a continuous voltage state during a readout operation. Below, the state of each signal waveform at each timing T is indicated as an H state or an L state.

[0026] At T301, in response to the image sensor 100 receiving the falling edge of the signal pulse HD, the vertical scanning unit 102 starts reading out pixel signals from a unit row.

[0027] At T302, when the signal pulse PSEL goes to H state, the selection switch 206 is turned on, and the SF 205 and the vertical signal line 106 are connected.

[0028] At T303, when the signal pulse PRES goes to the L state, the reset switch 204 is turned OFF and the FD 203 is reset to the reset voltage level.

[0029] During the period from T303 to T304d, the signal pulse PRES is in the L state and the signal pulse PC0R is in the H state, so that a pixel signal corresponding to the reset voltage level of the FD 203 is clamped in the clamp capacitor 209. This clamp operation prevents the reset voltage level of the FD 203 from falling outside the operating voltage range of the column amplifier unit 103 due to reset noise (mainly kTC noise components). On the other hand, the first embodiment is characterized by controlling the falling timing T304d of the signal pulse PC0R to change to T304a, T304b, or T304c depending on the set gain of the column amplifier unit 103. Details will be described later. The falling timing of the signal pulse PC0R is performed by a clamp switch 210 (second reset switch) that resets the clamp capacitor 209. The clamp switch 210 is a switch that connects the input and output of the column amplifier unit 103.

[0030] At T305, the AD conversion unit 104 performs AD conversion on the reset voltage level, and stores the resulting digital signal value in the digital memory as an "N signal."

[0031] During the period from T306 to T307, the signal pulse PTX goes to the H state, and a pixel signal based on the voltage level after the accumulated charge of the photoelectric conversion unit 201 is added to the reset voltage level of the FD 203 is output to the vertical signal line 106.

[0032] At T308, the AD conversion unit 104 performs AD conversion on the pixel signal, and stores the resulting digital signal value as an "S signal" in the digital memory.

[0033] The S signal and N signal are subjected to a differential process of "S signal-N signal" as a so-called CDS operation, and then output as a signal via output unit 107.

[0034] Here, we will again describe in detail the control of the falling timing of PC0R, which is a feature of the first embodiment. In Figure 3, the timing chart for when the falling timing of the signal pulse PC0R changes to T304a, T304b, and T304c is shown by dashed lines. Note that the falling timing refers to the timing at which each signal pulse changes from an H state to an L state. In this embodiment, the time between the reset release timing by the reset switch 204 and the reset release timing by the clamp switch 210 is changed according to the setting values ​​related to the imaging conditions.

[0035] At T304d, the voltage of the vertical signal line 106 has settled to the reset voltage level, whereas at T304a, T304b, and T304c, it is in a state before settling, higher than the reset voltage level. As a result, a voltage in a state where the reset noise is not yet determined is clamped in the clamp capacitor 209, and a "deviation" occurs between the voltage clamped in the clamp capacitor 209 and the voltage after settling. In this case, a voltage signal including this "deviation" is input to the AD conversion unit 104, and an N signal is obtained. Furthermore, because this "deviation" is based on random reset noise, it varies from pixel to pixel and from frame to frame.

[0036] However, when the signal pulse PC0R falls at T304d to completely clamp the reset noise, a quantization error specific to each column's AD conversion circuit occurs every frame. This causes vertical streaky fixed pattern noise in sensors using the column AD conversion method. Because quantization error does not depend on the amount of light, it can degrade image quality by appearing as vertical streaky fixed pattern noise, particularly in dark areas with low signal levels. Furthermore, this quantization error becomes more pronounced when the AD conversion circuit uses a small number of bits for AD conversion processing. Therefore, the image sensor control method of this embodiment varies the N signal for each pixel and each frame, thereby reducing the fixed pattern noise caused by quantization error.

[0037] The amount of quantization error does not depend on the gain setting of the column amplifier unit 103. Therefore, when the column amplifier unit 103 is set to a low gain, random noise is small and fixed pattern noise caused by quantization error is likely to affect image quality, so it is effective to set the falling timing of the signal pulse PC0R to T304a, T304b, or T304c. Furthermore, when the gain is set to a low value, even if a reset noise component that is not clamped is input to the column amplifier unit 103, the operating voltage range of the column amplifier unit 103 will not be exceeded.

[0038] When the gain is set high, random noise is large, and fixed pattern noise caused by quantization error is unlikely to affect image quality. Furthermore, unclamped reset noise components are further multiplied by the gain, which can cause the column amplifier unit 103 to fall outside its operating voltage range. For this reason, it is preferable to set the falling timing of the signal pulse PC0R to T304d. If the operating voltage of the column amplifier unit 103 falls outside its operating voltage range, the signal in the high-brightness area will sink to black, causing significant image degradation, and this should be avoided.

[0039] Note that by changing the falling edge timing of signal pulse PC0R to T304a, T304b, or T304c, the reset noise components that are not clamped are included in both the N signal and the S signal. These noise components are then removed by the CDS operation described above. Therefore, even if the falling edge timing of signal pulse PC0R is changed from T304d to T304a, T304b, or T304c, fixed pattern noise caused by quantization error can be reduced without worsening random noise.

[0040] 4 is a control table for the image sensor according to the first embodiment, showing the falling timing of the signal pulse PC0R according to the set gain of the column amplifier unit 103.

[0041] 3, when the column amplifier unit 103 is set to a low gain, it is preferable to set the falling timing of the signal pulse PC0R to T304a, T304b, or T304c, which is earlier than T304d, as this is effective in improving fixed pattern noise. When the column amplifier unit 103 is set to a high gain, it is preferable to set the falling timing to T304d.

[0042] When the set gain of the column amplifier unit 103 is 1, PC0R falls at T304a, which is before T303, the falling timing of the signal pulse PRES. In this case, the difference between the voltage clamped by the clamp capacitor 209 and the voltage after settling is particularly large, so the effect of improving fixed pattern noise is significant.

[0043] When the set gain of the column amplifier unit 103 is 2x or 4x, PC0R is turned off at T304b and T304c, respectively, after T303. As the set gain of the column amplifier increases, the margin of the operating voltage range of the column amplifier unit 103 is compressed, so the reset voltage level is clamped at a slightly higher voltage before it settles. At this time, if we focus only on the effect of improving fixed pattern noise, it is smaller than when the gain is 1x, which is turned off at T304a. However, this is not a problem because the random noise component, which depends on the set gain, increases.

[0044] If the set gain of the column amplifier unit 103 is 8 times or more, PC0R is turned off at T304d after T303. If the set gain is 8 times or more, the reset voltage level is clamped in a statically determined state to reliably prevent the column amplifier unit 103 from going outside its operating voltage range. At this time, random noise components that depend on the gain setting are dominant, so fixed pattern noise components that do not depend on the gain setting do not affect image quality.

[0045] The above drive control method is one example, and various modifications are possible within the scope of the present invention in accordance with the design, characteristics, and image quality of each image sensor. For example, the timing of the signal pulses may be controlled in accordance with the ISO sensitivity or the number of bits of the AD conversion circuit.

[0046] When the set value is the ISO sensitivity, the lower the ISO sensitivity, the shorter the time between the timing of reset release by reset switch 204 and the timing of reset release by clamp switch 210. Furthermore, when the ISO sensitivity is smaller than a predetermined value, the timing of reset release by clamp switch 210 may be made earlier than the timing of reset release by reset switch 204.

[0047] When the set value is the number of bits of the AD conversion circuit, the smaller the number of bits, the shorter the time between the timing of reset release by reset switch 204 and the timing of reset release by clamp switch 210. Furthermore, when the number of bits is smaller than a predetermined value, the timing of reset release by clamp switch 210 may be made earlier than the timing of reset release by reset switch 204.

[0048] [Second embodiment] A control method for an image sensor according to the second embodiment will be described below with reference to Figures 5 to 7. However, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0049] 5 is an equivalent circuit diagram of an image sensor according to the second embodiment. The equivalent circuit of the second embodiment differs from that of the first embodiment in that it does not include a column amplifier unit 103 and has a configuration in which a vertical signal line 106 and an AD conversion unit 104 are directly connected.

[0050] 5, the AD conversion unit 104 includes a comparator 501, a clamp capacitor 502, a clamp switch 503, a counter 504, and a CDS processing unit 505. As described above, the AD conversion unit 104 configures a single-slope AD conversion circuit.

[0051] The comparator 501 is a comparator that compares a ramp signal, the voltage of which changes at a constant rate over time, with the voltage signal of the pixel to determine which signal is larger.

[0052] The clamp capacitor 502 is a coupling capacitance of the input section of the comparator 501. The clamp switch 503 is a feedback switch that is driven by a signal pulse COMP_FB and shorts the input and output of the comparator.

[0053] The counter 504 outputs a count value at the timing when the output of the comparator 501 is inverted, and the count value is recorded in the digital memory of the CDS processing unit 505 .

[0054] The CDS processing unit 505 includes a plurality of digital memories and a differential processing circuit for performing so-called CDS operations.

[0055] 6 is a drive timing chart of the image sensor according to the second embodiment. The timing chart of the second embodiment differs from the first embodiment in that the signal pulse PC0R is not present, but the signal pulse COMP_FB is present.

[0056] In the period from T303 to T604d, the signal pulse PRES is in the L state and the signal pulse COMP_FB is in the H state. As a result, a pixel signal corresponding to the reset voltage level of the FD 203 is clamped in the clamp capacitor 502.

[0057] This clamping operation prevents reset noise at the reset voltage level of the FD 203 from going outside the operating voltage range of the AD conversion unit 104. On the other hand, the second embodiment, like the first embodiment, is characterized in that the falling timing T604d of the signal pulse COMP_FB is controlled to change to T604a, T604b, or T604c depending on the set gain.

[0058] The second embodiment does not have a column amplifier unit, so gain is achieved by changing the voltage change rate with respect to time of the ramp signal input to the comparator 501.

[0059] Fig. 7 is a control table for the image sensor according to the second embodiment, which shows the falling timing of the signal pulse COMP_FB according to the gain realized by the ramp signal.

[0060] At T604d, the voltage of the vertical signal line 106 has settled to the reset voltage level, while at T604a, T604b, and T604c, it is in a state before settling, higher than the reset voltage level. As a result, a voltage with undetermined reset noise is clamped in the clamp capacitor 502, resulting in a discrepancy between the voltage clamped in the clamp capacitor 502 and the voltage after settling. In this case, a voltage signal including the discrepancy is input to the AD converter 104, resulting in an N signal. Furthermore, because this discrepancy is due to random reset noise, it varies from pixel to pixel and from frame to frame. The image sensor control method of this embodiment varies the N signal from pixel to pixel and from frame to frame, thereby improving fixed pattern noise caused by quantization error.

[0061] The above drive control method is one example, and various modifications can be made within the scope of the present invention in accordance with the design, characteristics and image quality of each individual image sensor.

[0062] [Third embodiment] A control method for an image sensor according to the third embodiment will be described below with reference to Figures 8 to 10. However, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0063] 8 is an equivalent circuit diagram of the image sensor according to the third embodiment. The equivalent circuit of the third embodiment differs from that of the first embodiment in that the configuration of the constant current source 207 is shown in detail.

[0064] As shown in FIG. 8, the constant current source 207 includes a transistor 801 , a sample and hold capacitor 802 , and a sample and hold switch 803 .

[0065] The transistor 801 supplies a predetermined current load to a source follower circuit formed by the vertical signal line 106 and SF206 by applying a bias voltage to the gate thereof.

[0066] The sample and hold capacitor 802 is a voltage holding capacitor for holding the bias voltage constant.

[0067] The sample-and-hold switch 803 is driven by the signal pulse biasS / H and controls switching between the sample state and the hold state of the sample-and-hold capacitor 802. The sample-and-hold capacitor 802 is in the sample state when the signal pulse biasS / H is in the H state, and in the hold state when the signal pulse biasS / H is in the L state.

[0068] 9 is a drive timing chart of the image sensor according to the third embodiment. The timing chart of the third embodiment differs from that of the first embodiment in that a signal pulse biasS / H is added.

[0069] During the period from T303 to T304d, the signal pulse PRES is in the L state and the signal pulse PC0R is in the H state, so that the pixel signal corresponding to the reset voltage level of the FD 203 is clamped in the clamp capacitor 209.

[0070] The third embodiment is characterized in that the falling timing T904a of the signal pulse biasS / H is controlled to change to T904b in accordance with the set gain of the column amplifier unit 103.

[0071] 10 is a control table for the image sensor according to the third embodiment, which shows the falling timing of the signal pulse biasS / H according to the set gain of the column amplifier unit 103.

[0072] The sample and hold capacitor 802 holds the bias voltage during the signal readout period for one row, thereby suppressing noise components that change over time. Therefore, in the third embodiment, the sample and hold capacitor 802 is placed in a sample state at timing T304d when PC0R falls, thereby intentionally generating noise that changes over time.

[0073] As a result, the noise voltage generated by the constant current source 207 is clamped in the clamp capacitor 209, causing a "deviation" between the voltage clamped in the clamp capacitor 209 and the voltage (holding voltage) after the bias voltage is held. In this case, a voltage signal including the "deviation" is input to the AD conversion unit 104, and an N signal is obtained. Furthermore, since this "deviation" is based on random noise, it varies from pixel to pixel and from frame to frame. The control method for the image sensor of this embodiment varies the N signal from pixel to pixel and from frame to frame, thereby improving fixed pattern noise caused by quantization error.

[0074] When the set gain of the column amplifier unit 103 is 1, 2, or 4, biasS / H falls at T904b, which is after T304d, which is the falling timing of the signal pulse PC0R. In this case, a discrepancy occurs between the voltage clamped by the clamp capacitor 209 and the voltage after the bias voltage is held, which results in an improvement in fixed pattern noise.

[0075] If the set gain of the column amplifier unit 103 is 8x or greater, biasS / H is turned off at T904a before T304d. If the set gain is 8x or greater, the bias voltage is clamped after being held to ensure that it does not go outside the operating voltage range of the column amplifier unit 103. At this time, random noise components that depend on the gain setting are dominant, so fixed pattern noise components that do not depend on the gain setting do not affect image quality.

[0076] The above drive control method is one example, and various modifications can be made within the scope of the present invention in accordance with the design, characteristics and image quality of each individual image sensor.

[0077] [Fourth embodiment] A control method for an image sensor according to the fourth embodiment will be described below with reference to Figures 11 to 13. However, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0078] 11 is an equivalent circuit diagram of an image sensor according to the fourth embodiment. The equivalent circuit of the fourth embodiment differs from that of the first embodiment in that a gain switching function is added to the configuration of the pixel 105.

[0079] As shown in FIG. 11, the pixel 105 of the fourth embodiment includes a gain switching capacitor 1101 and a gain switching switch 1102.

[0080] The gain switching switch 1102 is driven by a signal pulse PFD to control the connection between the FD 203 and the gain switching capacitor 1101. When the signal pulse PFD is in the H state, the FD 203 is connected to the gain switching capacitor 1101, resulting in a high capacitance state and a low voltage level for the pixel signal. On the other hand, when the signal pulse PFD is in the L state, the FD 203 is disconnected from the gain switching capacitor 1101, resulting in a high voltage level for the pixel signal, making it possible to switch the gain. In the description of this embodiment, the gain ratio when the signal pulse PFD is in the L state compared to when it is in the H state is, for example, approximately 1.3 times.

[0081] 12 is a drive timing chart of the image sensor according to the fourth embodiment. The timing chart of the fourth embodiment differs from that of the first embodiment in that a signal pulse PFD is added.

[0082] During the period from T303 to T304d, the signal pulse PRES is in the L state and the signal pulse PC0R is in the H state, so that the pixel signal corresponding to the reset voltage level of the FD 203 is clamped in the clamp capacitor 209.

[0083] Fig. 13 is a control table for an image sensor according to the fourth embodiment. Fig. 13 shows a method for controlling the signal pulse PFD according to the set gain of the column amplifier unit 103. The fourth embodiment is characterized in that the waveform of the signal pulse PFD is controlled to change according to the set gain of the column amplifier unit 103.

[0084] The gain switch 1102 changes the capacitance of the FD 203, and therefore when the state changes from H to L or from L to H, the reset voltage level and kTC noise component of the pixel signal change. Therefore, in the fourth embodiment, the state of the signal pulse PFD is intentionally changed around the falling timing of the signal pulse PC0R that clamps the reset voltage level.

[0085] As a result, a "deviation" occurs between the voltage clamped by the clamp capacitor 209 and the voltage after the signal pulse PFD has changed. In this case, the voltage signal including the "deviation" is input to the AD conversion unit 104, and the N signal is obtained. Furthermore, since this "deviation" is based on random noise, it varies from pixel to pixel and from frame to frame. The control method for the image sensor of this embodiment varies the N signal from pixel to pixel and from frame to frame, thereby improving fixed pattern noise caused by quantization error.

[0086] If the gain is allocated so that AD conversion processing is performed with the signal pulse PFD in the H state when the set gain of the column amplifier unit 103 is 1x or 2x, the signal pulse PFD is set to the H state during periods T1204 to T309. Conversely, the signal pulse PFD is set to the L state during periods T301 to T1204. Note that T1204 is later than the above-mentioned T304d and earlier than T305.

[0087] If the gain is allocated so that AD conversion processing is performed with the signal pulse PFD in the L state when the set gain of the column amplifier unit 103 is 4 times, the signal pulse PFD is set to the L state during periods T1204 to T309. Conversely, the signal pulse PFD is set to the H state during periods T301 to T1204.

[0088] When the set gain is 1, 2, or 4, a difference occurs between the voltage clamped by the clamp capacitor 209 and the voltage after the signal pulse PFD has changed, and therefore, an improvement effect on fixed pattern noise can be obtained.

[0089] On the other hand, if the gain is allocated so that the signal pulse PFD performs AD conversion in the L state when the set gain of the column amplifier unit 103 is 8 times or more, the signal pulse PFD is set to the L state during periods T1204 to T309. The signal pulse PFD is also set to the L state during periods T301 to T1204.

[0090] When the set gain is 8 times or more, switching control of the signal pulse PFD is not performed to reliably avoid going outside the operating voltage range of the column amplifier unit 103. At this time, the random noise component that depends on the gain setting is dominant, so the fixed pattern noise component that does not depend on the gain setting does not affect the image quality.

[0091] [Other embodiments] While the present invention has been described in detail above based on preferred embodiments thereof, the present invention is not limited to these specific embodiments, and various modifications within the scope of the present invention are also included. Furthermore, parts of the above-described embodiments may be combined as appropriate. In particular, the drive control method of the above-described embodiment is merely an example, and various modifications are possible within the scope of the present invention in accordance with the design, characteristics, and image quality of each individual image sensor.

[0092] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions. [Explanation of symbols]

[0093] 100: Image sensor 101: Pixel section 102: Vertical scanning unit 103: Column amplifier section 104: AD conversion section 105: Pixels 106: Vertical signal line 201: Photoelectric conversion unit 203: Floating Diffusion 204: Reset switch 205: Source follower transistor 209: Clamp capacity 210: Clamp switch

Claims

1. a photoelectric conversion unit; a floating diffusion capable of holding charges generated in the photoelectric conversion unit; a first reset switch that resets the voltage of the floating diffusion; a source follower that outputs a pixel signal according to the voltage of the floating diffusion; a plurality of pixels arranged in a matrix, each having a Arranged for each pixel column, a vertical signal line connected to the source followers of the plurality of pixels; a clamp capacitor connected to the vertical signal line; a second reset switch for resetting the clamp capacitance; an inverting amplifier that, together with the clamp capacitor, constitutes a gain amplifier that amplifies an input voltage signal by a predetermined gain; an AD conversion circuit that performs AD conversion on the voltage signal output from the gain amplifier with a predetermined number of bits; and a column circuit having each of the A control method for an imaging element comprising: The time between the reset release timing by the first reset switch and the reset release timing by the second reset switch is changed according to any one of the set gain of the gain amplifier, the number of bits of the AD conversion circuit, and ISO sensitivity.

10. A method for controlling an imaging element, comprising:

2. The column circuitry includes: a column amplifier including the clamp capacitor; an AD conversion circuit that performs AD conversion on the output voltage of the column amplifier; Furthermore, the second reset switch is a switch that connects input and output of the column amplifier, The AD conversion circuit sequentially AD converts a pixel signal corresponding to a reset voltage level in the floating diffusion and a pixel signal corresponding to a voltage level obtained by adding the reset voltage level in the floating diffusion to the accumulated charge of the photoelectric conversion unit, thereby generating an N signal and an S signal.

2. The method for controlling an image pickup device according to claim 1.

3. The set value is an ISO sensitivity, The lower the ISO sensitivity, the shorter the time between the reset release timing by the first reset switch and the reset release timing by the second reset switch.

3. The method for controlling an image pickup device according to claim 1.

4. When the ISO sensitivity is smaller than a predetermined value, the reset release timing by the second reset switch is set earlier than the reset release timing by the first reset switch.

4. The method for controlling an image pickup device according to claim 3.

5. the set value is the number of bits of the AD conversion circuit, The smaller the number of bits, the shorter the time between the reset release timing by the first reset switch and the reset release timing by the second reset switch.

3. The method for controlling an image pickup device according to claim 1.

6. a photoelectric conversion unit; a floating diffusion capable of holding charges generated in the photoelectric conversion unit; a source follower that outputs a pixel signal according to the voltage of the floating diffusion; a plurality of pixels arranged in a matrix, each having a Arranged for each pixel column, a vertical signal line connected to the source followers of the plurality of pixels; a clamp capacitor connected to the vertical signal line; a reset switch for resetting the clamp capacitance; an inverting amplifier that, together with the clamp capacitor, constitutes a gain amplifier that amplifies an input voltage signal by a predetermined gain; and a column circuit having each of the The column circuitry includes: a transistor for supplying a current corresponding to a bias voltage to the vertical signal line; a sample and hold capacitor for holding the bias voltage; a sample-and-hold switch for switching between a sample state and a hold state of the sample-and-hold capacitor; A control method for an imaging element comprising: The timing at which the sample-hold switch is switched from the sample state to the hold state relative to the timing at which the reset switch is released from the reset state is changed in accordance with the gain setting value set in the gain amplifier.

10. A method for controlling an imaging element, comprising:

7. a photoelectric conversion unit; a floating diffusion capable of holding charges generated in the photoelectric conversion unit; a source follower that outputs a pixel signal according to the voltage of the floating diffusion; a gain switching capacitor connected to the floating diffusion; a gain switching switch connected to the floating diffusion and the gain switching capacitor for switching the capacitance of the floating diffusion; a plurality of pixels arranged in a matrix, each having a Arranged for each pixel column, a vertical signal line connected to the source followers of the plurality of pixels; a clamp capacitor connected to the vertical signal line; a reset switch for resetting the clamp capacitance; an inverting amplifier that, together with the clamp capacitor, constitutes a gain amplifier that amplifies an input voltage signal by a predetermined gain; and a column circuit having each of the A control method for an imaging element comprising: The timing of switching the gain changeover switch relative to the timing of reset release by the reset switch is changed in accordance with the gain setting value set in the gain amplifier.

10. A method for controlling an imaging element, comprising:

8. The column circuit further includes a CDS processing unit.

8. The method for controlling an imaging device according to claim 1.

9. The imaging device is controlled by the control method of any one of claims 1 to 8. An imaging device characterized by:

10. A method for controlling an image pickup device according to any one of claims 1 to 8, A program characterized by:

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