Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device capable of improving a surge current tolerance.SOLUTION: A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes an n-type first silicon carbide region having a first portion contacting a first plane, a p-type second silicon carbide region, an n-type third silicon carbide region, and a gate electrode. The diode region includes the n-type first silicon carbide region having a second portion in contact with the first plane and a p-type fourth silicon carbide region. The semiconductor device includes gate wiring electrically connected to the gate electrode. A distance between a high-concentration portion included in the fourth silicon carbide region and the gate wiring is larger than a distance between a high-concentration portion included in the second silicon carbide region and the gate wiring.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. By utilizing these properties, it is possible to realize, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that have high breakdown voltage, low loss, and can operate at high temperatures.

[0003] Vertical MOSFETs using silicon carbide have a built-in pn junction diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the built-in diode allows a freewheeling current to flow even when the MOSFET is off.

[0004] However, when a body diode is used to pass a return current, stacking faults grow in the silicon carbide layer due to carrier recombination energy, which increases the on-resistance of the MOSFET. An increase in the on-resistance of the MOSFET reduces the reliability of the MOSFET. For example, by incorporating a unipolar Schottky Barrier Diode (SBD) as a built-in diode in the MOSFET, it is possible to suppress the growth of stacking faults in the silicon carbide layer. The incorporation of an SBD as a built-in diode in the MOSFET improves the reliability of the MOSFET.

[0005] A large surge current may momentarily flow through a MOSFET, exceeding the steady state. When a large surge current flows, a large surge voltage is applied, generating heat and destroying the MOSFET. The maximum allowable peak current value (I FSM) is called surge current capability. It is desirable to improve the surge current capability of MOSFETs equipped with SBDs. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2022-9745 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device with improved surge current resistance. [Means for solving the problem]

[0008] A semiconductor device according to an embodiment includes a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region, wherein the plurality of transistor regions are a silicon carbide layer having a first surface and a second surface opposite to the first surface, the plurality of transistor regions including an n-type first silicon carbide region having a plurality of first portions in contact with the first surface, a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, the p-type second silicon carbide region having a first low concentration portion and a second low concentration portion provided between the first low concentration portion and the first surface, a silicon carbide layer including a second silicon carbide region having a first high concentration portion having a p-type impurity concentration higher than that of the first low concentration portion, and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode facing the second silicon carbide region; and a gate insulating layer provided between the gate electrode and the second silicon carbide region, the silicon carbide layer including: the first silicon carbide region of n type having a plurality of second portions in contact with a first surface; and a fourth silicon carbide region of p type provided between the first silicon carbide region and the first surface, the fourth silicon carbide region having a second low concentration portion and a second high concentration portion provided between the second low concentration portion and the first surface and having a p-type impurity concentration higher than that of the second low concentration portion; the first electrode in contact with the plurality of second portions and the fourth silicon carbide region; and the second electrode, a gate electrode pad provided on a side of the first surface and electrically connecting the gate electrode pad and the gate electrode, and extending in a first direction parallel to the first surface, wherein an occupation area per unit area of ​​the fourth silicon carbide region projected onto the first surface is larger than an occupation area per unit area of ​​the second silicon carbide region projected onto the first surface, and a first diode region which is one of the at least one diode region has a first transistor region which is one of the plurality of transistor regions, anda second transistor region that is one of the plurality of transistor regions provided in the first direction, and a distance in a second direction parallel to the first surface and perpendicular to the first direction between the second heavily doped portion in the first diode region and the gate wiring is greater than a distance in the second direction between the first heavily doped portion in the first transistor region and the gate wiring; [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 5] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 6] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 7] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 8] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 9] FIG. 2 is a schematic top view of a semiconductor device according to a first comparative example. [Figure 10] FIG. 2 is an equivalent circuit diagram of a semiconductor device of a first comparative example. [Figure 11] FIG. 2 is an equivalent circuit diagram of a semiconductor device of a first comparative example. [Figure 12] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second comparative example. [Figure 14] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 15] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 16] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 17] FIG. 10 is a schematic top view of a semiconductor device according to a third comparative example. [Figure 18] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third comparative example. [Figure 19] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third comparative example. [Figure 20] FIG. 10 is an explanatory diagram of a problem of the semiconductor device of the third comparative example. [Figure 21] FIG. 10 is an explanatory diagram of a problem of the semiconductor device of the third comparative example. [Figure 22] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 23] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 24] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 25] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 26] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 27] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 28] FIG. 10 is a schematic diagram of a drive device according to a fifth embodiment. [Figure 29] FIG. 10 is a schematic diagram of a vehicle according to a sixth embodiment. [Figure 30] FIG. 13 is a schematic diagram of a vehicle according to a seventh embodiment. [Figure 31] FIG. 13 is a schematic diagram of an elevator according to an eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described may be omitted as appropriate.

[0011] In the following description, n + , n, n - and p + , p, p - When the notation is used, the notation indicates the relative level of impurity concentration in each conductivity type.+ has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0012] The impurity concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the carrier concentration determined, for example, by scanning capacitance microscopy (SCM). The depth, thickness, and other distances of the impurity regions can be determined, for example, by SIMS. The depth, thickness, width, and spacing of the impurity regions can also be determined, for example, from a composite image of an SCM image and an atomic force microscope (AFM) image.

[0013] In this specification, the impurity concentration of a semiconductor region means the maximum impurity concentration of the semiconductor region, unless otherwise specified.

[0014] (First embodiment) The semiconductor device of the first embodiment includes a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region. The plurality of transistor regions are a silicon carbide layer having a first surface and a second surface opposite to the first surface, the plurality of transistor regions including an n-type first silicon carbide region having a plurality of first portions in contact with the first surface, a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, the first low concentration portion, and a first high concentration portion provided between the first low concentration portion and the first surface and having a p-type impurity concentration higher than that of the first low concentration portion. the first surface includes a silicon carbide layer including a second silicon carbide region having a plurality of first portions, an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode facing the second silicon carbide region; and a gate insulating layer provided between the gate electrode and the second silicon carbide region. The at least one diode region includes a silicon carbide layer including: an n-type first silicon carbide region having a plurality of second portions in contact with the first surface; a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, the fourth silicon carbide region having a second low concentration portion and a second high concentration portion provided between the second low concentration portion and the first surface and having a p-type impurity concentration higher than that of the second low concentration portion; a first electrode in contact with the plurality of second portions and the fourth silicon carbide region; and a second electrode. The peripheral region includes the silicon carbide layer, a gate electrode pad provided on the first surface side of the silicon carbide layer, and a gate wiring electrically connecting the gate electrode pad and the gate electrode and extending in a first direction parallel to the first surface. The area per unit area of ​​the fourth silicon carbide region projected onto the first surface is larger than the area per unit area of ​​the second silicon carbide region projected onto the first surface. Also, a first diode region which is one of the at least one diode region is provided between a first transistor region which is one of the plurality of transistor regions and a second transistor region which is one of the plurality of transistor regions provided in a first direction relative to the first transistor region.The distance in a second direction parallel to the first surface and perpendicular to the first direction between the second heavily doped portion in the first diode region and the gate wiring is greater than the distance in the second direction between the first heavily doped portion in the first transistor region and the gate wiring.

[0015] The semiconductor device of the first embodiment is a planar gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is, for example, a double implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation. The semiconductor device of the first embodiment also includes an SBD (Shottky Barrier Diode) as a built-in diode. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0016] 1(a) and 1(b) are schematic top views of a semiconductor device according to a first embodiment. Fig. 1(a) is a layout diagram of each region included in a MOSFET 100. Fig. 1(b) is a diagram showing electrode and wiring patterns on the top surface of the MOSFET 100.

[0017] 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line AA' in FIG.

[0018] 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line BB' in FIG.

[0019] 4(a) and 4(b) are schematic cross-sectional views of the semiconductor device of the first embodiment. Fig. 4(a) is a cross-sectional view taken along CC' in Fig. 1(a). Fig. 4(b) is a cross-sectional view taken along DD' in Fig. 1(a).

[0020] As shown in FIG. 1(a), the MOSFET 100 includes a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, a diode region 102a (first diode region), a diode region 102b, and a peripheral region 103. The transistor region 101a is an example of the first transistor region. The transistor region 101b is an example of the second transistor region. The diode region 102a is an example of the first diode region.

[0021] Hereinafter, the transistor region 101a, the transistor region 101b, the transistor region 101c, and the transistor region 101d may be individually or collectively referred to simply as the transistor region 101. Furthermore, the diode region 102a and the diode region 102b may be individually or collectively referred to simply as the diode region 102.

[0022] A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

[0023] The peripheral region 103 surrounds the transistor region 101 and the diode region 102. In the peripheral region 103, a gate electrode pad 22 and a gate wiring 24 are provided.

[0024] The peripheral region 103 is provided with, for example, a termination structure that improves the breakdown voltage of the MOSFET 100. The termination structure that improves the breakdown voltage of the MOSFET 100 is, for example, a resurf structure or a guard ring.

[0025] The diode region 102 is provided between two transistor regions 101. For example, the diode region 102a is provided between the transistor region 101a and the transistor region 101b. The transistor region 101b is provided in a first direction parallel to the first plane P1 relative to the transistor region 101a.

[0026] For example, the diode region 102b is provided between the transistor region 101c and the transistor region 101d. The transistor region 101d is provided in a first direction relative to the transistor region 101c.

[0027] The width of the diode region 102 in the first direction is, for example, 30 μm or more. For example, the width of the diode region 102a in the first direction is 30 μm or more.

[0028] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, a gate wiring 24, and a substrate insulating layer 40.

[0029] In the silicon carbide layer 10, n + a drain region 26 (fifth silicon carbide region), - a p-type drift region 28 (first silicon carbide region), a p-type body region 30 (second silicon carbide region), a p-type p region 32 (fourth silicon carbide region), + Included are an n-type source region 34 (third silicon carbide region), an n-type first bottom region 36, and an n-type second bottom region 38.

[0030] The drift region 28 includes a plurality of first portions 28 a and a plurality of second portions 28 b. The body region 30 includes a first lightly doped portion 30 a and a first heavily doped portion 30 b. The p region 32 includes a second lightly doped portion 32 a and a second heavily doped portion 32 b.

[0031] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H—SiC.

[0032] Silicon carbide layer 10 has a first surface ("P1" in FIG. 2) and a second surface ("P2" in FIG. 2). First surface P1 and second surface P2 are opposed to each other. Hereinafter, the first surface may be referred to as the front surface, and the second surface may be referred to as the back surface. Hereinafter, "depth" refers to the depth relative to the first surface.

[0033] The first plane P1 is, for example, a plane tilted at an angle of 0 to 8 degrees with respect to the (0001) plane. The second plane P2 is, for example, a plane tilted at an angle of 0 to 8 degrees with respect to the (000-1) plane. The (0001) plane is called a silicon plane. The (000-1) plane is called a carbon plane.

[0034] n + The n-type drain region 26 is provided on the back surface side of the silicon carbide layer 10. The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 26 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0035] n - A drift region 28 of the type is provided between the drain region 26 and the first plane P1. The drift region 28 is provided between the source electrode 12 and the drain electrode 14. The drift region 28 is provided between the gate electrode 18 and the drain electrode 14.

[0036] The drift region 28 is provided on the drain region 26. The drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 28 is lower than the n-type impurity concentration of the drain region 26. The n-type impurity concentration of the drift region 28 is, for example, 4×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the drift region 28 is, for example, not less than 5 μm and not more than 150 μm.

[0037] The drift region 28 includes a plurality of first portions 28a and a plurality of second portions 28b. The first portions 28a contact the first plane P1. The first portions 28a are sandwiched between two body regions 30. The first portions 28a function as n-type semiconductor regions of the SBD. The first portions 28a extend, for example, in the second direction.

[0038] The second portion 28b contacts the first plane P1. The second portion 28b is sandwiched between two p-regions 32. The second portion 28b functions as an n-type semiconductor region of the SBD.

[0039] The p-type body region 30 is provided between the drift region 28 and the first face P1. A part of the body region 30 functions as a channel region of the MOSFET 100. The body region 30 functions as a p-type semiconductor region of the pn junction diode.

[0040] The body region 30 includes a first low concentration portion 30a and a first high concentration portion 30b. The first high concentration portion 30b is provided between the first low concentration portion 30a and the first plane P1. The p-type impurity concentration of the first high concentration portion 30b is higher than the p-type impurity concentration of the first low concentration portion 30a.

[0041] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the first low-concentration portion 30a is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The p-type impurity concentration of the first high concentration portion 30b is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The first high concentration portion 30b extends, for example, in the second direction.

[0042] The depth of the body region 30 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0043] The body region 30 is fixed to the potential of the source electrode 12 .

[0044] The p-type p region 32 is provided between the drift region 28 and the first face P1. The p region 32 functions as a p-type semiconductor region of the pn junction diode.

[0045] The p-region 32 includes a second low-concentration portion 32a and a second high-concentration portion 32b. The second high-concentration portion 32b is provided between the second low-concentration portion 32a and the first plane P1. The p-type impurity concentration of the second high-concentration portion 32b is higher than the p-type impurity concentration of the second low-concentration portion 32a.

[0046] The p-type region 32 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the second low-concentration portion 32a is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The p-type impurity concentration of the second high concentration portion 32b is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0047] The p-type impurity concentration of the second low concentration portion 32 a of the p-region 32 is, for example, substantially equal to the p-type impurity concentration of the first low concentration portion 30 a of the body region 30 .

[0048] The p-type impurity concentration of the second heavily doped portion 32 b of the p-region 32 is, for example, substantially equal to the p-type impurity concentration of the first heavily doped portion 30 b of the body region 30 .

[0049] The width in the first direction of the p region 32 is, for example, larger than the width in the first direction of the body region 30. The depth of the p region 32 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0050] The p-region 32 is fixed to the potential of the source electrode 12 .

[0051] n +The n-type source region 34 is provided between the body region 30 and the first plane P1. The source region 34 is provided between the first low concentration portion 30a of the body region 30 and the first plane P1. + The source region 34 of the type extends, for example, in the second direction.

[0052] The source region 34 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 34 is higher than the n-type impurity concentration of the drift region 28.

[0053] The n-type impurity concentration of the source region 34 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The depth of the source region 34 is shallower than the depth of the body region 30. The depth of the source region 34 is, for example, not less than 0.1 μm and not more than 0.3 μm.

[0054] The n-type first bottom region 36 is provided between the drift region 28 and the body region 30. The first bottom region 36, for example, contacts the drift region 28 and the body region 30. The width of the first bottom region 36 in the first direction is, for example, substantially the same as the width of the body region 30 in the first direction.

[0055] The first bottom region 36 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the first bottom region 36 is higher than the n-type impurity concentration of the drift region 28.

[0056] The n-type impurity concentration of the first bottom region 36 is, for example, 1×10 16 cm -3 Over 2×10 17 cm -3 The thickness of the first bottom region 36 is, for example, not less than 0.4 μm and not more than 1.5 μm.

[0057] The n-type second bottom region 38 is provided between the drift region 28 and the p region 32. The second bottom region 38 is in contact with, for example, the drift region 28 and the p region 32. The width of the second bottom region 38 in the first direction is, for example, substantially the same as the width of the p region 32 in the first direction.

[0058] The second bottom region 38 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the second bottom region 38 is higher than the n-type impurity concentration of the drift region 28. The n-type impurity concentration of the second bottom region 38 is, for example, substantially the same as the n-type impurity concentration of the first bottom region 36.

[0059] The n-type impurity concentration of the second bottom region 38 is, for example, 1×10 16 cm -3 Over 2×10 17 cm -3 The thickness of the second bottom region 38 is, for example, not less than 0.4 μm and not more than 1.5 μm.

[0060] The gate electrode 18 is provided on the first face P1 side of the silicon carbide layer 10. The gate electrode 18 extends in a second direction that is parallel to the first face P1 and perpendicular to the first direction. A plurality of gate electrodes 18 are arranged parallel to each other in the first direction. The gate electrodes 18 have a so-called stripe shape.

[0061] The gate electrode 18 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0062] The gate electrode 18 faces, for example, a portion of the body region 30 that contacts the first face P1. The gate electrode 18 faces, for example, a portion of the drift region 28 that contacts the first face P1.

[0063] The gate insulating layer 16 is provided between the gate electrode 18 and the body region 30. The gate insulating layer 16 is provided between the gate electrode 18 and the drift region .

[0064] The gate insulating layer 16 is made of, for example, silicon oxide. For example, a high-k insulating material (high dielectric constant insulating material) can be used for the gate insulating layer 16.

[0065] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 has a function of electrically isolating the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is made of, for example, silicon oxide.

[0066] The source electrode 12 is provided on the first face P1 side of the silicon carbide layer 10. The source electrode 12 is in contact with the first face P1.

[0067] The source electrode 12 contacts a first portion 28 a of the drift region 28 , a second portion 28 b of the drift region 28 , the body region 30 , the p-region 32 , and the source region 34 .

[0068] The source electrode 12 has a first region 12a in the transistor region 101 and a second region 12b in the diode region 102.

[0069] The source electrode 12 includes a metal, and the metal forming the source electrode 12 has a laminated structure of, for example, titanium (Ti) and aluminum (Al).

[0070] Portions of the source electrode 12 in contact with the body region 30, the p region 32, and the source region 34 are made of, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. Portions of the source electrode 12 in contact with the first portion 28a of the drift region 28 and the second portion 28b of the drift region 28 are not provided with, for example, a metal silicide.

[0071] The junctions between the body region 30, the p region 32, and the source region 34 and the source electrode 12 are, for example, ohmic junctions. The junctions between the first portion 28a of the drift region 28 and the second portion 28b of the drift region 28 and the source electrode 12 are, for example, Schottky junctions.

[0072] The drain electrode 14 is provided on the second face P2 side of the silicon carbide layer 10. The drain electrode 14 is in contact with the second face P2. The drain electrode 14 is in contact with the drain region 26.

[0073] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound, and includes at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0074] The junction between the drain region 26 and the drain electrode 14 is, for example, an ohmic junction.

[0075] The gate electrode pad 22 is provided on the first face P1 side of the silicon carbide layer 10. The gate electrode pad 22 is provided on the interlayer insulating layer 20. The gate electrode pad 22 is provided to realize electrical connection between the gate electrode 18 and the outside.

[0076] The gate wiring 24 is provided on the first face P1 side of the silicon carbide layer 10. The gate wiring 24 is connected to the gate electrode pad 22. The gate wiring 24 is electrically connected to the gate electrode 18.

[0077] A portion of the gate wiring 24 extends in a first direction parallel to the first plane P1, and a portion of the gate wiring 24 extends in a second direction parallel to the first plane P1 and perpendicular to the first direction.

[0078] The gate electrode pad 22 and the gate wiring 24 contain a metal. The metal forming the gate electrode pad 22 and the gate wiring 24 has a laminated structure of, for example, titanium (Ti) and aluminum (Al). The gate electrode pad 22 and the gate wiring 24 are formed of, for example, the same metal material as the source electrode 12.

[0079] The gate wiring 24 between the two source electrodes 12 extends in a first direction. The source electrode 12 is sandwiched between the two gate wirings 24 extending in the first direction. The source electrode 12 is sandwiched between the two gate wirings 24 extending in a second direction.

[0080] 2, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The silicon carbide layer 10 of the transistor region 101 includes n + a drain region 26 (fifth silicon carbide region), - a p-type drift region 28 (first silicon carbide region), a p-type body region 30 (second silicon carbide region), + The transistor region 101 includes an n-type source region 34 (third silicon carbide region), and an n-type first bottom region 36. The drift region 28 of the transistor region 101 also includes a plurality of first portions 28a.

[0081] In the transistor region 101, the source electrode 12, the first portion 28a of the drift region 28, the drain region 26, and the drain electrode 14 form an SBD. Also, the source electrode 12, the body region 30, the first bottom region 36, the drain region 26, and the drain electrode 14 form a pn junction diode.

[0082] The first distance (d1 in FIGS. 4(a) and 4(b)) between two adjacent first portions 28a with the body region 30 sandwiched therebetween is, for example, not less than 3 μm and not more than 30 μm.

[0083] 3, the diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). + a drain region 26 (fifth silicon carbide region), - The diode region 102 includes a n-type drift region 28 (first silicon carbide region), a p-type p region 32 (fourth silicon carbide region), and an n-type second bottom region 38. The drift region 28 of the diode region 102 also includes a plurality of second portions 28b.

[0084] In the diode region 102, the source electrode 12, the second portion 28b of the drift region 28, the drain region 26, and the drain electrode 14 form an SBD. Also, the source electrode 12, the p region 32, the second bottom region 38, the drain region 26, and the drain electrode 14 form a pn junction diode.

[0085] The second distance (d2 in FIGS. 4(a) and 4(b)) between two adjacent second portions 28b with the p region 32 therebetween is, for example, not less than 3 μm and not more than 30 μm. The second distance d2 between two adjacent second portions 28b with the p region 32 therebetween is, for example, substantially equal to the first distance d1 between two adjacent first portions 28a with the body region 30 therebetween. The first distance d1 and the second distance d2 are distances in a first direction.

[0086] Fig. 5 is a schematic top view of the semiconductor device of the first embodiment. Fig. 5 is a diagram showing the pattern of the body region 30 projected onto the first surface P1 and the pattern of the p region 32 projected onto the first surface P1. The patterns of the body region 30 and the p region 32 in Fig. 5 are patterns projected onto the first surface P1 in a direction perpendicular to the first surface P1.

[0087] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. In other words, in an area of ​​a predetermined size, the occupancy rate of the p region 32 projected onto the first surface P1 is greater than the occupancy rate of the body region 30 projected onto the first surface P1. The occupancy rates are the occupancy rates of the transistor region 101 and the diode region 102 projected onto the first surface P1. In other words, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0088] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is, for example, 1.2 to 3 times the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1.

[0089] The unit area is not particularly limited as long as it is a size that allows comparison of the average occupancy rate of the body region 30 in the transistor region 101 and the average occupancy rate of the p region 32 in the diode region 102. The unit area is, for example, 30 μm×30 μm=900 μm 2 is.

[0090] Furthermore, the contact area per unit area between the source electrode 12 and the p region 32 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the p region 32 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0091] Fig. 6 is a schematic top view of the semiconductor device of the first embodiment. Fig. 6 is a pattern diagram of each region provided in the silicon carbide layer 10 of the MOSFET 100. Fig. 6 is a diagram showing the pattern of each region on the first surface P1 of the MOSFET 100. Fig. 6 shows region X in Fig. 1(a).

[0092] As shown in FIG. 6, the position of the end (E2 in FIG. 6) in the second direction of the second high-concentration portion 32b is shifted in the second direction by an amount ΔS from the position of the end (E1 in FIG. 6) in the second direction of the first high-concentration portion 30b.

[0093] 7 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line EE' of FIG.

[0094] 8 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line FF' in FIG.

[0095] The substrate insulating layer 40 is provided in the peripheral region 103. The substrate insulating layer 40 is provided on the silicon carbide layer 10. The substrate insulating layer 40 has a function of electrically isolating the gate electrode 18 and the silicon carbide layer 10 from each other.

[0096] The substrate insulating layer 40 includes, for example, an oxide, and is, for example, silicon oxide.

[0097] The gate electrode 18 is provided on the substrate insulating layer 40. The gate electrode 18 on the substrate insulating layer 40 extends, for example, in a first direction.

[0098] The gate wiring 24 is provided on the gate electrode 18. The gate wiring 24 is in contact with the gate electrode 18. The gate wiring 24 is electrically connected to the gate electrode 18. The gate wiring 24 extends, for example, in a first direction.

[0099] The distance in the second direction (dy in FIG. 7) between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 is greater than the distance in the second direction (dx in FIG. 8) between the first high-concentration portion 30b in the first transistor region 101a and the gate wiring 24.

[0100] The distance dy in the second direction between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 is, for example, at least twice the distance dx in the second direction between the first high-concentration portion 30b in the first transistor region 101a and the gate wiring 24.

[0101] The distance dy in the second direction between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 is, for example, equal to or greater than the distance (dt in FIG. 7) between the drain region 26 and the first plane P1.

[0102] The distance dy in the second direction between the second high concentration portion 32b in the first diode region 102a and the gate wiring 24 is, for example, 10 μm or more.

[0103] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0104] 9(a) and 9(b) are schematic top views of a semiconductor device of a first comparative example. FIG. 9(a) is a layout diagram of each region included in a MOSFET 901 of the first comparative example. FIG. 9(b) is a diagram showing electrode and wiring patterns on the top surface of the MOSFET 901 of the first comparative example. FIGS. 9(a) and 9(b) correspond to FIGS. 1(a) and 1(b) of the first embodiment.

[0105] Fig. 10 is a schematic cross-sectional view of a semiconductor device of a first comparative example. Fig. 10 is a cross-sectional view taken along line GG' in Fig. 9(a). Fig. 10 is a view corresponding to Fig. 4(a) of the first embodiment.

[0106] The MOSFET 901 of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not include the diode region 102.

[0107] The transistor region 101 of the MOSFET of the first comparative example is provided with a MOSFET and an SBD, similar to the MOSFET 100 of the first embodiment.

[0108] 11 is an equivalent circuit diagram of the semiconductor device of the first comparative example. A pn ​​junction diode and an SBD are connected as built-in diodes between a source electrode 12 and a drain electrode 14 in parallel with the transistor.

[0109] For example, consider a case where MOSFET 901 is used as a switching element connected to an inductive load. When MOSFET 901 is off, a load current caused by the inductive load may apply a voltage to source electrode 12 that is positive with respect to drain electrode 14. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0110] The forward voltage (Vf) at which forward current begins to flow through the SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, forward current initially flows through the SBD.

[0111] The forward voltage (Vf) of the SBD is, for example, 1.0 V. The forward voltage (Vf) of the pn junction diode is, for example, 2.5 V.

[0112] The SBD operates in a unipolar manner, so that stacking faults do not grow in silicon carbide layer 10 due to carrier recombination energy even when a forward current flows.

[0113] 12(a) and 12(b) are explanatory diagrams illustrating the operation and effect of the semiconductor device of the first embodiment. 12(a) and 12(b) are schematic cross-sectional views of a first comparative example. 12(a) and 12(b) are diagrams corresponding to FIG. 10.

[0114] 12(a) and 12(b) are diagrams showing the current flowing through the built-in diode of the MOSFET 901 of the first comparative example. Fig. 12(a) shows a state in which a forward current flows only through the SBD, and Fig. 12(b) shows a state in which a forward current flows through the SBD and the pn junction diode.

[0115] 12(a) shows a state in which the voltage applied across the pn junction of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode, and FIG. 12(b) shows a state in which the voltage applied across the pn junction of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0116] 12(a) and 12(b), the dotted arrows indicate the current flowing through the SBD, and in Fig. 12(b), the solid arrows indicate the current flowing through the pn junction diode.

[0117] 12(a), the current flowing through the SBD flows around to the bottom of the body region 30. This causes a leakage of electrostatic potential to the drift region 28 facing the bottom of the body region 30. This leakage of electrostatic potential reduces the voltage applied between the body region 30 and the drift region 28.

[0118] Therefore, the forward voltage (Vf) of the pn junction diode is less likely to be exceeded at the bottom of the body region 30. In other words, the forward voltage (Vf) of the pn junction diode of the MOSFET 901 of the first comparative example can be made higher than when an SBD is not provided. Therefore, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 10 due to carrier recombination energy is suppressed.

[0119] The forward voltage (Vf) of the pn junction diode of the MOSFET 901 of the first comparative example depends on the distance between two SBDs adjacent to each other in the first direction. By reducing the distance between two SBDs adjacent to each other in the first direction, the forward voltage (Vf) of the pn junction diode of the MOSFET 901 of the first comparative example can be increased.

[0120] A large surge current exceeding the steady state may be momentarily applied to a MOSFET, and the surge current flows from the source electrode 12 to the drain electrode 14.

[0121] When a large surge current flows, a large surge voltage is applied, generating heat and destroying the MOSFET. The maximum allowable peak current value of the surge current allowed for a MOSFET (I FSM ) is called surge current capability. It is desirable to improve the surge current capability of MOSFETs equipped with SBDs.

[0122] When a large surge voltage is applied to the MOSFET 901 of the first comparative example, the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode.

[0123] When the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, a current also flows through the pn junction diode, as shown in FIG. 12(b).

[0124] Fig. 13 is a schematic cross-sectional view of a semiconductor device of the second comparative example, which corresponds to Fig. 10 of the first comparative example.

[0125] The MOSFET 902 of the second comparative example differs from the MOSFET 901 of the first comparative example in that the transistor region does not include an SBD. The built-in diode of the MOSFET 902 of the second comparative example is only a pn junction diode.

[0126] 14 is an explanatory diagram of the operation and effect of the semiconductor device of Embodiment 1. FIG. 14 is a diagram showing voltage-current characteristics of the built-in diodes of a MOSFET 901 of the first comparative example and a MOSFET 902 of the second comparative example.

[0127] 14, in the MOSFET 902 of the second comparative example, a current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf2 of the pn junction diode is applied. On the other hand, in the MOSFET 901 of the first comparative example, a current flows through the SBD until a forward voltage Vf1 of the pn junction diode is applied. In the MOSFET 901 of the first comparative example, a current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf1 of the pn junction diode is applied.

[0128] The MOSFET 901 of the first comparative example operates in a unipolar manner up to a forward voltage Vf1, and therefore the gradient of the current increase is smaller than that of the MOSFET 902 of the second comparative example. Therefore, the maximum allowable peak current value I FSM 2, the maximum allowable peak current value I FSM 1 becomes smaller. In other words, the surge current withstand capability of the MOSFET 901 of the first comparative example becomes smaller than the surge current withstand capability of the MOSFET 902 of the second comparative example.

[0129] The MOSFET 903 of the third comparative example differs from the MOSFET 100 of the first embodiment only in that the end of the second direction of the second high-concentration portion 32b coincides with the end of the first high-concentration portion 30b in the second direction in position in the second direction.

[0130] The MOSFET 903 of the third comparative example includes a diode region 102 provided between transistor regions 101, similar to the MOSFET 100 of the first embodiment. The MOSFET 903 of the third comparative example has an improved surge current resistance due to the inclusion of the diode region 102. This will be described in detail below.

[0131] 15(a) and 15(b) are explanatory diagrams illustrating the operation and effect of the semiconductor device of the first embodiment. 15(a) and 15(b) are schematic cross-sectional views of a MOSFET 903 of a third comparative example. 15(a) and 15(b) correspond to FIG. 4(a).

[0132] 15(a) and 15(b) are diagrams showing the current flowing through the built-in diode of the MOSFET 903 of the third comparative example. Fig. 15(a) shows a state in which a forward current flows only through the SBD, and Fig. 15(b) shows a state in which a forward current flows through the SBD and the pn junction diode.

[0133] 15(a) shows a state in which the voltage applied across the pn junction of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode, and FIG. 15(b) shows a state in which the voltage applied across the pn junction of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0134] 15(a) and 15(b), the dotted arrows indicate the current flowing through the SBD, and in Fig. 15(b), the solid arrows indicate the current flowing through the pn junction diode.

[0135] In the diode region 102, the second distance d2 between two adjacent second portions 28b with the p region 32 therebetween is substantially equal to the first distance d1 between two adjacent first portions 28a with the body region 30 therebetween in the transistor region 101. In other words, in the diode region 102, the second portions 28b are provided at the same intervals as the first portions 28a in the transistor region 101. In yet other words, in the diode region 102, the SBD regions are provided at the same intervals as those in the transistor region 101.

[0136] 15(a), in the diode region 102, the current flowing through the SBD flows around to the bottom of the p region 32. This makes it difficult for the current to exceed the forward voltage (Vf) of the pn junction diode at the bottom of the p region 32. The forward voltage (Vf) of the pn junction diode in the diode region 102 becomes higher due to the presence of the SBD region.

[0137] When the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, a current also flows through the pn junction diode, as shown in FIG. 15(b).

[0138] In the MOSFET 903 of the third comparative example, the occupancy rate per unit area of ​​the p region 32 projected onto the first plane P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first plane P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0139] Furthermore, the contact area per unit area between the source electrode 12 and the p region 32 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the p region 32 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0140] Therefore, the current flowing through the pn junction diode in the diode region 102 is larger than the current flowing through the pn junction diode in the transistor region 101 .

[0141] Furthermore, a large current flows through the pn junction diode of the diode region 102, which causes carrier propagation and heat propagation to the adjacent transistor region 101. This promotes conductivity modulation in the transistor region 101 adjacent to the diode region 102. This increases the current flowing through the pn junction diode of the transistor region 101 adjacent to the diode region 102.

[0142] 16 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, showing the voltage-current characteristics of the built-in diodes of a MOSFET 901 of the first comparative example, a MOSFET 902 of the second comparative example, and a MOSFET 903 of the third comparative example.

[0143] 16, in the MOSFET 903 of the third comparative example, a current flows through the SBD until a forward voltage Vf3 of the pn junction diode is applied. In the MOSFET 903 of the third comparative example, when a voltage equal to or greater than the forward voltage Vf3 of the pn junction diode is applied, a current flows through the pn junction diode.

[0144] In the diode region 102 of the MOSFET 903 of the third comparative example, SBD regions are provided at the same intervals as those in the transistor region 101. Therefore, the forward voltage Vf3 of the pn junction diode of the MOSFET 903 of the third comparative example is equivalent to the forward voltage Vf1 of the pn junction diode of the MOSFET of the first comparative example.

[0145] On the other hand, the current after exceeding the forward voltage Vf3 of the pn junction diode in the MOSFET 903 of the third comparative example is larger than the current after exceeding the forward voltage Vf1 of the pn junction diode in the MOSFET 901 of the first comparative example. This is because the current flowing through the pn junction diode in the diode region 102 and the pn junction diode in the transistor region 101 adjacent to the diode region 102 is larger than that in the MOSFET 901 of the first comparative example.

[0146] The current increases after exceeding the forward voltage Vf3 of the pn junction diode, and the maximum allowable peak current value I FSM 3 is the maximum allowable peak current value I of the MOSFET 903 of the third comparative example. FSM 1. In other words, the surge current withstand capability of the MOSFET 903 of the third comparative example is greater than the surge current withstand capability of the MOSFET 903 of the third comparative example.

[0147] As described above, the MOSFET 903 of the third comparative example has the diode region 102 provided between the transistor regions 101, thereby improving the surge current resistance.

[0148] The occupancy rate per unit area of ​​the p region 32 projected onto the first plane P1 is preferably 1.2 to 3 times the occupancy rate per unit area of ​​the body region 30 projected onto the first plane P1. Exceeding the lower limit further improves surge current resistance. Keeping the occupancy rate below the upper limit suppresses a decrease in forward voltage Vf3, thereby suppressing a decrease in reliability.

[0149] Fig. 17 is a schematic top view of a semiconductor device of a third comparative example. Fig. 17 is a pattern diagram of each region included in silicon carbide layer 10 of MOSFET 903. Fig. 17 is a diagram showing the pattern of each region on first face P1 of MOSFET 903. Fig. 17 is a diagram corresponding to Fig. 6 of the first embodiment.

[0150] As shown in FIG. 17, the position of the end of the second direction of the second high-concentration portion 32b (E2 in FIG. 17) coincides with the position of the end of the first high-concentration portion 30b in the second direction (E1 in FIG. 17).

[0151] Fig. 18 is a schematic cross-sectional view of a semiconductor device of a third comparative example, which corresponds to Fig. 7 of the first embodiment.

[0152] Fig. 19 is a schematic cross-sectional view of a semiconductor device of a third comparative example, which corresponds to Fig. 8 of the first embodiment.

[0153] The distance in the second direction between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 (dy' in Figure 18) is equal to the distance in the second direction between the first high-concentration portion 30b in the first transistor region 101a and the gate wiring 24 (dx' in Figure 19).

[0154] The MOSFET 903 of the third comparative example differs from the MOSFET 100 of the first embodiment only in that the distance in the second direction (dy' in FIG. 18) between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 is equal to the distance in the second direction (dx' in FIG. 19) between the first high-concentration portion 30b in the first transistor region 101a and the gate wiring 24.

[0155] 20(a), 20(b), and 21 are explanatory diagrams of the problems of the semiconductor device of the third comparative example. 20(a) and 20(b) correspond to FIGS. 1(a) and 1(b) of the first embodiment. 21 corresponds to FIG. 18.

[0156] As described above, the MOSFET 903 of the third comparative example has an improved surge current resistance due to the diode region 102 provided between the transistor regions 101. However, the MOSFET 903 of the third comparative example has a problem in that the surge current resistance varies greatly from chip to chip. In other words, there is a problem in that a chip with a low surge current resistance may accidentally occur.

[0157] As a result of the inventors' failure analysis of chips with low surge current resistance, it became clear that one of the causes of low surge current resistance is a short circuit between the source electrode 12 and the gate wiring 24. It became clear that a short circuit between the source electrode 12 and the gate wiring 24 occurs when the source electrode 12 adjacent to the gate wiring 24 melts, flows laterally, and comes into contact with the gate wiring 24, as shown by the dotted circle in Figure 20(b) and Figure 21.

[0158] It has become clear that short circuits between the source electrode 12 and the gate wiring 24 are particularly likely to occur between the second region 12b of the source electrode 12 in the diode region 102 and the gate wiring 24, as shown in Figures 20(b) and 21.

[0159] The reason why a short circuit is likely to occur between the second region 12b and the gate wiring 24 is thought to be that a surge current flows in the diode region 102, which generates more heat, compared to the transistor region 101. In other words, the source electrode 12 is more likely to melt due to the increased heat generation.

[0160] As shown in FIGS. 7 and 8, in the MOSFET 100 of the first embodiment, the distance in the second direction between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 (dy in FIG. 7) is greater than the distance in the second direction between the first high-concentration portion 30b in the first transistor region 101a and the gate wiring 24 (dx in FIG. 8).

[0161] In the region of the first diode region 102a where the second high-concentration portion 32b is not present, the contact resistance between the second region 12b of the source electrode 12 and the p region 32 becomes high. Therefore, in the region of the first diode region 102a where the second high-concentration portion 32b is not present, the amount of surge current that flows becomes small.

[0162] Therefore, in the region of the first diode region 102a where the second high-concentration portion 32b is not present, the amount of heat generated is reduced, making it difficult for the source electrode 12 to melt. This prevents a short circuit between the source electrode 12 and the gate wiring 24, improving the surge current resistance of the MOSFET 100.

[0163] From the viewpoint of improving the surge current resistance of the MOSFET 100, the distance dy in the second direction between the second heavily doped portion 32b in the first diode region 102a and the gate wiring 24 is preferably equal to or greater than the distance dt between the drain region 26 and the first plane P1, more preferably equal to or greater than 10 times the distance dt, and even more preferably equal to or greater than 30 times the distance dt.

[0164] From the viewpoint of improving the surge current resistance of the MOSFET 100, the distance dy in the second direction between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 is preferably 10 μm or more, more preferably 100 μm or more, and even more preferably 300 μm or more.

[0165] As described above, according to the first embodiment, a MOSFET with improved surge current resistance is realized.

[0166] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the distance in the second direction between the interface between the first electrode and the fourth silicon carbide region in the first diode region and the gate wiring is greater than the distance in the second direction between the interface between the first electrode and the second silicon carbide region in the first transistor region and the gate wiring. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0167] Fig. 22 is a schematic cross-sectional view of a semiconductor device according to the second embodiment, which corresponds to Fig. 7 of the first embodiment.

[0168] Fig. 23 is a schematic cross-sectional view of a semiconductor device according to the second embodiment, which corresponds to Fig. 8 of the first embodiment.

[0169] In the MOSFET 200 of the second embodiment, similarly to the MOSFET 100 of the first embodiment, the distance in the second direction (dy in FIG. 22) between the second high-concentration portion 32b in the first diode region 102a and the gate wiring 24 is greater than the distance in the second direction (dx in FIG. 22) between the first high-concentration portion 30b in the first transistor region 101a and the gate wiring 24.

[0170] Furthermore, in the MOSFET 200 of the second embodiment, the distance in the second direction (db in FIG. 22) between the interface (S2 in FIG. 22) where the second region 12b of the source electrode 12 and the p region 32 in the first diode region 102a meet and the gate wiring 24 is larger than the distance in the second direction (da in FIG. 22) between the interface (S1 in FIG. 23) where the first region 12a of the source electrode 12 and the body region 30 in the first transistor region 101a meet and the gate wiring 24.

[0171] The distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is, for example, at least twice the distance da in the second direction between the interface S1 where the first region 12a and the body region 30 meet and the gate wiring 24.

[0172] The distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is, for example, equal to or greater than the distance (dt in FIG. 22) between the drain region 26 and the first plane P1.

[0173] The distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is, for example, 10 μm or more.

[0174] The amount of surge current that flows is reduced in a region of the first diode region 102a that does not have an interface S2 where the second region 12b and the p region 32 meet. Therefore, in a region of the first diode region 102a that does not have an interface S2, the amount of heat generated is reduced, making the source electrode 12 even less likely to melt. This suppresses short circuits between the source electrode 12 and the gate wiring 24, and the surge current resistance of the MOSFET 200 is even greater than that of the MOSFET 100.

[0175] From the viewpoint of improving the surge current resistance of the MOSFET 200, the distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is preferably equal to or greater than the distance dt between the drain region 26 and the first surface P1, more preferably equal to or greater than 10 times the distance dt, and even more preferably equal to or greater than 30 times the distance dt.

[0176] From the viewpoint of improving the surge current resistance of the MOSFET 200, the distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is preferably 10 μm or more, more preferably 100 μm or more, and even more preferably 300 μm or more.

[0177] As described above, according to the second embodiment, a MOSFET with improved surge current resistance is realized.

[0178] (Third embodiment) A semiconductor device according to a third embodiment includes a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region. The plurality of transistor regions include a silicon carbide layer having a first surface and a second surface opposite to the first surface, the silicon carbide layer including: an n-type first silicon carbide region having a plurality of first portions in contact with the first surface, a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode opposite the second silicon carbide region; and a gate insulating layer provided between the gate electrode and the second silicon carbide region. The at least one diode region includes a silicon carbide layer including an n-type first silicon carbide region having a plurality of second portions in contact with the first surface and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, a first electrode in contact with the plurality of second portions and the fourth silicon carbide region, and a second electrode. The peripheral region includes the silicon carbide layer, a gate electrode pad provided on the first surface side of the silicon carbide layer, and a gate wiring electrically connecting the gate electrode pad and the gate electrode and extending in a first direction parallel to the first surface. The area per unit area of ​​the fourth silicon carbide region projected on the first surface is larger than the area per unit area of ​​the second silicon carbide region projected on the first surface. A first diode region, which is one of the at least one diode region, is provided between a first transistor region, which is one of the plurality of transistor regions, and a second transistor region, which is one of the plurality of transistor regions provided in a first direction relative to the first transistor region. Also, a distance in a second direction, parallel to the first surface and perpendicular to the first direction, between an interface where the first electrode and the fourth silicon carbide region in the first diode region contact and the gate wiring is greater than a distance in the second direction between an interface where the first electrode and the second silicon carbide region in the first transistor region contact and the gate wiring.The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that the distance in a second direction parallel to the first surface and perpendicular to the first direction between the second heavily doped portion in the first diode region and the gate wiring is equal to the distance in the second direction between the first heavily doped portion in the first transistor region and the gate wiring. Hereinafter, some description of content that overlaps with the first or second embodiment may be omitted.

[0179] Fig. 24 is a schematic cross-sectional view of a semiconductor device according to the third embodiment, which corresponds to Fig. 7 of the first embodiment and Fig. 22 of the second embodiment.

[0180] Fig. 25 is a schematic cross-sectional view of a semiconductor device according to the third embodiment, Fig. 25 is a view corresponding to Fig. 8 of the first embodiment, and Fig. 23 of the second embodiment.

[0181] In the MOSFET 300 of the third embodiment, the distance in the second direction (db in FIG. 24) between the interface (S2 in FIG. 24) where the second region 12b of the source electrode 12 and the p region 32 in the first diode region 102a meet and the gate wiring 24 is larger than the distance in the second direction (da in FIG. 25) between the interface (S1 in FIG. 25) where the first region 12a of the source electrode 12 and the body region 30 in the first transistor region 101a meet and the gate wiring 24.

[0182] The distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is, for example, at least twice the distance da in the second direction between the interface S1 where the first region 12a and the body region 30 meet and the gate wiring 24.

[0183] The distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is, for example, equal to or greater than the distance (dt in FIG. 24) between the drain region 26 and the first plane P1.

[0184] The distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is, for example, 10 μm or more.

[0185] The amount of surge current that flows is reduced in a region of the first diode region 102a where there is no interface S2 between the second region 12b and the p region 32. Therefore, in a region of the first diode region 102a where there is no interface S2 between the second region 12b and the p region 32, the amount of heat generated is reduced, making the source electrode 12 even less likely to melt. This prevents a short circuit between the source electrode 12 and the gate wiring 24, improving the surge current resistance of the MOSFET 300.

[0186] From the viewpoint of improving the surge current resistance of the MOSFET 300, the distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is preferably equal to or greater than the distance dt between the drain region 26 and the first surface P1, more preferably equal to or greater than 10 times the distance dt, and even more preferably equal to or greater than 30 times the distance dt.

[0187] From the viewpoint of improving the surge current resistance of the MOSFET 300, the distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is preferably 10 μm or more, more preferably 100 μm or more, and even more preferably 300 μm or more.

[0188] As described above, according to the third embodiment, a MOSFET with improved surge current resistance is realized.

[0189] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the third embodiment in that the first electrode includes a first region of the first transistor region and a second region of the first diode region, and the distance in the second direction between the second region and the gate wiring is greater than the distance in the second direction between the first region and the gate wiring. Hereinafter, some description of content that overlaps with the semiconductor device of the third embodiment may be omitted.

[0190] Fig. 26 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment, which corresponds to Fig. 24 of the third embodiment.

[0191] Fig. 27 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment, which corresponds to Fig. 25 of the third embodiment.

[0192] In the MOSFET 400 of the fourth embodiment, the distance in the second direction (db in FIG. 26) between the interface (S2 in FIG. 26) where the second region 12b of the source electrode 12 meets the p region 32 in the first diode region 102a and the gate wiring 24 is larger than the distance in the second direction (da in FIG. 27) between the interface (S1 in FIG. 27) where the first region 12a of the source electrode 12 meets the body region 30 in the first transistor region 101a and the gate wiring 24.

[0193] The distance db in the second direction between the interface S2 where the second region 12b and the p region 32 meet and the gate wiring 24 is, for example, at least twice the distance da in the second direction between the interface S1 where the first region 12a and the body region 30 meet and the gate wiring 24.

[0194] The amount of surge current that flows is reduced in a region of the first diode region 102a where there is no interface S2 between the second region 12b and the p region 32. Therefore, in a region of the first diode region 102a where there is no interface S2 between the second region 12b and the p region 32, the amount of heat generated is reduced, making the source electrode 12 even less likely to melt. This prevents a short circuit between the source electrode 12 and the gate wiring 24, improving the surge current resistance of the MOSFET 400.

[0195] The source electrode 12 includes a first region 12a in the first transistor region 101a and a second region 12b in the first diode region 102a. In the MOSFET 400 of the fourth embodiment, the distance in the second direction between the second region 12b and the gate wiring 24 (dq in FIG. 26) is greater than the distance in the second direction between the first region 12a and the gate wiring 24 (dp in FIG. 27).

[0196] The distance dq in the second direction between the second region 12b and the gate wiring 24 is, for example, equal to or greater than the distance (dt in FIG. 26) between the drain region 26 and the first plane P1.

[0197] The distance dq in the second direction between the second region 12b and the gate wiring 24 is, for example, at least twice the distance dp in the second direction between the first region 12a and the gate wiring 24. The distance dq in the second direction between the second region 12b and the gate wiring 24 is, for example, at least 10 μm.

[0198] In the MOSFET 400 of the fourth embodiment, the distance between the source electrode 12 in the diode region 102, which generates a large amount of heat, and the gate wiring 24 is large. Therefore, even if the source electrode 12 melts and flows laterally, the melted source electrode 12 can be prevented from coming into contact with the gate wiring 24. This prevents a short circuit between the source electrode 12 and the gate wiring 24, improving the surge current resistance of the MOSFET 400.

[0199] From the viewpoint of improving the surge current resistance of the MOSFET 400, the distance dq in the second direction between the second region 12b and the gate wiring 24 is preferably equal to or greater than the distance dt between the drain region 26 and the first plane P1, more preferably equal to or greater than 10 times the distance dt, and even more preferably equal to or greater than 30 times the distance dt.

[0200] From the viewpoint of improving the surge current resistance of the MOSFET 400, the distance dq in the second direction between the second region 12b and the gate wiring 24 is preferably 10 μm or more, more preferably 100 μm or more, and even more preferably 300 μm or more.

[0201] As described above, according to the fourth embodiment, a MOSFET with improved surge current resistance is realized.

[0202] (Fifth embodiment) The inverter circuit and the drive device of the fifth embodiment are an inverter circuit and a drive device that include the semiconductor device of the first embodiment.

[0203] 28 is a schematic diagram of a driving device according to the fifth embodiment. The driving device 800 includes a motor 140 and an inverter circuit 150.

[0204] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140.

[0205] According to the fifth embodiment, the inverter circuit 150 and the driving device 800 are provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the inverter circuit 150 and the driving device 800.

[0206] (Sixth embodiment) The vehicle of the sixth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0207] 29 is a schematic diagram of a vehicle according to the sixth embodiment. The vehicle 900 according to the sixth embodiment is a railway vehicle. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0208] The inverter circuit 150 is composed of three semiconductor modules that use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 900 are rotated by the motor 140.

[0209] According to the sixth embodiment, the vehicle 900 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 900.

[0210] (Seventh embodiment) The vehicle of the seventh embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0211] 30 is a schematic diagram of a vehicle according to the seventh embodiment. The vehicle 1000 according to the seventh embodiment is an automobile. The vehicle 1000 includes a motor 140 and an inverter circuit 150.

[0212] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0213] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 1000.

[0214] According to the seventh embodiment, the vehicle 1000 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 1000.

[0215] (Eighth embodiment) The elevator of the eighth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0216] 31 is a schematic diagram of an elevator according to the eighth embodiment. The elevator 1100 according to the eighth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0217] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0218] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoisting machine 616, causing the car 610 to rise and fall.

[0219] According to the eighth embodiment, the elevator 1100 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the elevator 1100.

[0220] In the first to fourth embodiments, the crystalline structure of SiC has been described as 4H—SiC, but the present invention can also be applied to devices using SiC with other crystalline structures such as 6H—SiC, 3C—SiC, etc. Furthermore, a plane other than the (0001) plane can also be applied to the surface of the silicon carbide layer 10.

[0221] In the first to fourth embodiments, the gate electrode 18 has been described as having a so-called stripe shape, but the shape of the gate electrode 18 is not limited to a stripe shape. For example, the shape of the gate electrode 18 may be a lattice shape.

[0222] In the first to fourth embodiments, aluminum (Al) is used as an example of a p-type impurity, but boron (B) can also be used. Furthermore, nitrogen (N) and phosphorus (P) are used as examples of n-type impurities, but arsenic (As), antimony (Sb), etc. can also be used.

[0223] Furthermore, in the fifth to eighth embodiments, the configuration including the MOSFET 100 of the first embodiment has been described as an example, but it is also possible to use a configuration including the MOSFET of the second to fourth embodiments.

[0224] Furthermore, in the fifth to eighth embodiments, the semiconductor device of the present invention has been described as being applied to vehicles and elevators, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0225] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0226] 10 Silicon carbide layer 12 Source electrode (first electrode) 12a First Area 12b Second Region 14 Drain electrode (second electrode) 16 Gate insulating layer 18 gate electrode 22 gate electrode pad 24 Gate wiring 26 drain region (fifth silicon carbide region) 28 Drift region (first silicon carbide region) 28a First Part 28b Second Part 30 Body region (second silicon carbide region) 30a First low concentration portion 30b First high concentration portion 32 p region (fourth silicon carbide region) 32a Second low concentration part 32b Second high concentration part 34 source region (third silicon carbide region) 100 MOSFET (semiconductor device) 101 Transistor Area 101a transistor region (first transistor region) 101b transistor region (second transistor region) 102 Diode Region 102a diode region (first diode region) 103 Surrounding Area 800 Drive Unit 900 vehicles 1000 vehicles 1100 elevator P1 First side P2 Second side d1 First distance d2 Second distance

Claims

1. a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region; The plurality of transistor regions include: A silicon carbide layer having a first surface and a second surface opposite to the first surface, an n-type first silicon carbide region having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, the second silicon carbide region having a first low concentration portion and a first high concentration portion provided between the first low concentration portion and the first surface and having a p-type impurity concentration higher than that of the first low concentration portion; a silicon carbide layer including: an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode facing the second silicon carbide region; a gate insulating layer provided between the gate electrode and the second silicon carbide region; The at least one diode region the silicon carbide layer including: the first silicon carbide region of n type having a plurality of second portions in contact with the first surface; and a fourth silicon carbide region of p type provided between the first silicon carbide region and the first surface, the fourth silicon carbide region having a second low concentration portion and a second high concentration portion provided between the second low concentration portion and the first surface and having a p-type impurity concentration higher than that of the second low concentration portion; the first electrode in contact with the plurality of second portions and the fourth silicon carbide region; the second electrode; The peripheral region is the silicon carbide layer; a gate electrode pad provided on the first surface side of the silicon carbide layer; a gate wiring electrically connecting the gate electrode pad and the gate electrode and extending in a first direction parallel to the first surface, an occupation area per unit area of ​​the fourth silicon carbide region projected onto the first surface is larger than an occupation area per unit area of ​​the second silicon carbide region projected onto the first surface; a first diode region which is one of the at least one diode region is provided between a first transistor region which is one of the plurality of transistor regions and a second transistor region which is one of the plurality of transistor regions provided in the first direction with respect to the first transistor region; a distance in a second direction parallel to the first surface and perpendicular to the first direction between the second heavily doped portion in the first diode region and the gate wiring is greater than a distance in the second direction between the first heavily doped portion in the first transistor region and the gate wiring.

2. the silicon carbide layer further includes an n-type fifth silicon carbide region provided between the first silicon carbide region and the second surface and having an n-type impurity concentration higher than that of the first silicon carbide region; 2. The semiconductor device according to claim 1, wherein the distance in the second direction parallel to the first surface and perpendicular to the first direction between the second heavily doped portion in the first diode region and the gate wiring is equal to or greater than the distance between the fifth silicon carbide region and the first surface.

3. 2. The semiconductor device according to claim 1, wherein the distance in the second direction parallel to the first surface and perpendicular to the first direction between the second heavily doped portion in the first diode region and the gate wiring is 10 μm or more.

4. 2. The semiconductor device according to claim 1, wherein a distance in the second direction between the gate wiring and an interface where the first electrode and the fourth silicon carbide region in the first diode region contact each other is greater than a distance in the second direction between the gate wiring and an interface where the first electrode and the second silicon carbide region in the first transistor region contact each other.

5. a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region; The plurality of transistor regions include: A silicon carbide layer having a first surface and a second surface opposite to the first surface, an n-type first silicon carbide region having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; a silicon carbide layer including: an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode facing the second silicon carbide region; a gate insulating layer provided between the gate electrode and the second silicon carbide region; The at least one diode region the silicon carbide layer including: the first silicon carbide region of n type having a plurality of second portions in contact with the first surface; and a fourth silicon carbide region of p type provided between the first silicon carbide region and the first surface; the first electrode in contact with the plurality of second portions and the fourth silicon carbide region; the second electrode; The peripheral region is the silicon carbide layer; a gate electrode pad provided on the first surface side of the silicon carbide layer; a gate wiring electrically connecting the gate electrode pad and the gate electrode and extending in a first direction parallel to the first surface, an occupation area per unit area of ​​the fourth silicon carbide region projected onto the first surface is larger than an occupation area per unit area of ​​the second silicon carbide region projected onto the first surface; a first diode region which is one of the at least one diode region is provided between a first transistor region which is one of the plurality of transistor regions and a second transistor region which is one of the plurality of transistor regions provided in the first direction with respect to the first transistor region; a distance in a second direction parallel to the first surface and perpendicular to the first direction between the gate wiring and an interface where the first electrode and the fourth silicon carbide region in the first diode region contact each other is greater than a distance in the second direction between the gate wiring and an interface where the first electrode and the second silicon carbide region in the first transistor region contact each other.

6. the silicon carbide layer further includes an n-type fifth silicon carbide region provided between the first silicon carbide region and the second surface and having an n-type impurity concentration higher than that of the first silicon carbide region; 6. The semiconductor device according to claim 5, wherein the distance in the second direction between the gate wiring and an interface where the first electrode and the fourth silicon carbide region in the first diode region contact is equal to or greater than a distance between the fifth silicon carbide region and the first surface.

7. the first electrode includes a first region of the first transistor region and a second region of the first diode region; 6. The semiconductor device according to claim 5, wherein a distance in the second direction between said second region and said gate wiring is greater than a distance in the second direction between said first region and said gate wiring.

8. 8. The semiconductor device according to claim 7, wherein the distance in the second direction between the second region and the gate wiring is 10 [mu]m or more.

9. 6. The semiconductor device according to claim 1, wherein said first electrode, said gate electrode pad, and said gate wiring are made of the same metal material.

10. 6. The semiconductor device according to claim 1, wherein the contact area per unit area between the first electrode and the fourth silicon carbide region is larger than the contact area per unit area between the first electrode and the second silicon carbide region.

11. 6. The semiconductor device according to claim 1, wherein a second distance between two adjacent ones of the plurality of second portions sandwiching the fourth silicon carbide region therebetween is equal to a first distance between two adjacent ones of the plurality of first portions sandwiching the second silicon carbide region therebetween.

12. 6. The semiconductor device according to claim 1, wherein the width of the first diode region in the first direction is 30 [mu]m or more.

13. 6. An inverter circuit comprising the semiconductor device according to claim 1.

14. A driving device comprising the semiconductor device according to claim 1 or 5.

15. A vehicle comprising the semiconductor device according to claim 1 or 5.

16. An elevator comprising the semiconductor device according to claim 1 or 5.

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