Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device having a low gate capacitance and a low on-resistance.SOLUTION: A semiconductor device 1 includes: a gate electrode 6 facing a field plate (FP) insulating film 3 via a part of a drift region 24, a base region, a source region, and a gate insulating film 5, in a second direction perpendicular to a first direction directed from a base region 23 to a source region 21; a source electrode 11 having a portion 7 adjacent to a part of the base region and the source region, and electrically connected to an FP electrode 4, the base region, and the source region in the second direction; and an embedded electrode 8 provided in the FP insulating film, having a bottom located closer to the drain electrode 9 side than a bottom of the portion adjacent to the part of the base region and the source region, having a top located on an upper surface of the FP insulating film, and electrically connected to the source electrode. The FP electrode is disposed substantially at a center in the FP insulating film, the embedded electrode is disposed so as to surround the FP electrode in the FP insulating film, and the portion is disposed so as to surround the embedded electrode.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a structure in which the field plate electrode (FP electrode) and gate electrode are embedded in different trenches (separate-gate trench-FP structure) is known. Compared to a power MOSFET with a structure in which the field plate electrode and gate electrode are embedded in the same trench (trench FP structure), a separate-gate trench-FP structure power MOSFET makes it easier to control the dimensions of the gate electrode, making it possible to reduce the gate capacitance.

[0003] However, in the trench-FP structure, it is necessary to create a gate electrode that extends into the drift region located below the base region, which causes electric field concentration in the drift region near the bottom of the gate electrode. Therefore, even if you try to reduce the on-resistance, you cannot increase the impurity concentration in the drift region as much as in the trench-FP structure in order to maintain the breakdown voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-40105 [Patent Document 2] Patent Publication No. 2021-44470 [Patent Document 3] Japanese Patent Publication No. 2020-47742 [Patent Document 4] Japanese Patent Publication No. 2020-150185 [Patent Document 5] Japanese Patent Application Publication No. 2019-145633 Summary of the Invention [Problem to be solved by the invention]

[0005] Embodiments of the present invention provide a semiconductor device with low gate capacitance and low on-resistance. [Means for solving the problem]

[0006] a second electrode provided in the first semiconductor region via a first insulating film; a third electrode facing the first insulating film via a part of the first semiconductor region, the second semiconductor region, the third semiconductor region, and the second insulating film in a second direction perpendicular to a first direction from the second semiconductor region toward the third semiconductor region; a fourth electrode having a part adjacent to a part of the second semiconductor region and the third semiconductor region in the second direction and electrically connected to the second electrode, the second semiconductor region, and the third semiconductor region; and a fifth electrode provided in the first insulating film, having a bottom located closer to the first electrode than the bottom of the part and a top located on an upper surface of the first insulating film and electrically connected to the fourth electrode. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 4 is a plan view showing another configuration example of the semiconductor device according to the first embodiment. [Figure 3] 2 is a cross-sectional view of the semiconductor device according to the first embodiment, taken along line AA in FIG. 1. FIG. [Figure 4] FIG. 4 is an enlarged view of area A in FIG. 3. [Figure 5] FIG. 4 is a cross-sectional view showing a semiconductor device according to a modified example of the first embodiment. [Figure 6]3 is a diagram showing an example of the relationship between the impurity concentration in the drift region of the semiconductor device according to the first embodiment and the breakdown voltage of the semiconductor device. FIG. [Figure 7] FIG. 4 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment. [Figure 9] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 10] 10 is a cross-sectional view of the semiconductor device according to the fourth embodiment, taken along line RR in FIG. 9. FIG. [Figure 11] 10 is a cross-sectional view of the semiconductor device according to the fourth embodiment, taken along the line SS in FIG. 9. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0009] For ease of explanation, an XYZ Cartesian coordinate system is used as shown in Figures 1 to 4. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. In addition, in the X-axis direction, the side where the termination structure exists is also referred to as the "right," and the opposite side is also referred to as the "left." In addition, in the Z direction, the source electrode 11 side is also referred to as the "upper," and the drain electrode side is also referred to as the "lower." However, these expressions are for convenience and are unrelated to the direction of gravity.

[0010] In the following description, n is used to indicate the relative level of impurity concentration in each conductivity type. + , n, n - , and p + , p, p - In some cases, the notation n +has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The n-type is an example of the second conductivity type in the claims. Note that in the configuration of the semiconductor device described below, the n-type and p-type may be reversed. In other words, the first conductivity type may be p-type.

[0011] (First embodiment) A semiconductor device 1 according to a first embodiment will be described with reference to Figures 1 to 4. In this embodiment, the semiconductor device 1 is a vertical MOSFET.

[0012] 1 and 2 are plan views of a semiconductor device 1 according to a first embodiment. FIG. 2 is a plan view showing another example of the configuration of the semiconductor device 1 of FIG. 1. FIGS. 1 and 2 differ only in the structure (termination structure) of the portion outside the QQ line in the X-axis direction, and there is no difference in the structure of the portion inside the QQ line. Hereinafter, when the termination structure is not mentioned, this embodiment will be described with reference to the configuration of FIG. 1.

[0013] Fig. 3 is a cross-sectional view taken along line AA in Fig. 1. Fig. 4 is an enlarged view of area A enclosed by a dotted line in Fig. 3. Note that the cross-sectional view of the configuration example in Fig. 2 is the same as Figs. 3 and 4.

[0014] 3, the semiconductor device 1 includes a semiconductor region 2, a field plate insulating film (FP insulating film) 3, a field plate electrode (FP electrode) 4, a gate insulating film 5, a gate electrode 6, a source electrode (source metal) 11, a portion (source contact) 7 of the source electrode 11, a buried electrode 8, and a drain electrode 9. The semiconductor region 2 includes a semiconductor portion 20 and a drain region 10. To avoid complication, the source electrode 11 is not shown in FIG. 4 and subsequent drawings.

[0015] Each element will be described in detail below with reference to FIGS.

[0016] The semiconductor region 2 may be an epitaxial layer or a semiconductor substrate. The semiconductor region 2 is, for example, silicon (Si), but may also be made of a compound semiconductor such as SiC or GaN. When silicon (Si) is used as the semiconductor material, arsenic (As), phosphorus (P), or antimony (Sb) may be used as the n-type impurity. When silicon (Si) is used as the semiconductor material, boron (B) may be used as the p-type impurity. Hereinafter, for convenience of explanation, the surface of the semiconductor region 2 is assumed to be substantially planar, and the upper surface is referred to as the main surface 2s. Note that this does not limit the shape of the semiconductor region 2.

[0017] The semiconductor portion 20 includes a source region 21 , a contact region 22 , a base region 23 , and a drift region 24 .

[0018] The source region 21 is a semiconductor region that functions as the source of the MOSFET. As shown in FIGS. 3 and 4, the source region 21 is provided on the base region 23. The source region 21 is also disposed in the region between the gate insulating film 5 and the source contact 7. The source region 21 is, for example, an n + The source region 21 is an example of a third semiconductor region in the claims.

[0019] The contact region 22 is provided to prevent a potential difference from occurring between the base region 23 and the source contact 7 when a reverse voltage is applied to the MOSFET, thereby suppressing element breakdown due to a parasitic transistor. As shown in FIGS. 3 and 4, the contact region 22 is disposed in the region between the base region 23 and the source contact 7. The contact region 22 is, for example, p + It is a semiconductor area of ​​the shape.

[0020] The base region 23 is a semiconductor region that functions as the base of the MOSFET. The base region 23 is provided on the drift region 24. The base region 23 is also disposed between the drift region 24 and the source contact 7. When a voltage is applied to the gate electrode 6, the base region 23 forms a channel, allowing carriers to flow between the drain region 10 and the source region 21. The base region 23 is formed of, for example, p - The base region 23 is an example of the second semiconductor region in the claims.

[0021] The drift region 24 is a semiconductor region that functions as a drift region of the MOSFET. The drift region 24 is provided on the drain region 10. The drift region 24 is also disposed between the drain region 10 and the source contact 7. The drift region 24 is, for example, an n - The drift region 24 is an example of a first semiconductor region in the claims.

[0022] The FP insulating film 3 electrically insulates the FP electrode 4 from the semiconductor portion 20. The FP insulating film 3 fills a field plate trench (FP trench) FT formed in the main surface 2s of the semiconductor region 2. The FP trench FT is a trench formed to extend from the main surface 2s to the drift region 24. For convenience of explanation, it is assumed that the FP trench FT is provided in the main surface 2s of the semiconductor region 2, but this does not limit the shape of the semiconductor region 2.

[0023] The FP insulating film 3 is made of an insulating material such as silicon oxide or silicon nitride, etc. The FP insulating film 3 is an example of the first insulating film in the claims.

[0024] The FP electrode 4 is provided in the drift region 24 via the FP insulating film 3. The FP electrode 4 is arranged to reduce the concentration of a reverse electric field between the gate electrode 6 and the drain electrode 9 and increase the breakdown voltage. The FP electrode 4 is made of, for example, polysilicon. In this embodiment, as shown in FIG. 1 , the FP electrode 4 includes a source contact SC. The source contact SC is a portion that extends upward from a part of the FP electrode 4 and is connected to the source electrode 11. The FP electrode 4 is electrically connected to the portion (source contact) 7 via this source electrode 11. The FP electrode 4 is an example of a second electrode in the claims.

[0025] The gate insulating film 5 electrically insulates the gate electrode 6 from the semiconductor portion 20. The gate insulating film 5 fills a gate trench GT formed in the main surface 2s of the semiconductor region 2. The gate trench GT is a trench formed so as to reach the drift region 24 from the main surface 2s, and is formed shallower than the FP trench FT. For convenience of explanation, it is assumed that the gate trench GT is provided in the main surface 2s of the semiconductor region 2, but this does not limit the shape of the semiconductor region 2.

[0026] The gate insulating film 5 is made of an insulating material such as silicon oxide or silicon nitride. The gate insulating film 5 is formed by using, for example, a thermal oxidation method. The gate insulating film 5 is an example of the second insulating film in the claims.

[0027] The gate electrode 6 is an electrode that functions as the gate electrode of the MOSFET. The gate electrode 6 is disposed in the gate insulating film 5. The gate electrode 6 is disposed so as to face the FP insulating film 3 in the Y-axis direction, with part of the drift region 24, the base region 23, the source region 21, and the gate insulating film 5 interposed therebetween. The gate electrode 6 is made of, for example, polysilicon. In this embodiment, as shown in FIG. 1 , the gate electrode 6 includes a gate contact GC. The gate contact GC extends upward from part of the gate electrode 6 and is connected to a gate metal (not shown). The gate electrode 6 is an example of a third electrode in the claims.

[0028] 3 and 4, the lower end (corner) of the gate electrode 6 is located near the boundary between the base region 23 and the drift region 24. The base region 23 is p - The shape and drift region are n - Because of this shape, the lower end of the gate electrode 6 is located near the pn junction, which makes it easier for the electric field to concentrate near the pn junction.

[0029] The source electrode 11 is an electrode that functions as a source electrode of the MOSFET. As shown in FIGS. 3 and 4 , the source electrode 11 has a portion (source contact) 7 adjacent to a part of the base region 23 and the source region 21 in the Y-axis direction. The source electrode 11 is electrically connected to the FP electrode 4, the base region 23, and the source region 21. In this embodiment, for example, the source contact 7 is disposed in a source trench ST formed so as to straddle the boundary between the FP insulating film 3 and the semiconductor portion 20. In this embodiment, the source contact 7 is not in contact with the buried electrode 8 but is electrically connected to the buried electrode 8 via the source electrode. The source electrode 11 is an example of a fourth electrode in the claims. For convenience of explanation, it is assumed that a source trench ST is provided in the main surface 2s of the semiconductor region 2, but this does not limit the shape of the semiconductor region 2.

[0030] The buried electrode 8 is provided in the FP insulating film 3 so that its top is located on the upper surface of the FP insulating film 3. Note that the top of the buried electrode 8 does not have to be located on the upper surface of the FP insulating film 3. As will be described later, the buried electrode 8 is provided to relieve electric field concentration that occurs in the drift region 24 near the lower end of the gate electrode 6. As shown in FIG. 1 , the buried electrode 8 has a source contact SC. The source contact SC is a portion that extends upward from the buried electrode 8 and is connected to the source electrode 11. The buried electrode 8 is electrically connected to the source electrode 11 via the source contact SC. The buried electrode 8 is electrically connected to the source contact 7 via the source contact SC and the source electrode 11. The buried electrode 8 is an example of a fourth electrode in the claims.

[0031] The buried electrode 8 may be provided so as to be in contact with the source contact 7. A cross-sectional view of the semiconductor device 1 in this case is shown in Fig. 5. When the source contact 7 and the buried electrode 8 are in contact with each other in this way, for example, there is no need to provide the buried electrode 8 with a source contact SC, which can reduce the number of manufacturing steps.

[0032] 3 and 5, the upper end of the buried electrode 8 is located on the main surface 2s of the semiconductor region 2, and the lower end of the buried electrode 8 is located below the lower end of the source contact 7. In other words, as shown in FIG. 4, if the distance from the upper surface R of the drain electrode 9 to the bottom of the buried electrode 8 is D1 and the distance from the upper surface R to the bottom of the source contact 7 is D2, then the distance D1 is smaller than the distance D2. In other words, the bottom of the buried electrode 8 is located closer to the drain electrode 9 than the bottom of the source contact 7. This makes it possible to alleviate electric field concentration that occurs in the drift region 24 near the lower end of the gate electrode 6.

[0033] Furthermore, if the distance from the upper surface R to the bottom of the gate electrode 6 is D3, in this embodiment, the distance D1 is smaller than the distance D3. This further enhances the effect of alleviating electric field concentration by the buried electrode 8. The distances D1 and D3 are examples of the first distance and the second distance in the claims, respectively.

[0034] On the other hand, simulations have revealed that if the distance D1 becomes small, that is, if the length of the embedded electrode 8 in the Z-axis direction becomes excessively large, the effect of the embedded electrode 8 in alleviating electric field concentration is weakened. Specifically, if the difference between the distance D1 and the distance D3 becomes larger than the length of the gate electrode 6 in the Z-axis direction, the effect of alleviating electric field concentration is weakened. Furthermore, as the length of the embedded electrode 8 in the Z-axis direction increases, the capacitance between the drain and source increases. Therefore, it is preferable that the difference between the distance D1 and the distance D3 is equal to or smaller than the length of the gate electrode 6 in the Z-axis direction.

[0035] The positional relationship in the Z-axis direction among the buried electrode 8, the source contact 7, and the gate electrode 6 may be defined based on the boundary surface between the source electrode 11 and the FP insulating film 3 (i.e., the main surface 2s). That is, the distance from the main surface 2s to the innermost portion (bottom, lower end) of the buried electrode 8 is greater than the distance from the main surface 2s to the innermost portion of the source contact 7. Furthermore, the length from the main surface 2s to the innermost portion of the buried electrode 8 is equal to or less than twice the length from the main surface 2s to the innermost portion of the gate electrode 6. In this way, even when the main surface 2s is used as the reference, the positional relationship among the buried electrode 8, the source contact 7, and the gate electrode 6 can be defined to be the same as the positional relationship described using the distances D1 to D3 from the top surface R of the drain electrode 9.

[0036] The upper end of the buried electrode 8 is not limited to being located on the main surface 2s of the semiconductor region 2. That is, the buried electrode 8 may be provided so as to be buried inside the FP insulating film 3, and the upper end may be located below the main surface 2s.

[0037] The buried electrodes 8 are made of a conductive material such as polysilicon, or a metal such as titanium (Ti), tungsten (W), or aluminum (Al).

[0038] The buried electrode 8 may be made of the same material as the FP electrode 4. In this case, the buried electrode 8 and the FP electrode 4 can be produced in the same process in the manufacturing process of the semiconductor device 1. This improves manufacturing efficiency and reduces manufacturing costs.

[0039] Here, an example of a manufacturing method for forming the buried electrode 8 and the FP electrode 4 in the same process will be described. First, an insulating material such as silicon oxide or silicon nitride is deposited in the FP trench FT, for example, by CVD (Chemical Vapor Deposition). The insulating material is deposited so as to leave space inside the FP trench FT for the FP electrode 4 and the buried electrode 8. Next, polysilicon or the like is deposited in the space, for example, by CVD, to form the FP electrode 4 and the buried electrode 8. Excess polysilicon is removed by etch-back. After that, an insulating material is further deposited on top of the FP electrode 4, for example, by CVD, to seal the FP electrode 4 inside the FP trench FT. This completes the FP insulating film 3 in which the FP electrode 4 is buried.

[0040] The buried electrode 8 may be made of the same material as the source electrode 11 and the source contact 7. In this case, the buried electrode 8 and the source contact 7 can be formed in the same manufacturing process of the semiconductor device 1. This improves manufacturing efficiency and reduces manufacturing costs.

[0041] Here, an example of a manufacturing method for forming the buried electrode 8 and the source contact 7 in the same process will be described. First, a source trench ST is formed by selectively removing a portion of the semiconductor region 2 using RIE (Reactive Ion Etching) or the like. Simultaneously with the formation of the source trench ST, or before or after the formation of the source trench ST, a space for disposing the buried electrode 8 is formed in the FP insulating film 3 using RIE or the like. Thereafter, a metal is deposited in the source trench ST and in the space using, for example, a CVD method, thereby forming the source contact 7 and the buried electrode 8. The metal used here is, for example, titanium, tungsten, aluminum, or the like. Excess metal is removed by etch-back.

[0042] Next, the layout of the semiconductor device 1 will be described with reference to FIGS.

[0043] The semiconductor device 1 according to this embodiment includes multiple cells that constitute one MOSFET. The longitudinal direction of each cell extends along the X-axis direction, and multiple cells are arranged in parallel in the Y-axis direction. The FP electrode 4, source contact 7, and buried electrode 8 are arranged in parallel in a stripe pattern with their longitudinal direction aligned with the X-axis direction. As shown in FIG. 1, a gate electrode 6 is arranged between two adjacent cells. In other words, in this embodiment, two adjacent cells share the same gate electrode 6. However, this is not limited thereto, and each cell may have its own gate electrode 6.

[0044] As shown in Fig. 1, the embedded electrodes 8 are arranged in the FP insulating film 3 so as to sandwich the FP electrode 4. The ends of the two embedded electrodes 8 that sandwich the FP electrode 4 are open. On the other hand, in the configuration example of Fig. 2, the two embedded electrodes 8 arranged in the same FP insulating film 3 are joined together at their ends to form a single unit. In other words, in a plane perpendicular to the Z-axis direction (XY plane), the embedded electrodes 8 are arranged so as to surround the FP electrode 4.

[0045] The source contact 7 is disposed on the opposite side of the FP electrode 4 with the buried electrode 8 interposed therebetween. The gate electrode 6 is disposed on the opposite side of the source contact 7 with the buried electrode 8 interposed therebetween. The gate electrode 6 is spaced apart from the source contact 7 by the semiconductor portion 20 and the gate insulating film 5.

[0046] 1 and 2, the source contact 7 extends along the X-axis direction to the P-P line. The gate electrode 6 extends along the X-axis direction to the QQ line (to the position where the gate contact GC is located). Therefore, in the semiconductor device 1, the portion that actually operates as a MOSFET is the portion to the left of the P-P line (the portion where both the gate electrode 6 and the source contact 7 are provided). In other words, the gate electrode 6 located between the P-P line and the QQ line is not directly related to the operation of the semiconductor device 1.

[0047] 1 and 2, the buried electrode 8 extends along the X-axis direction at least as far as the QQ line. That is, the outermost end of the buried electrode 8 in the longitudinal direction is located at the same position as the outermost end of the gate electrode 6 in the longitudinal direction, or is located further outward than the outermost end of the gate electrode 6 in the longitudinal direction. This is because electric field concentration can occur where the gate electrode 6 is present, even if it is not directly related to the operation of the MOSFET. In order to effectively alleviate electric field concentration near the end portion of the gate electrode 6, it is preferable to dispose the buried electrode 8 so that it is located further outward than the outermost end of the gate electrode 6 in the longitudinal direction, as shown in FIGS. 1 and 2.

[0048] The drain electrode 9 is an electrode that functions as a drain electrode of the MOSFET. The drain electrode 9 is disposed below the semiconductor region 2. The drain electrode 9 is electrically connected to the drain region 10. The drain electrode 9 is an example of a first electrode in the claims.

[0049] The drain electrode 9 is made of a metal such as titanium (Ti), tungsten (W), or aluminum (Al).

[0050] The drain region 10 is a semiconductor region that functions as the drain of the MOSFET. The drain region 10 is provided on the drain electrode 9. The drain region 10 is also located between the drain electrode 9 and the drift region 24. The drain region 10 is, for example, an n + It is a semiconductor area of ​​the shape.

[0051] <Simulation results> The effect of arranging the buried electrodes 8 will be described with reference to FIG.

[0052] 6 is a graph showing an example of the relationship between the impurity concentration in the drift region 24 of the semiconductor device 1 and the breakdown voltage (maximum value of the drain-source voltage) of the semiconductor device 1. Fig. 6 also shows the relationship between the impurity concentration in the drift region and the breakdown voltage in the semiconductor devices according to Comparative Examples 1 and 2. Comparative Example 1 is a MOSFET with a trench FP structure, and Comparative Example 2 is a MOSFET with a separate gate trench-FP structure in which no buried electrode 8 is provided.

[0053] In Figure 6, V DSS is the breakdown voltage measured when the gate and source are short-circuited. DSX is the breakdown voltage measured when a reverse bias voltage is applied between the gate and source.

[0054] As can be seen from FIG. 6, in the separate gate trench-FP structure of Comparative Example 2, electric field concentration occurs at the bottom end of the gate electrode, resulting in a significant decrease in breakdown voltage at a lower impurity concentration than in the trench FP structure of Comparative Example 1.

[0055] In contrast, in semiconductor device 1, the breakdown voltage does not decrease even if the impurity concentration in the drift region is increased to the impurity concentration at which the breakdown voltage decreases in Comparative Examples 1 and 2. This is because the electric field concentration occurring at the lower end of gate electrode 6 is alleviated by buried electrode 8. Therefore, according to this embodiment, in the separate gate trench-FP structure, it is possible to increase the impurity concentration while maintaining a high breakdown voltage.

[0056] As described above, according to this embodiment, it is possible to increase the impurity concentration in the drift region, and therefore the semiconductor device 1 can improve the on-resistance compared to Comparative Examples 1 and 2. Simulations have shown that the on-resistance per unit area (RonA) is approximately 190 mΩ cm in Comparative Example 1. -2 , and about 210 mΩ·cm in Comparative Example 2. -2 In contrast, the semiconductor device 1 has a resistance of approximately 170 mΩ cm -2 It was confirmed that there was an improvement.

[0057] Furthermore, because the semiconductor device 1 has a separate gate trench-FP structure, it has a gate input charge (Qg) equivalent to that of Comparative Example 2. That is, according to this embodiment, it is possible to improve the on-resistance while maintaining the effect of being able to reduce the gate capacitance. The index (Ron·Qg) expressed as the product of the on-resistance and the gate input charge was approximately 580 mΩ·nC in Comparative Example 1 and approximately 500 mΩ·nC in Comparative Example 2, but it was confirmed that it was significantly improved to approximately 410 mΩ·nC in the semiconductor device 1.

[0058] Furthermore, as the on-resistance improves, the index (Ron·Qoss), which is the product of the on-resistance and the output charge (Qoss), also improves. That is, it was confirmed that Ron·Qoss, which was 1720 mΩ·nC or more in Comparative Example 1 and approximately 1800 mΩ·nC in Comparative Example 2, improved to less than 1650 mΩ·nC in Semiconductor Device 1. Here, the output charge is the amount of charge between the drain and source.

[0059] Additionally, it was confirmed that the present embodiment also improved the gate-drain charge (Qgd) and gate switch charge (Qsw) compared to the first and second comparative examples.

[0060] As described above, in the first embodiment, by adding the buried electrode 8 in the gate-specific trench-FP structure, it is possible to alleviate the electric field concentration that occurs in the drift region near the lower end of the gate electrode 6. This makes it possible to increase the impurity concentration in the drift region 24 while maintaining a high breakdown voltage, thereby achieving a low on-resistance. Therefore, according to this embodiment, it is possible to provide a semiconductor device with low gate capacitance and low on-resistance.

[0061] (Second embodiment) Next, a second embodiment will be described with reference to Fig. 7. Fig. 7 is a partial cross-sectional view of a semiconductor device 1A according to the second embodiment. In Fig. 7, elements with the same names or functions as those in Fig. 4 described in the first embodiment are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions.

[0062] In the first embodiment, it has been explained that the buried electrode 8 can alleviate the electric field concentration that occurs in the drift region near the bottom end of the gate electrode 6. However, at the same time, simulation results show that the effect of alleviating the electric field concentration decreases the closer to the upper part of the buried electrode 8.

[0063] 7, in the second embodiment, the width of the buried electrode 8a is increased toward the main surface 2s. Therefore, the thickness T of the FP insulating film 3 between the buried electrode 8a and the semiconductor portion 20 decreases from the drain electrode 9 toward the source contact 7. This makes it possible to suppress a decrease in the effect of alleviating electric field concentration above the buried electrode 8. In other words, by reducing the thickness T of the FP insulating film 3 and increasing the effect of alleviating electric field concentration by the buried electrode 8a, it is possible to compensate for the decrease in the effect of alleviating electric field concentration above the buried electrode 8.

[0064] Simulation results showed that the semiconductor device 1A according to the second embodiment showed improvements in the on-resistance (RonA), the index Ron·Qoss, the index Ron·Qg, Qgd, and Qsw compared to the semiconductor device 1 according to the first embodiment.

[0065] As described above, in the semiconductor device 1A according to the second embodiment, by decreasing the thickness T of the FP insulating film 3 between the buried electrode 8a and the semiconductor portion 20 toward the main surface 2s, it is possible to obtain an effect of alleviating electric field concentration across the entire gate electrode 6. This makes it possible to further increase the impurity concentration in the drift region 24 while maintaining a high breakdown voltage, thereby achieving a further reduction in on-resistance.

[0066] (Third embodiment) Next, a third embodiment will be described with reference to Fig. 8. Fig. 8 is a plan view showing a part of a semiconductor device 1B according to the third embodiment. Elements with the same names or functions as those in Fig. 1 described in the first embodiment are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions.

[0067] In the first and second embodiments, a plurality of cells are arranged in parallel in a stripe pattern in the Y-axis direction, as shown in Fig. 1. In contrast, in the third embodiment, a plurality of cells having a substantially square shape (dot-shaped cells) are arranged, as shown in Fig. 8. By using such a layout, the integration degree of the semiconductor device 1B can be improved.

[0068] In this embodiment, as shown in FIG. 8, the gate electrodes 6 are configured in a lattice pattern. The cells are arranged in gaps in the lattice formed by the gate electrodes 6. When such a layout is adopted, the area of ​​the gate electrodes 6 in contact with the semiconductor portion 20 increases near the vertices (corners) of the lattice. Therefore, electric field concentration is more likely to occur in the semiconductor portion 20 near the vertices of the approximately square shape of each cell. However, as will be described later, by applying buried electrodes 8 that alleviate electric field concentration to dot-shaped cells, it is possible to alleviate the electric field concentration that occurs in the semiconductor portion 20 near the vertices of the approximately square shape of the cell.

[0069] As shown in FIG. 8, when the semiconductor region 2 is viewed in the thickness direction, the FP electrode 4, the buried electrode 8, and the source contact 7 form a cell arranged in a concentric, substantially rectangular shape with the FP electrode 4 at the center.

[0070] The FP electrode 4 is disposed approximately in the center of the FP insulating film 3 (approximately in the center of the grid of the gate electrode 6). The buried electrode 8 is disposed in the FP insulating film 3 so as to surround the FP electrode 4. The source contact 7 is disposed so as to surround the buried electrode 8. The source contact 7 and the buried electrode 8 may be in contact with each other.

[0071] The shape in which the FP electrode 4, the buried electrode 8, and the source contact 7 are arranged is not limited to a concentric rectangular shape, but may be, for example, a concentric polygonal shape or a concentric circular shape.

[0072] Furthermore, the gate electrodes 6 may have any shape other than a lattice shape that improves the integration degree of the semiconductor device 1B. For example, the gate electrodes 6 may be configured in a hexagonal shape (honeycomb shape) on a plane perpendicular to the Z-axis direction, or in a shape in which the intersections of the gate electrodes 6 do not overlap in the X-axis direction or the Y-axis direction (staggered shape).

[0073] Also, adjacent cells do not have to share the same gate electrode 6. That is, each cell may have its own gate electrode 6.

[0074] As described above, according to the third embodiment, by applying the buried electrodes 8 to the dot-shaped cells, it is possible to alleviate the electric field concentration that occurs in the semiconductor portion 20 near the vertices of the approximately square shape of the cell. Therefore, it is possible to increase the integration density of the semiconductor device and achieve a low on-resistance while maintaining a low gate capacitance.

[0075] (Fourth embodiment) Next, a fourth embodiment will be described with reference to Fig. 9. Fig. 9 is a plan view showing a part of a semiconductor device 1C according to the fourth embodiment. Elements with the same names or functions as those in Fig. 1 described in the first embodiment are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions.

[0076] In the case of the substantially rectangular cell described in the third embodiment, the effect of the buried electrode 8 in alleviating electric field concentration is reduced at the corners where the distance between the buried electrode 8 and the gate electrode 6 is greater. Furthermore, the thickness of the FP insulating film 3 between the buried electrode 8 and the semiconductor portion 20 is also increased at the corners, further reducing the effect of alleviating electric field concentration. In this embodiment, as described below, the boundary B between the FP insulating film 3 and the semiconductor portion 20 is made substantially circular, thereby suppressing the reduction in the effect of alleviating electric field concentration.

[0077] 9, in this embodiment, when the semiconductor region 2 is viewed in the thickness direction, the boundary B between the FP insulating film 3 and the semiconductor portion 20 is substantially circular, and the source contacts 7 are arranged in a substantially circular shape along the boundary B. When the semiconductor region 2 is viewed in the thickness direction, the embedded electrode 8 is arranged in a substantially rectangular shape so as to surround the FP electrode 4. One side of the substantially rectangular shape formed by the embedded electrode 8 is substantially parallel to one side of the substantially rectangular shape of the lattice formed by the gate electrode 6.

[0078] The shape of the FP electrode 4 is not limited to the approximately circular shape shown in FIG. 9, but may be any shape.

[0079] 10 is a cross-sectional view of the semiconductor device 1C according to the fourth embodiment, taken along the line RR in FIG. 9. FIG. 11 is a cross-sectional view of the semiconductor device 1C according to the fourth embodiment, taken along the line SS in FIG. 9. Here, the line RR is a line that passes through the center of the approximate square formed by the lattice-shaped gate electrode 6 and is parallel to one side of the lattice. The line SS is a diagonal line of the approximate square formed by the lattice-shaped gate electrode 6.

[0080] 10 and 11, the thickness of the FP insulating film 3 between the buried electrode 8 and the semiconductor portion 20 is smaller than the thickness T1 in FIG. 10, as shown in FIG. 11. Furthermore, thickness T2 is smaller than the thickness of the FP insulating film 3 between the buried electrode 8 and the semiconductor portion 20 at the corners of the cell in the third embodiment. In this way, in this embodiment, the thickness of the FP insulating film 3 is made smaller at positions where the distance between the buried electrode 8 and the gate electrode 6 is relatively large. This makes it possible to prevent a decrease in the effect of mitigating electric field concentration at the corners of the approximately rectangular shape.

[0081] The shape of the boundary B is not limited to a substantially circular shape as long as the thickness of the FP insulating film 3 can be reduced at the position where the distance between the buried electrode 8 and the gate electrode 6 is relatively large. For example, if the buried electrode 8 is square, the boundary B may be a square that is concentric with the square and rotated by 45°.

[0082] As described above, according to the fourth embodiment, the electric field concentration occurring in the semiconductor portion 20 near the vertices of the substantially square shape of the cell can be alleviated compared to the third embodiment.

[0083] Although the embodiments of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These embodiments and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. [Explanation of symbols]

[0084] 1, 1A, 1B, 1C Semiconductor device 2. Semiconductor field 2s main surface 3 FP insulating film 4 FP electrodes 5 Gate insulating film 6 gate electrode 7 parts 8,8a Buried electrode 9 Drain electrode 10 Drain region 11 Source electrode 20 Semiconductor Department 21 Source Region 22 Contact Area 23 Base Area 24 Drift Region R top surface Area A B boundary FT FP Trench GC Gate Contact GT Gate Trench SC Source Contact ST Source Trench

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided above the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided in the first semiconductor region via a first insulating film; a third electrode facing the first insulating film via a part of the first semiconductor region, the second semiconductor region, the third semiconductor region, and a second insulating film in a second direction perpendicular to a first direction from the second semiconductor region toward the third semiconductor region; a fourth electrode having a portion adjacent to a part of the second semiconductor region and the third semiconductor region in the second direction, the fourth electrode being electrically connected to the second electrode, the second semiconductor region, and the third semiconductor region; a fifth electrode provided in the first insulating film, the bottom of which is located closer to the first electrode than the bottom of the portion, the top of which is located on the upper surface of the first insulating film, and the fifth electrode electrically connected to the fourth electrode; A semiconductor device comprising:

2. 2 . The semiconductor device according to claim 1 , wherein a first distance from an upper surface of said first electrode to a bottom of said fifth electrode is smaller than a second distance from said upper surface to a bottom of said third electrode.

3. The difference between the first distance and the second distance is equal to or less than the length of the third electrode in the first direction. The semiconductor device according to claim 2 .

4. The semiconductor device according to claim 1 , wherein the fifth electrode is in contact with the portion.

5. 2. The semiconductor device according to claim 1, wherein a thickness of said first insulating film between said fifth electrode and a semiconductor portion including said first semiconductor region and said second semiconductor region decreases from said first electrode side toward said portion.

6. The semiconductor device according to claim 1 , wherein said fifth electrode is made of the same material as said portion.

7. The semiconductor device according to claim 1 , wherein said fifth electrode is made of the same material as said second electrode.

8. the second electrodes and the fifth electrodes are arranged in parallel in a stripe pattern on a plane perpendicular to the first direction, the fifth electrodes are arranged to sandwich the second electrode, 8. The semiconductor device according to claim 1, wherein the fifth electrode has a longitudinally outermost end that is the same as or further outward than the longitudinally outermost end of the third electrode.

9. the fifth electrode is disposed so as to surround the second electrode in a plane perpendicular to the first direction, an outermost end of the fifth electrode in the longitudinal direction is located at the same position as an outermost end of the third electrode in the longitudinal direction, or is located further outward than an outermost end of the third electrode in the longitudinal direction; The semiconductor device according to any one of claims 1 to 7.

10. In a plane perpendicular to the first direction, the second electrode, the fifth electrode, and the portion are arranged in a concentric polygonal shape or a concentric circular shape with the second electrode as a center, the second electrode is disposed at the center of the first insulating film, the fifth electrode is disposed in the first insulating film so as to surround the second electrode, The portion is arranged to surround the fifth electrode. The semiconductor device according to any one of claims 1 to 7.

11. the third electrodes are configured in a lattice shape or a hexagonal shape on a plane perpendicular to the first direction, or in a shape in which intersections of the third electrodes do not overlap in the second direction or in a third direction perpendicular to the first direction and the second direction, the second electrode, the fifth electrode, and the portion are disposed in a gap formed by the third electrode. The semiconductor device according to claim 10.

12. In a plane perpendicular to the first direction, the third electrode is configured in a grid pattern, a boundary between the first insulating film and a semiconductor portion including the first semiconductor region and the second semiconductor region is arranged in a circular shape; the fifth electrodes are arranged in a square shape, The portions are arranged in a circular pattern along the boundary. The semiconductor device according to claim 10.

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