Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving a trade-off relation between turn-on loss Eon and reverse recovery dV / dt.SOLUTION: There is provided a trench gate type IGBT, wherein some trenches 6 among a plurality of trenches 6 provided at equal intervals are gate trenches 6a where gate electrodes 8a are embedded, and the remaining trenches 6 are dummy trenches 6b where dummy electrodes 8b for emitter electrode are embedded. Four dummy trenches 6a are arranged each time two gate trenches 6a are arranged in a direction parallel with a top surface of a semiconductor substrate. A first mesa region 20a between mutually adjacent gate trenches 6a is covered with an inter-layer insulation film 9 to be in an electrically floating state. A second mesa part 20b between a gate trench 6a and a dummy trench 6b which adjoin each other is fixed at an emitter potential. In an ON state, a channel is formed in a p-type base region 3 of the second mesa part 20b along a side wall of the gate trench 6a.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, a trench-gate IGBT (Insulated Gate Bipolar Transistor) has been known to have a structure including a trench (hereinafter referred to as a gate trench) in which a gate electrode is buried via an insulating film (gate insulating film), and a trench (hereinafter referred to as a dummy trench) in which a dummy electrode of an emitter potential is buried via an insulating film. The front surface of the semiconductor substrate is in contact with the emitter electrode at the portions (mesa portions) between all adjacent trenches.

[0003] The structure of a conventional trench gate IGBT will be described. Fig. 10 is a perspective view showing the structure of a conventional semiconductor device. Fig. 11 is a perspective view showing another example of the structure of a conventional semiconductor device. A conventional semiconductor device 131 shown in Fig. 10 is a trench gate IGBT having a plurality of trenches 106, in which electrodes 108 are buried via insulating films 107, on the front surface side of a semiconductor substrate (semiconductor chip) 110. The plurality of trenches 106 are arranged in a stripe pattern extending in a first direction X parallel to the front surface of the semiconductor substrate 110.

[0004] Inside the trench 106, an insulating film 107 is provided along the inner wall of the trench 106, and an electrode 108 is provided on the insulating film 107 so as to fill the trench 106. Of the multiple trenches 106, the electrode 108 inside some trenches (gate trenches) 106a is a gate electrode 108a of an IGBT (semiconductor device 131), and the electrode 108 inside the remaining trenches (dummy trenches) 106b excluding the gate trenches 106a is a dummy electrode 108b of the emitter potential (potential of the emitter electrode 111) of the IGBT.

[0005] Two dummy trenches 106b are arranged for every gate trench 106a in a second direction Y that is parallel to the front surface of the semiconductor substrate 110 and perpendicular to the first direction X. The trenches 106 are arranged such that a plurality of basic unit parts 121, each including one gate trench 106a and two dummy trenches 106b, are arranged in parallel in the second direction Y. In FIG. 10, the gate electrode 108a is illustrated as "Gate," and the dummy electrode 108b is illustrated as "Emitter" (the same applies to FIG. 11).

[0006] The portions (mesa portions) 120 between the adjacent trenches 106, including the mesa portion 120b between the adjacent gate trenches 106a and dummy trenches 106b and the mesa portion 120c between the adjacent dummy trenches 106b, all have the same cell structure. - Between the n-type drift region 101, an n-type accumulation region 102, a p-type base region 103, and an n-type + type emitter region 104 and p + Mold contact regions 105 are selectively provided.

[0007] The n-type accumulation region 102 is connected to the p-type base region 103 and - The p-type base region 103 is provided between the front surface of the semiconductor substrate 110 and the n-type accumulation region 102. + type emitter region 104 and p + The p-type contact regions 105 are selectively provided between the front surface of the semiconductor substrate 110 and the p-type base region 103, respectively.

[0008] n - a n-type drift region 101, an n-type accumulation region 102, a p-type base region 103, and an n-type +The emitter region 104 contacts the insulating film 107 on the sidewall of the trench 106 (the gate trench 106a in the portion adjacent to the gate trench 106a, and the dummy trench 106b in the portion adjacent to the dummy trench 106b). + through the p-type emitter region 104, the p-type base region 103 and the n-type accumulation region 102, - It terminates inside the drift region 101 .

[0009] All of the mesa portions 120 (120b, 120c) are in contact with the emitter electrode 111 on the front surface of the semiconductor substrate 110, and are fixed to the potential of the emitter electrode 111. - Between the n-type drift region 101, + The back surface of the semiconductor substrate 110 and the n-type buffer region 112 are + Between the mold buffer area 112, p + A collector region 113 is provided on the semiconductor substrate 110. A collector electrode 114 is provided on the entire rear surface of the semiconductor substrate 110. Reference numeral 109 denotes an interlayer insulating film.

[0010] 11 differs from the conventional semiconductor device 131 shown in FIG. 10 in that a basic unit 122 in which the trenches 106 are repeatedly arranged includes two gate trenches 106a arranged adjacent to each other in the second direction Y. Four dummy trenches 106b are arranged in the second direction Y for every two gate trenches 106a. The trenches 106 are arranged such that a plurality of basic unit 122, each including two gate trenches 106a and four dummy trenches 106b, are arranged in parallel in the second direction.

[0011] The mesa portions 120 between adjacent trenches 106 all have the same cell structure, including the first mesa portion 120a between adjacent gate trenches 106a, the second mesa portion 120b between adjacent gate trenches 106a and dummy trenches 106b, and the third mesa portion 120c between adjacent dummy trenches 106b. All of the mesa portions 120 (first to third mesa portions 120a to 120c) contact the emitter electrode 111 on the front surface of the semiconductor substrate 110 and are fixed to the potential of the emitter electrode 111 (emitter potential).

[0012] In the conventional semiconductor devices 131 and 132 shown in Figures 10 and 11, when a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 108a while a positive voltage (forward voltage) relative to the emitter electrode 111 is applied to the collector electrode 114, a channel (n-type inversion layer) is formed only in the portion of the p-type base region 103 along the gate trench 106a. + collector region 113 and n + The pn junction with the type buffer region 112 is forward biased, and the IGBT (semiconductor devices 131 and 132) is turned on.

[0013] When the IGBT is turned on, p + Type collector region 113 to n + n through the type buffer region 112 - Holes are injected into the n-type drift region 101. + The n-type emitter region 104 is connected to the n-type accumulation region 102 via the channel and the n-type emitter region 104. - Electrons are injected into the n-type drift region 101 - The carrier concentration in the n-type drift region 101 increases, causing conductivity modulation. - The resistance value of the type drift region 101 is reduced, and the forward voltage drop is suppressed, so that the IGBT becomes a switching device that turns on with a low on-voltage.

[0014] As a conventional trench gate IGBT, a device has been proposed in which the mesa portion and the bottom of the dummy trench are connected to each other by a p-type region, thereby improving gate controllability against noise during switching (see, for example, Patent Document 1 below). Patent Document 1 below describes a device that includes a gate trench and a dummy trench in which an electrode of an emitter potential, an electrically floating potential, or another gate potential is embedded, and + The document discloses a structure in which a mesa portion where no emitter region is disposed is made electrically floating.

[0015] In addition, as another conventional trench gate IGBT, n + The n-type emitter region is placed + A device has been proposed in which trenches that are not adjacent to p-type emitter regions are used as dummy trenches, thereby widening the safe operating area (see, for example, Patent Document 2 below). Patent Document 2 below discloses a structure in which two dummy trenches are arranged for every two gate trenches, and only electrically floating p-type base regions are arranged between some of the adjacent gate trenches or dummy trenches.

[0016] Another conventional trench gate IGBT is a multi-n + A device has been proposed in which only a part of the type emitter region is connected to the emitter electrode to promote electron injection and reduce the on-state voltage (see, for example, Patent Document 3 below). In Patent Document 3 below, the entire device is a gate trench, and + a cell in which a channel is formed by disposing an n-type emitter region; + The document discloses a structure in which a dummy cell has only a p-type base region without a p-type emitter region, and the dummy cell is separated by a gate trench to make the dummy cell electrically floating. [Prior art documents] [Patent documents]

[0017] [Patent Document 1] Japanese Patent Application Publication No. 2018-182313 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-184712 [Patent Document 3] Japanese Patent Application Publication No. 11-345969 Summary of the Invention [Problem to be solved by the invention]

[0018] However, in conventional IGBTs (semiconductor devices 131 and 132: see FIGS. 10 and 11), there is a trade-off between the switching loss Eon (hereinafter referred to as turn-on loss) at turn-on and the dV / dt (rate of voltage change per unit time: hereinafter referred to as reverse recovery dV / dt) of the anode-cathode voltage during reverse recovery of the diode connected inversely in parallel to the IGBT. Specifically, increasing the gate resistance of the IGBT can suppress the reverse recovery dV / dt that causes noise, but increases the turn-on loss Eon. On the other hand, decreasing the gate resistance of the IGBT can reduce the turn-on loss Eon, but increases the reverse recovery dV / dt.

[0019] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the trade-off relationship between turn-on loss Eon and reverse recovery dV / dt. [Means for solving the problem]

[0020] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: A first semiconductor region of a first conductivity type is provided within a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region. A fourth semiconductor region of a second conductivity type is provided between the back surface of the semiconductor substrate and the first semiconductor region. A trench is provided on the front surface of the semiconductor substrate. A first electrode is provided within the trench via an insulating film. An interlayer insulating film is provided on the front surface of the semiconductor substrate and covers the first electrode. A second electrode is provided on the front surface of the semiconductor substrate and is electrically connected to the second semiconductor region and the third semiconductor region via a contact hole in the interlayer insulating film.

[0021] A third electrode is provided on the back surface of the semiconductor substrate and is electrically connected to the fourth semiconductor region. A plurality of the trenches are arranged at equal intervals. Some of the plurality of trenches are gate trenches that pass through the third semiconductor region and the second semiconductor region to reach the first semiconductor region. The remaining trenches, excluding the gate trenches, are dummy trenches that pass through the second semiconductor region to reach the first semiconductor region. The first electrode is a gate electrode and a dummy electrode. The gate electrode is provided inside the gate trench. The dummy electrode is provided inside the dummy trench and is electrically connected to the second electrode. The gate trench is arranged adjacent to another of the gate trenches on at least one sidewall side. First portions between adjacent gate trenches are covered with the interlayer insulating film and are electrically floating.

[0022] In the semiconductor device according to the present invention, in the above-described invention, the third semiconductor region is provided in the first portion and a second portion between the gate trench and the dummy trench adjacent to each other, and the second electrode is electrically connected to the third semiconductor region in the second portion.

[0023] Moreover, in the semiconductor device according to the present invention, in the above-mentioned invention, a third portion between the adjacent dummy trenches is covered with the interlayer insulating film and is electrically floating.

[0024] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, two or more of the first portions are arranged between the second portions adjacent to each other so that the gate trenches are adjacent to each other.

[0025] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the third portions between adjacent dummy trenches are arranged between the second portions that are adjacent to each other so that the dummy trenches are adjacent to each other, and in a number greater than the number of first portions between the second portions that are adjacent to each other so that the gate trenches are adjacent to each other.

[0026] Furthermore, the semiconductor device according to the present invention is the above-described one, further comprising: a first element region in which a first element is disposed on the semiconductor substrate; and a second element region adjacent to the first element region in which a second element is disposed. The first element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the gate trench, the dummy trench, the gate electrode, the dummy electrode, the second electrode, and the third electrode. The second element includes the first semiconductor region, the second semiconductor region, the dummy trench, the dummy electrode, the second electrode, the third electrode, and a fifth semiconductor region of a first conductivity type. The fifth semiconductor region is provided between the back surface of the semiconductor substrate and the first semiconductor region and is electrically connected to the third electrode. The fifth semiconductor region has a higher impurity concentration than the first semiconductor region.

[0027] According to the above-described invention, the parasitic capacitance formed between the first and third electrodes in the insulating film on the inner wall of the gate trench during turn-on increases, thereby reducing the dV / dt of the voltage applied between the third and second electrodes during reverse recovery of the anti-parallel connected diodes (reverse recovery dV / dt). Furthermore, when the reverse recovery dV / dt is maintained, the gate resistance can be reduced to increase the dI / dt (rate of change of current per unit time) of the current flowing between the third and second electrodes, thereby suppressing turn-on loss Eon. [Effects of the Invention]

[0028] The semiconductor device according to the present invention has an advantage that the trade-off relationship between the turn-on loss Eon and the reverse recovery dV / dt can be improved. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a perspective view showing a structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view showing a layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. [Figure 3]FIG. 10 is a perspective view showing another example of the structure of the semiconductor device according to the first embodiment. [Figure 4] 10 is a plan view showing another example of the layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. FIG. [Figure 5] FIG. 10 is a perspective view showing the structure of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a perspective view showing the structure of a semiconductor device according to a third embodiment. [Figure 7] FIG. 10 is a perspective view showing the structure of a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 10 is a perspective view showing the structure of a semiconductor device according to a fifth embodiment. [Figure 9] FIG. 10 is a characteristic diagram showing the trade-off relationship between turn-on loss Eon and reverse recovery dV / dt in the embodiment. [Figure 10] FIG. 1 is a perspective view showing the structure of a conventional semiconductor device. [Figure 11] FIG. 10 is a perspective view showing another example of the structure of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0030] Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0031] (Embodiment 1) The structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a perspective view showing the structure of the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing the layout of FIG. 1 as viewed from the front surface side of the semiconductor substrate. FIG. 3 is a perspective view showing another example of the structure of the semiconductor device according to the first embodiment. FIG. 4 is a plan view showing another example of the layout of FIG. 3 as viewed from the front surface side of the semiconductor substrate. FIGS. 2 and 4 show n-type semiconductor devices in FIGS. 1 and 3, respectively. + type emitter region 4 and p + The layout of the contact region 5 is shown in Figs. + The mold contact region 5 is shown hatched, and the insulating film 7 is not shown.

[0032] The semiconductor device 31 according to the first embodiment shown in FIGS. 1 and 2 is a trench-gate IGBT having a plurality of trenches 6 in an active region on the front surface side of a semiconductor substrate (semiconductor chip) 10, with electrodes (first electrodes) 8 buried therein via an insulating film 7. The active region is a region through which a main current (collector-emitter current) flows when the IGBT is in an on-state, and is where basic unit sections 21, described below, are arranged. The active region has, for example, a substantially rectangular planar shape (not shown) and is arranged in the center of the semiconductor substrate. The active region is surrounded by an edge termination region (not shown).

[0033] The edge termination region is a region between the active region and the edge (chip edge) of the semiconductor substrate 10, and is a region that alleviates the electric field on the front surface side of the semiconductor substrate 10 and maintains a breakdown voltage. The breakdown voltage is the limit voltage at which an element does not malfunction or break down. In the edge termination region, breakdown voltage structures such as a field limiting ring (FLR), a mesa structure, a junction termination extension (JTE) structure, and a field plate are arranged.

[0034] The trenches 6 are arranged in stripes extending in a first direction X (longitudinal direction) parallel to the front surface of the semiconductor substrate 10 (see FIG. 2). All of the trenches 6 have approximately the same width (width in a second direction Y) and are arranged at equal intervals in a second direction Y (transverse direction) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X. "Approximately the same width" means that the widths are the same within a range that includes tolerances due to variations in the manufacturing process. Specifically, the tolerance for the width of the trenches 6 due to variations in the manufacturing process is approximately ±10% of the design value.

[0035] If the trenches 6 are not arranged at equal intervals, the breakdown voltage of the entire semiconductor device 31 (the entire semiconductor substrate 10) will be low, being determined by the breakdown voltage determined by the portions where the intervals between adjacent trenches 6 are relatively wide. By arranging the trenches 6 at equal intervals, the electric field is distributed approximately uniformly to all trenches 6, and the electric field strength at the bottom of each trench 6 can be reduced, thereby improving the breakdown voltage of the entire semiconductor device 31. The narrower the intervals between adjacent trenches 6, the smaller the electric field strength at the bottom of the trenches 6, making it possible to achieve a higher breakdown voltage.

[0036] All of the trenches 6 extend, for example, from the active region to the edge termination region and terminate in the edge termination region. Inside the trenches 6, an insulating film 7 is provided along the inner wall of the trench 6, and an electrode 8 is provided on the insulating film 7 so as to fill the trench 6. Of the multiple trenches 6, the electrode 8 inside some trenches (gate trenches) 6a is a gate electrode 8a of the gate potential of the IGBT (semiconductor device 31), and is electrically connected to a gate pad (electrode pad: not shown) at a portion not shown.

[0037] Of the multiple trenches 6, the electrodes 8 inside the remaining trenches (dummy trenches) 6b excluding the gate trench 6a are dummy electrodes 8b at the emitter potential of the IGBT (semiconductor device 31). All of the dummy electrodes 8b are electrically connected to the emitter electrode (second electrode) 11 at portions (e.g., longitudinal ends of the gate trench 6a) not shown. Providing the dummy electrodes 8b can prevent the total gate charge amount from becoming too high.

[0038] Specifically, for example, a gate runner (not shown) is provided on the front surface of the semiconductor substrate 10 via a field oxide film. The gate electrode 8a is connected to the gate runner at the end of the gate trench 6a and is electrically connected to a gate pad via the gate runner. The end of the dummy trench 6b terminates, for example, closer to the active region than the gate runner. At the end of the dummy trench 6b, the dummy electrode 8b and the emitter electrode 11 are directly connected or electrically connected.

[0039] A plurality of basic unit sections 21, each including two gate trenches 6a and n times the number of gate trenches 6a (where n is a natural number of 2 or more) of dummy trenches 6b, are arranged in parallel in the second direction Y. The two gate trenches 6a in each basic unit section 21 are arranged adjacent to each other. The arrangement of the dummy trenches 6b in each basic unit section 21 can be set as appropriate, but it is preferable that the gate trenches 6a and the dummy trenches 6b be arranged regularly over the entire semiconductor substrate 10 and that they be arranged in the same order in all basic unit sections 21.

[0040] For example, (2×n) dummy trenches 6b are arranged for every two gate trenches 6a in the second direction Y, so that a plurality of basic unit parts 21, each including two gate trenches 6a and (2×n) dummy trenches 6b, are arranged in parallel in the second direction Y. FIGS. 1 and 2 show a basic unit part 21 including two gate trenches 6a and four (n=2) dummy trenches 6b. Furthermore, the gate electrode 8a is labeled "Gate" and the dummy electrode 8b is labeled "Emitter" (the same applies to FIGS. 3 to 8).

[0041] The ratio of the number of gate trenches 6a to the number of dummy trenches 6b in the basic unit 21 is determined, for example, according to the total gate charge of the semiconductor device 31 and the drive capability (current supply capability) of a drive circuit that supplies a gate current (drive current) to the semiconductor device 31. The total gate charge of the semiconductor device 31 is the amount of charge (input capacitance: the sum of the gate-emitter capacitance and the gate-collector capacitance) charged to the gate electrode 8a required to turn on the semiconductor device 31.

[0042] The surface region of the front surface of the semiconductor substrate 10 is separated by trenches 6, and forms convex portions in portions (mesa portions) 20 between adjacent trenches 6. The mesa portions 20, including a first mesa portion (first portion) 20a between adjacent gate trenches 6a, a second mesa portion (second portion) 20b between adjacent gate trenches 6a and dummy trenches 6b, and a third mesa portion (third portion) 20c between adjacent dummy trenches 6b, all have the same cell structure.

[0043] One first mesa portion 20a is disposed between two second mesa portions 20b. One second mesa portion 20b is disposed between the first mesa portion 20a and the third mesa portion 20c. The third mesa portion 20c is disposed between two second mesa portions 20b. That is, the first mesa portions 20a and the third mesa portions 20c are disposed so as to be alternately sandwiched between the second mesa portions 20b. The number of third mesa portions 20c disposed between the second mesa portions 20b may be greater than the number of first mesa portions 20a disposed between the second mesa portions 20b (for example, three).

[0044] All mesa portions 20 (20a, 20b, 20c) have n-type accumulation regions 2, p-type base regions 3, n + type emitter region 4 and p + The n-type accumulation region 2, the p-type base region (second semiconductor region) 3, and the n-type contact region 5 are selectively provided. + type emitter region (third semiconductor region) 4 and p + type contact region 5 and the n +Type buffer area 12 and p + The type collector region (fourth semiconductor region) 13 is a diffusion region formed by ion implantation into the semiconductor substrate 10 made of, for example, silicon (Si).

[0045] n - The n-type semiconductor substrate 10 has an n-type accumulation region 2, a p-type base region 3, and an n-type + Type emitter region 4, p + Type contact region 5, n + Type buffer area 12 and p + The part excluding the collector region 13 is n - This becomes the n-type drift region (first semiconductor region) 1. - The p-type drift region 1 extends from the active region to the edge of the semiconductor substrate 10. The p-type base region 3 is formed between the front surface of the semiconductor substrate 10 and the n-type - The n-type accumulation region 2 is formed between the p-type base region 3 and the n-type drift region 1. - The metal layer is provided between the metal layer and the mold drift region 1 and in contact with these regions.

[0046] The n-type accumulation region 2 acts as a barrier to minority carriers (holes) when the IGBT is turned on, - The n-type drift region 1 functions as a carrier storage (CS) region that accumulates minority carriers near the boundary with the n-type accumulation region 2. When the IGBT is turned on, minority carriers accumulate near the n-type accumulation region 2, which increases the IE effect and reduces conduction loss. The n-type accumulation region 2 does not necessarily have to be provided. If the n-type accumulation region 2 is not provided, the p-type base region 3 and the n-type - The mold drift region 1 is in contact with the mold drift region 1.

[0047] n - The n-type drift region 1, the n-type accumulation region 2, and the p-type base region 3 extend linearly in the first direction X in each mesa portion 20. -In each mesa portion 20, the n-type drift region 1, the n-type accumulation region 2, and the p-type base region 3 reach the sidewalls of the trenches 6 on both sides in the second direction Y (the gate trench 6a in the portion adjacent to the gate trench 6a, and the dummy trench 6b in the portion adjacent to the dummy trench 6b) and contact the insulating film 7 on the sidewalls of the trenches 6. - The mold drift regions 1 are joined together below the trenches 6 .

[0048] n + type emitter region 4 and p + The emitter region 4 and the p-type contact region 5 are selectively provided in each mesa portion 20 between the front surface of the semiconductor substrate 10 and the p-type base region 3, and in contact with the p-type base region 3. + The contact regions 5 are alternately and repeatedly arranged adjacent to each other in the first direction X in each mesa portion 20 (FIG. 2). + The contact regions 5 are arranged in the first direction X at intervals of p + It may be wider or narrower than the width of the mold contact region 5 in the first direction X.

[0049] The n of the adjacent mesa portions 20 + The n-type emitter regions 4 are adjacent to each other in the second direction Y. + type emitter region 4 and p + The contact regions 5 extend in a stripe shape in the second direction Y, sandwiching the trenches 6 therebetween, and in each mesa portion 20, reach the side walls of the trenches 6 on both sides in the second direction Y (the gate trench 6a in the portion adjacent to the gate trench 6a, and the dummy trench 6b in the portion adjacent to the dummy trench 6b), and contact the insulating film 7 on the side walls of the trenches 6.

[0050] The trenches 6 (gate trenches 6a and dummy trenches 6b) are formed by arranging the trenches 6a and 6b in a depth direction Z from the front surface of the semiconductor substrate 10. + Type emitter region 4, p + through the p-type contact region 5, the p-type base region 3 and the n-type accumulation region 2, -The trenches 6 terminate inside the p-type drift region 1. All of the trenches 6 have approximately the same depth. "Approximately the same depth" means that they are the same depth within a range that includes tolerances due to variations in the manufacturing process. A channel (n-type inversion layer) is formed only in the portion of the second mesa portion 20b along the gate trench 6a of the p-type base region 3.

[0051] An interlayer insulating film 9 is provided on the front surface of the semiconductor substrate 10. The interlayer insulating film 9 covers the first mesa portion 20a, the gate electrode 8a, and the dummy electrode 8b. The gate electrode 8a is electrically insulated from the emitter electrode 11 by the interlayer insulating film 9. The first mesa portion 20a is electrically insulated from the emitter electrode 11 by the interlayer insulating film 9 and is electrically floating. Therefore, the p-type base region 3 of the first mesa portion 20a, the n-type base region 11, and the n-type base region 11 are electrically insulated from the emitter electrode 11 by the interlayer insulating film 9. + type emitter region 4 and p + The mold contact region 5 is electrically floating.

[0052] The second and third mesa portions 20b and 20c are exposed to different contact holes in the interlayer insulating film 9. The second and third mesa portions 20b and 20c are in contact with the emitter electrode 11 through the contact holes in the interlayer insulating film 9, and are fixed to the potential (emitter potential) of the emitter electrode 11. Therefore, the p-type base region 3 of the second mesa portion 20b and the n-type base region 4 of the n-type base region 4 are fixed to the potential (emitter potential) of the emitter electrode 11. + type emitter region 4 and p + The p-type contact region 5 and the p-type base region 3 of the third mesa portion 20c, + type emitter region 4 and p + The contact region 5 is fixed to the emitter potential.

[0053] By electrically floating the first mesa portion 20a, after the IGBT (semiconductor device 31) is turned on, the potential of the first mesa portion 20a decreases over time from a high potential (e.g., about 20 V) immediately after the IGBT is turned on, eventually fluctuating to a potential close to the emitter potential (e.g., ground potential), which is the lowest potential. Because a large amount of charge is required for this potential fluctuation of the first mesa portion 20a, the apparent gate-collector capacitance increases. This reduces the dV / dt (reverse recovery dV / dt) of the anode-cathode voltage during reverse recovery of the diode connected inversely in parallel with the IGBT.

[0054] If the reverse recovery dV / dt is maintained at the same level as in the conventional structure (see FIGS. 10 and 11), the gate resistance can be reduced, thereby reducing the turn-on loss Eon. The diode connected inversely in parallel to the IGBT is, for example, a free wheeling diode (FWD) for commutating the load current when an inductive load such as a motor is controlled by the switching operation of the bridge-connected IGBTs when the IGBT is used as an inverter device. The diode connected inversely in parallel to the IGBT may be an external component (not shown) or may be built into the semiconductor substrate 10 (see FIGS. 7 and 8).

[0055] The emitter electrode 11 is n-type in the second and third mesa portions 20b and 20c. + type emitter region 4 and p + The emitter electrode 11 is in ohmic contact with the p-type contact region 5. + The n-type contact region 5 is electrically connected to the p-type base region 3 of the second and third mesas 20b and 20c. + The lower surface of the p-type emitter region 4 forms a pn junction with the upper surface of the p-type base region 3. + The contact region 5 may not be provided. + When the contact region 5 is not provided, the emitter electrode 11 is p-type in the second and third mesa portions 20b and 20c. + The p-type contact region 5 is in contact with the p-type base region 3 .

[0056] The emitter electrode 11 covers almost the entire surface of the active region. A gate pad and a gate runner are provided on the front surface of the semiconductor substrate 10, spaced apart from the emitter electrode 11. All of the gate electrodes 8a are electrically connected to the gate pad via the gate runner. The gate runner is provided in the edge termination region and surrounds the periphery of the active region. The top layer on the front surface of the semiconductor substrate 10 is a passivation film. The portion of the emitter electrode 11 exposed through the opening in the passivation film becomes the emitter pad (electrode pad).

[0057] The back surface of the semiconductor substrate 10 and the n - Between the n-type drift region 1 and + Type buffer area 12 and p + A collector region 13 is provided. + Type buffer area 12 and p + The collector region 13 extends from the active region to the edge of the semiconductor substrate 10. + The n-type collector region 13 is connected to the back surface of the semiconductor substrate 10. - The n-type drift region 1 is provided between the n-type drift region 1 and the n-type drift region 2. + The mold buffer area 12 is p + collector region 13 and n - The metal layer is provided between the metal layer and the mold drift region 1 and in contact with these regions.

[0058] n + The n-type buffer region 12 is - The electric field generated in the drift region 1 is p + It has the function of preventing the metal particles from reaching the collector region 13. + The mold buffer area 12 may not be provided. + If the mold buffer area 12 is not provided, p + collector region 13 and n - The collector electrode (third electrode) 14 is provided on the entire rear surface of the semiconductor substrate 10. The collector electrode 14 is a p + An ohmic contact is made to the collector region 13 .

[0059] 3 and 4, the mesa portion 20 may have different cell structures for the first to third mesa portions 20a to 20c. In this case, for example, + type emitter region 4 and p + The layout of the contact region 5 as viewed from the front surface of the semiconductor substrate 40 differs among the first to third mesa portions 20a to 20c. Specifically, the first mesa portion 20a includes an n-type accumulation region 2, a p-type base region 3, and an n-type + 3 and 4, the first mesa portion 20a is provided with a p-type emitter region 4. + A mold contact region 5 may be provided.

[0060] The second mesa portion 20b includes an n-type accumulation region 2, a p-type base region 3, and an n + type emitter region 4 and p + The third mesa portion 20c is provided with an n-type accumulation region 2, a p-type base region 3, and a p-type contact region 5. + The third mesa portion 20c not adjacent to the gate trench 6a is provided with an n-type contact region 5. + No type emitter region 4 is provided. - The n-type drift region 1, the n-type accumulation region 2, and the p-type base region 3 extend linearly in the first direction X in all mesas 20, similar to the cell structure of FIGS.

[0061] More specifically, when the first to third mesa portions 20a to 20c have different cell structures, in the first mesa portion 20a, n + The p-type emitter region 4 is provided over the entire area between the front surface of the semiconductor substrate 10 and the p-type base region 3, and is in contact with the insulating film 7 on the side walls of the gate trenches 6a on both sides (see FIG. 4). + When the p-type contact region 5 is provided, + The mold contact regions 5 may be scattered in the first direction X, or may extend linearly in the first direction X (not shown).

[0062] In the second mesa portion 20b, n +The emitter region 4 is adjacent to the gate trench 6a, contacts the insulating film 7 on the sidewall of the gate trench 6a, and extends linearly in the first direction X along the gate trench 6a. + The contact region 5 is connected to the dummy trench 6b and the n-type contact region 5c. + The third mesa portion 20c contacts the insulating film 7 on the sidewall of the dummy trench 6b between the p-type emitter region 4 and the third mesa portion 20c, and extends linearly in the first direction X along the dummy trench 6b. + The p-type contact region 5 is provided over the entire area between the front surface of the semiconductor substrate 10 and the p-type base region 3, and is in contact with the insulating film 7 on the side walls of the dummy trenches 6b on both sides (see FIG. 4).

[0063] The gate trench 6a is formed by extending from the front surface of the semiconductor substrate 10 in the depth direction Z. + through the p-type emitter region 4, the p-type base region 3 and the n-type accumulation region 2, - The dummy trench 6b extends from the front surface of the semiconductor substrate 10 in the depth direction Z to the inside of the semiconductor substrate 10. + through the p-type contact region 5, the p-type base region 3 and the n-type accumulation region 2, - The emitter electrode 11 terminates inside the n-type drift region 1. The emitter electrode 11 is + type emitter region 4 and p + ohmic contact with the contact region 5, and + The metal layer 10 makes ohmic contact with the metal contact region 5 .

[0064] The operation of the semiconductor device 31 according to the first embodiment will be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 8a while a positive voltage (forward voltage) relative to the emitter electrode 11 is applied to the collector electrode 14, a channel (n-type inversion layer) is formed only in the portion of the p-type base region 3 in the second mesa portion 20b along the gate trench 6a. + collector region 13 and n + The pn junction with the type buffer region 12 is forward biased, and the IGBT (semiconductor device 31) is turned on.

[0065] When the IGBT is turned on, p + Type collector region 13 to n + n through the type buffer region 12 - Holes are injected into the n-type drift region 1. + The n-type emitter region 4 is connected to the n-type accumulation region 2 via the channel. - Electrons are injected into the n-type drift region 1 - The carrier concentration in the drift region 1 increases, causing conductivity modulation. - The resistance value of the type drift region 1 is reduced, and the forward voltage drop is suppressed, so the IGBT becomes a switching device that turns on at a low on-voltage.

[0066] As described above, according to the first embodiment, a trench-gate IGBT is provided in which some of the plurality of trenches arranged at equal intervals on the front surface side of a semiconductor substrate are gate trenches in which gate electrodes are embedded, and the remaining trenches are dummy trenches in which dummy electrodes of emitter potential are embedded. A basic unit in which the trenches (gate trenches and dummy trenches) are repeatedly arranged includes two gate trenches arranged adjacent to each other. A first mesa portion between these adjacent gate trenches is electrically floating.

[0067] By electrically floating the first mesa between adjacent gate trenches, the gate-collector capacitance increases, making it possible to reduce reverse recovery dV / dt. Furthermore, while maintaining reverse recovery dV / dt, the gate resistance can be reduced to increase the collector-emitter current dI / dt (rate of current change per unit time), thereby suppressing turn-on loss Eon. This improves the trade-off between turn-on loss Eon and reverse recovery dV / dt.

[0068] (Embodiment 2) Next, the structure of the semiconductor device according to the second embodiment will be described. Fig. 5 is a perspective view showing the structure of the semiconductor device according to the second embodiment. The semiconductor device 32 according to the second embodiment shown in Fig. 5 differs from the semiconductor device 31 according to the first embodiment (see Figs. 1 and 2) in that the third mesa portions 20c between the adjacent dummy trenches 6b are covered with the interlayer insulating film 9 and are electrically floating.

[0069] That is, in the second embodiment, the first mesa portion 20a between the adjacent gate trenches 6a and the third mesa portion 20c between the adjacent dummy trenches 6b are covered with the interlayer insulating film 9, are electrically insulated from the emitter electrode 11, and are electrically floating. The second mesa portion 20b between the adjacent gate trenches 6a and dummy trenches 6b is fixed to the potential of the emitter electrode 11, as in the first embodiment.

[0070] Some or all of the third mesa portions 20c among the multiple third mesa portions 20c in the basic unit portion 21 may be set to be electrically floating. It is preferable that the gate trenches 6a and dummy trenches 6b are arranged in the same manner in all the basic unit portions 21, and that the third mesa portions 20c at the same positions in all the basic unit portions 21 are set to be electrically floating.

[0071] In the semiconductor device 32 according to the second embodiment, for example, the cell structure shown in FIGS. 3 and 4 may be applied, and the first to third mesas 20a to 20c may have different cell structures.

[0072] As described above, according to the second embodiment, the first mesa portions between adjacent gate trenches are electrically floating, and therefore the same effects as those of the first embodiment are obtained. Furthermore, according to the second embodiment, the third mesa portions between adjacent dummy trenches are electrically floating, and therefore the on-voltage can be lowered and the conduction loss (loss when a collector-emitter current flows) can be reduced. The more third mesa portions that are electrically floating, the lower the on-voltage can be.

[0073] (Embodiment 3) Next, the structure of a semiconductor device according to embodiment 3 will be described. Fig. 6 is a perspective view showing the structure of a semiconductor device according to embodiment 3. A semiconductor device 33 according to embodiment 3 shown in Fig. 6 differs from the semiconductor device 31 according to embodiment 1 (see Figs. 1 and 2) in that a basic unit portion 23 in which the arrangement of trenches 6 is repeated includes three or more gate trenches 6a, all of these gate trenches 6a are arranged adjacent to one another in the second direction Y, and two or more first mesa portions 20a are adjacent to one another in the second direction Y.

[0074] Specifically, in the third embodiment, a plurality of basic unit sections 23, each including m (where m is a natural number of 3 or more) gate trenches 6a and (m×n) (where n is a natural number of 2 or more) dummy trenches 6b, are arranged in parallel in the second direction Y. All of the gate trenches 6a within the basic unit section 23 are arranged adjacent to each other. The arrangement of the dummy trenches 6b within the basic unit section 23 can be set as appropriate, but it is preferable that the gate trenches 6a and dummy trenches 6b be arranged in the same order within all of the basic unit sections 23.

[0075] For example, (m×n) dummy trenches 6b are arranged for every m gate trenches 6a arranged in the second direction Y, so that a plurality of basic unit parts 23, each including m gate trenches 6a and (m×n) dummy trenches 6b, are arranged in parallel in the second direction Y. FIG. 6 shows a basic unit part 23 including three (m=3) gate trenches 6a and six (n=2) dummy trenches 6b. The more the number (m) of gate trenches 6a arranged adjacent to each other in the second direction Y increases, the greater the effect of reducing turn-on loss Eon.

[0076] All of the first mesa portions 20a between adjacent gate trenches 6a are covered with the interlayer insulating film 9, as in the first embodiment, and are electrically insulated from the emitter electrode 11 and are electrically floating. The second mesa portions 20b between adjacent gate trenches 6a and dummy trenches 6b and the third mesa portions 20c between adjacent dummy trenches 6b are in contact with the emitter electrode 11 via contact holes in the interlayer insulating film 9, as in the first embodiment, and are fixed to the potential of the emitter electrode 11.

[0077] Two or more first mesas 20a are arranged between two second mesas 20b. Two or more third mesas 20c are arranged between two second mesas 20b. The number of third mesas 20c between the second mesas 20b may be greater (for example, four or more) than the number of first mesas 20a between the second mesas 20b. The configurations of the first to third mesas 20a to 20c in the third embodiment are similar to those of the first to third mesas 20a to 20c in FIG. 3, respectively.

[0078] In the semiconductor device 33 according to the third embodiment, for example, the cell structure shown in FIGS. 3 and 4 may be applied, and the first to third mesas 20a to 20c may have different cell structures.

[0079] The second embodiment (see FIG. 5) may be applied to the semiconductor device 33 according to the third embodiment, and the third mesa portion 20c may be covered with the interlayer insulating film 9 to make it electrically floating.

[0080] As described above, according to the third embodiment, the effect of the first embodiment can be further enhanced by increasing the number of gate trenches arranged adjacent to each other in the second direction.

[0081] (Fourth embodiment) Next, the structure of the semiconductor device according to the fourth embodiment will be described. Fig. 7 is a perspective view showing the structure of the semiconductor device according to the fourth embodiment. The semiconductor device 34 according to the fourth embodiment shown in Fig. 7 is an RC-IGBT (Reverse Conducting IGBT) obtained by incorporating a diode into the semiconductor device 31 according to the first embodiment (see Figs. 1 and 2).

[0082] Specifically, in the fourth embodiment, an IGBT section (first element region) 41 and a diode section (second element region) 42 are arranged adjacent to each other in the second direction in the active region of the semiconductor substrate 10. An IGBT is arranged in the IGBT section 41. The configuration of the IGBT in the IGBT section 41 is the same as that of the semiconductor device 31 according to the first embodiment. At least one trench 6 (preferably two or more trenches 6) closest to the diode section 42 of the IGBT section 41 is a dummy trench 6b.

[0083] The trench 6 on the diode section 42 side of the IGBT section 41 is used as a dummy trench 6b, and the farther the gate trench 6a is from the diode section 42, the more the mutual interference between the IGBT in the IGBT section 41 and the diode in the diode section 42 can be suppressed. + collector region 13 and the n + The cathode region 43 may be located at the boundary between the cathode region 43 and the SiO 2 layer.

[0084] The diode section 42 has a diode connected in anti-parallel to the IGBT of the IGBT section 41. The diode of the diode section 42 functions as a FWD for commutating a load current when the IGBT of the IGBT section 41 is used as an inverter device, for example. The diode section 42 also has trenches 6 arranged therein, similar to the IGBT section 41. All of the trenches 6 in the diode section 42 are dummy trenches 6b.

[0085] A dummy electrode 8b is provided inside the dummy trench 6b of the diode section 42 via an insulating film 7, similar to the dummy trenches 6b of the IGBT section 41. In the fourth mesa section 20d between adjacent dummy trenches 6b in the diode section 42, only a p-type base region 3 is provided throughout the entire fourth mesa section 20d. The p-type base region 3 in the fourth mesa section 20d functions as an anode region.

[0086] The fourth mesa portion 20d has an n-type accumulation region 2 and an n + Although not shown, the fourth mesa portion 20d has a p-type emitter region 4 formed in the entire area between the front surface of the semiconductor substrate 10 and the p-type base region 3. + A contact region 5 may be provided. The fourth mesa portion 20d is in contact with the emitter electrode 11 through a contact hole in the interlayer insulating film 9, and is fixed to the potential of the emitter electrode 11.

[0087] The emitter electrode 11 is in contact with and electrically connected to the p-type base region 3 in the fourth mesa portion 20d. + When the contact region 5 is provided, the emitter electrode 11 is + ohmic contact with the p-type contact region 5, + The emitter electrode 11 is electrically connected to the p-type base region 3 via the p-type contact region 5. The emitter electrode 11 also serves as the anode electrode of the diode section .

[0088] The back surface of the semiconductor substrate 10 is connected to the back surface of the semiconductor substrate 10 in the diode section 42. + The entire area between the mold buffer region 12 and + A type cathode region (fifth semiconductor region) 43 is provided. + The n-type cathode region 43 is a diffusion region formed by ion implantation into the semiconductor substrate 10. + The impurity concentration of the n-type cathode region 43 is + The impurity concentration is higher than that of the mold buffer region.

[0089] n +The cathode region 43 is a p-type cathode region of the IGBT section 41. + The collector electrode 14 is adjacent to the p-type collector region 13 in the second direction Y. + ohmic contact with the n-type collector region 13 and + The collector electrode 14 is in ohmic contact with the cathode region 43. The collector electrode 14 also serves as the cathode electrode of the diode section .

[0090] In the semiconductor device 34 according to the fourth embodiment, for example, the cell structure of FIGS. 3 and 4 may be applied, and the first to third mesas 20a to 20c may have different cell structures.

[0091] The third embodiment (see FIG. 6) may be applied to the semiconductor device 34 according to the fourth embodiment, and the IGBT of the IGBT section 41 may be the semiconductor device 33 according to the third embodiment.

[0092] As described above, according to the fourth embodiment, even when a diode is built into the semiconductor device of the first embodiment to form an RC-IGBT, the same effects as those of the first embodiment can be obtained for the IGBT that constitutes the RC-IGBT.

[0093] (Embodiment 5) Next, the structure of a semiconductor device according to a fifth embodiment will be described. Fig. 8 is a perspective view showing the structure of a semiconductor device according to the fifth embodiment. A semiconductor device 35 according to the fifth embodiment shown in Fig. 8 is obtained by applying the second embodiment (see Fig. 5) to the semiconductor device 34 according to the fourth embodiment (see Fig. 7), with the third mesa portion 20c between adjacent dummy trenches 6b in the IGBT portion 41 being covered with an interlayer insulating film 9 and being electrically floating.

[0094] As described above, according to the fifth embodiment, the first mesa portion between adjacent gate trenches and the third mesa portion between adjacent dummy trenches are electrically floating, and therefore, the fifth embodiment has the same effects as the first, third, and fourth embodiments, as well as the second embodiment.

[0095] (Example) The trade-off relationship between turn-on loss Eon and reverse recovery dV / dt of the semiconductor device 31 according to the first embodiment (hereinafter referred to as the example; see FIGS. 1 to 3) was examined. FIG. 9 is a characteristic diagram showing the trade-off relationship between turn-on loss Eon and reverse recovery dV / dt of the example. FIG. 9 shows the results of measuring the trade-off relationship between turn-on loss Eon and reverse recovery dV / dt of the example and conventional examples 1 and 2. Conventional examples 1 and 2 are the conventional semiconductor devices 131 and 132 described above (see FIGS. 10 and 11).

[0096] Conventional Example 1 differs from the Examples in that the arrangement of the gate trenches 106a and dummy trenches 106b is different and there is no first mesa portion between adjacent gate trenches 106a. Conventional Example 2 differs from the Examples in that the first mesa portions 120a between adjacent gate trenches 106a are fixed to the potential (emitter potential) of the emitter electrode 111. In both Conventional Examples 1 and 2, the potential of all mesa portions 120 in the on state is always the lowest potential, the emitter potential (e.g., ground potential), and does not fluctuate.

[0097] 9, it was confirmed that the Example can improve the trade-off relationship between turn-on loss Eon and reverse recovery dV / dt compared to Conventional Examples 1 and 2. In FIG. 9, the more the trade-off curve between turn-on loss Eon and reverse recovery dV / dt moves diagonally downward to the left (the direction in which turn-on loss Eon approaches 0 kV / μs and reverse recovery dV / dt approaches 0 mJ), the more the trade-off relationship between turn-on loss Eon and reverse recovery dV / dt is improved.

[0098] When the Example and Conventional Example 2 are compared, for example, when the reverse recovery dV / dt is 5 kV / μs, it is found that the Example has a 40% reduction in turn-on loss Eon compared to Conventional Example 2 in which the first mesa portion 120a between adjacent gate trenches 106a is fixed to the potential of the emitter electrode 111. Therefore, it was confirmed that the trade-off relationship between the turn-on loss Eon and the reverse recovery dV / dt is improved by electrically floating the first mesa portion 20a between adjacent gate trenches 6a as in the Example.

[0099] Although not shown in the figures, the present inventors have confirmed that the semiconductor device 32 according to the second embodiment (see FIG. 5) also has a trade-off curve between turn-on loss Eon and reverse recovery dV / dt that is similar to that of the example. Although not shown in the figures, the present inventors have confirmed that the semiconductor device 33 according to the third embodiment (see FIG. 6) has a turn-on loss Eon that is reduced by 45% compared to Conventional Example 2, for example, when the reverse recovery dV / dt is 5 kV / μs.

[0100] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, while the above-described embodiments describe an IGBT alone or an RC-IGBT, the present invention is not limited to these and can be applied to a semiconductor device having an IGBT section in which an IGBT is arranged. Furthermore, while the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0101] As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0102] 1n - Type Drift Region 2 n-type accumulation region 3 p-type base region 4n + Type emitter area 5 p + Mold contact area 6. Trench 6a Gate trench 6b Dummy trench 7. Insulating film 8a Gate electrode 8b Dummy electrode 9 Interlayer insulating film 10. Semiconductor substrate 11 Emitter electrode 12n + Type buffer area 13 p + Type Collector Region 14 Collector electrode 20, 20a, 20b, 20c Mesa section 21,23 Basic Unit 31~35 Semiconductor devices 41 IGBT section 42 Diode section 43n + Type cathode area X: the first direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. a first semiconductor region of a first conductivity type provided inside a semiconductor substrate; a second semiconductor region of a second conductivity type provided between the front surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided between the front surface of the semiconductor substrate and the second semiconductor region; a fourth semiconductor region of a second conductivity type provided between the back surface of the semiconductor substrate and the first semiconductor region; a trench provided on a front surface of the semiconductor substrate; a first electrode provided inside the trench via an insulating film; an interlayer insulating film provided on a front surface of the semiconductor substrate and covering the first electrode; a second electrode provided on the front surface of the semiconductor substrate and electrically connected to the second semiconductor region and the third semiconductor region via a contact hole in the interlayer insulating film; a third electrode provided on a rear surface of the semiconductor substrate and electrically connected to the fourth semiconductor region; Equipped with The trenches are arranged at equal intervals, some of the plurality of trenches are gate trenches that penetrate the third semiconductor region and the second semiconductor region to reach the first semiconductor region; the remaining trenches excluding the gate trench are dummy trenches that penetrate the second semiconductor region and reach the first semiconductor region, The first electrode is a gate electrode provided inside the gate trench; a dummy electrode provided inside the dummy trench and electrically connected to the second electrode; the gate trench is disposed adjacent to another gate trench on at least one sidewall side, a first portion between the adjacent gate trenches being covered with the interlayer insulating film and being electrically floating;

2. the third semiconductor region is provided in the first portion and a second portion between the gate trench and the dummy trench adjacent to each other, 2. The semiconductor device according to claim 1, wherein the second electrode is electrically connected to the third semiconductor region at the second portion.

3. 3. The semiconductor device according to claim 1, wherein a third portion between the adjacent dummy trenches is covered with the interlayer insulating film and is electrically floating.

4. 3. The semiconductor device according to claim 2, wherein two or more of the first portions are arranged between the second portions adjacent to each other so that the gate trenches are adjacent to each other.

5. 5. The semiconductor device according to claim 2, wherein the third portions between adjacent dummy trenches are arranged between the second portions adjacent to each other so that the dummy trenches are adjacent to each other, and the number of the third portions between the second portions adjacent to each other so that the gate trenches are adjacent to each other is greater than the number of the first portions between the second portions adjacent to each other so that the gate trenches are adjacent to each other.

6. The semiconductor substrate is a first element region in which a first element is disposed; a second element region provided adjacent to the first element region and in which a second element is arranged, the first element includes the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the gate trench, the dummy trench, the gate electrode, the dummy electrode, the second electrode, and the third electrode; The second element is the first semiconductor region, the second semiconductor region, the dummy trench, the dummy electrode, the second electrode, and the third electrode; The semiconductor device according to any one of claims 1 to 5, further comprising: a fifth semiconductor region of the first conductivity type provided between the back surface of the semiconductor substrate and the first semiconductor region, electrically connected to the third electrode, and having a higher impurity concentration than the first semiconductor region.

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