Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device in which a higher negative gate voltage can be used and malfunctions can be prevented during switching by changing the gate voltage at which holes begin to accumulate at the sidewall interface of a trench to a higher negative voltage.SOLUTION: A silicon carbide semiconductor device 50 includes a first conductivity type silicon carbide semiconductor substrate 1, a first semiconductor layer 2 of the first conductivity type, a second semiconductor layer 6 of a second conductivity type, a first semiconductor region of the first conductivity type, a trench 16, a gate electrode 10 provided through a gate insulating film 9, a second semiconductor region 3 of a second conductivity type that covers the bottom surface of the trench 16, a third semiconductor region 4 of the second conductivity type between adjacent trenches 16, a first electrode 12, and a second electrode 13, and the third semiconductor region 4 is located apart from the side wall of the trench 16 at the end of the active region where the first semiconductor region is not provided, and is connected to the second semiconductor region 3.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material that will replace silicon (Si). Compared to conventional semiconductor devices that use silicon carbide as the semiconductor material, semiconductor devices that use silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the device in the on-state to one-hundredth of that of conventional semiconductor devices that use silicon as the semiconductor material, and the ability to be used in higher temperature environments (over 200°C). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.

[0003] To date, commercially available silicon carbide semiconductor devices include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) with planar gate structures or trench gate structures.

[0004] The planar gate structure is a MOS gate structure in which a flat MOS gate is provided on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. This allows for a higher density of unit cells (element constituent units) per unit area compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, thereby increasing the current density per unit area, and is therefore advantageous in terms of cost.

[0005] The structure of a conventional silicon carbide semiconductor device will be described using a trench MOSFET as an example. Fig. 9 is a cross-sectional view showing the structure of an active region of a conventional silicon carbide semiconductor device. The active region is a region where an element structure is formed and through which current flows when the device is in the on state.

[0006] The trench gate structure of the trench MOSFET 150 is + The front surface of the silicon carbide substrate 101 is - A silicon carbide epitaxial layer 102 is deposited. - n type silicon carbide epitaxial layer 102 + On the surface side opposite to the silicon carbide substrate 101 side, an n-type high concentration region 105 is provided. In the n-type high concentration region 105, a first p + The first p-type base region 103 is selectively provided between the trenches 116. + The lower second p at the same height as the mold base region 103 + The mold base region 104b and the lower second p + The upper second p + The second p + A mold base region 104 is provided.

[0007] The MOS gate of the trench gate structure is made up of a p-type base layer 106, an n + Type source region 107, p + The semiconductor device is composed of a contact region 108, a trench 116, a gate insulating film 109, and a gate electrode 110. An interlayer insulating film 111 is provided to cover the gate electrode 110 embedded in the trench 116. + The mold contact region 108 may not be provided. + type source region 107 and p + A source electrode 112 is provided on the contact region 108 via a barrier metal (not shown). + A back surface electrode 113 serving as a drain electrode is provided on the back surface of the silicon carbide substrate 101 .

[0008] In order to prevent malfunction due to turning on at a low voltage, the electron channel threshold is set as high as possible in such a trench MOSFET 150. To achieve this, the electron channel threshold is increased by, for example, making the p-type base layer 106 highly doped, providing a channel implantation layer 114 in which impurities are ion-implanted into the p-type base layer 106, or providing a large flat band voltage.

[0009] Fig. 10 is a cross-sectional view showing the structure of an active region end portion of a conventional silicon carbide semiconductor device. Fig. 11 is a top view showing the structure of the conventional silicon carbide semiconductor device. Fig. 9 is a cross-sectional view taken along line A-A' in Fig. 11, and Fig. 10 is a cross-sectional view taken along line B-B' in Fig. 11. Here, active region end portion 141 is a portion between an edge termination region (not shown) and active region 140, and specifically, n + The p-type source region 107 is not provided, and the p-type region (second p + The edge termination region is a region where the p-type base region 104, p-type base layer 106, and channel implantation layer 114 are provided. The edge termination region is a region that relieves the electric field on the front surface side of the substrate in the drift region and maintains the breakdown voltage.

[0010] As shown in FIG. 10, in the conventional silicon carbide semiconductor device, the upper second p + The mold base region 104a contacts the sidewall of the trench 116, and the lower second p + The mold base region 104b is the first p + The active region end 141 is connected to the base region 103. This prevents the potential from rising at the active region end 141.

[0011] In addition, a first and second p-type semiconductor substrate are provided near the sidewall of the trench, at a predetermined distance from the sidewall of the trench. + A semiconductor device is known that can improve the trade-off between lowering on-resistance and suppressing a decrease in gate threshold voltage by providing a third p-type region separate from the p-type region (see, for example, Patent Document 1 listed below).

[0012] In addition, the p-type base region has p + A high concentration region is provided, and p+ Type-rich region and n + Between the type source region and,p + A silicon carbide semiconductor device is known in which the portion between the high-concentration region and the outermost trench is made into a p-type silicon carbide epitaxial layer and exposed on the front surface of the semiconductor substrate, thereby improving current controllability through gate voltage control at high temperatures (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 2019-050352 [Patent Document 2] Japanese Patent Publication No. 2020-004876 Summary of the Invention [Problem to be solved by the invention]

[0014] Here, if the impurity concentration of the p-type base layer 106 or the channel implantation layer 114 is increased in order to increase the gate threshold voltage, the on-resistance increases, and therefore there is an upper limit to the impurity concentration. Furthermore, to prevent malfunction, a large negative gate bias of about −5 V, −10 V, or −15 V is preferable, but conventional silicon carbide semiconductor devices are designed to turn off at a gate voltage that does not accumulate holes.

[0015] However, depending on the plane orientation of the SiC channel, the type of trap, and the oxidation method of the gate insulating film 109, the voltage at which intrinsic holes begin to accumulate may be low. FIG. 12 is a cross-sectional view showing hole accumulation in the active region of a conventional silicon carbide semiconductor device. FIG. 13 is a cross-sectional view showing hole accumulation at the edge of the active region of a conventional silicon carbide semiconductor device. In conventional silicon carbide semiconductor devices, holes accumulate at the sidewall interface of the trench even when the negative gate bias is −3 V or −2 V, as shown in FIGS. 12 and 13, and these holes remain even when the device is turned on. This poses a problem in that a large negative gate bias cannot be obtained, which can cause malfunctions during switching.

[0016] In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a silicon carbide semiconductor device that enables the use of a higher negative gate voltage and prevents malfunction during switching by changing the gate voltage at which holes begin to accumulate at the sidewall interface of the trench to a higher negative voltage. [Means for solving the problem]

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. The silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type, which has a lower impurity concentration than the silicon carbide semiconductor substrate, provided on a front surface of the silicon carbide semiconductor substrate. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of the first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. A second semiconductor region of the second conductivity type is selectively provided inside the first semiconductor layer, covering a bottom surface of the trench. A third semiconductor region of a second conductivity type is selectively provided inside the first semiconductor layer and the second semiconductor layer between adjacent trenches and in contact with the second semiconductor layer. A first electrode is provided in contact with the second semiconductor layer and the first semiconductor region. A second electrode is provided on the back surface of the silicon carbide semiconductor substrate. The third semiconductor region is disposed apart from a sidewall of the trench at an end of the active region where the first semiconductor region is not provided, and is connected to the second semiconductor region.

[0018] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the second semiconductor region is arranged away from the bottom of the trench at an end of the active region where the first semiconductor region is not provided.

[0019] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first semiconductor layer and the second semiconductor layer are provided between the third semiconductor region and a sidewall of the trench at an end of the active region.

[0020] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the trenches are stripe-shaped, and the ends of the active regions are longitudinal ends of the trenches where the first semiconductor region is not provided between adjacent trenches.

[0021] According to the above-mentioned invention, the high concentration second p + The p-type base region (third semiconductor region of the second conductivity type) is separated from the sidewall of the trench. This prevents induced holes at the edge of the active region from diffusing into the low-impurity-concentration p-type base layer (second semiconductor layer of the second conductivity type). As a result, holes are prevented from accumulating at the sidewall interface of the gate insulating film in the active region at a negative gate voltage lower than the hole channel threshold of the p-type base layer. This makes it possible to use a higher negative gate voltage, preventing malfunctions during switching. [Effects of the Invention]

[0022] According to the silicon carbide semiconductor device of the present invention, by changing the gate voltage at which holes begin to accumulate at the sidewall interface of the trench to a high negative voltage, it becomes possible to use a higher negative gate voltage, thereby achieving the effect of preventing malfunction during switching. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a cross-sectional view showing a structure of an active region of a silicon carbide semiconductor device according to an embodiment. [Figure 2A] 1 is a cross-sectional view showing a structure of an end portion of an active region of a silicon carbide semiconductor device according to an embodiment; [Figure 2B] FIG. 10 is a cross-sectional view showing another structure of the active region end portion of the silicon carbide semiconductor device according to the embodiment. [Figure 3] 1 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 4] 1 is a graph showing a potential barrier required for interface induction. [Figure 5]FIG. 10 is a cross-sectional view showing the operation of an end portion of an active region of a conventional silicon carbide semiconductor device when it is turned off. [Figure 6] FIG. 10 is a plan view showing the operation of an end portion of an active region of a conventional silicon carbide semiconductor device when it is turned off. [Figure 7] 1 is a cross-sectional view showing an operation at an end of an active region of a silicon carbide semiconductor device according to an embodiment when the device is turned off; [Figure 8] 1 is a plan view showing an operation at an end of an active region of a silicon carbide semiconductor device according to an embodiment when the device is turned off; FIG. [Figure 9] FIG. 1 is a cross-sectional view showing the structure of an active region of a conventional silicon carbide semiconductor device. [Figure 10] FIG. 1 is a cross-sectional view showing a structure of an edge portion of an active region of a conventional silicon carbide semiconductor device. [Figure 11] FIG. 1 is a top view showing the structure of a conventional silicon carbide semiconductor device. [Figure 12] FIG. 1 is a cross-sectional view showing hole accumulation in an active region of a conventional silicon carbide semiconductor device. [Figure 13] FIG. 1 is a cross-sectional view showing accumulation of holes at the edge of an active region of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0024] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. The same n or p symbol, including + and -, indicates similar concentrations, but does not necessarily mean that the concentrations are equivalent. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of manufacturing variations.

[0025] (Embodiment) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as the wide bandgap semiconductor will be described using a trench MOSFET 50 as an example. Figure 1 is a cross-sectional view showing the structure of an active region of the silicon carbide semiconductor device according to the embodiment.

[0026] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has n + A first main surface (front surface) of a silicon carbide substrate (silicon carbide semiconductor substrate of a first conductivity type) 1, for example, a (0001) surface (Si surface), is provided with an n - A silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 2 is deposited on the silicon carbide epitaxial layer.

[0027] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The silicon carbide epitaxial layer 2 is + The impurity concentration is lower than that of the silicon carbide substrate 1, and is, for example, a low-concentration n-type drift layer. - The n-type silicon carbide epitaxial layer 2+ An n-type heavily doped region 5 may be provided on the surface opposite to the silicon carbide substrate 1 side. + Lower n than silicon carbide substrate 1 - The n-type silicon carbide epitaxial layer 2 is a high-concentration n-type drift layer having a higher impurity concentration than the n-type silicon carbide epitaxial layer 2.

[0028] n - The n-type silicon carbide epitaxial layer 2 + On the surface opposite to the silicon carbide substrate 1 side, a p-type base layer (a second semiconductor layer of a second conductivity type) 6 is provided. + A silicon carbide substrate 1 and an n - The silicon carbide epitaxial layer 2, the n-type high concentration region 5, and the p-type base layer 6 are combined to form a silicon carbide semiconductor substrate (a semiconductor substrate made of silicon carbide).

[0029] n + A back surface electrode 13 serving as a drain electrode is provided on a second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the back surface electrode 13.

[0030] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the trench 16 is formed between the n-type + The n-type heavily doped region 5 (or the n-type heavily doped region 5 when the n-type heavily doped region 5 is not provided) penetrates the p-type base layer 6 from the surface opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor base). - The trench 16 has a silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) extending therethrough. A gate insulating film 9 is formed on the bottom and side walls of the trench 16 along the inner wall thereof, and a gate electrode 10 is formed inside the gate insulating film 9 within the trench 16. The gate insulating film 9 insulates the gate electrode 10 from the n-type high concentration region 5 (2) and the p-type base layer 6. A portion of the gate electrode 10 may protrude from above the trench 16 (the side where a source electrode 12, described later, is provided) toward the source electrode 12.

[0031] n - A first p-type silicon carbide epitaxial layer 2 and an n-type heavily doped region 5(2) are formed in contact with the bottom of the trench 16. + A first p-type base region (a second semiconductor region of a second conductivity type) 3 is provided. + The base region 3 is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the back surface electrode 13). + The width of the mold base region 3 is equal to or wider than the width of the trench 16. The bottom of the trench 16 is the first p + The p-type base layer 6 and the first p-type base region 3 may be connected to each other. + The second p-type base layer 6 may be located in the n-type high concentration region 5(2) sandwiched between the p-type base regions 3. The second p-type base layer 6 may be located in the n-type high concentration region 5(2) sandwiched between the p-type base regions 3. + A second p-type base region (third semiconductor region of the second conductivity type) 4 is provided. + The mold base region 4 is a first p + The lower second p at the same height as the mold base region 3 + The mold base region 4b and the lower second p + The upper second p provided on the surface of the mold base region 4b + The upper part 2p is made up of a mold base region 4a. + The width of the mold base region 4a is + It may be narrower than the width of the mold base region 4b.

[0032] Inside the p-type base layer 6, an n-type silicon carbide semiconductor substrate is formed on the first main surface side. + A p-type source region (first semiconductor region of the first conductivity type) 7 is selectively provided. + The n-type contact region 8 may be selectively provided. + Type source region 7 and p + The p-type contact regions 8 are in contact with each other. In addition, a p-type channel implantation layer 14 having a higher impurity concentration than the p-type base layer 6 is provided in the vicinity of the channel inside the p-type base layer 6 in order to suppress an increase in leakage current and an increase in saturation current due to the short channel effect when the drain voltage is high.

[0033] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 is connected to the n-type semiconductor layer 11 through a contact hole opened in the interlayer insulating film 11. + The p-type source region 7 and the p-type base layer 6 are in contact with each other. + When the n-type contact region 8 is provided, the source electrode 12 is + Type source region 7 and p + The source electrode 12 is in contact with the gate electrode 10 through the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A barrier metal (not shown) may be provided between the source electrode 12 and the interlayer insulating film 11 to prevent, for example, diffusion of metal atoms from the source electrode 12 to the gate electrode 10.

[0034] FIG. 2A is a cross-sectional view showing the structure of an active region end portion of a silicon carbide semiconductor device according to an embodiment. FIG. 2B is a cross-sectional view showing another structure of an active region end portion of a silicon carbide semiconductor device according to an embodiment. FIG. 3 is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 1 is a cross-sectional view taken along line A-A' in FIG. 3, and FIGS. 2A and 2B are cross-sectional views taken along line B-B' in FIG. 3. Here, active region end portion 41 refers to a portion between an edge termination region (not shown) and active region 40, and specifically refers to n + The p-type source region 7 is not provided, and the p-type region (second p + The edge termination region is a region where the p-type base region 4, p-type base layer 6, and channel implantation layer 14 are provided. The edge termination region is a region where the JTE, spatial modulation, guard ring, etc. are formed to reduce the electric field on the front surface side of the substrate in the drift region and maintain the breakdown voltage.

[0035] As shown in FIG. 2A, in the silicon carbide semiconductor device according to the embodiment, the upper second p + The mold base region 4a is spaced apart from the sidewall of the trench 16. +The p-type base layer 6 and the n-type high concentration region 5(2) are provided between the p-type base region 4a and the trench 16. + The distance between the mold base region 4a and the trench 16 is preferably 0.1 μm or more, and more preferably 0.3 μm or more. + The mold base region 4b is the first p + It is connected to the mold base region 3.

[0036] As shown in FIG. 2B, in the silicon carbide semiconductor device of the embodiment, the first p + The base region 3 may be spaced apart from the bottom of the trench 16. + An n-type high concentration region 5(2) is provided between the n-type base region 3 and the bottom of the trench 16. + The distance between the mold base region 3 and the bottom of the trench 16 is preferably 0.1 μm or more, and more preferably 0.3 μm or more. + The mold base region 4b is the first p + In this case, the active region 40 is also connected to the first p + The mold base region 3 may be spaced apart from the bottom of the trench 16 .

[0037] 4 is a graph showing potential. In FIG. 4, the horizontal axis represents the distance from the interface (0.35 μm) of the trench 16 with the gate insulating film 9 to the channel implantation layer 14 or the upper second p + The vertical axis represents the distance to the mold base region 4a side (inside the SiC) in μm, and the vertical axis represents the potential in V.

[0038] In Figure 4, the dotted triangle line indicates the potential of the high-impurity-concentration p-type region, and the solid circle line indicates the potential of the low-impurity-concentration p-type region. Arrow A indicates the potential barrier that must be overcome to induce holes from inside the SiC to the trench interface in the high-impurity-concentration p-type region, arrow B indicates a similar potential barrier in the low-impurity-concentration p-type region, and arrow C indicates the potential difference required to induce holes to reach the oxide film interface of the low-impurity-concentration p-type region via the oxide film interface of the high-impurity-concentration p-type region.

[0039] In order for holes that have reached the trench interface of the high-impurity-concentration p-type region to move to the interface of the low-impurity-concentration p-type region, they must overcome a lateral potential barrier corresponding to arrow C. However, the lateral potential barrier (arrow C) is smaller than the potential barrier (arrow B) with the substrate side. For this reason, in a low-impurity-concentration p-type region such as the channel implantation layer 14, holes begin to diffuse laterally from the high-impurity-concentration p-type region with the assistance of heat at a bias smaller than the expected gate negative bias.

[0040] FIG. 5 is a cross-sectional view showing the operation of the edge of the active region of a conventional silicon carbide semiconductor device when it is off. FIG. 6 is a plan view showing the operation of the edge of the active region of a conventional silicon carbide semiconductor device when it is off. FIG. 6 is a cross-sectional view of the CC' portion of FIG. 5. In most of the active region 140, the impurity concentration of the channel implantation layer 114, which determines the threshold of the electron channel, is the highest in the p-type base layer 106. In the active region edge 141, there is no need to form an electron channel, so a second p + A mold base region 104 is disposed.

[0041] The high electron channel threshold is the low hole channel threshold. Therefore, when a negative gate bias is applied during the off state, the second p + A hole 117 is induced at the interface between the trench 116 in which the mold base region 104 is located and the gate insulating film 109 .

[0042] Highly doped 2p + Although a potential barrier exists between the p-type base region 104 and the low-impurity-concentration p-type base layer 106, as explained in Fig. 4, the difference between these potential barriers is relatively small, so the induced holes 117 at the active region edge 141 overcome the potential barrier and diffuse into the low-impurity-concentration p-type base layer 106 through the trench interface, as shown by the arrows in Fig. 6. As a result, even in the active region 140, the holes 117 reach the interface with the gate insulating film 109 at a gate negative voltage that is smaller than the hole channel threshold of the low-impurity-concentration p-type base layer 106.

[0043] 7 is a cross-sectional view showing the operation of the end of the active region of the silicon carbide semiconductor device according to the embodiment when it is off. FIG. 8 is a plan view showing the operation of the end of the active region of the silicon carbide semiconductor device according to the embodiment when it is off. FIG. 8 is a cross-sectional view of the CC' portion of FIG. 7. In the silicon carbide semiconductor device according to the embodiment, too, in most of the active region 40, the impurity concentration of the channel implantation layer 14 that determines the threshold of the electron channel is the highest in the p-type base layer 6. In the active region end 41, there is no need to form an electron channel, so the impurity concentration of the second p + A mold base region 4 is arranged.

[0044] Since the high p-type impurity concentration portion is the portion with a low hole channel threshold, when a negative gate bias is applied during the off state, holes 17 are transported to the lower second p-type impurity concentration portion with a smaller gate negative voltage, as shown in FIG. + The electrons are induced at the interface of the gate insulating film 9 in the trench 16 where the base region 4b is located.

[0045] In the embodiment, the active region edge 41 is heavily doped with the second p +The n-type base region 4 is separated from the sidewall of the trench 16. Because the potential seen from the holes at the trench interface in the heavily doped n-type region 5 is higher than that in the lightly doped p-type region, the induced holes 17 at the edge 41 of the active region cannot overcome the potential barrier and do not diffuse, as shown in FIG. 8. As a result, holes 17 are prevented from reaching the interface of the gate insulating film 9 in the active region 40 at a negative gate voltage lower than the hole channel threshold of the lightly doped p-type base layer 6. This makes it possible to use a higher negative gate voltage, preventing malfunctions during switching.

[0046] 3, the trench 16 has a stripe shape, and the active region end 41 exists at the end of the trench 16 in the longitudinal direction (X-axis direction) and at the end of the trench 16 in the direction perpendicular to the longitudinal direction (Y-axis direction). The sidewall of the trench 16 and the upper second p-type base region 4a do not come into contact with each other at either location. Although not shown in FIG. 3, the active region end 41 includes the lower second p-type base region 4a, including below the trench 16. + The mold base region 4b is provided on the entire surface. + The base region 4a may be provided on a part of the side wall of the trench 16 at the edge 41 of the active region as shown in FIG. 3, or may be provided on the upper second p + A mold base region 4a may be provided.

[0047] The silicon carbide semiconductor device according to the embodiment has, for example, a second p + When forming the base region 4, the layout of the mask used for ion implantation is changed to form the upper second p + The mold base region 4a is spaced from the sidewall of the trench 16, and the lower second p + The mold base region 4b is the first p + By forming the first p-type base region 3 so as to be connected to the first p-type base region 3, the structure of FIG. +2B can be formed by changing the implantation energy during ion implantation to form the base region 3 away from the bottom of the trench 16. Other structures can also be fabricated in the same manner as when fabricating a MOSFET with a breakdown voltage of, for example, 1200 V.

[0048] As described above, according to the embodiment, the high concentration second p + The p-type base region is separated from the sidewall of the trench. This makes it difficult for holes to be induced at the trench interface at the edge of the active region. As a result, holes are prevented from accumulating at the interface of the gate insulating film in the active region at a negative gate voltage lower than the hole channel threshold of the p-type base layer. This makes it possible to use a higher negative gate voltage, preventing malfunctions during switching.

[0049] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each component and the impurity concentration are variously set according to the required specifications. Furthermore, while each of the above-described embodiments has been described using silicon carbide as the wide bandgap semiconductor, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, while each of the embodiments has described the first conductivity type as n-type and the second conductivity type as p-type, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0050] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, and the like. [Explanation of symbols]

[0051] 1, 101 n + Silicon carbide substrate 2, 102 n - Silicon carbide epitaxial layer 3, 103 1st p. + Type-based domain 4, 104 2nd p. + Type-based domain 4a, 104a Upper 2nd p. + Type-based domain 4b, 104b Lower 2nd p + Type-based domain 5, 105 n-type high concentration region 6, 106 p-type base layer 7, 107 n + Type Source Area 8, 108 p. + Mold contact area 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 12, 112 Source electrode 13, 113 Back electrode 14, 114 Channel implantation layer 16, 116 trenches 17th and 117th holes 40, 140 active area 41, 141 Active area edge 50, 150 Trench MOSFET

Claims

1. a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer; a gate electrode provided inside the trench via a gate insulating film; a second semiconductor region of a second conductivity type selectively provided inside the first semiconductor layer and covering a bottom surface of the trench; a third semiconductor region of the second conductivity type selectively provided inside the first semiconductor layer and the second semiconductor layer between adjacent trenches and in contact with the second semiconductor layer; a first electrode in contact with the second semiconductor layer and the first semiconductor region; a second electrode provided on a back surface of the silicon carbide semiconductor substrate; Equipped with the third semiconductor region is disposed apart from a sidewall of the trench at an end of an active region where the first semiconductor region is not provided, and is connected to the second semiconductor region.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the second semiconductor region is disposed at an end of the active region where the first semiconductor region is not provided, away from a bottom of the trench.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer are provided between the third semiconductor region and a sidewall of the trench at an end of the active region. 4 .

4. the trench is stripe-shaped; 4. The silicon carbide semiconductor device according to claim 1, wherein the active region end is an end of the trench in a longitudinal direction where the first semiconductor region is not provided between adjacent trenches.

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