Spin devices

Abstract

A spin element according to the present invention is provided with: a semiconductor layer (102) which is formed on a substrate (101); a source (103) and a drain (104), which are formed in the semiconductor layer (102) at a specific distance from each other; and a channel (105) which is formed in the semiconductor layer (102) between the source (103) and the drain (104). The channel (105) is a region that is obtained by adding a magnetic impurity to the semiconductor layer (102). This spin element is also provided with a gate (106) which is configured from a ferroelectric body and applies an electric field to the channel (105).

Description

[Technical Field]

[0001] The present invention relates to a spin element. [Background technology]

[0002] A field known as semiconductor spintronics, which utilizes carrier spin in semiconductors, is attracting attention. For example, next-generation spin elements, such as spin memories and quantum computing elements, which add a new degree of spin freedom to conventional semiconductors, are being developed. As one example, technology for electrically controlling magnetization is attracting attention as an operating principle for new electronic devices, and proposals have been made to utilize this technology as an element for non-volatile logic circuits, such as power-saving multi-valued memories. As basic technologies for this, multiferroic materials and ferromagnetic semiconductors have been developed (Patent Document 1, Non-Patent Document 1).

[0003] For example, multiferroic materials are systems in which ferroelectricity and ferromagnetism coexist, and the direction of magnetization changes depending on the direction of polarization. In multiferroic materials, the direction of polarization can be controlled by an electric field, and is maintained when the electric field is turned off, making it possible to control the magnetization direction using an electromagnetic field. In other words, they are elements that can calculate and record multiple information media (polarization and magnetization) using an electric field. The properties of these multiferroic materials are derived from the crystalline structure and orientation of multi-component materials with precisely controlled composition, and therefore require advanced fabrication technology.

[0004] However, multiferroic materials have the following problems. Molecular beam epitaxial growth (MBE) and metalorganic chemical vapor deposition (MOCVD) are primarily used to fabricate multiferroic materials. Crystal growth using the MBE method imposes limitations on the precise composition control of multiple elements and the type of underlayer suitable for forming a crystal structure. Deviations in composition or incompatible underlayers can cause the formation of heterogeneous phases and reduced orientation, resulting in a loss of material functionality. Even the MOCVD method, which is practical for fabricating large-area devices, faces the same challenges as the MBE method, as well as problems with device fabrication, such as the formation of discontinuous films due to non-uniform crystal growth.

[0005] Ferromagnetic semiconductors are materials that combine semiconductor properties with ferromagnetism, and can express or erase a ferromagnetic state (magnetization) by inducing or suppressing charges using an electric field. This property makes it possible to add the functionality of an electric-field-controllable magnetic material to any conventional semiconductor device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 8,860,006 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Ikeda et al., "Magnetic Tunnel Junctions for Spintronic Memories and Beyond", IEEE Transactions on Electron Devices, vol. 54, no. 5, pp. 991-1002, 2007. Summary of the Invention [Problem to be solved by the invention]

[0008] As mentioned above, ferromagnetic semiconductors are expected to be materials for next-generation spin devices, but no new spin devices using ferromagnetic semiconductors have been proposed.

[0009] The present invention has been made to solve the above problems, and has as its object to provide a new spin element using a ferromagnetic semiconductor. [Means for solving the problem]

[0010] The spin element according to the present invention comprises a semiconductor layer formed on a substrate, a source and a drain formed in the semiconductor layer with a predetermined gap therebetween, a channel formed in the semiconductor layer between the source and the drain and doped with magnetic impurities, and a first ferroelectric layer and a second ferroelectric layer made of a ferroelectric material, which apply an electric field to both ends of the channel in the direction from the source to the drain to deplete both ends of the channel. By applying a voltage between the source and the drain, charges are injected into the channel, and the magnetization information in the channel into which the charges are injected is maintained depending on the polarity of the voltage applied to the first ferroelectric layer and the second ferroelectric layer. do.

[0011] The spin element according to the present invention comprises a semiconductor layer formed on a substrate, a source and a drain formed in the semiconductor layer at a predetermined interval, a channel formed in the semiconductor layer between the source and the drain and doped with magnetic impurities, and a gate made of a ferroelectric material for applying an electric field to the channel. By applying a voltage between the source and the drain, charges are injected into the channel, and by applying a voltage to the gate, the magnetization information in the channel into which the charges are injected is maintained. do. [Effects of the Invention]

[0012] As described above, according to the present invention, a ferroelectric layer is provided on a channel formed by adding magnetic impurities between a source and a drain formed in a semiconductor layer, and therefore a new spin element using a ferromagnetic semiconductor can be provided. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a cross-sectional view showing the configuration of a spin element according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing the configuration of a spin element according to a second embodiment of the present invention. [Figure 3] FIG. 3 is a cross-sectional view showing the configuration of a spin element according to a third embodiment of the present invention. [Figure 4A] FIG. 4A is an explanatory diagram showing charge spin and spontaneous magnetization generated by the interaction between charges and impurity ions in a semiconductor doped with magnetic impurities. [Figure 4B] FIG. 4B is an explanatory diagram for explaining control of the ferromagnetic and non-magnetic states by injecting and discharging charges from the source 203 into the channel 205. In FIG. [Figure 4C]FIG. 4C is an explanatory diagram showing a state in which the potential of the semiconductor channel directly below the first ferroelectric layer 206a and the second ferroelectric layer 206b increases due to spontaneous polarization of the first ferroelectric layer 206a and the second ferroelectric layer 206b, and the charge injected into the channel 205 is trapped. [Figure 4D] FIG. 4D is a characteristic diagram showing the potential of the entire device when the charge injected into the channel 205 is trapped. [Figure 5A] FIG. 5A is a cross-sectional view showing the state of a spin element in the middle of a process, illustrating a method for manufacturing a spin element according to a third embodiment of the present invention. [Figure 5B] FIG. 5B is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5C] FIG. 5C is a plan view showing the state of the spin element in the middle of the process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5D] FIG. 5D is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5E] FIG. 5E is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5F] FIG. 5F is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5G] FIG. 5G is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5H] FIG. 5H is a plan view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5I] FIG. 5I is a plan view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5J]FIG. 5J is a plan view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5K] FIG. 5K is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5L] FIG. 5L is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5M] FIG. 5M is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5N] FIG. 5N is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5O] FIG. 5O is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5P] FIG. 5P is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5Q] FIG. 5Q is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5R] FIG. 5R is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating the method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 5S] FIG. 5S is a cross-sectional view showing the state of the spin element in the middle of a process, for illustrating a method for manufacturing the spin element according to the third embodiment of the present invention. [Figure 6A] FIG. 6A is an explanatory diagram for explaining the operation of the spin element according to the third embodiment as a nonvolatile multi-valued memory. [Figure 6B] FIG. 6B is an explanatory diagram for explaining the operation of the spin element according to the third embodiment as a nonvolatile multi-valued memory. [Figure 7]FIG. 7 is a characteristic diagram showing the current characteristics of the channel 205. [Figure 8] 8A and 8B are a transparent circuit diagram showing a state in which the channel 205 and the control line 209 are electrostatically coupled by floating electrostatic capacitance, and a characteristic diagram showing the state of the current flowing through the control line 209. [Figure 9] FIG. 9 shows a state of multi-level memory operation in which the value of the current I(CH) in the channel 205 can maintain a plurality of states even when the input to the first ferroelectric layer 206a and the second ferroelectric layer 206b is cut off. [Figure 10A] FIG. 10A is an explanatory diagram showing the electronic state in the channel 205 when the dimensions of the channel 205 and the distance between the first ferroelectric layer 206a and the second ferroelectric layer 206b are nanometer-sized. [Figure 10B] FIG. 10B is an explanatory diagram showing the electronic state in the channel 205 when the dimensions of the channel 205 and the distance between the first ferroelectric layer 206a and the second ferroelectric layer 206b are nanometer-sized. [Figure 11] FIG. 11(a) is a plan view showing a state in which a plurality of spin elements are connected in a lattice pattern, and FIG. 11(b) is a characteristic diagram showing the magnetization state of adjacent channels 205. DETAILED DESCRIPTION OF THE INVENTION

[0014] A spin element according to an embodiment of the present invention will be described below.

[0015] [Embodiment 1] First, a spin element according to a first embodiment of the present invention will be described with reference to Fig. 1. This spin element includes a semiconductor layer 102 formed on a substrate 101, a source 103 and a drain 104 formed in the semiconductor layer 102 at a predetermined distance, and a channel 105 formed in the semiconductor layer 102 between the source 103 and the drain 104. The channel 105 is a region in which magnetic impurities are added to the semiconductor layer 102. The spin element also includes a gate 106 made of a ferroelectric material and applying an electric field to the channel 105. An electrode 107 made of a metal is formed on and in contact with the gate 106.

[0016] The substrate 101 may be, for example, a silicon substrate. In this case, a semiconductor layer 102 is formed on the substrate 101 with an insulating layer 108 interposed therebetween. The semiconductor layer 102 may be made of, for example, silicon. The magnetic impurities added to the semiconductor layer 102 in the region of the channel 105 may be, for example, Fe, Co, Mn, etc. The channel 105 to which the magnetic impurities have been added becomes a ferromagnetic semiconductor. The gate 106 may be made of, for example, HfO2.

[0017] For example, a charge can be injected into the channel 105 by applying a positive voltage between the source 103 and the drain 104. In addition, a charge can be induced in the channel 105 by adjusting the potential of the channel 105 by applying a voltage between the gate 106 and the substrate 101.

[0018] Furthermore, by applying a positive voltage between the source 103 and the drain 104 and further adjusting the potential of the channel 105 by applying a voltage between the gate 106 and the substrate 101, the charge in the channel 105 can be released to the drain 104. Furthermore, by adjusting the potential of the channel 105 by applying a voltage between the gate 106 and the substrate 101, the charge in the channel 105 can be eliminated.

[0019] In the channel 105 where charges exist, spontaneous magnetization in the opposite direction to the charge spin occurs due to the interaction between the charges and the impurities. As described above, the state of magnetization in the channel 105 can be controlled by controlling the injection of charges into the channel 105 and the emission of charges from the channel 105.

[0020] Furthermore, application of a positive voltage to the gate 106 can maintain the magnetization information in the channel 105 into which the charge has been injected. Depending on the polarity of the voltage applied to the gate 106, two states of polarization in the gate 106 can be set, and when the voltage applied to the gate 106 is positive, the magnetization direction in the channel 105 into which the charge has been injected is maintained. Hereinafter, the description will be given assuming that the charge is an electron having a negative polarity, but the charge can also be a hole having a positive polarity. In this case, the polarity of the gate voltage in the device operation is reversed from that in the case of an electron.

[0021] This spin element can be used as a multi-valued memory by reading out the presence / absence of charge in the channel 105 and the magnetization state in the channel 105 into which charge has been injected. For example, control of the magnetization state and reading out the presence / absence of charge can be achieved by using a control line (not shown) that is electrostatically coupled to the channel 105.

[0022] [Embodiment 2] Next, a spin element according to a second embodiment of the present invention will be described with reference to Fig. 2. This spin element first includes a semiconductor layer 102 formed on a substrate 101, a source 103 and a drain 104 formed in the semiconductor layer 102 with a predetermined distance between them, and a channel 105 formed in the semiconductor layer 102 between the source 103 and the drain 104. The channel 105 is a region in the semiconductor layer 102 doped with magnetic impurities. These configurations are the same as those in the first embodiment described above.

[0023] In the second embodiment, a first ferroelectric layer 106a and a second ferroelectric layer 106b are provided, each made of a ferroelectric material, for applying an electric field to both ends of a channel 105 in the direction from the source 103 to the drain 104 to deplete both ends of the channel 105. A first electrode 107a made of a metal is formed on and in contact with the first ferroelectric layer 106a, and a second electrode 107b made of a metal is formed on and in contact with the second ferroelectric layer 106b. The first ferroelectric layer 106a and the second ferroelectric layer 106b can be made of, for example, HfO2.

[0024] For example, a charge can be injected into the channel 105 by applying a positive voltage between the source 103 and the drain 104. In addition, a charge can be induced in the channel 105 by adjusting the potential of the channel 105 by applying a voltage to the substrate 101.

[0025] Furthermore, by applying a positive voltage between the source 103 and the drain 104 and further adjusting the potential of the channel 105 by the voltage applied to the substrate 101, the charge in the channel 105 can be released to the drain 104. Furthermore, by adjusting the potential of the channel 105 by the voltage applied to the substrate 101, the charge in the channel 105 can be eliminated.

[0026] In the channel 105 where charges exist, spontaneous magnetization in the opposite direction to the charge spin occurs due to the interaction between the charges and the impurities. As described above, the state of magnetization in the channel 105 can be controlled by controlling the injection of charges into the channel 105 and the emission of charges from the channel 105.

[0027] In the second embodiment, the polarity of the voltage applied to the first ferroelectric layer 106a and the second ferroelectric layer 106b can be set to two polarization states in each of the first ferroelectric layer 106a and the second ferroelectric layer 106b. This polarization state is maintained even after the application of the voltage is stopped due to spontaneous polarization of the ferroelectric. Due to this spontaneous polarization in the first ferroelectric layer 106a and the second ferroelectric layer 106b, the semiconductor layer 102 directly below the first ferroelectric layer 106a and the second ferroelectric layer 106b is depleted. As a result, the channel 105 is sandwiched between depleted regions, and the charge injected into the channel 105 is trapped.

[0028] As described above, according to the second embodiment, charge can be steadily accumulated in the channel 105 without applying an electrical signal, and the magnetization information in the channel 105 can be retained, thereby making the magnetization non-volatile.

[0029] Unlike multiferroic materials, ferromagnetic semiconductors, which are constructed by adding magnetic impurities to a semiconductor layer, are extremely easy to manufacture. However, the magnetization of ferromagnetic semiconductors is lost due to the movement and recombination of charges caused by external disturbances. Therefore, in order to utilize ferromagnetic semiconductors as recording elements that retain magnetic information, it is important to develop a technology that allows charges to be stored and accumulated.

[0030] For example, to construct a nonvolatile logic circuit using a ferromagnetic semiconductor, it is necessary to maintain the charge accumulation and depletion state at a given location and record magnetization information when the external electric field is turned off.However, with a single ferromagnetic semiconductor (especially one with a microstructure), the surface and interface potentials have a strong influence on the internal charge, and charge is also released due to heat, making it difficult to realize the operation required for the above-mentioned logic circuit.

[0031] To address this problem, according to the second embodiment, a first ferroelectric layer 106a and a second ferroelectric layer 106b made of a ferroelectric material are used, and an electric field is applied to both ends of the channel 105 by the spontaneous polarization of the ferroelectric material, thereby depleting both ends of the channel 105, thereby realizing retention and accumulation of electric charges in the channel 105.

[0032] [Embodiment 3] Next, a spin element according to a third embodiment of the present invention will be described with reference to Fig. 3. This spin element first includes a semiconductor layer 202 formed on a substrate 201, a source 203 and a drain 204 formed in the semiconductor layer 202 with a predetermined distance between them, and a channel 205 formed in the semiconductor layer 202 between the source 203 and the drain 204. The channel 205 is a region in the semiconductor layer 202 doped with magnetic impurities.

[0033] This spin element is also made of a ferroelectric material and includes a first ferroelectric layer 206a and a second ferroelectric layer 206b that apply an electric field to both ends of a channel 205 in the direction from the source 203 to the drain 204 to deplete both ends of the channel 205. A first electrode 207a made of a metal is formed on and in contact with the first ferroelectric layer 206a, and a second electrode 207b made of a metal is formed on and in contact with the second ferroelectric layer 206b. These configurations are the same as those in the second embodiment described above.

[0034] In the third embodiment, a gate electrode 207 is provided in a region between the first ferroelectric layer 206a and the second ferroelectric layer 206b, for applying an electric field to the channel 205. Also provided is a control line 209 that is electrostatically coupled to the channel 205 to control the magnetization state of the channel 205 and read out the magnetization state of the channel 205. The control line 209 is disposed as close to the channel 205 as possible to be electrostatically coupled to the channel 205. The control line 209 can be made of a metal (conductor) such as aluminum.

[0035] The substrate 201 may be, for example, a silicon substrate. In this case, a semiconductor layer 202 is formed on the substrate 201 with an insulating layer 208 interposed therebetween. The semiconductor layer 202 may be made of, for example, silicon. The magnetic impurities added to the semiconductor layer 202 in the region of the channel 205 may be, for example, Fe, Co, Mn, or the like. The channel 205 to which the magnetic impurities are added becomes a ferromagnetic semiconductor. The substrate 201 made of silicon may function as a back gate.

[0036] In this spin element, the source 203, the drain 204, the gate electrode 207, and the substrate 201 functioning as a back gate play a role in injecting charges (electrons or holes) into the channel 205. The injected charges play a role in confining the charges in the channel 205 therebetween by depleting the semiconductor layer 202 directly below the first ferroelectric layer 206a and the second ferroelectric layer 206b due to the electric field (electric field) applied from the first ferroelectric layer 206a and the second ferroelectric layer 206b.

[0037] Furthermore, the first ferroelectric layer 206a and the second ferroelectric layer 206b dynamically change the potential of the semiconductor layer 202 directly below them to inject charges into the channel 205 and to control the speed and timing of charge injection into the channel 205. The source 203, gate electrode 207, and substrate 201 function to modulate the energy level and concentration of carriers in the channel 205. The substrate 201 is also used to simultaneously refresh the information in the channels 205 on the substrate 201. The control line 209 serves as a write electrode that controls the direction of magnetization recorded in the channel 205 and as a read electrode that detects the charge accumulated in the channel 205.

[0038] This spin element has the following two features. First, the channel 205 is made into a ferromagnetic semiconductor by adding magnetic impurities to the semiconductor, and the ferromagnetic state is expressed and controlled by inducing electric charges in the channel 205. This gives the spin element the ability to electrically induce and eliminate magnetization.

[0039] Second, the first ferroelectric layer 206a and the second ferroelectric layer 206b are made of a ferroelectric material. Due to the spontaneous polarization of the ferroelectric material, charge can be steadily accumulated in the channel 205 even when the input to the first ferroelectric layer 206a and the second ferroelectric layer 206b is cut off, and the magnetization information in the channel 205 made of a ferromagnetic semiconductor can be maintained. In other words, this spin element can be made nonvolatile in magnetization. In this way, by using the first ferroelectric layer 206a and the second ferroelectric layer 206b, it becomes possible to treat the ferromagnetic semiconductor like a multiferroic material.

[0040] Next, we will explain the operation of this spin element. In semiconductors doped with magnetic impurities, the interaction between charge and impurity ions generates spontaneous magnetization in the opposite direction to the charge spin indicated by the downward arrow, as shown in Figure 4A (References 1, 2, and 3). Note that the upward arrow indicates the impurity spin. In this spin element, the channel 205 is doped with magnetic impurities, and as shown in Figure 4B, the ferromagnetic and nonmagnetic states can be controlled by injecting and ejecting charge into and from the channel 205 from the source 203 (Input 1). Similarly, magnetism in the channel 205 can be expressed or erased by applying a voltage between the gate electrode 207 and the substrate 201 to adjust the potential in the channel 205, thereby generating or erasing charge in the channel 205 (Input 2).

[0041] Furthermore, because the exchange interaction is a function of charge energy (Reference 3), it can be modulated by controlling the charge concentration in the channel 205. Specifically, the charge concentration is modulated by controlling the potential by the gate electrode 207 and the substrate 201, and by controlling the confinement of carriers in the channel 205 by the electric fields from the first ferroelectric layer 206a and the second ferroelectric layer 206b.

[0042] To store the charge injected into the channel 205 after Input 1 and to manipulate the electric field by applying a voltage to the gate electrode 207 and substrate 201, an electric field must be applied to the first ferroelectric layer 206a and the second ferroelectric layer 206b (Input 3) to insulate the channel 205 from the source 203 and the drain 204. Figure 4C shows how the spontaneous polarization of the first ferroelectric layer 206a and the second ferroelectric layer 206b increases the potential of the semiconductor channel directly below, trapping the charge injected into the channel 205. At this time, the potential of the entire device becomes as shown in Figure 4D.

[0043] Even after Input3 is stopped, charges continue to accumulate in the channel 205 due to the spontaneous polarization of the first ferroelectric layer 206a and the second ferroelectric layer 206b. In other words, the magnetization information in the channel 205 is preserved (Memory 1). On the other hand, even when the channel 205 is insulated, the release and accumulation of charges can be controlled by controlling the gate electric field (Input2) of the gate electrode 207 or the substrate 201, as shown by the potentials of the lines (a) and (b) in Figure 4D. Since the first ferroelectric layer 206a and the second ferroelectric layer 206b are located on the left (source 203 side) and right (drain 204 side) of the channel 205, the operation of applying an electric field to them is defined as Input3 (first ferroelectric layer 206a) and Input3' (second ferroelectric layer 206b), respectively. The above operations correspond to electrically generating and maintaining magnetization.

[0044] Next, the magnetization direction of Memory 1 is electrically controlled. This operation is achieved by passing a current through control line 209. Passing a current through control line 209 generates a magnetic field. For example, a magnetic field generated according to the right-hand rule, centered on the straight portion of control line 209 facing channel 205, penetrates channel 205 in the thickness direction in accordance with the polarity of the current. This magnetic field penetrating channel 205 causes the magnetization within channel 205 to be oriented in the direction of the applied magnetic field (thickness direction). The magnetic field direction of the magnetization within channel 205 can also be continuously changed (analog signal processing) in response to changes in the strength and waveform of the current input to control line 209. This operation is referred to as Input 4, and the magnetization direction is referred to as Memory 1.

[0045] For example, if the reference direction of the magnetization to be read is defined as the direction perpendicular to the plane of the substrate, Memory 1 can use not only the three magnetization directions of horizontal (the direction of the plane of the substrate 201), upward, and downward, but also a state where there is no magnetization or a state where the magnetization is tilted from three axes (x-axis, y-axis, and z-axis) as information. The gate length direction is the x-axis, the gate width direction is the y-axis, and the thickness direction is the z-axis. Thus, ferromagnetic semiconductors made of semiconductors doped with magnetic impurities have a higher degree of freedom in magnetization direction compared to multiferroic materials, in which the magnetization direction is uniquely determined according to the polarization direction.

[0046] Next, a method for manufacturing a spin element according to the third embodiment will be described with reference to Figures 5A to 5S. This spin element can be manufactured using existing semiconductor device manufacturing techniques. Note that the numerical values ​​shown below are merely examples and are not limiting; various values ​​can be assumed depending on the combination of materials, the amount of magnetic impurities added, etc.

[0047] First, as shown in FIG. 5A, a semiconductor layer 221 is formed on a substrate 201 made of silicon via an insulating layer 208. Since the substrate 201 is used as a back gate, the insulating layer 208 is formed on the substrate 201 to suppress charge migration in the thickness direction of the device. The insulating layer 208 can be made of, for example, silicon oxide. The semiconductor layer 221 can be made of, for example, silicon. The semiconductor layer 221 is formed to a thickness of, for example, about 20 nm. The semiconductor layer 221 is a layer that forms the source 203, the drain 204, and the channel 205, and is set to a thickness equal to or less than the thickness at which the semiconductor layer 221 is depleted by the electric field applied from the first ferroelectric layer 206a and the second ferroelectric layer 206b.

[0048] 5B and 5C, a mask pattern 222 is formed on the semiconductor layer 221. The mask pattern 222 has a pattern shape for forming the shapes of the source 203, the drain 204, and the channel 205 in a plan view. For example, the mask pattern 222 can be formed by patterning a photosensitive resist using a known lithography technique.

[0049] Next, the semiconductor layer 221 is etched using the mask pattern 222 as a mask, and then the mask pattern 222 is removed to form the semiconductor layer 202 having regions to be the source 203 and the drain 204, as shown in FIG. 5D. The region (to be the channel 205) sandwiched between the source 203 and the drain 204 of the semiconductor layer 202 has a width W in the gate width direction in a plan view, for example. ch The width of the channel 205 in plan view is set to a length that allows control of the magnetization direction across the entire width of the channel 205. The strength of the magnetic field and electrostatic coupling applied from the control line 209 attenuates inversely proportional to the first power of the distance between the control line 209 and the channel 205. For this reason, the width of the channel 205 in plan view is set to be equal to or less than the length that allows control of the magnetization direction across the entire width of the channel 205.

[0050] Next, as shown in FIG. 5E, a ferroelectric film 223 is formed on the semiconductor layer 202, and a conductive film 224 is formed on the ferroelectric film 223. For example, a ferroelectric material can be deposited by sputtering or atomic layer deposition to form the ferroelectric film 223, and then a conductive material can be deposited to form the conductive film 224. Any material can be used for the ferroelectric film 223, but HfO2 is particularly suitable. HfO2 is a binary material and can be deposited by atomic layer deposition, which can cover the entire surface of devices with complex shapes (Reference 4).

[0051] Next, as shown in Fig. 5F, a mask pattern 225 is formed on the conductor film 224. Next, using the mask pattern 225 as a mask, the conductor film 224 and the ferroelectric film 223 are selectively etched in sequence, and then the mask pattern 225 is removed to form a first ferroelectric layer 206a and a second ferroelectric layer 206b as shown in Fig. 5G and Fig. 5H. A first electrode 207a is formed on the first ferroelectric layer 206a, and a second electrode 207b is formed on the second ferroelectric layer 206b.

[0052] By forming the first ferroelectric layer 206a and the second ferroelectric layer 206b, the length L of the channel 205 is increased. ch The length L of the channel 205 is defined as chIn operating the spin element according to the third embodiment, the length L of the channel 205 is set to, for example, about 20 nm. ch There is no limit to the length, but in order to reduce the resistance of the entire element from the viewpoints of precise control of ferromagnetic interactions and charge transport and storage, noise and power consumption, the length should be made as short as possible using microfabrication technology.

[0053] Next, the control line 209 is fabricated. First, as shown in Fig. 5I, a mask pattern 226 having an opening 226a in an area to form the control line 209 is formed. The mask pattern 226 is formed on the insulating layer 208, covering the semiconductor layer 202 (source 203, drain 204), the first ferroelectric layer 206a (first electrode 207a), and the second ferroelectric layer 206b (second electrode 207b).

[0054] Next, a metal that will form control line 209 is deposited on mask pattern 226. The deposited metal film is formed on mask pattern 226 and on insulating layer 208 exposed in opening 226a. Thereafter, mask pattern 226 is removed (lifted off), leaving the metal film in the opening 226a, and control line 209 is formed as shown in FIG. 5J.

[0055] To effectively apply the magnetic field and electrostatic coupling generated from the control line 209 to the channel 205, it is preferable that the gap G between the channel 205 and the control line 209 is as narrow as possible. This gap can be set to, for example, 40 nm.

[0056] Next, magnetic impurities are ion-implanted into the semiconductor layer 202 between the source 203 and the drain 204 to transform it into a ferromagnetic semiconductor, thereby forming a channel 205. Compared to other methods of forming ferromagnetic semiconductors, the ion implantation method has the advantage of being able to locally ferromagnetize a desired position in an already formed semiconductor layer.

[0057] First, as shown in Fig. 5K, an insulating layer 227 is formed over the entire device. Next, as shown in Fig. 5L, a mask pattern 228 having an opening 228a in a region to become channel 205 is formed on insulating layer 227. Thereafter, by selectively etching insulating layer 227 using mask pattern 228 as a mask, opening 227a is formed in insulating layer 227 in a region to become channel 205, as shown in Fig. 5M.

[0058] Next, magnetic impurities are implanted into the semiconductor layer 202 exposed through the opening 227a by ion implantation using the mask pattern 228 and the insulating layer 227 with the opening 227a as a mask. For example, 1 at. % Mn atoms are implanted. The impurities are then activated by heat treatment, forming a channel 205 in the semiconductor layer 202 between the source 203 and the drain 204, as shown in FIG. 5N. The upper limit of the concentration of the magnetic impurities is a concentration that does not generate heterogeneous phases such as intermetallic compounds (1 at. % in the case of Si). Note that clusters of metals or intermetallic compounds can also be selected as part of ferromagnetic semiconductors because they are expected to be capable of controlling magnetism through an electric field at the nanoscale. The ion species to be implanted is not critical as long as they can ferromagnetize the semiconductor channel.

[0059] Next, after removing mask pattern 228, insulating film 229 is formed on insulating layer 227 as shown in Fig. 5O. Then, as shown in Fig. 5P, mask pattern 230 is formed on insulating film 229 in alignment with the position of opening 227a. Next, insulating film 229 is etched using mask pattern 230 as a mask, and mask pattern 230 is removed, thereby forming gate insulating layer 206 on channel 205 at the bottom of opening 227a as shown in Fig. 5Q.

[0060] Next, as shown in FIG. 5R, a mask pattern 231 is formed on the insulating layer 227 (a part of the gate insulating layer 206). The mask pattern 231 has openings 231a where the gate electrodes 207 are to be formed. Next, a metal constituting the gate electrodes 207 is deposited on the mask pattern 231. The deposited metal film is formed on the mask pattern 231 and on the gate insulating layer 206 exposed in the openings 231a. Thereafter, the mask pattern 231 is removed (lifted off), so that the metal film in the openings 231a remains, and the gate electrodes 207 are formed as shown in FIG. 5S. The gate insulating layer 206 depletes the channel 205 at the interface where the gate insulating layer 206 comes into contact, and has a layer structure (HfO2 / SiO x etc.) is desirable.

[0061] Next, a configuration in which the spin element according to the third embodiment is utilized as a nonvolatile multilevel memory will be described with reference to FIGS. 6A and 6B. In this example, the gate insulating layer 206 in the spin element is made of a ferroelectric material, and a structure in which spin element 200a and spin element 200b are connected is used. Spin element 200a serves as the reference element, and spin element 200b serves as the read element. With this configuration, not only magnetization but also charge can be simultaneously read and written, thereby achieving the function of a multilevel memory. In FIGS. 6A and 6B, "S" indicates source 203, "D" indicates drain 204, "G" indicates gate insulating layer 206, and "CH" indicates channel 205.

[0062] First, the presence and direction of magnetization are detected by measuring the series resistance of the entire element. When two ferromagnetic materials are joined and a current is applied, the series resistance changes in proportion to the cosine of the relative angle between the magnetizations (spin resistance). This characteristic is applied to the magnetization of this element.

[0063] Specifically, the magnetization direction of the CH of spin element 200a, which serves as the reference element for coupled spin elements 200a and 200b, is defined in advance [reference magnetization (a)] by passing a current through control line 209 (Input 4). A magnetic field generated by passing a current through control line 209 penetrates channel 205, and the magnetization in channel 205 is oriented in the direction of the applied magnetic field (thickness direction) (Input 4).

[0064] The read magnetization (a) read from the CH of the spin element 200b serving as the read element can be oriented in any direction depending on the signal (Input 4) applied to the control line 209 of the spin element 200b. When a current is passed from S of the spin element 200a to D of the spin element 200b, the spin resistance is maximized when the read magnetization (b) is antiparallel to the reference magnetization (a), as shown in Figure 6A. In other words, the value of the current [I(CH)] in the channel 205 is minimized.

[0065] Conversely, I(CH) is maximized when the read magnetization (b) is parallel to the reference magnetization (a), as shown in Figure 6B. When the magnetizations are perpendicular to each other, or when either magnetization is absent, the spin resistance disappears, and only the resistance dependent on the polarization direction in the channel 205 is read by I(CH).

[0066] The polarization of the gate insulating layer 206 is read by measuring the resistance of the channel 205 or the control line 209. Since the channel 205 is a ferromagnetic semiconductor, the resistance of the channel 205 changes (transistor operation) due to the electric field applied from the gate insulating layer 206 (gate electrode 207).

[0067] 7A shows the current characteristics [I(CH)] of the channel 205 when an electric field, Input2, is swept from the gate insulating layer 206 (gate electrode 207) having spontaneous polarization. When Input2 is swept from V=0 to the positive side (V(+)) and negative side (V(-)), respectively, and then Input2 is turned off, positive and negative polarizations are retained in the gate insulating layer 206, respectively. This corresponds to a state in which opposite positive and negative gate electric fields are applied, so a difference between I(+) and I(-) occurs in I(CH) at V=0. In other words, the resistance changes depending on the polarization retained in the gate insulating layer 206, and the direction of polarization is read out by transistor operation.

[0068] The direction of polarization in this gate insulating layer 206 is defined as Memory2. For example, when Input2 is swept as shown in (b) of Figure 7, I(CH) settles into two values, I(+) and I(-), and the signal changes according to the reversal of the polarity of Input2 (rotation of polarization).

[0069] The channel 205 and the control line 209 are sufficiently close to each other and are electrostatically coupled. Figure 8(a) shows a transparent circuit diagram of the state in which the channel 205 and the control line 209 are coupled by a floating electrostatic capacitance (C). When charge accumulates in CH (channel 205), the potential of WRL (control line 209) changes via the capacitance C. This potential change causes a resistance change in the control line 209 in proportion to the charge density of the channel 205. Therefore, when a constant voltage is applied to the circuit of the control line 209, the charge density of the channel 205 can be read out by measuring the current I(WRL) of the control line 209.

[0070] The corresponding polarization direction (Memory2) is read out from the read charge density. This technology is mainly applied when the channel 205 is completely insulated from the source 203 and drain 204 by Input3 of the first ferroelectric layer 206a and the second ferroelectric layer 206b. For example, when Input2 is swept as shown in Figure 8(b), the current I(WRL) flowing through the control line 209 settles into two values, I(R-) and I(R+), and the signal changes according to the polarity reversal (polarization rotation) of Input2.

[0071] As described above, a combination of Memory2 via Input2 and Memory1 via Input4 can be read. The relationship between these combinations and I(CH) is shown in Table 1 below. For simplicity, the reference magnetization is fixed upward. Depending on the combination of the polarization states of the first ferroelectric layer 206a (TG1) and the second ferroelectric layer 206b (TG2) and the read magnetization state, I(CH) can take five values: I(++↑↑), I(++↑↓), I(++), I(+-), and I(--). Furthermore, since the relative angle of the magnetization in the channel 205 can take continuous values ​​independent of the polarization direction, the analog signal of the continuous I(CH) is expressed as I(++↑↑cosθ). θ is the relative angle between the reference magnetization and the read magnetization. Furthermore, a combination state in which the "magnetization-dependent resistance (spin resistance)" is 0 indicates a condition in which no spin resistance occurs.

[0072] [Table 1]

[0073] FIG. 9 shows the state of multi-valued memory operation in which the output [I(CH)], which is a function of Input2 and Input4, can retain multiple states even when the inputs to the first ferroelectric layer 206a and the second ferroelectric layer 206b are cut off.

[0074] Incidentally, in the spin element according to the first embodiment, after injecting (inducing) charge into the channel 105, magnetization in the channel 105 can be generated and controlled using a control line. In addition, in the spin element according to the first embodiment, magnetization information is retained by applying V(+) to the gate 106 (electrode 107), and there are two options for polarization in the gate 106 depending on the polarity of the applied voltage. Therefore, when the applied voltage is in a positive (+) state, two different or continuous magnetization directions are retained in the magnetization in the channel 105. In addition, in the spin element according to the first embodiment, two spin elements provided with a control line can be connected together to be used as a multi-level memory, as in the description using FIGS. 6A and 6B.

[0075] In the spin element according to the second embodiment, the polarization states of the first ferroelectric layer 106a and the second ferroelectric layer 106b correspond to Memory 2 in the spin element according to the third embodiment. The polarization states of the first ferroelectric layer 106a and the second ferroelectric layer 106b can also be selected according to the polarity of the applied voltage. When the applied voltage is V(+) (magnetization generation state), charge can be accumulated in the channel 105, and magnetization occurs. By controlling this magnetization state using a control line, the magnetization state in the channel 105 can be given two directions, up and down, or a continuous magnetization direction. In addition, the spin element according to the second embodiment can also be used as a multi-level memory by connecting two spin elements provided with control lines, as described with reference to FIGS. 6A and 6B.

[0076] Furthermore, the spin element according to the first embodiment and the spin element according to the second embodiment have a simpler element structure than the spin element according to the third embodiment, and have the advantage of simplifying the process of fabricating the element.

[0077] Furthermore, in the spin element according to the second embodiment, the magnetization direction can be controlled by irradiating the channel 105 with circularly polarized light (Reference 5). For example, by irradiating the surface of the channel 105 with right-handed circularly polarized light from a direction perpendicular to the channel 105, the magnetization direction of the charge injected (induced) into the channel 105 can be made upward. On the other hand, by irradiating the surface of the channel 105 with left-handed circularly polarized light from a direction perpendicular to the channel 105, the magnetization direction of the charge injected (induced) into the channel 105 can be made downward.

[0078] Furthermore, since the channel in which magnetic impurities are added to the semiconductor layer can be regarded as a ferromagnetic memory cell, a method of writing and reading magnetization using a magnetic head can be applied. In this case, since no control line is required, the element can be further integrated. For these operations, the structure of the spin element according to the second embodiment, which does not use a gate, is suitable.

[0079] On the other hand, in the spin element according to the third embodiment, the gate electrode 207, the first electrode 207a, and the second electrode 207b can substitute for the control line 209 that serves as Input 4 by passing a current through them. For example, in the case of the gate electrode 207, the gate insulating layer 206 can be thinned to about 10 nm, so that the distance between the gate electrode 207 used as a control line and the channel 205 can be further narrowed. Therefore, the magnetization of the channel 205 can be controlled with a smaller Input 4. This also means that higher density magnetization can be controlled.

[0080] Next, by making the width and thickness of the channel in plan view nano-sized enough to manifest quantum effects, and also by making the distance between the two ferroelectric layers sandwiching the channel nano-sized, the effect of confining charges in the channel can be further strengthened.

[0081] By setting the dimensions of the channel 205 and the distance between the first ferroelectric layer 206a and the second ferroelectric layer 206b to nanometer scale, a discrete electronic state is generated in the channel 205, as shown in FIG. 10A. Since the voltage required for charge injection into the channel 205 is discrete, the value of I(CH) is also discrete. In other words, the possible values ​​of I(CH) are multi-valued. In FIG. 10A, downward arrows indicate charge spins, and upward arrows indicate impurity spins.

[0082] Furthermore, when the charge state of the channel 205 is quantized, the spin state of the charge in the channel 205 becomes single spin or singlet depending on whether the charge number is even or odd. In this state, the spin number of the channel 205 can be either finite [(a) in Figure 10A] or zero [(b) in Figure 10A]. Because the spin number and the exchange interaction are proportional, the generation and annihilation of magnetization (Memory1) caused by the exchange interaction can be controlled by whether the charge number is even or odd. In other words, with respect to the state shown in Table 1, an option is added in which magnetization does not occur when Input2 of V(+) is applied to the gate electrode 207.

[0083] As described above, when the state in the channel 205 is discretized by making it nano-sized and the state becomes a ferromagnetic semiconductor state with a finite exchange interaction, the direction of the charge spin that can be injected and accumulated from the source 203 into the channel 205 becomes a fixed single number. For example, as shown in (a) of FIG. 10B, the energy level [E ch (N,↑)] below the level of the source 203, and the Fermi level (E F_D ), the state of the charge transported from the source 203 to the channel 205 is limited to the possible states of the charge in the channel 205 (number of electrons N × up spin), and a state is formed in which only up spin is transported.

[0084] On the other hand, as shown in FIG. 10B(b), the energy level of the source 203 is set to a virtual level [E ch (N+1,↓)] and E F_D Ech When the value is lower than (N+1,↓), only down spins are transported. This phenomenon is called spin filtering or spin blockade, and can be used to generate spin-polarized current.

[0085] A feature of the spin filter realized by this spin element is that it can be controlled (ON / OFF) without applying an external magnetic field. Furthermore, the strength of the exchange interaction that serves as the driving force reaches approximately 40 meV, which corresponds to a temperature of 200°C and a magnetic field of 340 T. In terms of operation without a magnetic field and resistance to thermal disturbance, this spin filter has advantages in terms of device applications over conventional magnetic-field-induced spin filters that use semiconductor quantum dots.

[0086] When two of the above-described spin elements are connected, spin resistance similar to that described using Figures 6A and 6B occurs. Therefore, memory operation is possible. Furthermore, for the reasons described above, this spin element can operate with the transport of a single charge, which is the minimum current.

[0087] Furthermore, the spin element according to the present invention can be used for purposes other than memory. For example, as shown in FIG. 11(a), multiple spin elements can be connected in a lattice configuration. Around the charge spins in the ferromagnetic semiconductor channel 205, there exists a spin state that oscillates and spreads (Friedel oscillations) (Reference 2). As shown by the direction of the arrows indicating the charge spins in FIG. 11(a), the above-mentioned oscillations change depending on the distance and the Fermi wave number as an exchange interaction.

[0088] Thus, even in a configuration in which multiple spin elements are connected in a lattice, the exchange interaction value of adjacent channels 205 can be controlled from positive to negative by controlling the distance between adjacent channels 205 and the Fermi wave number. In this control, the magnetizations of adjacent channels 205 are stabilized in an arrangement in which they are parallel, antiparallel, or have a certain relative angle, as shown in Figure 11(b) (Reference 6). In Figure 11(b), "2D" indicates the value of a two-dimensional channel, and "3D" indicates the value of a three-dimensional channel.

[0089] This phenomenon can be described by the Ising model based on exchange interactions via charge and spin, so this array structure operates as an Ising machine. Here, the Fermi wave number is controlled by the electric field from the first ferroelectric layer, the second ferroelectric layer, or the substrate (back gate). When the channels 205 are insulated from each other by the electric field from the first and second ferroelectric layers, the magnetization remains, but the magnetic interaction between the channels 205 disappears.

[0090] In this state, if the magnetic interaction within the channel 205 is weakened by an electric field from the gate electrode or substrate, the magnetization begins to rotate randomly due to thermal disturbance. Again, exchange interactions between each channel 205 are generated by manipulating the first and second ferroelectric layers. Repeating this operation at high speed is equivalent to annealing the magnetization. When charge spins are released from the channel 205 by applying a predetermined voltage to the source 203, substrate, and gate electrode, the magnetization information of each channel 205 is lost and the information in the spin element is initialized.

[0091] Furthermore, the arrangement of multiple spin elements can be freely selected, such as a square, hexagonal, or kagome lattice. Therefore, if the channel 205 is considered as a pseudo-magnetic atom, it is possible to mimic the relationship between the magnetization behavior and exchange interaction in various magnetic atomic lattices.

[0092] As explained above, according to the present invention, a ferroelectric layer is provided on a channel formed by adding magnetic impurities between a source and drain formed in a semiconductor layer, making it possible to provide a new spin element using a ferromagnetic semiconductor. A spin element combining a ferromagnetic semiconductor and a ferroelectric layer can realize a charge-magnetization memory capable of multi-value operation that can be manufactured using conventional semiconductor element manufacturing processes without using a ferromagnetic metal film. Furthermore, because magnetization can be electrically generated, controlled, and maintained, it can be used as a general-purpose memory element having the characteristics of both a transistor and a hard disk.

[0093] In the above explanation, an example was shown in which the semiconductor constituting the ferromagnetic semiconductor used as the channel is silicon and the magnetic impurities added are Fe, Co, or Mn, but this is not limited thereto, and ferromagnetic materials formed by the combination of any semiconductor that can become a ferromagnetic semiconductor and any magnetic impurity can be applied to the present invention. Furthermore, the materials constituting the first ferroelectric layer, the second ferroelectric layer, and the gate are not limited to HfO2, and any ferroelectric material can be applied to the present invention.

[0094] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0095] [References] [References 1] MA Ruderman and C. Kittel, "Indirect Exchange Coupling of Nuclear Magnetic Moments by Conduction Electrons", Physical Review, vol. 96, no. 1, pp. 99-102, 1954. [Reference 2] T. Kasuya, "A Theory of Metallic Ferro- and Antiferromagnetism on Zener's Model", Progress of Theoretical Physics, vol. 16, no. 1, pp. 45-57, 1956. [Reference 3] K. Yosida, "Magnetic Proyerties of Cu-Mn Alloys", Physical Review, vol. 106, no. 5, pp. 893-898, 1957. [Reference 4] TS Boscke et al., "Ferroelectricity in hafnium oxide thin films", Applied Physics Letters, vol. 99, 102903, 2011. [Reference 5] RC Myers et al., "Zero-field optical manipulation of magnetic ions in semiconductors", Nature Materials, vol. 7, pp. 203-208, 2008. [Reference 6] H. Tamura et al., "Tunable Exchange Interaction in Quantum Dot Devices", Japanese Journal of Applied Physics, vol. 43, no. 5B, pp. L691-L693, 2004. [Explanation of symbols]

[0096] 101...Substrate, 102...Semiconductor layer, 103...Surface, 104...Door, 106...Surface, 106a...First ferroelectric layer, 106b...Second ferroelectric layer, 107a...First electrode, 107b...Second electrode, 108...Insulating layer.

Claims

1. a semiconductor layer formed on a substrate; a source and a drain formed at a predetermined interval in the semiconductor layer; a magnetically doped channel formed in the semiconductor layer between the source and the drain; a first ferroelectric layer and a second ferroelectric layer, each made of a ferroelectric material, for applying an electric field to both ends of the channel in a direction from the source to the drain to deplete both ends of the channel; Equipped with A spin element in which charge is injected into the channel by applying a voltage between the source and the drain, and magnetization information in the channel into which charge has been injected is retained depending on the polarity of the voltage applied to the first ferroelectric layer and the second ferroelectric layer.

2. 2. The spin element according to claim 1, The spin element further comprises a gate electrode for applying an electric field to the channel in a region between the first ferroelectric layer and the second ferroelectric layer.

3. a semiconductor layer formed on a substrate; a source and a drain formed at a predetermined interval in the semiconductor layer; a magnetically doped channel formed in the semiconductor layer between the source and the drain; a gate made of a ferroelectric material for applying an electric field to the channel; Equipped with A spin element in which charge is injected into the channel by applying a voltage between the source and the drain, and magnetization information in the channel into which charge has been injected is retained by applying a voltage to the gate.

4. The spin element according to any one of claims 1 to 3, The spin element further comprises a control line that is electrostatically coupled to the channel and controls and reads out the magnetization state of the channel.

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