Semiconductor Devices

Abstract

The present invention improves the radiation resistance of a solid-state imaging element.　A semiconductor device (100) includes a pixel circuit (10) formed on a semiconductor substrate (1). The pixel circuit has: a first semiconductor region (1) of a first conductive type; a second semiconductor region (3) of a second conductive type that is formed on the first semiconductor region and that constitutes a photodiode (PPD) together with the first semiconductor region; a third semiconductor region (6) of the second conductive type that is formed on the semiconductor substrate separated from the second semiconductor region so as to surround the photodiode in plan view; a gate region (5) that is formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region in the plan view and that constitutes, together with the second semiconductor region and the third semiconductor region, an overflow transistor (Mpdr) for discharging charge accumulated in the photodiode; and an insulating layer (9) that is formed on the semiconductor substrate separated from the third semiconductor region so as to surround the third semiconductor region in the plan view.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device having a solid-state image sensor formed on a semiconductor substrate. [Background technology]

[0002] In decommissioning work at nuclear facilities, imaging devices are attached to the tip of robot arms, etc., in order to perform work while understanding the situation inside the facility in a high-radiation environment. In recent years, as imaging devices to be used in high-radiation environments, there has been a demand for radiation-resistant cameras that are small, lightweight, and have high image quality, rather than the large, low-image-quality image pickup tubes used in conventional radiation-resistant cameras.

[0003] However, it is known that the characteristics of solid-state imaging devices formed on semiconductor substrates are degraded by the total dose effect of radiation such as gamma rays. For example, in the case of solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors, the dark current of the photodiodes acting as optical sensors increases due to the ionization caused by the total dose effect of gamma rays, resulting in operational malfunctions due to whiteout. Whiteout due to the total dose effect can shorten the life of solid-state imaging devices and, ultimately, cameras. For example, the cumulative radiation dose, which is an indicator of the radiation resistance of image pickup tubes, is several megaGy, while the cumulative radiation dose of solid-state imaging devices is several kiloGy to 100 kiloGy. As described above, conventional solid-state imaging devices cannot be said to have high radiation resistance.

[0004] Meanwhile, a technology for improving the radiation resistance of solid-state imaging devices is disclosed in Patent Document 1. Specifically, Patent Document 1 discloses a solid-state imaging device with improved radiation resistance by employing a pinned photodiode (PPD) in which an N-well is formed on a P-well of a semiconductor substrate and a P-type semiconductor region of a pinning layer is formed on the surface portion in contact with an interlayer insulating oxide film (pre-metal dielectric: PMD). Here, the PPD has a structure surrounded by an element isolation layer (element isolation oxide film layer) made of STI (Shallow Trench Isolation). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-201164 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the technique disclosed in Patent Document 1 alone is not sufficient to suppress the dark current of the photodiode that causes whiteout.

[0007] For example, when radiation hits the element isolation oxide layer (hereinafter also referred to as "STI") around the photodiode, fixed positive charges (Radiation-induced positive charges) are generated due to the total dose effect, and the influence of these fixed positive charges causes the P-well region near the STI to invert to N-type, forming an N-type inversion region (Induced N-region). Dark current flows from this N-type inversion region into the N-type diffusion region of the photodiode, which may cause whiteout in the image.

[0008] Prior to filing this application, the inventors of the present invention have investigated a solid-state imaging device having a new structure to solve the above problems.

[0009] FIG. 12 is a diagram showing the configuration of one pixel circuit constituting a solid-state imaging device that the present inventors have studied prior to filing the present application. FIG. 13A is a plan view showing the layout configuration of the pixel circuit shown in FIG. 12 as a semiconductor device. FIG. 13B is a diagram schematically showing a cross-sectional structure of the pixel circuit shown in FIG. 13A taken along line AA'.

[0010] As shown in Figures 13A and 13B, one pixel circuit 90 constituting a solid-state imaging device as an example of prior study by the inventors of the present application has a structure in which the periphery of a photodiode PPD is surrounded not by STI (e.g., SiO2) but by the gate and drain of an overflow transistor (transistor for discharging charge) Mpdr for resetting the photodiode PPD on a P-type semiconductor substrate 91.

[0011] According to this structure, the drain of the overflow transistor Mpdr functions as a guard ring around the photodiode PPD, and the photodiode PPD and the STI99 are not in direct contact with each other, so that dark current may be suppressed.

[0012] However, even when the above-described structure is adopted, an STI is inevitably formed around the overflow transistor Mpdr, and the inventors' investigations have revealed that dark current generated near the STI due to the total dose effect of radiation may flow into the photodiode through the semiconductor substrate, causing whiteout in the image. This point will be explained in detail below.

[0013] FIG. 14 is a diagram schematically showing the expansion of the space charge region when no power supply voltage is applied to the pixel circuit shown in FIG. 13A.

[0014] FIG. 15 is a diagram for explaining the principle of generation of dark current when radiation is irradiated onto the pixel circuit shown in FIG. 13A in the case where no power supply voltage is applied to the pixel circuit.

[0015] FIG. 16 is a diagram for explaining the principle of generation of dark current when radiation is irradiated onto the pixel circuit shown in FIG. 13A in a case where a power supply voltage is applied to the pixel circuit.

[0016] 14 and 15, in order to represent a state in which no power supply voltage (VDD, VRR, etc.) is applied to the pixel circuit 90, the drain electrode (N well 96) of the overflow transistor Mpdr will be described as being connected to ground potential (0V).

[0017] 14 to 16, a space charge region (depletion layer) 80 formed in a semiconductor substrate (P-type silicon substrate) 91 is schematically represented by a dotted line.

[0018] For example, consider a case where radiation (ionizing radiation) such as gamma rays is irradiated onto the pixel circuit 90. In this case, as shown in FIG. 15, electron-hole pairs are generated in the STI 99 of the pixel circuit 90 due to the ionization caused by the radiation.

[0019] Of the electron-hole pairs generated within the STI 99, the negatively charged electrons have high mobility and are swept to the surrounding electrodes in a relatively short time, where they disappear. On the other hand, the positively charged holes have lower mobility than the electrons and are left behind within the insulator (STI). These holes are gradually swept outward from the insulator, but in the process, they are captured by defects near the interface between the STI 99 and the semiconductor substrate (P-type silicon substrate) 91, and become fixed positive charges (radiation-induced positive charges) within the STI 99, as shown in Figure 15.

[0020] This fixed positive charge causes a portion of the STI 99 near the boundary with the semiconductor substrate 91 to be positively charged up (+), so that, as shown in FIG. 14, the region of the semiconductor substrate 91 with a low concentration of P-type impurities near the boundary with the STI 99 is inverted to N-type, forming an N-type inversion region (induced N-region) 81.

[0021] Here, since the interface between the semiconductor substrate 91 and the STI 99 has many defects such as dangling bonds, dark current due to thermal excitation is likely to occur via defect levels, even at room temperature. Furthermore, since the P-type impurity concentration of the semiconductor substrate 91 is low, a space charge region 80 near the N-type region 81 in the semiconductor substrate 91 expands significantly, as shown in FIG. 15 . This results in a state in which the drain of the charge discharging transistor Mpdr and the photodiode PPD are connected via the space charge region 80 in the semiconductor substrate 91. Therefore, electrons that become dark current and are generated in the N-type inversion region 81 in the semiconductor substrate 91 are likely to flow into the photodiode PPD.

[0022] 16, when the pixel circuit 90 is actually operated, a positive power supply voltage VRR (>0V) is applied to the drain electrode of the charge discharging transistor Mpdr, and some of the multiple electrons that become dark current generated in the N-type inversion region 81 in the semiconductor substrate 91 flow into the power supply voltage VRR via the drain of the overflow transistor Mpdr. This makes it possible to reduce the dark current that flows into the photodiode PPD.

[0023] However, when a positive power supply voltage VRR is applied to the drain electrode of the overflow transistor Mpdr, the space charge region 80 expands further in the depth direction of the semiconductor substrate 91. As a result, electrons that become dark current may flow into the photodiode PPD through a relatively deep region of the semiconductor substrate 91, increasing the dark current.

[0024] The present invention has been made in view of the above-mentioned problems, and has an object to improve the radiation resistance of a solid-state imaging device. [Means for solving the problem]

[0025] A semiconductor device according to a representative embodiment of the present invention comprises a semiconductor substrate and a pixel circuit formed on the semiconductor substrate, the pixel circuit comprising: a first semiconductor region of a first conductivity type in the semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region; a third semiconductor region of the second conductivity type formed in the semiconductor substrate at a distance from the second semiconductor region so as to surround the photodiode in a plan view seen from a direction perpendicular to the plane of the semiconductor substrate; a gate region formed between the second semiconductor region and the third semiconductor region in the semiconductor substrate in the plan view and constituting an overflow transistor together with the second semiconductor region and the third semiconductor region that discharges charge accumulated in the photodiode; and an insulating layer formed in the semiconductor substrate at a distance from the third semiconductor region so as to surround the third semiconductor region in the plan view. [Effects of the Invention]

[0026] According to the semiconductor device of the present invention, it is possible to improve the radiation resistance of the solid-state imaging device. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a diagram showing the configuration of one pixel circuit that constitutes a solid-state imaging device as a semiconductor device according to a first embodiment. [Figure 2A] 1 is a plan view showing a layout configuration of a pixel circuit of a semiconductor device according to a first embodiment. [Figure 2B] 2B is a diagram schematically showing a cross-sectional structure of the pixel circuit shown in FIG. 2A taken along the line BB'. FIG. [Figure 3] 1 is a plan view showing a layout configuration of a semiconductor device in which a plurality of pixel circuits according to a first embodiment are arranged. [Figure 4] 4 is a diagram schematically showing the expansion of a space charge region when no power supply voltage is applied to the pixel circuit according to the first embodiment. FIG. [Figure 5]5 is a diagram schematically showing the effect of suppressing dark current when radiation is irradiated onto a pixel circuit according to Embodiment 1 in the case where no power supply voltage is applied to the pixel circuit. FIG. [Figure 6] 5 is a diagram schematically showing the effect of suppressing dark current when radiation is irradiated onto a pixel circuit according to the first embodiment in a case where a power supply voltage is applied to the pixel circuit. FIG. [Figure 7A] FIG. 10 is a plan view showing a layout configuration of a pixel circuit of a semiconductor device according to a second embodiment. [Figure 7B] 7B is a diagram schematically showing a cross-sectional structure of the pixel circuit shown in FIG. 7A taken along the line CC'. FIG. [Figure 8] 10 is a plan view showing a layout configuration of a semiconductor device in which a plurality of pixel circuits according to a second embodiment are arranged. FIG. [Figure 9] 10 is a diagram schematically showing the expansion of a space charge region when no power supply voltage is applied to the pixel circuit according to the second embodiment. FIG. [Figure 10] 10 is a diagram schematically showing the effect of suppressing dark current when radiation is irradiated onto a pixel circuit according to Embodiment 2 in the case where no power supply voltage is applied to the pixel circuit. FIG. [Figure 11] 10 is a diagram schematically showing the effect of suppressing dark current when a pixel circuit according to Embodiment 2 is irradiated with radiation in a case where a power supply voltage is applied to the pixel circuit. FIG. [Figure 12] 1 is a diagram showing the configuration of one pixel circuit constituting a solid-state imaging device that the present inventors have studied prior to filing the present application; [Figure 13A] 13 is a plan view showing the layout configuration of the pixel circuit shown in FIG. 12 as a semiconductor device. FIG. [Figure 13B] 13B is a diagram schematically showing a cross-sectional structure of the pixel circuit shown in FIG. 13A taken along the line AA'. FIG. [Figure 14] 13B is a diagram schematically illustrating the expansion of a space charge region when no power supply voltage is applied to the pixel circuit shown in FIG. 13A. FIG. [Figure 15]13B is a diagram for explaining the principle of generation of dark current when radiation is irradiated to the pixel circuit shown in FIG. 13A in the case where no power supply voltage is applied to the pixel circuit. FIG. [Figure 16] 13B is a diagram for explaining the principle of generation of dark current when radiation is irradiated to the pixel circuit shown in FIG. 13A in a case where a power supply voltage is applied to the pixel circuit. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0028] 1. Overview of the embodiment First, a typical embodiment of the invention disclosed in this application will be outlined. In the following description, for example, reference numerals in the drawings corresponding to components of the invention are written in parentheses.

[0029] [1] A semiconductor device (100, 100A) according to a representative embodiment of the present invention comprises a semiconductor substrate (1) and a pixel circuit (10, 10A) formed on the semiconductor substrate, the pixel circuit comprising a first semiconductor region (1) of a first conductivity type (e.g., P-type) in the semiconductor substrate, a second semiconductor region (3) of a second conductivity type (e.g., N-type) formed on the first semiconductor region and constituting a photodiode (PPD) together with the first semiconductor region, and a front semiconductor region (4) surrounding the photodiode in a plan view seen from a direction perpendicular to the plane of the semiconductor substrate (e.g., the positive side in the Z direction). The photodiode is characterized by having a third semiconductor region (6) of the second conductivity type formed in the semiconductor substrate at a distance from the second semiconductor region, a gate region (5) formed between the second semiconductor region and the third semiconductor region in the semiconductor substrate in the planar view, and constituting an overflow transistor (Mpdr) that, together with the second semiconductor region and the third semiconductor region, discharges charge accumulated in the photodiode, and an insulating layer (9) formed in the semiconductor substrate at a distance from the third semiconductor region so as to surround the third semiconductor region in the planar view.

[0030] [2] The semiconductor device (100, 100A) described in [1] above may further include a fourth semiconductor region (13) of the second conductivity type formed in the semiconductor substrate, spaced apart from the third semiconductor region and adjacent to the insulating layer in the planar view.

[0031] [3] In the semiconductor device described in [2] above, in the planar view, the semiconductor substrate may further include a fifth semiconductor region (11) of the first conductivity type formed between the second semiconductor region and the insulating layer and spaced apart from the second semiconductor region and the insulating layer, and the third semiconductor region may be formed on the fifth semiconductor region.

[0032] [4] The semiconductor device (100A) described in [3] above may further include, in the planar view, a sixth semiconductor region (14) of the first conductivity type formed between the fifth semiconductor region and the insulating layer in the semiconductor substrate, the fourth semiconductor region being formed on the sixth semiconductor region, and the impurity concentration of the sixth semiconductor region being lower than the impurity concentration of the fifth semiconductor region.

[0033] [5] In the semiconductor device described in [4] above, the sixth semiconductor region may be further formed below the insulating layer.

[0034] [6] In the semiconductor device described in any one of [3] to [5] above, the voltage (VDR) that can be applied to the fourth semiconductor region (13) may be equal to or greater than the voltage (VRR) that can be applied to the third semiconductor region (6).

[0035] [7] In the semiconductor device described in [6] above, a voltage (VRR) that can be applied to the third semiconductor region may be equal to or lower than a withstand voltage of the semiconductor device.

[0036] [8] In the semiconductor device according to any one of [1] to [7] above, the pixel circuit further includes a transfer transistor (Mtg) that transfers charges of the photodiode, a charge storage unit (FD) that stores the charges transferred by the transfer transistor, a reset transistor (Mfdr) that resets the voltage of the charge storage unit, an amplifier transistor (Mdrv) that amplifies a signal corresponding to the charges stored in the charge storage unit, and a selection transistor (Msel) that switches whether or not to output the signal amplified by the amplifier transistor to a signal line, The diode may be formed in a polygonal shape in the planar view, the third semiconductor region may be formed in a form surrounding at least one side of the polygonal photodiode except for one side in the planar view, the gate region may be formed between the second semiconductor region and the third semiconductor region in a form surrounding at least the other side of the photodiode in the planar view, and the transfer transistor, the reset transistor, the amplifying transistor, and the selection transistor may be formed in a region on the one side of the photodiode in the planar view.

[0037] [9] The semiconductor device described in [8] above may have a plurality of pixel circuits, and the plurality of pixel circuits may be formed side by side in a column direction (e.g., a Y-axis direction) that is a predetermined direction in the plane of the semiconductor substrate and a row direction (e.g., an X-axis direction) that is a direction perpendicular to the column direction, in the planar view, and the pixel circuits adjacent to each other in the row direction may have the insulating layer common to each other in the row direction.

[0038] 2. Specific examples of embodiments Specific examples of embodiments of the present invention will be described below with reference to the drawings. In the following description, components common to each embodiment will be given the same reference numerals, and repeated description will be omitted. It should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from the actual situation. The drawings may also include portions with different dimensional relationships and ratios. Furthermore, in this specification, the first conductivity type is described as P type and the second conductivity type is described as N type as an example, but the present invention is not limited to this.

[0039] First Embodiment FIG. 1 is a diagram showing the configuration of one pixel circuit that constitutes a solid-state imaging device as a semiconductor device according to the first embodiment.

[0040] The semiconductor device 100 according to the first embodiment is, for example, a CMOS image sensor serving as a solid-state imaging element. The semiconductor device 100 is formed on a single semiconductor substrate such as silicon using, for example, a known CMOS LSI (Large Scale Integration) manufacturing process technology.

[0041] The semiconductor device 100 has a plurality of pixel circuits 10 formed on a semiconductor substrate 1. The pixel circuit 10 is, for example, a five-transistor pixel circuit that further adds an overflow transistor Mpdr to a four-transistor pixel circuit having four transistors, also known as an APS (Active Pixel Sensor). Specifically, the pixel circuit 10 has a photodiode PPD, a transfer transistor Mtg, a charge storage unit FD, a reset transistor Mfdr, an amplification transistor Mdrv, a selection transistor Msel, and an overflow transistor Mpdr.

[0042] The photodiode PPD is, for example, a pinned photodiode, as will be described later. In the photodiode PPD, the anode electrode is connected to the ground potential GND, and the cathode electrode is connected to the source of the transfer transistor Mtg.

[0043] The transfer transistor Mtg is an element for transferring the charge of the photodiode PPD, and is, for example, a MOS transistor of the second conductivity type (N-type).

[0044] The source electrode of the transfer transistor Mtg is connected to the cathode electrode of the photodiode PPD, and the drain electrode is connected to the gate electrode of the amplifier transistor Mdrv and the source electrode of the reset transistor Mfdr. A binary signal φTG is input to the gate electrode of the transfer transistor Mtg. The transfer transistor Mtg is switched on and off by the signal φTG.

[0045] The charge storage unit (Floating Diffusion) FD stores the charge transferred by the transfer transistor Mtg. The charge storage unit FD is formed at a node where the drain electrode of the transfer transistor Mtg, the gate electrode of the amplification transistor Mdrv, and the source electrode of the reset transistor Mfdr are commonly connected. The charge storage unit FD is realized, for example, by parasitic capacitance and stray capacitance present at the node.

[0046] The reset transistor Mfdr is a charge discharging element that resets the voltage of the charge storage unit FD. The reset transistor (charge discharging transistor) Mfdr is, for example, a second conductivity type (N-channel) MOS transistor. The source electrode of the reset transistor Mfdr is connected to the charge storage unit FD, and the drain electrode of the reset transistor Mfdr is connected to the power supply voltage VRR. A binary signal φFDR is input to the gate electrode of the reset transistor Mfdr. The reset transistor Mfdr is switched on / off by the signal φFDR.

[0047] The amplifier transistor Mdrv is an element that amplifies a signal corresponding to the charge stored in the charge storage unit FD. The amplifier transistor Mdrv is, for example, a MOS transistor of a second conductivity type (N-channel type), and forms a source follower circuit.

[0048] The drain electrode of the amplifier transistor Mdrv is connected to the power supply voltage VDD, the gate electrode of the amplifier transistor is connected to the charge storage unit FD, and the source electrode of the amplifier transistor Mdrv is connected to the output signal line OUT via the selection transistor Msel.

[0049] The selection transistor Msel is an element that switches whether or not the signal amplified by the amplification transistor Mdrv is output to the output signal line OUT. The selection transistor Msel is, for example, a MOS transistor of a second conductivity type (N-channel type).

[0050] The drain electrode of the selection transistor Msel is connected to the source electrode of the amplification transistor Mdrv, and the source electrode of the selection transistor Msel is connected to the output signal line OUT. A signal φSEL is input to the gate electrode of the selection transistor Msel. The selection transistor Msel is switched on and off by the signal φSEL.

[0051] The overflow transistor Mpdr is an element that discharges the charge accumulated in the photodiode PPD. The overflow transistor Mpdr is, for example, a MOS transistor of the second conductivity type (N-channel type).

[0052] The overflow transistor Mpdr is connected between the power supply voltage VRR and the cathode electrode of the photodiode PPD. Specifically, the drain electrode of the overflow transistor Mpdr is connected to the power supply voltage VRR, and the source electrode of the overflow transistor Mpdr is connected to the cathode electrode of the photodiode PPD. A binary signal φPDR is input to the gate electrode of the overflow transistor Mpdr. The on / off of the overflow transistor Mpdr is switched by the signal φPDR.

[0053] Here, the power supply voltage VDD is the power supply for the source follower circuit (amplification transistor Mdrv), and the power supply voltage VRR is the power supply for resetting the charge storage unit FD and the photodiode PPD. By separating the power supply voltage VDD and the power supply voltage VRR, it becomes possible to optimize the operating conditions of the pixel. Note that the power supply voltage for resetting the charge storage unit FD and the power supply voltage for resetting the photodiode PPD may be separate. Furthermore, although the present embodiment illustrates a case where the power supply voltage VDD and the power supply voltage VRR are separate, this is not limiting, and the power supply voltage VDD and the power supply voltage VRR may be a common voltage.

[0054] The photodiode PPD accumulates charge in response to the received optical signal. The transfer transistor Mtg turns on when the signal φTG is enabled and transfers the charge accumulated by the photodiode PPD to the charge accumulation unit FD. The amplification transistor Mdr amplifies a signal corresponding to the charge accumulated in the charge accumulation unit FD and outputs it to node N1. The selection transistor Msel turns on when the signal φSEL is enabled and outputs the signal from node N1 to the output signal line OUT. The reset transistor Mfdr turns on when the signal φFDR is enabled and connects the power supply voltage VRR to the charge accumulation unit FD. This causes the electrons accumulated in the charge accumulation unit FD to be discharged to the power supply voltage VRR, resetting the charge accumulation unit FD.

[0055] The overflow transistor Mpdr turns on when the signal φPDR is enabled, connecting the power supply voltage VRR, which is higher than the depletion voltage of the photodiode, to the cathode electrode of the photodiode PPD, where charge is accumulated. This causes the electrons accumulated in the photodiode PPD to be discharged to the power supply voltage VRR, resetting the photodiode PPD. In this way, the overflow transistor Mpdr can function as an electronic shutter for the photodiode PPD.

[0056] As shown in FIG. 1, the pixel circuit 10 according to the first embodiment further includes diodes D1 and D2 formed on the semiconductor substrate 1 due to the structure of the semiconductor device 100, which will be described later. The cathode electrode of the diode D1 is connected to the drain electrode of the overflow transistor Mpdr, and the anode electrode of the diode D1 is connected to the ground potential. The anode electrode of the diode D2 is connected to the ground potential together with the anode electrode of the diode D1. The cathode electrode of the diode D2 is connected to a power supply voltage VDR. Here, the power supply voltage VDR is preferably equal to or higher than the power supply voltage VRR (VDR≧VRR). The power supply voltage VDR will be described in detail later.

[0057] FIG. 2A is a plan view showing the layout configuration of pixel circuit 10 of semiconductor device 100 according to Embodiment 1. FIG.

[0058] FIG. 2B is a diagram schematically showing a cross-sectional structure of the pixel circuit 10 shown in FIG. 2A taken along line BB'.

[0059] In the following description, in the plan views and cross-sectional views of Figures 2A and 2B, the semiconductor substrate 1 is placed in a three-dimensional space consisting of the X-axis, Y-axis, and Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Also, the line segment connecting point B and point B' is parallel to the X-axis. For convenience of explanation, the positive side of the Z-axis direction may be referred to as "up" and the negative side of the Z-axis direction may be referred to as "down."

[0060] 2A shows the layout configuration of the pixel circuit 10 in a plan view seen from a direction perpendicular to the plane (XY plane) of the semiconductor substrate 1 that constitutes the semiconductor device 100. Note that in FIGS. 2A and 2B, wiring layers other than the bottom layer among the wiring layers that connect circuit elements to each other are not shown.

[0061] The semiconductor substrate 1 is, for example, a P-type semiconductor substrate. The semiconductor substrate 1 is formed by doping silicon with a P-type impurity such as B (boron), and functions as a first semiconductor region (P--) of a first conductivity type.

[0062] An N-well (N-) 3 is formed as a second semiconductor region of a second conductivity type on a first semiconductor region (P--) of a first conductivity type. In this embodiment, the first semiconductor region is the semiconductor substrate 1 (P--) itself. The first semiconductor region (semiconductor substrate 1) and the N-well 3 form a PN junction photodiode.

[0063] In the semiconductor device 100, a pinning layer 4 is formed on the N well 3 as a P-type semiconductor layer (P+) having a higher P-type impurity concentration than the semiconductor substrate 1. The pinning layer 4 is formed, for example, by doping (e.g., ion implantation) the surface of the semiconductor substrate 1 with a P-type impurity (e.g., boron (B) or the like). By forming the pinning layer 4, the photodiode becomes a buried photodiode PPD. In this embodiment, the buried photodiode PPD is also simply referred to as a "photodiode PPD."

[0064] As described above, in this embodiment, the semiconductor substrate 1 itself is used as a P-type semiconductor region that constitutes the photodiode PPD. The reason for this will be described in detail below.

[0065] Generally, image sensors for visual imaging require photodiodes that are sensitive to visible light. To improve the sensitivity of photodiodes, it is necessary to separate electron-hole pairs generated by photoelectric conversion before they recombine and accumulate the electrons in the floating N-well of the photodiode. To achieve this, the space charge region (depletion layer) in the PN junction of the photodiode must be formed deep enough to allow light to penetrate the P-type semiconductor substrate (silicon substrate). This is because the electrons and holes generated by photoelectric conversion in the deep space charge region can quickly move—electrons to the N-well side and holes to the P-type semiconductor substrate side (GND)—before they disappear due to recombination, reducing photoelectric conversion loss and significantly improving the quantum efficiency of photoelectric conversion.

[0066] On the other hand, the attenuation distance d of light in a semiconductor substrate (Si substrate) (the distance at which light decays to 1 / e) is expressed as the reciprocal of the absorption coefficient α of silicon (Si). The attenuation distance d of blue light (near λ = 440 nm), which has a short wavelength among visible light, is about 0.3 μm, while the attenuation distance d of red light (near λ = 600 to 700 nm), which has a long wavelength, is 3 to 4 μm. Therefore, it is desirable for the space charge region to be formed to a depth of 3 to 4 μm (several microns) from the surface of the semiconductor substrate.

[0067] However, in typical CMOS LSI manufacturing process technology, the depth from the surface of the semiconductor substrate where the N diffusion regions serving as the source and drain of the transistor are formed is approximately 0.2 μm (submicron). Furthermore, since the N well of the photodiode also serves as the source of the transfer transistor Mtg, if the N well of the photodiode were formed deeper, the channel portion of the gate of the transfer transistor Mtg and the source would be misaligned in the depth direction of the semiconductor substrate, potentially preventing the transfer transistor from turning on properly. Therefore, it is undesirable to form the N well of the photodiode deeper.

[0068] Therefore, in the semiconductor device 100 according to this embodiment, an N well 3 (N-) is formed to a depth of submicrons (<1.0 μm) (however deeper than the pinning layer) without further forming a P well in a P type (P--) semiconductor substrate 1 with a low impurity concentration, and a photodiode PPD is formed by the N well 3 and the P type semiconductor substrate 1. This causes the space charge region generated at the PN junction of the photodiode to expand toward areas with a lower impurity concentration, and the space charge region can be expanded to a depth of several microns from the surface of the semiconductor substrate 1, making it possible to realize a photodiode that has sufficient sensitivity even to red light with a long wavelength.

[0069] If sufficient sensitivity of the photodiode can be achieved, for example, a P-well may be formed by doping a low concentration of P-type impurities into the semiconductor substrate 1, and an N-well 3 may be formed on the P-well to form the photodiode PPD. In this case, the P-well serves as the first semiconductor region. In other words, the first semiconductor region is not limited to the semiconductor substrate 1 itself.

[0070] As shown in FIG. 2A, in a plan view seen from a direction perpendicular to the plane of the semiconductor substrate 1 (positive side of the Z axis), an N diffusion region 6 as a third semiconductor region of the second conductivity type (N type) is formed at a distance from the N well 3 (pinning layer 4) so ​​as to surround the photodiode PPD.

[0071] More specifically, the photodiode PPD is formed, for example, in a polygonal shape in a plan view. Here, a polygonal shape refers to a shape having three or more corners, and examples thereof include a triangular shape, a rectangular shape (quadrilateral shape), a pentagonal shape, and a hexagonal shape. In this embodiment, as an example, the photodiode PPD is described as being formed in a rectangular shape, but is not limited to this.

[0072] In a plan view, the N diffusion region 6 is formed in a shape that surrounds at least one side of the polygonal photodiode PPD except for one side. For example, in the case where the photodiode PPD is rectangular as in the present embodiment, the N diffusion region 6 is formed in a shape that surrounds at least three of the four sides of the photodiode PPD.

[0073] The N diffusion region 6 is formed by, for example, doping (for example, ion implantation) the surface of the semiconductor substrate 1 with an N-type impurity (such as phosphorus (P)).

[0074] Furthermore, in plan view, a gate region 5 is formed on the semiconductor substrate 2 between the N well 3 as the second semiconductor region and the N diffusion region 6 as the third semiconductor region. The gate region 5 is, for example, a gate portion of a MOS (Metal-Oxide-Semiconductor) structure formed from a gate oxide film (e.g., SiO2) and an electrode (e.g., polysilicon) formed on the gate oxide film. For example, as shown in FIG. 2A, the gate region 5 is formed between the N well 3 and the N diffusion region 6 in a form that surrounds at least three sides of the N well 3 of the photodiode PPD in plan view.

[0075] Here, an overflow transistor Mpdr is configured with the N well 3 as a source electrode, the N diffusion region 6 as a drain electrode, and the gate region 5 as a gate electrode.

[0076] 2A, in a plan view, in an area on the one side (an edge other than the three edges) of the rectangular photodiode PPD, circuit elements other than the overflow transistor Mpdr that constitute the pixel circuit 10 are formed. For example, in an area on the one edge on the negative side of the Y axis of the photodiode PPD, a transfer transistor Mtg, a charge storage unit FD, a reset transistor Mfdr, an amplifier transistor Mdrv, and a selection transistor Msel are formed.

[0077] As shown in FIG. 2B, a PMD (Pre Metal Dielectric) 8, which is a transparent insulating film such as SiO 2 , is formed on the surface of the semiconductor substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method.

[0078] Furthermore, the pixel circuit 10 according to the first embodiment further includes an insulating layer 9, a fourth semiconductor region 13 of the second conductivity type (N-type), and a fifth semiconductor region 11 of the first conductivity type (P-type).

[0079] The insulating layer 9 is an element isolation layer (element isolation oxide layer: STI) for isolating adjacent elements (pixel circuits 10) in the semiconductor device 100. The insulating layer 9 is formed of, for example, a silicon oxide film (SiO2). Hereinafter, the insulating layer 9 will also be referred to as "STI 9."

[0080] As shown in FIG. 2A, the STI 9 is formed in the semiconductor substrate 1 at a distance from the N diffusion region 6 (N++) as the third semiconductor region so as to surround the N diffusion region 6 (N++) as the third semiconductor region in a plan view.

[0081] The fourth semiconductor region 13 is, for example, a diffusion region (N++) of a second conductivity type (N type) formed by doping (for example, ion implantation) an N type impurity (such as phosphorus (P)) into the surface of the semiconductor substrate 1. Hereinafter, the fourth semiconductor region 13 is also referred to as an "N diffusion region 13."

[0082] As shown in FIG. 2A, the N diffusion region 13 is formed in the semiconductor substrate 1 so as to be spaced apart from the N diffusion region 6 (N++) as the third semiconductor region and adjacent to the STI 9 in plan view.

[0083] The fifth semiconductor region 11 is, for example, a first conductivity type region (P) formed by doping (e.g., ion implantation) a P-type impurity (such as boron (B)) into the surface of the semiconductor substrate 1. That is, the impurity concentration of the fifth semiconductor region 11 (P) is higher than the impurity concentration of the semiconductor substrate 1 (P--) as the first semiconductor region. Hereinafter, the fifth semiconductor region 11 is also referred to as a "P well 11."

[0084] 2A, the P well 11 is formed between the N well 3 and the STI 9 as a second semiconductor region in the semiconductor substrate 1, and is spaced apart from the N well 3 and the STI 9 in a plan view. As shown in FIG. 2B, the P well 11 is formed in a layer below the N diffusion region 6 as a third semiconductor region. In other words, the N diffusion region 6 is formed on the P well 11.

[0085] 2A and 2B, a P diffusion region 12 having a higher P-type impurity concentration than the P well 11 is formed in a region of the semiconductor substrate 1 that at least partially overlaps with the P well 11 in a plan view, and the P diffusion region 12 is connected to the ground potential. As a result, the P well 11 is connected to the ground potential via the P diffusion region 12.

[0086] The above-described P well 11 (P diffusion region 12) and the N diffusion region 6 serving as the drain electrode of the overflow transistor Mpdr form a diode D1. That is, the diode D1 is formed with the P well 11 (P diffusion region 12) as the anode electrode and the N diffusion region 6 as the cathode electrode.

[0087] Furthermore, a diode D2 is formed by the N diffusion region 13 and the semiconductor substrate 1 (P diffusion region 12, P-Sub). That is, the diode D2 is formed with the semiconductor substrate 1 (P diffusion region 12, P-Sub) as the anode electrode and the N diffusion region 13 as the cathode electrode.

[0088] Next, an example of arrangement in which a plurality of pixel circuits 10 shown in FIGS. 2A and 2B are arranged on semiconductor substrate 1 will be described.

[0089] FIG. 3 is a plan view showing the layout configuration of a semiconductor device 100 in which a plurality of pixel circuits 10 according to the first embodiment are arranged.

[0090] 2A and 2B, the semiconductor substrate 1 is arranged in a three-dimensional space defined by the X-axis, Y-axis, and Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Note that, in FIG. 3, wiring layers connecting circuit elements, except for the bottommost layer, are not shown. In the plane of the semiconductor substrate 1 shown in FIG. 3, the Y-axis direction, which is a predetermined direction, is the column direction, and the X-axis direction is the row direction.

[0091] 3, in the semiconductor device 100, a plurality of pixel circuits 10 are formed on a semiconductor substrate, aligned in the row and column directions in the plane of the semiconductor substrate 1. In each pixel circuit 10, for example, a transfer transistor Mtg, a reset transistor Mfdr, an amplification transistor Mdrv, and a selection transistor Msel are formed (arranged) on one side in the column direction (negative side in the Y-axis direction), and a photodiode PPD, an overflow transistor Mpdr, and diodes D1 and D2 are formed on the other side in the column direction (positive side in the Y-axis direction).

[0092] As shown in FIG. 3, pixel circuits 10 adjacent to each other in the row direction (X-axis direction) have a common STI 9 in the row direction.

[0093] Here, it is preferable to adjust the range of the STI 9 in the row direction (X-axis direction) so that the distance between adjacent photodiodes PPD in the row direction (X-axis direction) is equal, thereby making it possible to make the pixel resolution in the horizontal direction uniform. Similarly, it is preferable to adjust the range of the STI 9 in the column direction so that the distance between adjacent photodiodes PPD in the column direction (Y-axis direction) is equal, thereby making it possible to make the pixel resolution in the column direction uniform.

[0094] Next, the effects of the semiconductor device 100 according to the first embodiment having the above-described structure will be described.

[0095] FIG. 4 is a diagram schematically showing the expansion of the space charge region when no power supply voltage is applied to pixel circuit 10 according to the first embodiment.

[0096] FIG. 5 is a diagram schematically showing the dark current suppression effect when the pixel circuit 10 according to the first embodiment is irradiated with radiation in the case where no power supply voltage is applied to the pixel circuit 10. In FIG.

[0097] In Figures 4 and 5, to represent a state in which no power supply voltage (VDR, VRR, VDD, etc.) is applied to the pixel circuit 90, the N diffusion regions 6, 13 and the P well 11 (P diffusion region 12) are assumed to be connected to ground potential (0V).

[0098] 4, in pixel circuit 10 of semiconductor device 100 according to embodiment 1, N diffusion region 6 serving as the drain electrode of overflow transistor Mpdr is not in contact with STI 9 as in pixel circuit 90 of the previously discussed prior example, but is formed at a distance from STI 9. As a result, even if electrons that become dark current are generated around STI 9, as shown in FIG. 5, these electrons are less likely to flow into photodiode PPD via the space charge region below the drain of overflow transistor Mpdr than in pixel circuit 90 of the previously discussed prior example, making it possible to suppress the inflow of dark current into photodiode PPD.

[0099] 4, the N diffusion region 13 is formed apart from the N diffusion region 6 and adjacent to the STI 9. This allows the N diffusion region 13 to function as a drain (discharge destination) of dark current electrons generated near the STI 9. Furthermore, because the N diffusion region 13 is separated from the N diffusion region 6, it becomes possible to independently adjust the voltage of the N diffusion region 13 to an optimum value that allows the N diffusion region 13 to function as a drain (discharge destination) of dark current electrons.

[0100] Furthermore, as shown in FIG. 4, a P-well 11 is formed apart from the N-well 3 and the STI 9, and an N-diffusion region 6 serving as the drain electrode of the overflow transistor Mpdr is formed on the P-well 11. According to this, since the P well 11 having a higher impurity concentration than the semiconductor substrate 1 is present below the N diffusion region 6 serving as the drain electrode of the overflow transistor Mpdr, the expansion of the space charge region downward (in the negative direction of the Z axis) of the N diffusion region 6 is suppressed compared to the pixel circuit 90 of the previously studied example, as shown in Fig. 4. This makes it possible to narrow the connection between the space charge region near the photodiode PPD and the space charge region near the edge of the STI 9, as shown in Fig. 4.

[0101] For example, consider a case where radiation (ionizing radiation) such as gamma rays is irradiated onto the pixel circuit 10. In this case, as shown in FIG. 5, due to the effect of fixed positive charges generated by the radiation at the edge of the STI 9, a portion of the region adjacent to the STI 9 in the semiconductor substrate 1 is inverted to N-type, forming an N-type inversion region 51, and a space charge region 50 also spreads near the edge of the STI 9. However, as shown in FIG. 5, due to the presence of the P-well 11 between the edge of the STI 9 and the N-well 3, the space charge region 50 between the edge of the STI 9 and the N-well 3 is narrowed, making it difficult for electrons generated by the radiation in the STI 9 to reach the photodiode PPD. This makes it possible to suppress the inflow of dark current into the photodiode PPD.

[0102] FIG. 6 is a diagram schematically showing the dark current suppression effect when the pixel circuit 10 according to the first embodiment is irradiated with radiation in a case where a power supply voltage is applied to the pixel circuit 10. In FIG.

[0103] As shown in FIG. 6, by applying a power supply voltage VRR to the N diffusion region 6 that is the drain electrode of the overflow transistor Mpdr, some of the electrons generated in the STI 9 by radiation are discharged to the power supply voltage VRR side.

[0104] Furthermore, by applying the power supply voltage VDR to the N diffusion region 13 formed adjacent to the STI 9, the potential gradient at the edge of the STI 9 increases, and as shown in Fig. 6, electrons generated in the STI 9 by radiation are more likely to be discharged to the power supply voltage VDR side via the N diffusion region 13. This makes it possible to further suppress the inflow of dark current into the photodiode PPD.

[0105] Here, the voltage (power supply voltage VDR) that can be applied to N diffusion region 13 as the fourth semiconductor region can be equal to or higher than the voltage (power supply voltage VDD) that can be applied to N diffusion region 6 as the third semiconductor region. For example, if the voltage (power supply voltage VDD) that can be applied to N diffusion region 6 is equal to or lower than the withstand voltage of overflow transistor Mpdr, the voltage (power supply voltage VDR) that can be applied to N diffusion region 13 can be equal to or higher than the withstand voltage. The power supply voltage VDR will be described in detail below.

[0106] As described above, by increasing the voltage (power supply voltage VDR) of the N diffusion region 13 adjacent to the STI 9 and increasing the potential gradient, electrons generated near the STI 9 by radiation are discharged to the power supply voltage VDR side, making it possible to suppress the inflow of dark current into the photodiode PPD. Therefore, it is desirable to make the voltage (power supply voltage VDR) of the N diffusion region 13 as high as possible.

[0107] CMOS image sensors are generally manufactured using CMOS LSI manufacturing process technology. Currently, CMOS image sensors are often manufactured using fine CMOS LSI manufacturing process technology with a process rule of 0.18 μm or less, in which case the CMOS image sensor's withstand voltage is approximately 3.3 V. For example, if an NMOS transistor formed using CMOS LSI manufacturing process technology is made an enhancement (normally off) type instead of a depletion (normally on) type, the impurity concentration of the P well used to form the NMOS transistor must be increased. In this case, the PN junction withstand voltage between the N diffusion region, which serves as the source or drain electrode of the NMOS transistor, and the P well is approximately 3.3 V, and this PN junction withstand voltage is the withstand voltage of the CMOS image sensor.

[0108] Here, the semiconductor device 100 according to the first embodiment will be considered. In the semiconductor device 100, the power supply voltage VRR applied to the N diffusion region 6 serving as the drain electrode of the overflow transistor Mpdr is limited by the PN junction withstand voltage between the N diffusion region 6 and the P well 11. This PN junction withstand voltage is the withstand voltage of the semiconductor device 100. For example, if the PN junction withstand voltage between the N diffusion region 6 and the P well 11, i.e., the withstand voltage of the overflow transistor Mpdr, is 3.3 V, the power supply voltage VRR that can be applied to the N diffusion region 6 must be 3.3 V or less.

[0109] On the other hand, the power supply voltage VDR applied to the N diffusion region 13 adjacent to the STI 9 is limited by the PN junction breakdown voltage between the N diffusion region 13 and the semiconductor substrate 1 serving as the first semiconductor region. Here, the semiconductor substrate 1 has a lower impurity concentration than the above-described P well 11. Therefore, the PN junction breakdown voltage between the N diffusion region 13 and the semiconductor substrate 1 is higher than the above-described PN junction breakdown voltage (e.g., 3.3 V) between the N diffusion region 6 and the P well 11.

[0110] Therefore, it is possible to make the power supply voltage VDR that can be applied to the N diffusion region 13 higher than the power supply voltage VRR that can be applied to the N diffusion region 6. Here, the power supply voltage VRR is equal to or lower than the withstand voltage of the overflow transistor Mpdr (for example, 3.3 V or lower), so the power supply voltage VDR can be set to a magnitude equal to or higher than the withstand voltage of the overflow transistor Mpdr (VDR≧VRR).

[0111] By setting the power supply voltage VDR higher than the power supply voltage VRR (the withstand voltage of the overflow transistor Mpdr), electrons that become dark current due to radiation near the STI 9 are more easily discharged to the power supply voltage VDR side, thereby making it possible to further suppress the inflow of dark current into the photodiode PPD.

[0112] Increasing the power supply voltage VDR increases the expansion of the space charge region at the edge of the STI 9, but the P well 11, which has a higher impurity concentration than the semiconductor substrate 1 and is present below the drain electrode (N diffusion region 6) of the overflow transistor Mpdr, narrows the space charge region directly below the P well 11, making it possible to suppress the inflow of dark current into the photodiode PPD.

[0113] As described above, the solid-state imaging element as the semiconductor device 100 according to the first embodiment can effectively discharge electrons generated by radiation and cause the electrons to flow into the photodiode PPD, thereby significantly suppressing dark current due to the total dose effect of radiation and preventing whiteout in images from the solid-state imaging element. In other words, the semiconductor device 100 according to the first embodiment can improve the radiation resistance of the solid-state imaging element.

[0114] Second Embodiment FIG. 7A is a plan view showing the layout configuration of a pixel circuit 10A of a semiconductor device 100A according to the second embodiment.

[0115] FIG. 7B is a diagram schematically showing a cross-sectional structure of the pixel circuit 10 shown in FIG. 7A taken along the line CC'.

[0116] FIG. 8 is a plan view showing the layout configuration of a semiconductor device 100A in which a plurality of pixel circuits 10A according to the second embodiment are arranged.

[0117] 7A, 7B, and 8, similarly to the first embodiment, the semiconductor substrate 1 is arranged in a three-dimensional space defined by the X-axis, Y-axis, and Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Note that in FIGS. 7A, 7B, and 8, wiring layers connecting circuit elements together, except for the bottommost layer, are not shown. In FIG. 8, the Y-axis direction is the column direction, and the X-axis direction is the row direction.

[0118] The semiconductor device 100A of embodiment 2 differs from the semiconductor device 100 of embodiment 1 in that a P well 14 different from the P well 11 is formed between the P well 11 and the STI 9 in each pixel circuit 10A, but is otherwise similar to the semiconductor device 100 of embodiment 1.

[0119] 7A and 7B, in plan view, a P well 14 (L-Pwell / P-) as a sixth semiconductor region of a first conductivity type (P type) is formed between a P well 11 as a fifth semiconductor region and an STI 9 as an insulating layer. For example, the P well 14 is formed in a layer below the N diffusion region 13. In other words, the N diffusion region 13 is formed on the P well 14. Furthermore, for example, the P well 14 may also be formed below the STI 9 as an insulating layer.

[0120] 7A and 7B, P wells 11 and 14 are formed in the range from the end of the STI 9 on the photodiode PPD side to the end of the N diffusion region 6 on the photodiode PPD side. As an example, in FIGS. 7A and 7B, P wells 11 and 14 are formed so that the ratio of P wells 11 to P wells 14 in the above range is 1:1. Note that the ratio of P wells 11 to P wells 14 is not limited to the above example.

[0121] Here, the impurity concentration of the P well 14 (L-Pwell / P-) is lower than the impurity concentration of the P well 11 (Pwell / P). That is, in the semiconductor device 100, the magnitude relationship of the P-type impurity concentrations is P well 11 (P)>P well 14 (P-)>semiconductor substrate 1 (P--).

[0122] For example, by ion-implanting different concentrations of P-type impurities such as B (boron) into the region of the semiconductor substrate 1 (P--) where the P-well 14 is to be formed and the region of the semiconductor substrate 1 (P--) where the P-well 11 is to be formed, it is possible to form the P-well 14 and the P-well 11 having different impurity concentrations. Alternatively, for example, first, P-type impurities such as B (boron) are ion-implanted into the entire region of the semiconductor substrate 1 where the P-well 14 and the P-well 11 are to be formed, and then further P-type impurities such as B (boron) are ion-implanted only into the region where the P-well 11 is to be formed, it is possible to form the P-well 14 and the P-well 11 having different impurity concentrations.

[0123] 7A, P diffusion region 12 is formed so as to overlap at least a portion of P well 11 and at least a portion of P well 14 in a plan view. That is, as shown in Fig. 7B, P diffusion region 12 is formed on P well 11 and P well 14. For example, by connecting P diffusion region 12 to a ground potential, P well 11 and P well 14 can be connected (biased) to the ground potential.

[0124] Next, the effects of the semiconductor device 100A according to the second embodiment having the above-described structure will be described.

[0125] FIG. 9 is a diagram schematically showing the expansion of the space charge region when no power supply voltage is applied to pixel circuit 10A according to the second embodiment.

[0126] FIG. 10 is a diagram schematically showing the dark current suppression effect when the pixel circuit 10A according to the second embodiment is irradiated with radiation in the case where no power supply voltage is applied to the pixel circuit 10A.

[0127] 9 and 10, in order to represent a state in which no power supply voltage (VDR, VRR, VDD, etc.) is applied to the pixel circuit 10A, it is assumed that the N diffusion regions 6 and 13 and the P wells 11 and 14 (P diffusion region 12) are connected to ground potential.

[0128] As shown in FIG. 9, in the pixel circuit 10A of the semiconductor device 100A according to the second embodiment, a P-well 14 having a higher P-type impurity concentration than the semiconductor substrate 1 is formed around the STI 9, and therefore, the expansion of the space charge region 50 directly below the N diffusion region 13 is suppressed compared to the semiconductor device 100 according to the first embodiment.

[0129] 10, when the pixel circuit 10A is irradiated with radiation (ionizing radiation) such as gamma rays, the N-type inversion region 51 formed therein narrows, and accordingly the space charge region 50 also narrows. As a result, compared to the semiconductor device 100 according to the first embodiment, electrons generated in the STI 9 by radiation are less likely to reach the photodiode PPD, and it becomes possible to further suppress the inflow of dark current into the photodiode PPD.

[0130] FIG. 11 is a diagram schematically showing the dark current suppression effect when the pixel circuit 10A according to the second embodiment is irradiated with radiation in a case where a power supply voltage is applied to the pixel circuit 10A.

[0131] As shown in FIG. 11, by applying a power supply voltage VRR to the N diffusion region 6, which is the drain electrode of the overflow transistor Mpdr, some of the electrons generated in the STI 9 by radiation are discharged to the power supply VRR side, as in the semiconductor device 100 according to the first embodiment.

[0132] Furthermore, by applying the power supply voltage VDR to the N diffusion region 13 formed adjacent to the STI 9, electrons generated in the STI 9 by radiation are more likely to be discharged to the power supply voltage VDR side via the N diffusion region 13, as in the semiconductor device 100 according to the first embodiment, as shown in FIG. 11 .

[0133] Here, since the P well 14 directly below the N diffusion region 13 has a lower impurity concentration than the P well 11, the power supply voltage VDR that can be applied to the P well 14 can be equal to or higher than the power supply voltage VRR. By setting the power supply voltage VDR higher than the power supply voltage VRR, as in the semiconductor device 100 according to the first embodiment, it becomes easier to discharge electrons generated near the STI 9 due to radiation to the power supply voltage VDR, thereby making it possible to further suppress the inflow of dark current into the photodiode PPD.

[0134] As described above, according to the semiconductor device 100A according to the second embodiment, it is possible to further improve the radiation resistance of the solid-state imaging element.

[0135] <<Extension of Embodiment>> The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the invention is not limited thereto and can be modified in various ways without departing from the spirit of the invention.

[0136] For example, elements such as transistors and photodiodes may be formed with the first conductivity type being N-type and the second conductivity type being P-type.

[0137] Furthermore, in the above embodiment, the semiconductor substrate 1 is of P type, but this is not limiting, and the semiconductor substrate 1 may be of N type. In this case, for example, a P-well may be formed by doping a low concentration of P-type impurities into an N-type semiconductor substrate, and the circuit elements constituting the pixel circuits 10 and 10A described above may be formed on the P-well.

[0138] Furthermore, in the above embodiment, the case where the power supply voltage VDR is higher than the power supply voltage VDD has been exemplified, but this is not limiting, and the power supply voltage VDR and the power supply voltage VDD may be the same voltage. [Explanation of symbols]

[0139] 1...semiconductor substrate (first semiconductor region), 3...N well (second semiconductor region), 4...pinning layer, 5...gate region, 6...N diffusion region (third semiconductor region), 8...PMD, 9...STI (insulating layer), 10, 10A...pixel circuit, 11...P well (fifth semiconductor region), 12...P diffusion region, 13...N diffusion region (fourth semiconductor region), 14...P well (sixth semiconductor region), 50...space charge region, 51...N-type inversion region, 100, 100A...semiconductor device, D1, D2...diode VDD, VRR, VDR... power supply voltage, φFDR... signal, φPDR... signal, φSEL... signal, φTG... signal.

Claims

1. a semiconductor substrate; a pixel circuit formed on the semiconductor substrate, The pixel circuit a first semiconductor region of a first conductivity type in the semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region; a third semiconductor region of the second conductivity type formed in the semiconductor substrate at a distance from the second semiconductor region so as to surround the photodiode in a plan view seen from a direction perpendicular to the plane of the semiconductor substrate; a gate region formed between the second semiconductor region and the third semiconductor region in the semiconductor substrate in the plan view, and constituting an overflow transistor together with the second semiconductor region and the third semiconductor region that discharges charges accumulated in the photodiode; an insulating layer formed on the semiconductor substrate at a distance from the third semiconductor region so as to surround the third semiconductor region in the plan view; a fourth semiconductor region of the second conductivity type formed in the semiconductor substrate, the fourth semiconductor region being spaced apart from the third semiconductor region and adjacent to the insulating layer in the plan view; a fifth semiconductor region of the first conductivity type formed between the second semiconductor region and the insulating layer in the semiconductor substrate and spaced apart from the second semiconductor region and the insulating layer in the plan view, The third semiconductor region is formed on the fifth semiconductor region. Semiconductor device.

2. 2. The semiconductor device according to claim 1, a sixth semiconductor region of the first conductivity type formed between the fifth semiconductor region and the insulating layer in the semiconductor substrate in the plan view, the fourth semiconductor region is formed on the sixth semiconductor region; The sixth semiconductor region has an impurity concentration lower than the impurity concentration of the fifth semiconductor region. Semiconductor device.

3. 3. The semiconductor device according to claim 2, The sixth semiconductor region is further formed under the insulating layer. Semiconductor device.

4. 4. The semiconductor device according to claim 3, A voltage that can be applied to the fourth semiconductor region is equal to or greater than a voltage that can be applied to the third semiconductor region. Semiconductor device.

5. 5. The semiconductor device according to claim 4, The voltage that can be applied to the third semiconductor region is equal to or less than the withstand voltage of the semiconductor device. Semiconductor device.

6. 6. The semiconductor device according to claim 1, the pixel circuit further includes a transfer transistor that transfers charges of the photodiode, a charge accumulation unit that accumulates the charges transferred by the transfer transistor, a reset transistor that resets a voltage of the charge accumulation unit, an amplification transistor that amplifies a signal corresponding to the charges accumulated in the charge accumulation unit, and a selection transistor that switches whether or not the signal amplified by the amplification transistor is output to a signal line; the photodiode is formed in a polygonal shape in the plan view, the third semiconductor region is formed in a shape that surrounds at least one side of the polygonal photodiode in the plan view, except for one side; the gate region is formed between the second semiconductor region and the third semiconductor region in a form surrounding at least the other side of the photodiode in the plan view, The transfer transistor, the reset transistor, the amplification transistor, and the selection transistor are formed in a region on one side of the photodiode in the plan view. Semiconductor device.

7. 7. The semiconductor device according to claim 6, a plurality of the pixel circuits; the plurality of pixel circuits are formed side by side in a column direction, which is a predetermined direction in a plane of the semiconductor substrate, and in a row direction, which is a direction perpendicular to the column direction, in the plan view; The pixel circuits adjacent to each other in the row direction have the insulating layer common to each other in the row direction. A semiconductor device characterized by:

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