Silicon carbide semiconductor device

Abstract

To provide an SiC semiconductor device which can suppress breakage of a gate insulation film.SOLUTION: In an SiC semiconductor device having a trench gate structure, a trench 25 extends with one direction in a surface direction of a first impurity region 11 as an extension direction, and a first deep layer 15 has such a shape that has a portion in which a first constitution part 15a extending in a direction being the surface direction of the first impurity region 11 and orthogonal to the extension direction is connected with a second constitution part 15b extending in the extension direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a SiC semiconductor device made of silicon carbide (hereinafter also simply referred to as SiC). [Background technology]

[0002] Conventionally, a SiC semiconductor device has been proposed in which a MOSFET (short for metal oxide semiconductor field effect transistor) having a trench gate structure is formed (see, for example, Patent Document 1). Specifically, in this SiC semiconductor device, an n + On a type substrate, an n-type substrate with a lower impurity concentration than the substrate is - A p-type buffer layer is formed, and a low-concentration layer having a lower impurity concentration than the buffer layer is formed on the buffer layer. A p-type first deep layer and an n-type first current spreading layer are formed on the low-concentration layer, extending in one direction as the longitudinal direction. The first deep layers and first current spreading layers are alternately arranged in a direction intersecting the longitudinal direction, with the first current spreading layers located between adjacent first deep layers.

[0003] An n-type second current spreading layer and a p-type second deep layer are disposed on the first deep layer and the first current spreading layer. A p-type base layer is disposed on the second current spreading layer and the second deep layer. The second deep layer is disposed to connect the first deep layer and the base layer.

[0004] The surface of the base layer is +A source region of a type is formed. Then, a plurality of trenches are formed so as to penetrate the source region and the base layer and reach the second current spreading layer, and a gate insulating film and a gate electrode are formed in each trench in that order. This forms a trench gate structure. The trenches are formed so as not to reach the first current spreading layer and the first deep layer. In this SiC semiconductor device, the first deep layer extends in a direction intersecting the longitudinal direction of the trenches.

[0005] In such a SiC semiconductor device, an electric field is generated between the gate and drain when the device is in the off state. However, in such a SiC semiconductor device, the first deep layer and the first current spreading layer are provided at a position deeper than the trench. Therefore, the depletion layer formed between the first deep layer and the first current spreading layer makes it difficult for a high electric field to penetrate into the gate insulating film when the device is in the off state. Therefore, it is possible to suppress breakdown of the gate insulating film. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2019-046908 Summary of the Invention [Problem to be solved by the invention]

[0007] The present inventors have been studying ways to simplify the manufacturing process of the SiC semiconductor device described above. Specifically, the present inventors have been studying a method for forming a semiconductor substrate by simultaneously growing an epitaxial layer on a substrate from a first deep layer to a portion constituting a source region, and then forming the first deep layer by implanting ions from one surface of the semiconductor substrate. In this case, the length from one surface of the semiconductor substrate to the first deep layer becomes long, making it difficult to thicken the first deep layer. Furthermore, if the thickness of the first deep layer becomes too thin, the electric field relaxation function of the first deep layer and the first current spreading layer decreases, which may result in destruction of the gate insulating film.

[0008] In view of the above, an object of the present invention is to provide a SiC semiconductor device that can prevent the gate insulating film from being destroyed. [Means for solving the problem]

[0009] In claim 1 for achieving the above object, a SiC semiconductor device having a trench gate structure includes a first impurity region (11) of a first conductivity type or a second conductivity type, a first deep layer (15) of a second conductivity type arranged on the first impurity region, a first current spreading layer (14) of the first conductivity type arranged on the first impurity region and having a portion sandwiched between the first deep layers, a second current spreading layer (17) of the first conductivity type arranged on the first current spreading layer, a second deep layer (18) of the second conductivity type arranged on the first deep layer, a base layer (21) of the second conductivity type arranged on the second current spreading layer and the second deep layer, and a second impurity region (22) of the first conductivity type formed in a surface layer portion of the base layer. a trench gate structure having a gate insulating film (26) formed on a wall surface of a trench (25) that penetrates the second impurity region and the base layer to reach the second current spreading layer, a gate electrode (27) formed on the gate insulating film, a first electrode (29) electrically connected to the second impurity region and the base layer, and a second electrode (30) electrically connected to the first impurity region, wherein the trench extends in one direction in the surface direction of the first impurity region, and the first deep layer has a shape having a portion where a first component part (15a) extending in a direction perpendicular to the extension direction, which is in the surface direction of the first impurity region, and a second component part (15b) extending in the extension direction are connected. Furthermore, in the first deep layer, the impurity concentration at the intersection (15c) between the first component part and the second component part is higher than the impurity concentration at the other part than the intersection part. .

[0010] According to this, the first deep layer has a first component portion extending in a direction perpendicular to the longitudinal direction of the trench and a second component portion extending along the longitudinal direction of the trench, which makes it possible to suppress breakdown of the gate insulating film compared to when the first deep layer has a configuration including only the first component portion.

[0011] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0012] [Figure 1]1 is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment. [Figure 2] 2 is a perspective cross-sectional view showing the positional relationship between a first current spreading layer, a first deep layer, a trench, and a second deep layer in FIG. 1. FIG. [Figure 3] 2 is a plan view showing the positional relationship between the first current spreading layer, the first deep layer, the trench, and the second deep layer in FIG. 1. FIG. [Figure 4] FIG. 10 is a diagram showing the relationship between the electric field applied to the gate insulating film and the on-resistance. [Figure 5] FIG. 10 is a plan view showing the positional relationship between a current spreading layer, a first deep layer, a trench, and a second deep layer in the second embodiment. [Figure 6] FIG. 11 is a plan view showing the positional relationship between a first current spreading layer, a first deep layer, a trench, and a second deep layer in a third embodiment. [Figure 7] FIG. 11 is a plan view showing the positional relationship between a first current spreading layer, a first deep layer, a trench, and a second deep layer in a modified example of the third embodiment. [Figure 8] FIG. 10 is a perspective cross-sectional view showing the positional relationship between a first current spreading layer, a first deep layer, a trench, and a second deep layer in a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0014] (First embodiment) A first embodiment will be described with reference to the drawings. In this embodiment, an SiC semiconductor device in which an inversion MOSFET with a trench gate structure is formed will be described as an example. Note that, although the configuration of the cell region in the SiC semiconductor device in which the MOSFET is formed will be described below, an actual SiC semiconductor device will have an outer periphery region in which an FLR (abbreviation for Field Limiting Ring) structure or the like is formed so as to surround the cell region. Furthermore, the SiC semiconductor device of this embodiment is suitable for use, for example, as a device mounted on a vehicle such as an automobile and used to drive various electronic devices for the vehicle.

[0015] In the following description, one direction in the surface direction of the substrate 11 (described later) is referred to as the X-axis direction, a direction intersecting the one direction in the surface direction of the substrate is referred to as the Y-axis direction, and a direction perpendicular to the X-axis direction and the Y-axis direction is referred to as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other. Furthermore, the Z-axis direction in this embodiment corresponds to the thickness (i.e., depth) direction of the semiconductor substrate 10 (described later) and also corresponds to the stacking direction of the substrate 11 and the low concentration layer 13 (described later), etc.

[0016] As shown in Fig. 1, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device is configured using an n-type SiC semiconductor device. + In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and has an n-type impurity concentration of 1.0×10 19 / cm 3 The substrate 11 has a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes the drain region, and corresponds to the first impurity region.

[0017] On the surface of the substrate 11, a n-type SiC film is formed. -An n-type buffer layer 12 is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration that is between that of the substrate 11 and a low-concentration layer 13, which will be described later, and has a thickness of about 1 μm.

[0018] On the surface of the buffer layer 12, for example, an n-type impurity concentration of 5.0 to 20.0×10 15 / cm 3 The thickness is about 10 to 15 μm, and the n - A low-concentration layer 13 of a mold is formed. The impurity concentration of this low-concentration layer 13 may be constant in the Z-axis direction, but it is preferable to provide a gradient in the concentration distribution so that the low-concentration layer 13 has a higher concentration on the substrate 11 side than on the side away from the substrate 11. For example, the low-concentration layer 13 has an impurity concentration of 2.0×10 in a portion about 3 to 5 μm from the surface of the substrate 11. 15 / cm 3 It is preferable that the internal resistance of the low concentration layer 13 is set to be higher than that of other portions. By adopting such a configuration, the internal resistance of the low concentration layer 13 can be reduced, and the on-resistance can be reduced.

[0019] A first current spreading layer 14 and a first deep layer 15 are formed on the surface of the low-concentration layer 13. In this embodiment, as shown in FIGS. 2 and 3, the first deep layer 15 has a lattice shape in which a first component portion 15a extending along the X-axis direction and a second component portion 15b extending along the Y-axis direction are connected. In other words, the first deep layer 15 has a lattice shape in which a first component portion 15a extending in a direction perpendicular to the longitudinal direction of a trench 25 (described later) and a second component portion 15b extending along the longitudinal direction of the trench 25 (described later) are connected. The first current spreading layer 14 is disposed between the first component portion 15a and the second component portion 15b. In other words, the first current spreading layer 14 is disposed interspersed among the first deep layers 15 in the Z-axis direction. Note that "in the Z-axis direction" refers to the normal direction to the surface of the substrate 11, and can also be referred to as when viewed from the Z-axis direction.

[0020] The first deep layer 15 of this embodiment is formed so that the second component portion 15b is connected to the second deep layer 18 described later. That is, the second component portion 15b of this embodiment is formed in a portion different from the portion facing the trench 25 described later, and is formed so as not to overlap with the trench 25 in the Z-axis direction.

[0021] The first current spreading layer 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a depth (i.e., thickness) of 1.55 μm. In this embodiment, the first current spreading layer 14 has an n-type impurity concentration of 5.0×10 16 ~3.0×10 17 / cm 3 The first deep layer 15 has a depth of 1.5 μm and a p-type impurity concentration of 2.0×10 17 ~2.0×10 18 / cm 3 It is said to be about that level.

[0022] The first deep layer 15 in this embodiment is formed shallower than the first current spreading layer 14. That is, the first deep layer 15 is formed so that its bottom is located within the first current spreading layer 14. In other words, the first deep layer 15 is formed so that the first current spreading layer 14 is located between the first deep layer 15 and the low-concentration layer 13. In this embodiment, the first current spreading layer 14 and the first deep layer 15 are formed by appropriately ion-implanting impurities from one surface 10a of the semiconductor substrate 10. Note that the one surface 10a of the semiconductor substrate 10 refers to the surfaces of the source region 22 and the contact region 23, which will be described later. Furthermore, the first deep layer 15 in a conventional SiC semiconductor device is formed, for example, by depositing an epitaxial layer only in the portion that constitutes the first deep layer 15, and has a depth of approximately 2.3 μm.

[0023] On the first current spreading layer 14 and the first deep layer 15, a second current spreading layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, and the like are formed.

[0024] The second current spreading layer 17 is of n-type and has a higher impurity concentration than the low-concentration layer 13, and is formed so as to be connected to the first current spreading layer 14. Therefore, in this embodiment, the low-concentration layer 13, the first current spreading layer 14, and the second current spreading layer 17 are connected, and these layers form the drift layer 19. The second current spreading layer 17 has a thickness of 0.5 to 2.0 μm and an n-type impurity concentration of 1.0×10 17 ~3.0×10 17 cm 3 It is said to be about that level.

[0025] The second deep layer 18 is of p-type and has the same thickness as the second current spreading layer 17. The second deep layer 18 is formed so as to be connected to the first deep layer 15. The second deep layer 18 of this embodiment has a p-type impurity concentration of 2.0×10 17 ~2.0×10 18 / cm 3 It is said to be about that level.

[0026] The second current spreading layer 17 and the second deep layer 18 are arranged so that they extend in the Y-axis direction as their longitudinal direction, and are arranged in multiple layers alternately in the X-axis direction. The second deep layer 18 is formed directly above the second component portion 15b so as to be connected to the second component portion 15b. The formation pitch of the second current spreading layer 17 and the second deep layer 18 matches the formation pitch of a trench gate structure described later, and the second deep layers 18 are formed so as to sandwich a trench 25 described later.

[0027] The second current spreading layer 17 and the second deep layer 18 are formed by ion-implanting impurities from the surface 10a of the semiconductor substrate 10.

[0028] The base layer 21 is of p-type and is formed on the second current spreading layer 17 and the second deep layer 18. Therefore, the first deep layer 15 is connected to the base layer 21 via the second deep layer 18. The base layer 21 has a p-type impurity concentration of, for example, 5.0×10 16 ~2.0×10 19 / cm 3 The thickness is said to be about 2.0 μm.

[0029] The source region 22 is + The contact region 23 is a p + The source region 22 is formed in a surface layer portion of the base layer 21. Specifically, the source region 22 is formed so as to contact the side surface of a trench 25, which will be described later, and the contact region 23 is formed on the opposite side of the source region 22 from the trench 25, which will be described later. In this embodiment, the source region 22 has an n-type impurity concentration (i.e., surface concentration) in the surface layer portion of the source region 22 of, for example, 1.0×10 21 / cm 3 The contact region 23 has a p-type impurity concentration in the surface layer (i.e., surface concentration) of, for example, 1.0×10 21 / cm 3 The thickness is set to about 0.3 μm. In this embodiment, the source region 22 corresponds to the second impurity region.

[0030] In this embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, buffer layer 12, low-concentration layer 13, first current spreading layer 14, first deep layer 15, second current spreading layer 17, second deep layer 18, base layer 21, source region 22, contact region 23, etc. Since the semiconductor substrate 10 is configured as described above, it can be said that the semiconductor substrate 10 is configured of SiC. Furthermore, in this embodiment, one surface 10a of the semiconductor substrate 10 is configured by the source region 22 and the contact region 23, and the other surface 10b of the semiconductor substrate 10 is configured by the substrate 11.

[0031] In the semiconductor substrate 10, a trench 25 having a width of, for example, 1.4 to 2.0 μm is formed so as to penetrate the source region 22, the base layer 21, etc., from the one surface 10a side to reach the second current spreading layer 17, and so that the bottom surface is located within the second current spreading layer 17.

[0032] The trench 25 is formed so as not to reach the first current spreading layer 14 and the first deep layer 15. In other words, the trench 25 is formed so that the first current spreading layer 14 and the first deep layer 15 are located below the bottom surface and separated from the trench 25. Although only one trench 25 is shown in FIG. 1 , in reality, a plurality of trenches 25 are provided extending along the Y-axis direction and are arranged at equal intervals in the X-axis direction to form a stripe pattern. In other words, in this embodiment, the trench 25 is formed with its longitudinal direction being the extension direction of the second component portion 15b of the first deep layer 15. The trench 25 is also formed so as to be sandwiched between the second deep layers 18.

[0033] A gate insulating film 26 is formed on the inner wall surface of the trench 25, and a gate electrode 27 made of doped poly-Si or the like is formed on the gate insulating film 26. This forms a trench gate structure. Although not particularly limited, the gate insulating film 26 is formed by thermally oxidizing the inner wall surface of the trench 25 or by performing a CVD (short for chemical vapor deposition) method. The gate insulating film 26 has a thickness of about 100 nm on both the side and bottom sides of the trench 25.

[0034] The gate insulating film 26 is also formed on surfaces other than the inner wall surfaces of the trench 25. Specifically, the gate insulating film 26 is formed so as to cover a portion of the one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 26 is formed so as to cover a portion of the surface of the source region 22. In other words, the gate insulating film 26 has contact holes 26a that expose the source region 22 and the contact region 23 in a portion different from the portion where the gate electrode 27 is disposed.

[0035] An interlayer insulating film 28 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 27, the gate insulating film 26, etc. The interlayer insulating film 28 is made of BPSG (abbreviation of borophosphosilicate glass) or the like.

[0036] A contact hole 28a is formed in the interlayer insulating film 28, communicating with the contact hole 26a and exposing the source region 22 and the contact region 23. The contact hole 28a formed in the interlayer insulating film 28 is formed to communicate with the contact hole 26a formed in the gate insulating film 26, and functions together with the contact hole 26a as a single contact hole. For this reason, hereinafter, the contact holes 26a and 28a are collectively referred to as contact holes 26b. The contact holes 26b may have any pattern, including, for example, a pattern in which multiple squares are arranged, a pattern in which rectangular lines are arranged, or a pattern in which lines are lined up. In this embodiment, the contact holes 26b are linear along the longitudinal direction of the trench 25.

[0037] An upper electrode 29 is formed on the interlayer insulating film 28. The upper electrode 29 is electrically connected to the source region 22 and the contact region 23 through the contact hole 26b. In this embodiment, the upper electrode 29 corresponds to the first electrode.

[0038] The upper electrode 29 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 22) is made of a metal that can make ohmic contact with the n-type SiC. Furthermore, the portion of the plurality of metals that contacts at least the p-type SiC (i.e., the contact region 23) is made of a metal that can make ohmic contact with the p-type SiC.

[0039] A lower electrode 30 electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 30 corresponds to the second electrode.

[0040] In the SiC semiconductor device of this embodiment, an n-channel inversion type trench gate MOSFET is configured with such a structure. - type, n type, n + The first conductivity type corresponds to p-type, p + The type corresponds to the second conductivity type.

[0041] The above is the configuration of the SiC semiconductor device according to this embodiment. Next, the operation and effects of the SiC semiconductor device will be described.

[0042] First, in the SiC semiconductor device, in the off state before a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, no inversion layer is formed in the base layer 21. Therefore, even if a positive voltage, for example, 1600 V, is applied to the lower electrode 30, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device enters an off state in which no current flows between the upper electrode 29 and the lower electrode 30.

[0043] Furthermore, when the SiC semiconductor device is in an off state, an electric field is applied between the gate and drain, which can cause electric field concentration at the bottom of the gate insulating film 26. However, in the above-described SiC semiconductor device, the first deep layer 15 and the first current spreading layer 14 are provided at a position deeper than the trench 25. Therefore, the depletion layer formed between the first deep layer 15 and the first current spreading layer 14 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film 26. Therefore, in this embodiment, it is possible to suppress breakdown of the gate insulating film 26.

[0044] In this case, the first deep layer 15 of this embodiment is configured to have a first component portion 15a extending in the X-axis direction and a second component portion 15b extending in the Y-axis direction. Therefore, for example, compared to when the first deep layer 15 is configured to have only the first component portion 15a, the depletion layer generated is larger, and breakdown of the gate insulating film 26 can be suppressed. In other words, even if the thickness of the first deep layer 15 is reduced, breakdown of the gate insulating film 26 can be suppressed. For example, if a SiC semiconductor device in which the first deep layer 15 is configured only with the first component portion 15a is used as a comparative example, as shown in FIG. 4, it is confirmed that the electric field applied to the gate insulating film 26 can be reduced in the SiC semiconductor device of this embodiment compared to the semiconductor device of the comparative example. Note that FIG. 4 shows the results of a simulation in which the thickness of the first deep layer 15 in the SiC semiconductor device of this embodiment is 1.6 μm and the thickness of the first deep layer 15 in the comparative example is 2.3 μm, with the other configurations remaining the same.

[0045] When a gate voltage equal to or higher than the threshold voltage, for example, 20 V, is applied to gate electrode 27, an inversion layer is formed on the surface of base layer 21 that contacts trench 25. As a result, a current flows between upper electrode 29 and lower electrode 30, and the SiC semiconductor device is turned on. In this embodiment, electrons that have passed through the inversion layer pass through second current spreading layer 17, first current spreading layer 14, and low-concentration layer 13 and flow to substrate 11, so that drift layer 19 having second current spreading layer 17, first current spreading layer 14, and low-concentration layer 13 can be said to be configured.

[0046] According to the present embodiment described above, the first deep layer 15 has a first component portion 15a extending in a direction perpendicular to the longitudinal direction of the trench 25 and a second component portion 15b extending in the longitudinal direction of the trench 25. Therefore, compared to when the first deep layer 15 has only the first component portion 15a, it is possible to suppress breakdown of the gate insulating film 26.

[0047] Here, for example, it is also conceivable to provide the first component 15a extending in a direction inclined with respect to the longitudinal direction of the trench 25 (for example, at 45° with respect to the longitudinal direction of the trench 25) and the second component 15b extending in a direction perpendicular to the inclined direction. However, in this configuration, the area surrounded by the trench 25, the first component 15a, and the second component 15b in the Z-axis direction has a substantially triangular shape in plan view. Therefore, in this configuration, the size of the area through which current can flow is likely to vary from part to part, making current concentration more likely to occur. Furthermore, in this configuration, the electric field relaxation function is likely to vary from part to part. Therefore, by providing the first component 15a extending in a direction perpendicular to the longitudinal direction of the trench 25 and providing the second component 15b extending in the longitudinal direction of the trench 25, as in this embodiment, it is possible to suppress variations in current concentration and electric field relaxation function while also suppressing destruction of the gate insulating film 26.

[0048] (1) In this embodiment, the second component portion 15b is formed directly below the second deep layer 18. That is, the second component portion 15b is formed at a position away from the trench 25. Therefore, compared to the case where the second component portion 15b is formed directly below the trench 25, when the SiC semiconductor device is turned on, the flow of electrons flowing from the inversion layer formed in the base layer 21 can be prevented from being blocked by the second component portion 15b, and an increase in on-resistance can be prevented.

[0049] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the location of the first component portion 15a is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0050] 5, in the SiC semiconductor device of this embodiment, the second component 15b is formed directly below the trench 25. In other words, the second component 15b is formed so as to face the bottom of the trench 25. The second deep layer 18 is connected to the first component 15a of the first deep layer 15.

[0051] As in the present embodiment described above, even if the second component 15b is formed to face the bottom of the trench 25, the first deep layer 15 has the first component 15a and the second component 15b, and therefore, the same effect as in the first embodiment can be obtained.

[0052] (Third embodiment) A third embodiment will be described. In this embodiment, the second component 15b is separated from the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0053] In the SiC semiconductor device of this embodiment, the second component 15b is divided as shown in Fig. 6. The second component 15b of this embodiment is disposed between two adjacent first component parts 15a so as to protrude from one first component part 15a toward the other first component part 15a, and is formed so as to be separated from the other first component part 15a.

[0054] In addition, the second constituent portions 15b of this embodiment are formed between two adjacent first constituent portions 15a so that portions separated from the first constituent portions 15a alternate along the X-axis direction. In other words, the first constituent portions 15a and the second constituent portions 15b are formed in a comb-like shape, and the second constituent portions 15b provided on two adjacent first constituent portions 15a are arranged so as to intermesh with each other.

[0055] According to the present embodiment described above, the first deep layer 15 has the first component portion 15a and the second component portion 15b, and therefore, the same effects as those of the first embodiment can be obtained.

[0056] (1) In this embodiment, the second component portion 15b is divided. Therefore, compared to the first embodiment, the area that becomes the first current spreading layer 14 is increased, and the on-resistance can be reduced.

[0057] (2) In this embodiment, the second component 15b is formed between two adjacent first component parts 15a so that portions separated from the first component parts 15a alternate along the X-axis direction. Therefore, compared to a case where the second component part 15b is provided only on one of the two adjacent first component parts 15a, current concentration can be suppressed when the SiC semiconductor device is in the on state.

[0058] (Modification of the third embodiment) A modified example of the third embodiment will be described. In the third embodiment, an example in which the second component 15b of the SiC semiconductor device in the first embodiment is divided has been described. However, in the third embodiment, as shown in FIG. 7, the second component 15b of the SiC semiconductor device in the second embodiment may be divided. Also, in the third embodiment, the portions of the second component 15b separated from the first component 15a may be on the same side along the X-axis direction. Furthermore, in the third embodiment, the portions of the second component 15b separated from the first component 15a may be intermittently present along the X-axis direction.

[0059] (Fourth embodiment) A fourth embodiment will be described. In this embodiment, the impurity concentration of the first deep layer 15 is specified, in contrast to the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0060] The SiC semiconductor device of this embodiment has a basic configuration similar to that of the first embodiment. However, in this embodiment, as shown in Fig. 8, if the portion where the first component portion 15a and the second component portion 15b of the first deep layer 15 intersect is defined as an intersection portion 15c, the impurity concentration of the intersection portion 15c is made higher than the impurity concentration of portions other than the intersection portion 15c.

[0061] Such a relationship in impurity concentration is formed by performing ion implantation into the portion constituting the first component 15a and then into the portion constituting the second component 15b, thereby performing two ion implantations at the intersection 14c.

[0062] According to the present embodiment described above, the first deep layer 15 has the first component portion 15a and the second component portion 15b, and therefore, the same effects as those of the first embodiment can be obtained.

[0063] (1) In this embodiment, the impurity concentration of the intersection 15c of the first deep layer 15 is higher than the impurity concentration of the portions other than the intersection 15c. This makes it easier to limit the portion where breakdown BD occurs to the intersection 15c, facilitating design. Furthermore, in this embodiment, the intersection 15c is also connected to the second deep layer 18. Therefore, when breakdown occurs at the intersection 15c, the holes h are more likely to escape to the second deep layer 18, and the movement of the holes h toward the trench 25 can be suppressed. This reduces the stress that may be applied to the gate insulating film 26.

[0064] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0065] For example, in the above-described embodiments, an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the SiC semiconductor device may be configured by forming a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted from that of the n-channel type. Furthermore, the SiC semiconductor device may be configured by forming an IGBT with a similar structure in addition to the MOSFET. In the case of an IGBT (abbreviation for Insulated Gate Bipolar Transistor), the n-channel type MOSFET in the above-described embodiments may be formed by forming a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted from that of the n-channel type. + The substrate 11 is + Except for the change to the substrate 11 of the same type, the MOSFET is the same as that described in the first embodiment.

[0066] The above embodiments may be combined, for example, by combining the fourth embodiment with the second and third embodiments, the impurity concentration at the intersection 15c may be increased. (Features of the present invention) [Claim 1] A silicon carbide semiconductor device having a trench gate structure, a first impurity region (11) of a first conductivity type or a second conductivity type; a first deep layer (15) of a second conductivity type disposed on the first impurity region; a first current spreading layer (14) of a first conductivity type disposed on the first impurity region and having a portion sandwiched between the first deep layers; a second current spreading layer (17) of the first conductivity type disposed on the first current spreading layer; a second deep layer (18) of a second conductivity type disposed on the first deep layer; a base layer (21) of a second conductivity type disposed on the second current spreading layer and the second deep layer; a second impurity region (22) of the first conductivity type formed in a surface layer portion of the base layer; the trench gate structure including a gate insulating film (26) formed on a wall surface of a trench (25) that penetrates the second impurity region and the base layer to reach the second current spreading layer, and a gate electrode (27) formed on the gate insulating film; a first electrode (29) electrically connected to the second impurity region and the base layer; a second electrode (30) electrically connected to the first impurity region, the trench extends in one direction in a surface direction of the first impurity region, The first deep layer is a silicon carbide semiconductor device in which a first component portion (15a) extending in a direction perpendicular to the extension direction in the surface direction of the first impurity region and a second component portion (15b) extending in the extension direction are connected to form a lattice shape. [Claim 2] the second component portion is formed in a state facing the second deep layer, 2. The silicon carbide semiconductor device according to claim 1, wherein the second deep layer is connected to the second component portion. [Claim 3] 3. The silicon carbide semiconductor device according to claim 1, wherein the second component protrudes from one of the first components toward the other of the first components between adjacent first components and is spaced apart from the other of the first components. [Claim 4] 4. The silicon carbide semiconductor device according to claim 3, wherein a plurality of the second components are formed along the extension direction of the first component, and between adjacent first components, portions separated from the first component are formed alternately along the extension direction of the first component. [Claim 5] 4. The silicon carbide semiconductor device according to claim 1, wherein the first deep layer has an impurity concentration at an intersection (15c) between the first component and the second component that is higher than the impurity concentration at a portion other than the intersection. [Explanation of symbols]

[0067] 11 Substrate (first impurity region) 14 1st current distribution layer 15 First Deep Layer 17 Second current distribution layer 18 Second Deep Layer 22 Source region (second impurity region) 25 Trench 26 Gate insulating film 27 Gate electrode 29 Upper electrode (1st electrode) 30 Lower electrode (second electrode)

Claims

1. A silicon carbide semiconductor device having a trench gate structure, a first impurity region (11) of a first conductivity type or a second conductivity type; a first deep layer (15) of a second conductivity type disposed on the first impurity region; a first current spreading layer (14) of the first conductivity type disposed on the first impurity region and having a portion sandwiched between the first deep layers; a second current spreading layer (17) of the first conductivity type disposed on the first current spreading layer; a second deep layer (18) of a second conductivity type disposed on the first deep layer; a base layer (21) of a second conductivity type disposed on the second current spreading layer and the second deep layer; a second impurity region (22) of the first conductivity type formed in a surface layer portion of the base layer; the trench gate structure having a gate insulating film (26) formed on a wall surface of a trench (25) that penetrates the second impurity region and the base layer to reach the second current spreading layer, and a gate electrode (27) formed on the gate insulating film; a first electrode (29) electrically connected to the second impurity region and the base layer; a second electrode (30) electrically connected to the first impurity region; the trench extends in one direction in a surface direction of the first impurity region, the first deep layer has a shape in which a first component part (15a) extending in a direction perpendicular to the extension direction in the surface direction of the first impurity region and a second component part (15b) extending in the extension direction are connected to each other; Furthermore, in the first deep layer, the impurity concentration at an intersection (15c) between the first component portion and the second component portion is higher than the impurity concentration at a portion other than the intersection portion.

2. the second component portion is formed in a state facing the second deep layer, The silicon carbide semiconductor device according to claim 1 , wherein the second deep layer is connected to the second component portion.

3. 3. The silicon carbide semiconductor device according to claim 1, wherein the second component protrudes from one of the first components toward the other of the first components between adjacent first components and is spaced apart from the other of the first components.

4. 4. The silicon carbide semiconductor device according to claim 3, wherein the second component portions are formed in plurality along the extension direction of the first component portions, and between adjacent first component portions, portions separated from the first component portions are formed alternately along the extension direction of the first component portions.

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