Silicon carbide semiconductor device

Abstract

A unit cell (16) is a section between the centers of adjacent source trenches (11), includes two or more gate trenches (7) and one source trench (11), and has four or more channels formed therein. The two or more gate trenches (7) and the one source trench (11) are arranged repeating in an alternating manner in a direction parallel to the obverse surface of a semiconductor substrate (30). The total number of gate trenches (7) is greater than the total number of source trenches (11). The total area of the gate trenches (7) is greater than the total area of the source trenches (11). The width (w1) of the gate trenches (7) is equal to or less than the width (w2) of the source trenches (11). The depth (d2) of the source trenches (11) is equal to or greater than the depth (d1) of the gate trenches (7). A p-type base depth portion (4) of the bottom surfaces of the source trenches (11) relaxes an electric field in the vicinity of the bottom surfaces of the gate trenches (7). As a result, it is possible to reduce on-resistance.

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, a well-known trench-gate SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide film-semiconductor) using silicon carbide (SiC) as the semiconductor material has a double trench structure provided with a gate trench in which a gate electrode is embedded and a source trench in which a source electrode is embedded and a source contact (electrical contact portion) with the source electrode is formed along the inner wall.

[0003] The structure of a conventional silicon carbide semiconductor device will be described. Fig. 9 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in Fig. 9 is a trench gate type SiC-MOSFET with a double trench structure having a source trench 111 on the front surface (main surface on the epitaxial layer 132 side) of a semiconductor substrate 130 made of silicon carbide. The semiconductor substrate 130 is an n-type silicon carbide semiconductor device. + On the starting substrate 131 - n type drift region 102 - The mold epitaxial layer 132 is epitaxially grown.

[0004] n + The starting substrate 131 is n + The epitaxial layer 132 includes a diffusion region (p-type base region 103, n-type drain region 101) formed by ion implantation into the epitaxial layer 132. + type source region 105 and p ++ The part excluding the contact region 106) is n - The n-type drift region 102 is a p-type base region 103 on the front surface side of the semiconductor substrate 130. + type source region 105, p ++The mold contact region 106, the gate trench 107, the gate insulating film 108 and the gate electrode 109 form a trench gate structure.

[0005] Gate trenches 107 and source trenches 111 are alternately arranged one by one in a first direction X parallel to the front surface of the semiconductor substrate 130. A unit cell (functional unit of an element) 116 has one gate trench 107 and half of a source trench 111 on each side of the gate trench 107. The gate trench 107 is formed in a depth direction Z from the front surface of the semiconductor substrate 130 to n + through the p-type source region 105 and the p-type base region 103; - The gate electrode 109 terminates inside the type drift region 102. Inside the gate trench 107, a gate electrode 109 is provided with a gate insulating film 108 interposed therebetween.

[0006] The source trench 111 is formed in a depth direction Z from the front surface of the semiconductor substrate 130 to the n-type + The source trench 111 penetrates the n-type source region 105. The depth of the source trench 111 is equal to or greater than the depth of the gate trench 107. The portion between the centers of the adjacent source trenches 111 in the first direction X forms one unit cell 116. A source electrode 113 is buried inside the source trench 111. - A p-type base region 103 extends along the inner wall of the source trench 111 between the p-type drift region 102 and the source trench 111 .

[0007] The p-type base region 103 has a portion (hereinafter referred to as a deep p-type base portion) 104 along the bottom surface of the source trench 111, which is located at a depth of n-type from the bottom surface of the gate trench 107. + n type drain region 101 - A pn junction is formed between the source trench 111 and the source drift region 102. In the double trench structure, the p-type deep base portion 104 at the bottom of the source trench 111 can reduce the electric field applied to the gate insulating film 108 at the bottom of the gate trench 107. For this reason, no p-type region is disposed at a position facing the bottom of the gate trench 107.

[0008] By not arranging a p-type region at a position facing the bottom surface of the gate trench 107, the width of the JFET (Junction FET) portion is increased, and the JFET resistance is significantly reduced, thereby reducing the on-resistance. - This is a portion of the n-type drift region 102 that is adjacent to a channel (n-type inversion layer) formed along the gate trench 107 in the p-type base region 103 when the SiC-MOSFET is on, and serves as a current path for the main current (drift current) that flows through the channel.

[0009] The source trench 111 is exposed through a contact hole 112a in the interlayer insulating film 112. The source electrode 113 is buried in the source trench 111 through the contact hole 112a in the interlayer insulating film 112, and is connected to the p-type base region 103 and the n-type base region 104 on the inner wall of the source trench 111. + type source region 105 and p ++ The drain electrode 114 is in contact with the back surface (n + The mold starting substrate 131 is provided on the entire surface of the substrate 131. + The gate electrode 102 is electrically connected to the drain region 101 .

[0010] Conventional trench gate SiC-MOSFETs have a single trench structure with only a gate trench, and a p + A device has been proposed in which the mold regions are all disposed at positions facing the bottom surfaces of the gate trenches, and are thinned out between adjacent gate trenches (mesa portions) (see, for example, Patent Documents 1 and 2 below). + By providing a mesa portion where no mold region is arranged, the area occupied by the trench gate structure relative to the area of ​​the active region is increased, thereby reducing the on-resistance. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Patent No. 6919159 [Patent Document 2] Patent No. 5751213 Summary of the Invention [Problem to be solved by the invention]

[0012] However, in conventional silicon carbide semiconductor device 110 (see FIG. 9 ), although it is possible to reduce on-resistance by using a double trench structure in which a p-type region for alleviating the electric field near the bottom of gate trench 107 is not disposed in a position facing the bottom of gate trench 107, it is necessary to dispose one gate trench 107 per unit cell 116, with half of source trench 111 disposed on each side of gate trench 107. This makes it difficult to shrink the cell pitch (the spacing between unit cells 116), and further reduce the on-resistance.

[0013] In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a trench gate type silicon carbide semiconductor device having a source trench, which is capable of reducing on-resistance. [Means for solving the problem]

[0014] In order to solve the above-mentioned problems and achieve the objects of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: A first semiconductor region of a first conductivity type is provided within a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A first trench penetrates the third semiconductor region and the second semiconductor region in the depth direction to reach the first semiconductor region. A gate electrode is provided within the first trench via a gate insulating film.

[0015] The second trench is provided at a distance from the first trench, penetrates the third semiconductor region in the depth direction to a depth equal to or greater than the depth of the first trench, and is surrounded by the second semiconductor region. A first electrode is provided on the first main surface of the semiconductor substrate, embedded in the second trench, and contacts the second semiconductor region and the third semiconductor region on the inner wall of the second trench. A second electrode is provided on the second main surface of the semiconductor substrate. The second trenches are arranged at a predetermined pitch in a first direction parallel to the first main surface of the semiconductor substrate. A plurality of the first trenches are arranged at a predetermined pitch in the first direction between adjacent second trenches. The second semiconductor region is provided between the second trench and the first semiconductor region, extending from the third semiconductor region on one side of the second trench to the third semiconductor region on the other side, and surrounding the second trench.

[0016] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the second trenches adjacent to each other with a plurality of the first trenches therebetween and the second trenches adjacent to each other without the first trenches therebetween are alternately and repeatedly arranged in the first direction.

[0017] Furthermore, to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: A first semiconductor region of a first conductivity type is provided within a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A first trench penetrates the third semiconductor region and the second semiconductor region in the depth direction to reach the first semiconductor region.

[0018] A gate electrode is provided inside the first trench with a gate insulating film interposed therebetween. A second trench is provided away from the first trench, penetrates the third semiconductor region in the depth direction to a depth equal to or greater than the depth of the first trench, and is surrounded by the second semiconductor region. A first electrode is provided on the first main surface of the semiconductor substrate, embedded in the second trench, and contacts the second semiconductor region and the third semiconductor region on the inner wall of the second trench. A second electrode is provided on the second main surface of the semiconductor substrate. The total number of the first trenches is greater than the total number of the second trenches. The second semiconductor region is provided between the second trench and the first semiconductor region, extending from the third semiconductor region on one side of the second trench to the third semiconductor region on the other side, and surrounding the second trench.

[0019] Moreover, in the silicon carbide semiconductor device according to the present invention, a total area of ​​the first trenches is larger than a total area of ​​the second trenches.

[0020] Moreover, in the silicon carbide semiconductor device according to the present invention, a width of the first trench is narrower than a width of the second trench.

[0021] Furthermore, the silicon carbide semiconductor device according to the present invention is the above-described invention, and further includes a gate pad provided on the first main surface of the semiconductor substrate, electrically insulated from the first electrode by an interlayer insulating film, and electrically connected to the gate electrode. The first trench and the second trench are arranged with the same layout in both a first region facing the first electrode in the depth direction and a second region facing the gate pad in the depth direction. An insulating layer is embedded in the second trench in the second region.

[0022] Furthermore, the silicon carbide semiconductor device according to the present invention is the above-described one, further comprising: an active region in which the first electrode is arranged; a termination region surrounding the periphery of the active region; an intermediate region between the active region and the termination region; and a gate runner provided on a first main surface of the semiconductor substrate in the intermediate region via an oxide film, surrounding the periphery of the active region and connected to the gate electrode. The first trenches and the second trenches are arranged in the same layout in both the active region and the intermediate region. An insulating layer is embedded in the second trench in the intermediate region.

[0023] According to the above-described invention, the number of gate trenches (first trenches) per unit cell can be increased without increasing the number of source trenches (second trenches) that become ineffective regions, which increases the number of channels per unit cell and increases the current density of the drift current. [Effects of the Invention]

[0024] Advantageous Effects of Invention The silicon carbide semiconductor device according to the present invention is a trench gate type silicon carbide semiconductor device having a source trench, and has an effect of being able to reduce on-resistance. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to a first embodiment as viewed from the front surface side of a semiconductor substrate. [Figure 2] FIG. 2 is a cross-sectional view showing the cross-sectional structure taken along the line AA' in FIG. [Figure 3] FIG. 3 is a cross-sectional view showing the cross-sectional structure taken along the line BB' in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing the cross-sectional structure taken along the line CC' in FIG. [Figure 5] FIG. 5 is a cross-sectional view showing the cross-sectional structure taken along the line DD' in FIG. [Figure 6]FIG. 6 is a cross-sectional view showing the cross-sectional structure taken along the line EE' in FIG. [Figure 7] FIG. 7 is an enlarged plan view of the rectangular frame F in FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0026] Preferred embodiments of a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0027] (Embodiment 1) The structure of a silicon carbide semiconductor device according to a first embodiment will be described. FIG. 1 is a plan view showing a layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. FIGS. 2 to 6 are cross-sectional views showing cross-sectional structures along the cutting lines A-A', B-B', C-C', D-D', and E-E' in FIG. 1, respectively. FIG. 7 is an enlarged plan view of a rectangular frame F in FIG. 1. FIG. 2 shows two adjacent unit cells 16 (functional unit of an element) in an active region 51. One unit cell 16 is formed in the portion between the centers of adjacent source trenches 11 in the first direction X. FIGS. 3 to 5 show the structure of an intermediate region 52. FIG. 6 shows a cross-sectional view of a silicon carbide semiconductor device directly below a gate pad 15 (n + The structure of the gate electrode (type drain region 1) is shown.

[0028] FIG. 7 shows the layout of the gate trench 7 and source trench 11 near the boundary between the source electrode 13 and the gate pad 15. While FIG. 7 shows the vicinity of one corner (vertex of a rectangle) of the gate pad 15, the layout of the gate trench 7 and source trench 11 along the outer periphery of the gate pad 15 corresponds to the layout of the gate trench 7 and source trench 11 of the source electrode 13. In FIG. 7, the gate electrode 9 is illustrated as "trench gate," and the source electrode 13 buried in the source trench 11 is illustrated as "source electrode." In FIGS. 3, 4, 6, and 7, the buried insulating layers 22 and 42 buried in the insulating trenches 21 and 41 are illustrated as "SiO2."

[0029] 1 to 7, a silicon carbide semiconductor device 10 according to the embodiment is a trench-gate SiC-MOSFET with a multi-trench structure in which two or more gate trenches (first trenches) 7 are provided for one source trench (second trench) 11 on the front surface side of a semiconductor substrate (semiconductor chip) 30 made of silicon carbide in an active region 51. The active region 51 is a region through which a main current (drift current) flows in a direction perpendicular to the front surface of the semiconductor substrate 30 when the silicon carbide semiconductor device 10 is turned on. A plurality of unit cells 16 of the SiC-MOSFET having the same structure are arranged adjacent to each other in the active region 51. The active region 51 has, for example, a substantially rectangular planar shape and is provided approximately in the center of the semiconductor substrate 30 (chip center).

[0030] In the active region 51, a source electrode 13 (first electrode: not shown in FIG. 1, see FIGS. 2 and 3) and a gate pad 15 are provided on the front surface of the semiconductor substrate 30. The source electrode 13 covers almost the entire front surface of the semiconductor substrate 30 in the active region 51. The source electrode 13 has, for example, a substantially rectangular planar shape with a portion recessed inward (toward the center of the chip). The source electrode 13 also serves as a source pad (electrode pad). The gate pad 15 has, for example, a substantially rectangular planar shape (not shown). The gate pad 15 is provided, for example, in a partially recessed recess of the source electrode 13 near the boundary between the active region 51 and the intermediate region 52, and three sides of the gate pad 15 face the source electrode 13.

[0031] Edge termination region 53 is a region between active region 51 and the edge (chip edge) of semiconductor substrate 30, and surrounds the periphery of active region 51 in a substantially rectangular shape via intermediate region 52. In FIG. 1, the boundary between active region 51 and intermediate region 52 and the boundary between intermediate region 52 and edge termination region 53 are indicated by dashed lines. Gate runner 48 is provided in intermediate region 52 between active region 51 and edge termination region 53. Intermediate region 52 is a transition region in which a structure is disposed for electrically connecting the trench gate structure of active region 51 and the breakdown voltage structure of edge termination region 53. Gate runner 48 surrounds the periphery of active region 51 in a substantially rectangular shape. Gate runner 48 is connected to gate pad 15.

[0032] The edge termination region 53 has the function of alleviating the electric field on the front surface side of the semiconductor substrate 30 to maintain a breakdown voltage. The breakdown voltage is the maximum voltage at which the silicon carbide semiconductor device 10 (SiC-MOSFET) does not malfunction or break down at the operating voltage. In the edge termination region 53, for example, a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring is disposed, which is a general breakdown voltage structure (not shown) composed of multiple p-type regions concentrically surrounding the active region 51. For example, FIG. 3 shows the innermost p-type region of the multiple p-type regions constituting the JTE structure, in which p-type regions with lower impurity concentrations are disposed from the inside to the outside (chip edge side). - The mold area 49 is shown.

[0033] The semiconductor substrate 30 is made of silicon carbide. + On the front surface of the starting substrate 31, - n-type drift region (first semiconductor region) 2 - The semiconductor substrate 30 is formed by epitaxially growing an n-type epitaxial layer 32. The first main surface of the semiconductor substrate 30, which faces the epitaxial layer 32, is the front surface. + The second main surface on the mold starting substrate 31 side is referred to as the back surface. + The starting substrate 31 is n +The epitaxial layer 32 includes a p-type base region (second semiconductor region) 3 and an n-type drain region 1. + type source region (third semiconductor region) 5 and p ++ The part excluding the contact region 6 is n - The n-type drift region 2 is a p-type base region 3 on the front surface side of the semiconductor substrate 30. + Type source region 5, p ++ The mold contact region 6, the gate trench 7, the gate insulating film 8 and the gate electrode 9 form a trench gate structure.

[0034] p-type base region 3, n + Type source region 5 and p ++ The p-type contact region 6 is a diffusion region formed by ion implantation inside the epitaxial layer 32. The p-type base region 3 is connected to the front surface of the semiconductor substrate 30 over the entire area of ​​the active region 51 and the intermediate region 52. - The n-type drift region 2 is provided between the n-type drift region 2 and the n-type drift region 3. + The n-type source region 5 is provided over substantially the entire region (first region) 51a directly below the source electrode 13 between the front surface of the semiconductor substrate 30 and the p-type base region 3, in contact with the p-type base region 3. The region 51a directly below the source electrode 13 is the portion of the active region 51 excluding the region (second region) 51b directly below the gate pad 15. + The source region 5 is in ohmic contact with the source electrode 13 on the front surface of the semiconductor substrate 30 .

[0035] p ++ The p-type contact region 6 is provided between the bottom surface of the source trench 11 and a p-type base deep portion 4, which will be described later, and in contact with the p-type base deep portion 4. ++ The contact region 6 is in ohmic contact with the source electrode 13 at the bottom of the source trench 11. ++ By not providing the p-type contact region 6 between the front surface of the semiconductor substrate 30 and the p-type base region 3, it becomes easy to form a trench gate structure even if the cell pitch is narrow. ++The contact region 6 may be provided partially on the bottom surface of the source trench 11 or may be provided over the entire bottom surface of the source trench 11. ++ The p-type contact region 6 penetrates the p-type base deep portion 4 in the depth direction Z and - It may contact the drift region 2. ++ The mold contact region 6 may not be provided.

[0036] Two or more gate trenches 7 (two in FIGS. 2 to 7 ) and one source trench 11 constitute one unit cell 16. Specifically, one source trench 11 is arranged for every two or more gate trenches 7 arranged at a distance from each other in a first direction X parallel to the front surface of the semiconductor substrate 30, so that two or more gate trenches 7 and one source trench 11 are arranged alternately in the first direction X. In other words, two or more gate trenches 7 are arranged at a predetermined pitch in the first direction X between adjacent source trenches 11 arranged at a predetermined pitch in the first direction X, spaced apart from the source trench 11. The total number of gate trenches 7 is greater than the total number of source trenches 11 within the surface of the semiconductor substrate 30.

[0037] Increasing the number of gate trenches 7 per unit cell increases the number of channels (n-type inversion layers) formed along the gate trenches 7 in the p-type base region 3 per unit cell when the silicon carbide semiconductor device 10 is on. This increases the current density of the drift current flowing through the channel and reduces the on-resistance compared to a conventional structure (see FIG. 9 ) having only one gate trench 107 per unit cell 116. On the other hand, the more gate trenches 7 per unit cell there are, the smaller the effect of alleviating the electric field near the bottom of the gate trench 7 due to the deep p-type base portion 4 (described later) at the bottom of the source trench 11. For this reason, it is preferable that the number of gate trenches 7 per unit cell be approximately three at most.

[0038] In addition, the on-resistance is further reduced by increasing the number of gate trenches 7 per unit cell and making the total area (surface area) of the gate trenches 7 larger than the total area of ​​the source trenches 11. The total area of ​​the gate trenches 7 may be, for example, more than half the area of ​​the active region 51. The spacing w11 between adjacent gate trenches 7 (mesa portions) is substantially the same between all adjacent gate trenches 7. By arranging the gate trenches 7 adjacent to each other in the first direction X in the same layout pattern, the spacing w11 between adjacent gate trenches 7 can be made narrower than the spacing w12 between adjacent gate trenches 7 and source trenches 11 (mesa portions), making it easier to reduce the cell pitch.

[0039] Furthermore, in the conventional structure, only one gate trench 107 is disposed in one unit cell 116, and therefore, adding one gate trench 107 also adds one source trench 111. Therefore, one unit cell 116 is configured with each of two gate trenches 107, resulting in a total of two unit cells 116 being disposed. On the other hand, as described above, in the first embodiment, even if one gate trench 7 is added, one unit cell 16 can be configured without adding any source trenches 11, and two gate trenches 7 can be disposed with a width (width in the first direction X) that is less than twice the width of the unit cells 116 of the conventional structure. Therefore, compared to the conventional structure, the total area of ​​the gate trenches 7 relative to the area of ​​the active region can be increased.

[0040] Furthermore, by making the interval w12 between adjacent gate trenches 7 and source trenches 11 wider than the interval w11 between adjacent gate trenches 7, the margin for the formation region of the source trench 11 can be widened. For example, making the depth d2 of the source trench 11 (the depth of the front surface of the semiconductor substrate 30) deeper than the depth d1 of the gate trench 7 is useful because the source trench 11 is formed in a different etching process from the gate trench 7. The deeper the depth d2 of the source trench 11, the more easily etching progresses in a direction parallel to the front surface of the semiconductor substrate 30. For this reason, it is preferable to widen the margin for the formation region of the source trench 11.

[0041] Of the two or more gate trenches 7 arranged between adjacent source trenches 11, the distance w10 between the sidewalls of each gate trench 7 closest to the source trenches 11 on the source trench 11 side (hereinafter referred to as the distance between the outermost sidewalls of adjacent gate trenches 7) may be approximately the same as the width w2 of the source trench 11 in the first direction X. In this case, the layout pattern of insulation trenches (second trenches) 21, 41 described below can be formed in a stripe shape with distances w13, w14 that are approximately the same as the distance w12 between the gate trench 7 and the source trench 11. This allows the mask patterns for forming the source trench 11 and the insulation trenches 21, 41 to be uniform.

[0042] The width w1 of the gate trench 7 in the first direction X is preferably narrower than the width w2 of the source trench 11 in the first direction X. Specifically, the width w1 of the gate trench 7 in the first direction X is preferably less than half the width w2 of the source trench 11 in the first direction X, for example. This makes it possible to further obtain the effect (increase in the current density of the drift current) obtained by arranging two or more gate trenches 7 per unit cell. The width w1 of the gate trench 7 in the first direction X and the width w2 of the source trench 11 in the first direction X may be approximately the same. "Approximately the same width" and "approximately the same spacing" mean that the width and spacing are the same within a range that includes tolerances due to variations in the manufacturing process.

[0043] The gate trench 7 is formed in a depth direction Z from the front surface of the semiconductor substrate 30 to the n + through the p-type source region 5 and the p-type base region 3, - The n-type drift region 2 terminates at the bottom of the gate trench 7. + Between the n-type drain region 1 - Only the n-type drift region 2 is disposed, and the bottom surface of the gate trench 7 is - The JFET section is surrounded by the n-type drift region 2. Therefore, compared to when a p-type region for electric field relaxation is placed at the bottom of the gate trench 7, the width of the JFET section is wider and the JFET resistance is significantly reduced. - The gate trench 7 is a portion of the type drift region 2 that is adjacent to the channel and serves as a current path for the drift current. A gate electrode 9 made of, for example, polysilicon (poly-Si) is provided inside the gate trench 7 with a gate insulating film 8 interposed therebetween.

[0044] The gate trenches 7 and the source trenches 11 extend linearly (i.e., in a stripe pattern across the entire active region 51) in a second direction Y that is parallel to the front surface of the semiconductor substrate 30 and perpendicular to the first direction X. Two or more gate trenches 7 and one source trench 11 may be alternately arranged in the first direction X, and two or more gate trenches 7 and one source trench 11 may be alternately arranged in the second direction Y. In this case, the gate trenches 7 and the source trenches 11 have a substantially rectangular planar shape and are scattered in an island pattern (i.e., in a matrix pattern across the entire active region 51), with a plurality of unit cells 16 arranged adjacent to each other in the first direction X and a plurality of unit cells 16 arranged adjacent to each other in the second direction Y.

[0045] The source trench 11 is formed in a depth direction Z from the front surface of the semiconductor substrate 30 to the n + The n-type source region 5 is formed at a depth substantially the same as the bottom surface of the gate trench 7 or at a depth lower than the bottom surface of the gate trench 7. +The source trenches 11 and 11 reach a deep position on the gate trench 7 side. "Substantially the same depth" means that the depths are the same within a range that includes tolerances due to variations in the manufacturing process (for example, within ±10%, preferably within ±5%). When the depth d2 of the source trenches 11 is substantially the same as the depth d1 of the gate trenches 7, the width w2 of the source trenches 11 in the first direction X can be made substantially the same as the width w1 of the gate trenches 7 in the first direction X, thereby allowing the source trenches 11 and the gate trenches 7 to be formed simultaneously, thereby simplifying the manufacturing process.

[0046] On the other hand, the deeper the depth d2 of the source trench 11 is made than the depth d1 of the gate trench 7, the more the p-type base deep portion 4 (described later) at the bottom of the source trench 11 is made to have an n + The p-type base deep portion 4 at the bottom of the source trench 11 can be formed deeper toward the drain region 1. The deeper the p-type base deep portion 4 at the bottom of the source trench 11, the more effective the p-type base deep portion 4 is in alleviating the electric field near the bottom of the gate trench 7. Furthermore, the deeper the p-type base deep portion 4 at the bottom of the source trench 11, the more the p-type base deep portion 4 becomes a resistance component when a large current (short-circuit current) exceeding the rated current flows between the drain and source of the SiC-MOSFET (silicon carbide semiconductor device 10) during a load short circuit or an arm short circuit, thereby improving the short-circuit resistance.

[0047] A source electrode 13 is buried inside the source trench 11. - The p-type base region 3 extends along the inner wall of the source trench 11 between the source electrode and the p-type drift region 2. ++ A source contact (electrical contact portion) is formed with the gate contact region 6. Even if the depth d2 of the source trench 11 is deeper than the depth d1 of the gate trench 7, by appropriately widening the interval w12 between the gate trench 7 and the source trench 11 adjacent to each other, there is no adverse effect on the gate characteristics. In addition, the source electrode 13 embedded in the source trench 11 is closer to the n-type contact region 6 than the gate electrode 9 embedded in the gate trench 7. + Even if it is located on the side of the gate drain region 1, it does not adversely affect the gate characteristics.

[0048] Furthermore, a portion 4 of the p-type base region 3 along the bottom surface of the source trench 11 (hereinafter referred to as a deep p-type base portion) surrounds the entire bottom surface of the source trench 11. The deep p-type base portion 4 at the bottom surface of the source trench 11 is located at a position closer to the n-type base than the bottom surface of the gate trench 7. + n deep in the drain region 1 - A pn junction is formed between the source trench 11 and the n-type drift region 2, and the electric field applied to the gate insulating film 8 at the bottom of the gate trench 7 is alleviated. In addition, by providing the source trench 11 and ion-implanting p-type impurities to form the p-type base region 3 at the bottom of the source trench 11, the n-type base region 3 is formed at a higher potential than the bottom of the gate trench 7. + Therefore, the p-type deep base portion 4 can be formed at a deep position on the side of the p-type drain region 1 without variations in impurity concentration.

[0049] For example, if the source trench 11 is not provided between the adjacent gate trenches 7, n + To form a p-type region deep inside the drain region 1, it is necessary to implant p-type impurities into the front surface of the semiconductor substrate 30 with high acceleration energy, or to implant p-type impurities into the epitaxial layer 32 each time the epitaxial layer 32 is epitaxially grown in multiple stages. Therefore, ion implantation with high acceleration energy can cause variations in the impurity concentration in the p-type region and crystal defects. Furthermore, forming a p-type region by implanting p-type impurities into the epitaxial layer 32 each time the epitaxial layer 32 is epitaxially grown in multiple stages increases the number of steps.

[0050] In the present embodiment, after source trench 11 is formed in the front surface of semiconductor substrate 30, p-type impurity ions are implanted into the entire front surface of semiconductor substrate 30 in active region 51 and intermediate region 52 and the entire surface of the inner wall of source trench 11 to form p-type base region 3. As a result, p-type base region 3 is formed in the surface region of the front surface of semiconductor substrate 30 in active region 51 and intermediate region 52 and the entire surface region of the inner wall of source trench 11, and the portion of p-type base region 3 along the bottom surface of source trench 11 becomes p-type deep base portion 4. Therefore, there is no need for ion implantation at high acceleration energy or a process of epitaxially growing epitaxial layer 32 in multiple stages.

[0051] The thickness of the p-type base deep portion 4 (the thickness of the p-type base region 3 between the bottom surface of the source trench 11 and the n - The thickness t2 of the p-type base region 3 (the thickness of the portion between the front surface of the semiconductor substrate 30 and the n-type drift region 2) of the mesa portion is - The thickness t2 of the deep p-type base portion 4 of the p-type base region 3 can be made relatively thicker by further ion-implanting p-type impurities into the bottom surface of the source trench 11 when forming the p-type base region 3. For example, by implanting p ++ By performing ion implantation of p-type impurities to form the contact region 6, the thickness t2 of the deep p-type base portion 4 of the p-type base region 3 can be made relatively thick.

[0052] In the active region 51, a trench 21 filled with a buried insulating layer 22 (hereinafter referred to as an insulating trench) is provided in a region 51b directly below the gate pad 15. The insulating trench 21 and n -Between the active region 51 and the p-type drift region 2, the p-type base region 3 extends along the inner wall of the isolation trench 21 from the active region 51, surrounding the entire bottom surface of the isolation trench 21. The isolation trench 21 extends in a stripe shape in the second direction Y. The width w3 of the isolation trench 21 in the first direction X may be, for example, approximately the same as the width w2 of the source trench 11 in the first direction X. The spacing w13 between adjacent isolation trenches 21 may be, for example, approximately the same as the spacing w12 between adjacent gate trenches 7 and source trenches 11.

[0053] The insulating trenches 21 are arranged in a stripe shape having the above dimensions, and the distance w10 between the outermost sidewalls of the adjacent gate trenches 7 in the region 51a directly below the source electrode 13 is set to Width w3 of the insulation trench 21 in the first direction X As a result, the insulation trenches 21 are arranged in stripes facing the source trenches 11 and all the gate trenches 7 between adjacent source trenches 11 alternately and repeatedly in the second direction Y (see FIG. 7). The p-type base regions 3 between adjacent insulation trenches 21 and the p-type base regions 3 between adjacent gate trenches 7 and source trenches 11 are connected with approximately the same widths w12 and w13 and extend linearly in the second direction Y.

[0054] The p-type base region 3 directly below the gate pad 15 has the function of suppressing the rise in potential of the region 51b directly below the gate pad 15 due to a sudden rise in the voltage applied to the drain electrode 14. By arranging the insulating trench 21 in the region 51b directly below the gate pad 15, a portion 23 of the p-type base region 3 along the bottom surface of the insulating trench 21 (hereinafter referred to as the deep p-type base portion) becomes n + The p-type deep base portion 23 is formed at a deep position toward the source drain region 1. The thickness t3 of the p-type deep base portion 23 is, for example, approximately the same as the thickness t2 of the p-type deep base portion 4 at the bottom surface of the source trench 11. By making the depth d3 of the insulation trench 21 approximately the same as the depth d2 of the source trench 11, the p-type deep base portion 23 can be formed at approximately the same depth as the p-type deep base portion 4.

[0055] The deep p-type base portions 23 at the bottom surfaces of the adjacent insulating trenches 21 are connected to each other, so that the lower surface (n + The region 51b directly under the gate pad 15 has a substantially rectangular planar shape with dimensions substantially the same as or slightly larger than the gate pad 15, and faces the entire surface of the gate pad 15. ... the gate pad 15, and faces the entire surface of the gate pad 15. The region 51b directly under the gate pad 15 has a substantially rectangular planar shape with dimensions substantially larger than the gate pad 15, and faces the entire surface of the gate pad 15. ++ Similarly to the p-type contact region 6, the p-type base ++ A mold contact region 24 may be provided.

[0056] The interlayer insulating film 12 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 9. A plurality of contact holes 12a to 12c are provided penetrating the interlayer insulating film 12 in the depth direction Z. The source trench 11 is exposed through the contact hole 12a. The n-type contact hole 12b is provided between the adjacent gate trenches 7. + The p-type source region 5 is exposed through the contact hole 12c. A gate polysilicon wiring layer 46, which will be described later, in the intermediate region 52 is exposed through the contact hole 12c. The source electrode 13 is embedded in the source trench 11 through the contact hole 12a in the interlayer insulating film 12, and is connected to the p-type base region 3, n-type base region 4, and n-type base region 5 on the inner wall of the source trench 11. + Type source region 5 and p ++ It contacts the mold contact region 6.

[0057] A gate pad 15 is provided on the interlayer insulating film 12 in the active region 51. The source electrode 13 and the gate pad 15 are provided on the same layer and are metal electrode layers electrically insulated from each other by the interlayer insulating film 12. The gate pad 15 faces the insulating trench 21, the buried insulating layer 22, and the deep p-type base 23 via the interlayer insulating film 12. All the gate electrodes 9 are electrically connected to the gate pad 15 via gate runners 48. The drain electrode (second electrode) 14 is connected to the back surface (n +The drain electrode 14 is in ohmic contact with the back surface of the semiconductor substrate 30 and is provided on the entire surface of the back surface of the semiconductor substrate 30. + Type drain region 1(n + The mold is electrically connected to the starting substrate 31).

[0058] The intermediate region 52 is provided with a gate trench 7 extending from the active region 51 and an insulating trench 41 in which a buried insulating layer 42 is buried. - Between the active region 51 and the n-type drift region 2, the p-type base region 3 extends along the inner wall of the insulation trench 41 from the active region 51, surrounding the entire bottom surface of the insulation trench 41. The width w4 of the insulation trench 41 in the first direction X is, for example, substantially the same as the width w2 of the source trench 11 in the first direction X. The insulation trenches 41 are provided on a pair of opposite sides parallel to the first direction X of the intermediate region 52 that surrounds the periphery of the active region 51 in a substantially rectangular shape, facing the source trench 11 in the second direction Y, and are scattered in the first direction X with two or more gate trenches 7 sandwiched therebetween (FIG. 4).

[0059] On the other hand, the insulation trenches 41 extend linearly (or in stripes) in the second direction Y along a pair of opposite sides of the intermediate region 52 that are parallel to the second direction Y across the entire area of ​​the pair of opposite sides ( FIG. 5 ). In this case, along a pair of opposite sides of the intermediate region 52 that are parallel to the second direction Y, the entire area of ​​the insulation trenches 41 faces in the depth direction Z a pair of opposite sides of the gate runner 48 that are parallel to the second direction Y. When the gate trenches 7 and the source trenches 11 are scattered in an island-like pattern (matrix-like pattern) with substantially rectangular planar shapes, the insulation trenches 41 may be scattered in the second direction Y with two or more gate trenches 7 sandwiched between them (not shown) along a pair of opposite sides of the intermediate region 52 that are parallel to the second direction Y.

[0060] By disposing the insulating trench 41 in the intermediate region 52, a portion 43 of the p-type base region 3 along the bottom surface of the insulating trench 41 (hereinafter referred to as a deep p-type base portion) +The p-type deep base portion 43 is formed at a deep position on the side of the source trench 1. The thickness t4 of the p-type deep base portion 43 is, for example, approximately the same as the thickness t2 of the p-type deep base portion 4 at the bottom of the source trench 11. By making the depth d4 of the insulation trench 41 approximately the same as the depth d2 of the source trench 11, the p-type deep base portion 43 can be formed at approximately the same depth as the p-type deep base portion 4. ++ Similarly to the p-type contact region 6, the p-type base ++ A mold contact region 44 may be provided.

[0061] The p-type base region 3 in the intermediate region 52 surrounds the periphery of the active region 51 in a substantially rectangular shape along the boundary between the active regions 51 and 52. The p-type base region 3 in the intermediate region 52 functions to make the electric field uniform within the surface of the front surface of the semiconductor substrate 30 in the intermediate region 52. A field oxide film 45 is provided between the front surface of the semiconductor substrate 30 and the interlayer insulating film 12 in the intermediate region 52 and the edge termination region 53. The field oxide film 45 may extend between the front surface of the semiconductor substrate 30 in the active region 51 and the interlayer insulating film 12 so as to face the entire surface of the gate pad 15. The buried insulating layers 22 and 42 may be formed simultaneously with the field oxide film 45.

[0062] In the intermediate region 52, a gate polysilicon wiring layer 46 is provided between the field oxide film 45 and the interlayer insulating film 12. A gate electrode 9 is connected to the gate polysilicon wiring layer 46 at an end of the gate trench 7 in the longitudinal direction (second direction Y). A gate metal wiring layer 47 is provided on the gate polysilicon wiring layer 46 via a contact hole 12c in the interlayer insulating film 12. The gate metal wiring layer 47 is connected to the gate pad 15. The gate polysilicon wiring layer 46 and the gate metal wiring layer 47 form a gate runner 48 surrounding the active region 51. The gate runner 48 faces the p-type base region 3, the deep p-type base portion 43, the insulating trench 41, and the buried insulating layer 42 via insulating layers (the field oxide film 45 and the interlayer insulating film 12).

[0063] The operation of the silicon carbide semiconductor device 10 (SiC-MOSFET) according to the first embodiment will be described. During normal operation, a positive voltage is applied to the drain electrode 14 with respect to the source electrode 13 (a forward bias is formed between the drain and source), and p ++ a p-type contact region 6 and a p-type base region 3; and - Type drift region 2 and n + A reverse bias is applied to the pn junction between the gate electrode 9 and the gate-drain region 1. In this state, if the voltage applied to the gate electrode 9 is less than the gate threshold voltage, the SiC-MOSFET remains in the off state.

[0064] On the other hand, when a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 9 while a positive voltage relative to the source electrode 13 is applied to the drain electrode 14, a channel (n-type inversion layer) is formed in the p-type base region 3 along the sidewall of the gate trench 7. + Type drain region 1 to n - through the drift region 2 and the channel + A main current (drift current) flows toward the type source region 5, and the SiC-MOSFET turns on.

[0065] In a conventional structure (see FIG. 9 ) having only one gate trench 107 per unit cell 116, two channels are formed per unit cell. On the other hand, in the first embodiment, two or more gate trenches 7 are disposed in one unit cell 116, thereby forming four or more channels per unit cell. This increases the current density of the drift current compared to the conventional structure, thereby reducing the on-resistance.

[0066] As described above, according to the first embodiment, by arranging two or more gate trenches between adjacent source trenches, the number of gate trenches per unit cell increases, and therefore the number of channels per unit cell can be increased. Therefore, compared to the conventional structure having only one gate trench per unit cell (see FIG. 9), the current density of the drift current flowing through the channel increases, and the on-resistance is reduced.

[0067] Furthermore, by arranging two or more gate trenches between adjacent source trenches, the number of gate trenches can be increased without increasing the number of source trenches that become ineffective regions that do not function as MOSFETs. Two gate trenches can be arranged in an area less than two unit cells of a conventional structure, and the total area of ​​the gate trenches relative to the area of ​​the active region can be increased compared to the conventional structure, thereby reducing the on-resistance.

[0068] (Embodiment 2) The structure of a silicon carbide semiconductor device according to the second embodiment will be described. Fig. 8 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the second embodiment. The layout of a silicon carbide semiconductor device 60 according to the second embodiment, as viewed from the front surface side of a semiconductor substrate 30, is the same as that of the first embodiment (see Fig. 1). The silicon carbide semiconductor device 60 according to the second embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment (see Figs. 1 to 7) in that the silicon carbide semiconductor device 60 has alternately arranged, in a first direction X, gaps between adjacent source trenches 11 sandwiching a gate trench 7 therebetween and gaps between adjacent source trenches 11 without sandwiching a gate trench 7 therebetween.

[0069] Specifically, in the second embodiment, two or more (two in FIG. 8 ) gate trenches 7 and two source trenches 11 are alternately and repeatedly arranged in the first direction X, thereby forming a plurality of unit cells 61 spaced apart from one another in the first direction X. As in the first embodiment, one unit cell 61 is formed between the centers in the first direction X of the source trenches 11 that are adjacent to one another with two or more gate trenches 7 therebetween. The space between the adjacent unit cells 61 is between the centers in the first direction X of the source trenches 11 that are adjacent to one another with only the p-type base region 3 sandwiched therebetween, and forms an ineffective region 62 that does not function as a MOSFET.

[0070] In the ineffective region 62, only the p-type base region 3 is disposed between the adjacent source trenches 11 (mesa portion), and the gate trench 7 and the n + In this case, the p-type source region 5 is not arranged. Since the source electrode 13 and the p-type base region 3 are in contact with each other over substantially the entire surface of the inner wall of the source trench 11, the contact area between the source electrode 13 and the p-type base region 3 increases compared to when one source trench 11 having the same width as the total width (=2×w2) of the two source trenches 11 in the first direction X is provided instead of two source trenches 11 arranged adjacent to each other in the same invalid region 62. Therefore, the avalanche resistance can be improved.

[0071] In addition, the contact area between the source electrode 13 and the p-type base region 3 increases, and the p ++ The p-type contact region 6 and the p-type base region 3 and the n - Type drift region 2 and n + The area of ​​the parasitic diode (body diode) formed by the pn junction with the source trench 11 increases. This allows the forward voltage Vf of the body diode to be lowered. Furthermore, by providing the invalid region 62, the width of the contact hole 12a exposing the source trench 11 increases, making it easier to embed the source electrode 13 in the source trench 11 and reducing the likelihood of a cavity being formed inside the source electrode 13. This prevents the plating film formed on the source electrode 13 for wire bonding from penetrating into the semiconductor substrate 30.

[0072] Furthermore, the improved embedding of the source electrode 13 in the source trench 11 improves the flatness of the source electrode 13 in the contact hole 12a. In addition, the wider contact hole 12a reduces the slope of the edge of the step (the portion connecting the portion of the source electrode 13 on the interlayer insulating film 12 with the portion inside the contact hole 12a) formed on the surface of the source electrode 13 due to the difference in elevation between the interlayer insulating film 12 and the front surface of the semiconductor substrate 30. This improves the flatness of the source electrode 13 over the entire surface, making it easier to bond a bonding wire to the surface of the source electrode 13. Furthermore, it is possible to suppress local stress on the source electrode 13 during wire bonding.

[0073] The interval w21 between adjacent source trenches 11 arranged in the same invalid region 62 is approximately the same as the interval w12 between adjacent gate trenches 7 and source trenches 11, for example. By forming the invalid region 62 by two adjacent source trenches 11, it is possible to align the patterns of the mesa portions (semiconductor portions sandwiched between adjacent trenches) within the plane of the active region 51, compared to when one source trench 11 having the same width as the total width of these two source trenches 11 in the first direction X is provided, making it easier to form the gate trenches 7 and the source trenches 11.

[0074] Three or more source trenches 11 may be adjacent to each other in the first direction X in the same invalid region 62, but the more source trenches 11 there are, the narrower the operating region of the MOSFET becomes. As the number of gate trenches 7 per unit cell increases, the effect of the deep p-type base portion 4 at the bottom of the source trench 11 on alleviating the electric field near the bottom of the gate trench 7 decreases. Therefore, the number of gate trenches 7 arranged in one unit cell 61 is at most two more than the number of source trenches 11 arranged in the same invalid region 62, and preferably one more.

[0075] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, according to the second embodiment, the unit cells are arranged apart from each other, which improves the embedding of the source electrode into the source trench and improves the flatness of the source electrode.

[0076] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0077] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0078] 1n + Type drain region 2n - Type Drift Region 3 p-type base region 4,23,43 deep p-type base 5n + Type Source Area 6,24,44 p ++ Mold contact area 7 Gate Trench 8 Gate insulating film 9 Gate electrode 10,60 Silicon carbide semiconductor device 11 Source Trench 12 Interlayer insulating film 12a to 12c: contact holes in interlayer insulating film 13 Source electrode 14 Drain electrode 15 Gate Pad 16,61 unit cell 21,41 Isolation trench 22,42 Buried insulating layer 30 Semiconductor substrate 31n + Starting substrate 32 Epitaxial layer 45 Field Oxide 46 Gate polysilicon wiring layer 47 Gate metal wiring layer 48 Gate Runner 49 pages - type area 51,51a, 51b active region 52 Intermediate area 53 Edge Termination Area 62 Invalid area X: the first direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction d1 Gate trench depth d2 Source trench depth d3,d4 Depth of insulation trench t1 Thickness of the p-type base region of the mesa t2~t4 Thickness of the deep p-type base w1 Width of the gate trench in the first direction w2 Width of source trench in the first direction w3, w4 Width of the insulation trench in the first direction w11: Distance between adjacent gate trenches w12: Distance between adjacent gate and source trenches w13, w14: Distance between adjacent insulation trenches

Claims

1. a semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided inside the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a first trench that penetrates the third semiconductor region and the second semiconductor region in a depth direction and reaches the first semiconductor region; a gate electrode provided inside the first trench via a gate insulating film; a second trench provided apart from the first trench, penetrating the third semiconductor region in a depth direction to a depth equal to or greater than the depth of the first trench, and surrounded by the second semiconductor region; a first electrode provided on the first main surface of the semiconductor substrate, embedded in the second trench, and in contact with the second semiconductor region and the third semiconductor region on an inner wall of the second trench; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with the second trenches are arranged at a predetermined pitch in a first direction parallel to the first main surface of the semiconductor substrate; a plurality of the first trenches are arranged at a predetermined pitch in the first direction between the second trenches adjacent to each other, the second semiconductor region is provided between the second trench and the first semiconductor region, extending from the third semiconductor region on one side of the second trench to the third semiconductor region on the other side, and surrounding the second trench.

2. 2. The silicon carbide semiconductor device according to claim 1, wherein the second trenches are spaced apart from each other by a plurality of the first trenches and the second trenches are spaced apart from each other by a plurality of the first trenches, and the second trenches are spaced apart from each other by a plurality of the first trenches and the second trenches are spaced apart from each other by a plurality of the first trenches.

3. a semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided inside the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a first trench that penetrates the third semiconductor region and the second semiconductor region in a depth direction and reaches the first semiconductor region; a gate electrode provided inside the first trench via a gate insulating film; a second trench provided apart from the first trench, penetrating the third semiconductor region in a depth direction to a depth equal to or greater than the depth of the first trench, and surrounded by the second semiconductor region; a first electrode provided on the first main surface of the semiconductor substrate, embedded in the second trench, and in contact with the second semiconductor region and the third semiconductor region on an inner wall of the second trench; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with the total number of the first trenches is greater than the total number of the second trenches; the second semiconductor region is provided between the second trench and the first semiconductor region, extending from the third semiconductor region on one side of the second trench to the third semiconductor region on the other side, and surrounding the second trench.

4. 4. The silicon carbide semiconductor device according to claim 1, wherein a total area of ​​the first trenches is larger than a total area of ​​the second trenches.

5. 4. The silicon carbide semiconductor device according to claim 1, wherein the width of the first trench is narrower than the width of the second trench.

6. a gate pad provided on the first main surface of the semiconductor substrate, electrically insulated from the first electrode by an interlayer insulating film, and electrically connected to the gate electrode; the first trench and the second trench are arranged in the same layout in a first region facing the first electrode in a depth direction and in a second region facing the gate pad in a depth direction, 4. The silicon carbide semiconductor device according to claim 1, wherein an insulating layer is buried in the second trench in the second region.

7. an active region in which the first electrode is disposed; a termination region surrounding the active region; an intermediate region between the active region and the termination region; a gate runner provided on the first main surface of the semiconductor substrate in the intermediate region via an oxide film, surrounding the active region, and connected to the gate electrode; Equipped with the first trench and the second trench are arranged in the same layout in both the active region and the intermediate region; 4. The silicon carbide semiconductor device according to claim 1, wherein an insulating layer is buried in the second trench in the intermediate region.

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