Silicon carbide semiconductor device

Abstract

According to the present invention, a front surface side of a semiconductor substrate (30) is provided with a source trench structure that comprises a gate trench (7), in which a gate electrode (9) is buried, and a source trench (11), in which a source electrode (13) is buried. A p-type base region (3) extends along the inner wall of the source trench (11) between the source trench (11) and an n- type drift region (2); and the bottom surface of the source trench (11) is surrounded by the p-type base region (3). An n-type current diffusion region (16) is provided so as to face the lower surface of a p-type base deep portion (4) of the p-type base region (3) in the depth direction (Z), the p-type base deep portion (4) extending along the bottom surface of the source trench (11). The n-type current diffusion region (16) has a function of lowering the breakdown voltage by making avalanche breakdown likely to occur in the vicinity of the bottom surface of the source trench (11) when an SiC-MOSFET is in an off state. Consequently, the present invention is capable of reducing the on-resistance.

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, a trench-gate SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate having a three-layer structure of metal-oxide-semiconductor) using silicon carbide (SiC) as a semiconductor material has been known to have a double-trench source trench structure in which a gate trench in which a gate electrode is buried and a source trench in which a source electrode is buried are provided.

[0003] The structure of a conventional silicon carbide semiconductor device will be described. Fig. 9 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in Fig. 9 is a trench gate type SiC-MOSFET with a source trench structure having a source trench 111 on the front surface (main surface on the epitaxial layer 132 side) of a semiconductor substrate 130 made of silicon carbide. The semiconductor substrate 130 is an n-type silicon carbide semiconductor device. + On the starting substrate 131 - n-type drift region 102 - The mold epitaxial layer 132 is epitaxially grown.

[0004] n + The starting substrate 131 is n + The epitaxial layer 132 includes a diffusion region (p-type base region 103, n-type drain region 101) formed by ion implantation into the epitaxial layer 132. + type source region 105 and p ++ The part excluding the contact region 106) is n - The n-type drift region 102 is a p-type base region 103 on the front surface side of the semiconductor substrate 130. + type source region 105, p ++The mold contact region 106, the gate trench 107, the gate insulating film 108 and the gate electrode 109 form a trench gate structure.

[0005] The gate trenches 107 and the source trenches 111 are alternately arranged one by one in a first direction X parallel to the front surface of the semiconductor substrate 130. A unit cell (functional unit of an element) has one gate trench 107 and half of the source trenches 111 on both sides of the gate trench 107. The gate trenches 107 are arranged in the depth direction Z from the front surface of the semiconductor substrate 130 to n + The n-type source region 105 and the p-type base region 103 are connected to the n-type - The gate electrode 109 terminates inside the type drift region 102. Inside the gate trench 107, a gate electrode 109 is provided with a gate insulating film 108 interposed therebetween.

[0006] The source trench 111 is formed in a depth direction Z from the front surface of the semiconductor substrate 130 to the n-type + The source trench 111 penetrates the n-type source region 105. The depth of the source trench 111 is equal to or greater than the depth of the gate trench 107. The portion between the centers of the adjacent source trenches 111 in the first direction X forms one unit cell. A source electrode 113 is buried inside the source trench 111. - A p-type base region 103 extends along the inner wall of the source trench 111 between the p-type drift region 102 and the source trench 111 .

[0007] The p-type base region 103 has a portion (hereinafter referred to as a deep p-type base portion) 104 along the bottom surface of the source trench 111, which is located at a depth of n-type from the bottom surface of the gate trench 107. + n type drain region 101 - A pn junction is formed between the source trench 111 and the p-type drift region 102. In the source trench structure, the p-type deep base portion 104 at the bottom of the source trench 111 can reduce the electric field applied to the gate insulating film 108 at the bottom of the gate trench 107. For this reason, no p-type region is disposed at a position facing the bottom of the gate trench 107.

[0008] By not arranging a p-type region at a position facing the bottom surface of the gate trench 107, the width of the JFET (Junction FET) portion is increased, and the JFET resistance is significantly reduced, thereby reducing the on-resistance. - This is a portion of the p-type drift region 102 that is adjacent to a channel (n-type inversion layer) formed along the gate trench 107 of the p-type base region 103 when the SiC-MOSFET is on, and serves as a current path for the main current (drift current) that flows through the channel.

[0009] The source trench 111 is exposed through a contact hole 112a in the interlayer insulating film 112. The source electrode 113 is buried in the source trench 111 through the contact hole 112a in the interlayer insulating film 112, and is connected to the p-type base region 103 and the n-type base region 104 on the inner wall of the source trench 111. + type source region 105 and p ++ The drain electrode 114 is in contact with the back surface (n + The mold starting substrate 131 is provided on the entire surface of the substrate 131. + The gate electrode 102 is electrically connected to the drain region 101 .

[0010] As a conventional trench-gate type SiC-MOSFET with a source trench structure, a device has been proposed in which a source insulating film is provided between a source electrode embedded in the source trench and a p-type base region at the bottom of the source trench to suppress the occurrence of punch-through (see, for example, Patent Document 1 below). In Patent Document 1 below, - The bottom surface of the gate trench and the p-type base region at the bottom surface of the source trench are surrounded by an n-type region provided throughout the entire area between the gate trench and the p-type drift region.

[0011] As a conventional trench-gate SiC-MOSFET with a single trench structure that only has a gate trench, there are p +A device in which a mold region is arranged has been proposed (see, for example, Patent Document 2 below). In Patent Document 2 below, + Directly below the mold area (n + An n-type region is provided only on the p-type drain region side. + By setting the avalanche breakdown point directly below the mold region, the occurrence of avalanche breakdown at the bottom of the gate trench is suppressed.

[0012] In a conventional trench gate Si (silicon) MOSFET with a source trench structure, the p + A device has been proposed in which an n-type region is provided directly below the n-type region, and the avalanche breakdown point is directly below the bottom surface of the source trench, which is shallower than the gate trench (see, for example, Patent Document 3 below). + By reducing the cell pitch by providing a p-type region between the n-type and p-type regions, low on-resistance is achieved in the low breakdown voltage class of 100V or less, where channel resistance is dominant. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 2019-161200 [Patent Document 2] Patent No. 6617657 [Patent Document 3] Japanese Patent Application Laid-Open No. 2005-057049 Summary of the Invention [Problem to be solved by the invention]

[0014] However, in conventional silicon carbide semiconductor device 110 (see FIG. 9 ), gate trench 107 and source trench 111 need to be disposed close to each other in order to alleviate the electric field near the bottom surface of gate trench 107 by deep p-type base portion 104 at the bottom surface of source trench 111. Therefore, by not disposing a p-type region at a position facing the bottom surface of gate trench 107, the JFET resistance can be made relatively low, but the JFET resistance increases compared to when deep p-type base portion 104 is not disposed at the bottom surface of source trench 111.

[0015] In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a trench gate type silicon carbide semiconductor device having a source trench, which is capable of reducing on-resistance. [Means for solving the problem]

[0016] In order to solve the above-mentioned problems and achieve the objects of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: A first semiconductor region of a first conductivity type is provided within a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A first trench penetrates the third semiconductor region and the second semiconductor region in the depth direction to reach the first semiconductor region. A gate electrode is provided within the first trench via a gate insulating film.

[0017] The second trench is provided at a distance from the first trench, penetrates the third semiconductor region in the depth direction to a depth equal to or greater than the depth of the first trench, and is surrounded by the second semiconductor region. A fourth semiconductor region of a first conductivity type is provided in the depth direction, facing a portion of the second semiconductor region along the bottom surface of the second trench. The fourth semiconductor region has a higher impurity concentration than the first semiconductor region. A first electrode is provided on the first main surface of the semiconductor substrate, embedded in the second trench, and in contact with the second semiconductor region and the third semiconductor region on the inner wall of the second trench. A second electrode is provided on the second main surface of the semiconductor substrate.

[0018] In addition, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further comprises a fifth semiconductor region of the first conductivity type, which is provided facing a bottom surface of the first trench in the depth direction and has a higher impurity concentration than the first semiconductor region.

[0019] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the impurity concentration of the fifth semiconductor region is equal to or lower than the impurity concentration of the fourth semiconductor region.

[0020] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the fourth semiconductor region is provided across the entire area between the second semiconductor region and the first semiconductor region, faces a portion of the second semiconductor region along a bottom surface of the second trench in the depth direction, and faces a bottom surface of the first trench in the depth direction.

[0021] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the fourth semiconductor region is in contact with the gate insulating film at a bottom surface of the first trench.

[0022] Moreover, in the silicon carbide semiconductor device according to the present invention, the fourth semiconductor region is provided away from a bottom surface of the first trench.

[0023] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the thickness of the fourth semiconductor region is uniform from the portion facing the bottom surface of the second trench to the portion facing the bottom surface of the first trench.

[0024] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the fourth semiconductor region is in contact with a portion of the second semiconductor region that is along a bottom surface of the second trench.

[0025] Moreover, in the silicon carbide semiconductor device according to the present invention, a bottom surface of the first trench is surrounded by the first semiconductor region.

[0026] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the second trenches are arranged at a predetermined pitch in a first direction parallel to the first main surface of the semiconductor substrate, and a plurality of the first trenches are arranged at a predetermined pitch in the first direction between adjacent second trenches.

[0027] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the second trenches adjacent to each other with a plurality of the first trenches therebetween and the second trenches adjacent to each other without the first trenches therebetween are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate.

[0028] According to the above-described invention, since the electric field can be concentrated near the bottom of the second trench during off-state, avalanche breakdown can be intentionally induced near the bottom of the second trench. This reduces the breakdown voltage, thereby reducing the electric field strength near the bottom of the first trench. Therefore, by widening the gap between the adjacent first and second trenches and widening the width of the JFET section in the first direction, the JFET resistance can be reduced. [Effects of the Invention]

[0029] Advantageous Effects of Invention The silicon carbide semiconductor device according to the present invention is a trench gate type silicon carbide semiconductor device having a source trench, and has an effect of being able to reduce on-resistance. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Figure 2] FIG. 2 is a cross-sectional view showing the cross-sectional structure taken along the line AA' in FIG. [Figure 3] FIG. 3 is a cross-sectional view showing the cross-sectional structure taken along the line BB' in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing the cross-sectional structure taken along the line CC' in FIG. [Figure 5] FIG. 5 is a cross-sectional view showing the cross-sectional structure taken along the line DD' in FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the third embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the fourth embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0031] Preferred embodiments of a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0032] (Embodiment 1) The structure of a silicon carbide semiconductor device according to a first embodiment will be described. Fig. 1 is a plan view showing the layout of the silicon carbide semiconductor device according to the first embodiment as seen from the front surface side of the semiconductor substrate. Figs. 2 to 5 are cross-sectional views taken along line A-A', line B-B', and line C-C' in Fig. 1, respectively. C-C' and cutting lines D-D' 2 shows a cross-sectional view of a cross-sectional structure in FIG. 2. One unit cell (functional unit of the element) of the active region 51 is shown. FIGS. 3 and 4 show the structure of the intermediate region 52. FIG. 5 shows a cross-sectional view of a portion directly below the gate pad 15 (n + The structure of the gate electrode (type drain region 1) is shown.

[0033] Figures 1 to 5 to 1 shows the structure of a silicon carbide semiconductor device according to a first embodiment. vinegar. The silicon carbide semiconductor device 10 according to the embodiment shown in FIG. 1 is a trench-gate SiC-MOSFET having a double-trench source trench structure in which a gate trench (first trench) 7 in which a gate electrode 9 is embedded and a source trench (second trench) 11 in which a source electrode 13 is embedded are provided on the front surface side of a semiconductor substrate (semiconductor chip) 30 made of silicon carbide (SiC) in an active region 51.

[0034] The active region 51 is a region through which a main current (drift current) flows in a direction perpendicular to the front surface of the semiconductor substrate 30 when the silicon carbide semiconductor device 10 is turned on. A plurality of unit cells of the SiC-MOSFET having the same structure are arranged adjacent to each other in the active region 51. The active region 51 has, for example, a substantially rectangular planar shape and is provided approximately in the center (chip center) of the semiconductor substrate 30. In the active region 51, a source electrode 13 (first electrode: not shown in FIG. 1, see FIGS. 2 and 3) and a gate pad 15 are provided on the front surface of the semiconductor substrate 30.

[0035] The source electrode 13 covers almost the entire front surface of the semiconductor substrate 30 in the active region 51. The source electrode 13 has, for example, a substantially rectangular planar shape with a portion recessed inward (toward the center of the chip). The source electrode 13 also serves as a source pad (electrode pad). The gate pad 15 has, for example, a substantially rectangular planar shape (not shown). The gate pad 15 is provided, for example, in a partially recessed recess of the source electrode 13 near the boundary between the active region 51 and the intermediate region 52, and is arranged so that three sides of the gate pad 15 face the source electrode 13.

[0036] Edge termination region 53 is a region between active region 51 and the edge (chip edge) of semiconductor substrate 30, and surrounds active region 51 in a substantially rectangular shape via intermediate region 52. In FIG. 1, the boundary between active region 51 and intermediate region 52 and the boundary between intermediate region 52 and edge termination region 53 are indicated by dashed lines. Edge termination region 53 has the function of alleviating the electric field on the front surface side of semiconductor substrate 30 to maintain a breakdown voltage. The breakdown voltage is the maximum voltage at which silicon carbide semiconductor device 10 (SiC-MOSFET) can be used without malfunctioning or breaking down.

[0037] In the edge termination region 53, a general breakdown voltage structure is arranged, such as a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring, which is composed of multiple p-type regions concentrically surrounding the periphery of the active region 51. For example, FIG. 3 shows a JTE structure in which p-type regions with lower impurity concentrations are arranged from the inside to the outside (chip edge side). - The mold area 49 is shown.

[0038] In an intermediate region 52 between the active region 51 and the edge termination region 53, a gate runner 48 is provided on the front surface of the semiconductor substrate 30 via an insulating layer (a field oxide film 45 described below and an interlayer insulating film 12 described below). The intermediate region 52 is a transition region in which a structure is disposed for electrically connecting the trench gate structure of the active region 51 and the breakdown voltage structure of the edge termination region 53. The gate runner 48 surrounds the periphery of the active region 51 in a substantially rectangular shape. The gate runner 48 is connected to a gate pad 15.

[0039] The semiconductor substrate 30 is made of silicon carbide. + On the front surface of the starting substrate 31, - n-type drift region (first semiconductor region) 2 - The semiconductor substrate 30 is formed by epitaxially growing an n-type epitaxial layer 32. The first main surface of the semiconductor substrate 30, which faces the epitaxial layer 32, is the front surface. + The second main surface on the mold starting substrate 31 side is referred to as the back surface. + The starting substrate 31 is n + The epitaxial layer 32 includes a p-type base region (second semiconductor region) 3 and an n-type drain region 1. + p-type source region (third semiconductor region) 5 ++ The portion excluding the n-type contact region 6 and the n-type current diffusion region (fourth semiconductor region) 16 is n - This is the type drift region 2.

[0040] The p-type base region 3, n + Type source region 5, p ++ The p-type contact region 6, the gate trench 7, the gate insulating film 8, and the gate electrode 9 form a trench gate structure. + Type source region 5, p ++ The p-type contact region 6 and the n-type current diffusion region 16 are diffusion regions formed by ion implantation inside the epitaxial layer 32. The p-type base region 3 is connected to the front surface of the semiconductor substrate 30 and the n-type current diffusion region 16 over the entire active region. - It is provided between the mold drift region 2.

[0041] n + The n-type source region 5 is provided over substantially the entire region 51a directly below the source electrode 13 between the front surface of the semiconductor substrate 30 and the p-type base region 3, and in contact with the p-type base region 3. + a p-type source region 5, a p-type base region 3 and an n - The n-type drift region 2 contacts the gate insulating film 8 on the sidewall of the gate trench 7. + The n-type source region 5 is in ohmic contact with the source electrode 13 on the front surface of the semiconductor substrate 30 and on the sidewall of the source trench 11. + The type source region 5 is not provided between the gate trench 7 and the insulating trenches 21 and 41 described later.

[0042] p ++ The p-type contact region 6 is provided between the bottom surface of the source trench 11 and a p-type base deep portion 4, which will be described later, and in contact with the p-type base deep portion 4. ++ The contact region 6 is in ohmic contact with the source electrode 13 at the bottom of the source trench 11. ++ The p-type contact region 6 is not provided between the front surface of the semiconductor substrate 30 and the p-type base region 3. ++ By not providing the contact region 6 between the front surface of the semiconductor substrate 30 and the p-type base region 3, it becomes easy to form a trench gate structure even if the cell pitch is narrow.

[0043] p ++The contact region 6 is preferably provided over the entire bottom surface of the source trench 11, but may be provided only partially on the bottom surface of the source trench 11 as long as an ohmic contact with the source electrode 13 can be formed on the bottom surface of the source trench 11. ++ The contact region 6 is an n - The p-type base 4 may be formed at a depth so as not to contact the n-type drift region 2, and may penetrate the p-type base deep portion 4 in the depth direction Z and terminate inside the n-type current diffusion region 16. ++ The mold contact region 6 may not be provided.

[0044] The gate trenches 7 and the source trenches 11 are alternately and repeatedly arranged apart from each other in a first direction X parallel to the front surface of the semiconductor substrate 30. One unit cell is formed between the centers of adjacent source trenches 11 in the first direction X with a gate trench 7 sandwiched therebetween. Two or more gate trenches 7 may be arranged adjacent to each other in the first direction X in one unit cell. In this case, the source trenches 11 are arranged at a predetermined pitch in the first direction X, and two or more gate trenches 7 are arranged at a predetermined pitch in the first direction X between the adjacent source trenches 11.

[0045] Furthermore, two or more source trenches 11 may be arranged adjacent to each other in the first direction X in one unit cell, with the number of source trenches 11 being equal to or less than the number of gate trenches 7 included in one unit cell. In this case, the source trenches 11 adjacent to each other with one or more gate trenches 7 therebetween and the source trenches 11 adjacent to each other without a gate trench 7 therebetween are alternately arranged in the first direction X. The areas between the source trenches 11 adjacent to each other without a gate trench 7 therebetween are ineffective areas that do not function as a MOSFET.

[0046] The greater the number of gate trenches 7 per unit cell, the greater the number of channels (n-type inversion layers) formed along the gate trenches 7 in the p-type base region 3 per unit cell when the silicon carbide semiconductor device 10 is on, thereby reducing the on-resistance. On the other hand, the greater the number of gate trenches 7 per unit cell, the smaller the effect of alleviating the electric field near the bottom of the gate trench 7 by the deep p-type base portion 4, described below, at the bottom of the source trench 11. For this reason, it is preferable that the number of gate trenches 7 per unit cell be a maximum of about three.

[0047] The width w1 of the gate trench 7 in the first direction X may be narrower than the width w2 of the source trench 11 in the first direction X. In this case, if the depth d2 of the source trench 11 is deeper than the depth d1 of the gate trench 7, the source trench 11 can be formed simultaneously with the gate trench 7, simplifying the manufacturing process. The width w1 of the gate trench 7 in the first direction X and the width w2 of the source trench 11 in the first direction X may be approximately the same. "Approximately the same width" means that the widths are the same within a range that includes tolerances due to variations in the manufacturing process.

[0048] The gate trench 7 is formed in a depth direction Z from the front surface of the semiconductor substrate 30 to the n + through the p-type source region 5 and the p-type base region 3, - The n-type drift region 2 terminates at the bottom of the gate trench 7. + Between the n-type drain region 1 - Only the n-type drift region 2 is disposed, and the bottom surface of the gate trench 7 is - The p-type drift region 2 is surrounded by the p-type drift region 2. Therefore, compared to when a p-type region for alleviating the electric field is disposed at a position facing the bottom surface of the gate trench 7 in the depth direction Z, the width of the JFET section in the first direction X is wider, and the JFET resistance is significantly reduced.

[0049] The JFET section is -The source trench 11 is a portion of the source drift region 2 between adjacent gate trenches 7 and a deep p-type base portion 4 (described later), and is adjacent to the channel and serves as a current path for the drift current. A gate insulating film 8 is provided along the inner wall (side wall and bottom surface) of the gate trench 7. A gate electrode 9 made of, for example, polysilicon (poly-Si) is provided on the gate insulating film 8 inside the gate trench 7. The gate trench 7 and the source trench 11 extend linearly (i.e., in a stripe pattern across the entire active region 51) in a second direction Y that is parallel to the front surface of the semiconductor substrate 30 and perpendicular to the first direction X.

[0050] Although not shown, the gate trenches 7 and the source trenches 11 may be alternately and repeatedly arranged in the first direction X, and the gate trenches 7 and the source trenches 11 may be alternately and repeatedly arranged in the second direction Y. In this case, the gate trenches 7 and the source trenches 11 have a substantially rectangular planar shape and are scattered in an island pattern (i.e., in a matrix pattern across the entire active region 51). Therefore, a plurality of unit cells are arranged adjacent to each other in the first direction X, and a plurality of unit cells are arranged adjacent to each other in the second direction Y.

[0051] The source trench 11 is formed in a depth direction Z from the front surface of the semiconductor substrate 30 to the n + The n-type source region 5 is formed at a depth substantially the same as the bottom surface of the gate trench 7 or at a depth lower than the bottom surface of the gate trench 7. + The depth d2 of the source trench 11 reaches a deep position on the p-type drain region 1 side. "Approximately the same depth" means that the depth is the same within a range including tolerances due to variations in the manufacturing process (for example, within ±10%, preferably within ±5%). The deeper the depth d2 of the source trench 11, the closer the p-type base deep portion 4 (described later) at the bottom of the source trench 11 becomes to the n-type base deep portion 4. + It is formed at a deep position on the side of the drain region 1.

[0052] The depth d2 of the source trench 11 is preferably deeper than the depth d1 of the gate trench 7. SiC has a maximum electric field strength that is one order of magnitude greater than that of silicon (Si), making it useful for high-voltage applications, for example, of 1200 V or higher, and the electric field applied to the gate insulating film 8 is greater than that of a Si-MOSFET. By making the depth d2 of the source trench 11 deeper than the depth d1 of the gate trench 7, the electric field tends to concentrate at the bottom surface of the source trench 11, and the electric field applied to the gate insulating film 8 at the bottom surface of the gate trench 7 is alleviated.

[0053] Even if the depth d2 of the source trench 11 is made deeper than the depth d1 of the gate trench 7, there is no adverse effect on the gate characteristics by appropriately setting the interval (mesa width) w12 between the adjacent gate trench 7 and source trench 11 (mesa portion) to be wider. In addition, since the depth d2 of the source trench 11 is deeper than the depth d1 of the gate trench 7, the source electrode 13 buried in the source trench 11 as described later becomes larger than the gate electrode 9 buried in the gate trench 7. + Even if it is located on the side of the gate drain region 1, it does not adversely affect the gate characteristics.

[0054] A source electrode 13 is buried inside the source trench 11. - The p-type base region 3 extends along the inner wall of the source trench 11 between the source electrode 13 and the p-type drift region 2. The source electrode 13 and the p-type base region 3 extend along the inner wall (side wall and bottom surface) of the source trench 11. ++ A source contact (electrical contact portion) is formed with the p-type contact region 6. A portion 4 of the p-type base region 3 along the bottom surface of the source trench 11 (hereinafter referred to as the deep p-type base portion) surrounds the entire bottom surface of the source trench 11.

[0055] The p-type base deep portion 4 at the bottom of the source trench 11 is located closer to the n-type base than the bottom of the gate trench 7. +A pn junction with an n-type current diffusion region 16 (described later) is formed at a position deep on the side of the source and drain regions 1, and the electric field applied to the gate insulating film 8 at the bottom of the gate trench 7 is alleviated. By ion implanting p-type impurities to form the p-type base region 3 at the bottom of the source trench 11, the pn junction is formed at a position deeper than the bottom of the gate trench 7. + Therefore, the p-type deep base portion 4 can be formed at a deep position on the side of the p-type drain region 1 without variations in impurity concentration.

[0056] For example, the source trench 11 is not provided between the adjacent gate trenches 7, and n + When forming a p-type region that reaches a deep position toward the drain region 1, ion implantation of p-type impurities from the front surface of the semiconductor substrate 30 with high acceleration energy may cause variations in the impurity concentration of the p-type region or crystal defects in the semiconductor substrate 30. Alternatively, forming the p-type region by repeatedly ion implanting p-type impurities each time the epitaxial layer 32 is epitaxially grown in multiple stages may increase the number of steps.

[0057] On the other hand, in this embodiment, ion implantation of p-type impurities to form p-type base region 3 is also performed on the inner wall of source trench 11. P-type base region 3 is formed in the surface region of the front surface of semiconductor substrate 30 in active region 51 and intermediate region 52 and in the surface region of the entire inner wall of source trench 11, and the portion of p-type base region 3 along the bottom surface of source trench 11 becomes p-type deep base portion 4. Therefore, ion implantation at high acceleration energy or a process of epitaxially growing epitaxial layer 32 in multiple stages is not required.

[0058] In addition, the p-type base deep portion 4 at the bottom of the source trench 11 is n + The deeper the p-type base deep portion 4 is disposed on the side of the n-type drain region 1, the more effective it is at alleviating the electric field near the bottom of the gate trench 7. +The deeper the p-type base deep portion 4 is positioned toward the drain region 1, the more improved the short-circuit resistance becomes, since the deep p-type base portion 4 becomes a resistance component when a large current (short-circuit current) exceeding the rated current flows between the drain and source of the SiC-MOSFET (silicon carbide semiconductor device 10) during a load short circuit or arm short circuit.

[0059] The thickness of the p-type base deep portion 4 (the thickness of the p-type base region 3 between the bottom surface of the source trench 11 and the n - The thickness t2 of the p-type base region 3 (the thickness of the portion between the front surface of the semiconductor substrate 30 and the n-type drift region 2) of the mesa portion is - The thickness t2 of the deep p-type base portion 4 of the p-type base region 3 can be made relatively thicker by further ion-implanting p-type impurities into the bottom surface of the source trench 11 when forming the p-type base region 3. For example, if p ++ By performing ion implantation of p-type impurities to form the contact region 6, the thickness t2 of the deep p-type base portion 4 of the p-type base region 3 can be made relatively thick.

[0060] p-type base deep 4 and n - Only between the n-type drift region 2 and - The n-type base 4 is in contact with the n-type drift region 2 and extends in the depth direction Z. + An n-type current diffusion region 16 is provided facing the p-type deep base region 4 (the surface facing the drain region 1). The n-type current diffusion region 16 is in contact with the entire lower surface of the p-type deep base region 4 and surrounds the entire lower surface of the p-type deep base region 4. The n-type current diffusion region 16 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 16 also has the function of making avalanche breakdown more likely to occur near the bottom of the source trench 11 when the SiC-MOSFET is turned off, thereby lowering the breakdown voltage (drain-source breakdown voltage).

[0061] The n-type current diffusion region 16 may be provided at a position facing the p-type deep base portion 4 in the depth direction Z, but away from the p-type deep base portion 4, as long as it can facilitate avalanche breakdown near the bottom surface of the source trench 11 when the SiC-MOSFET is off. The n-type current diffusion region 16 preferably faces the entire bottom surface of the p-type deep base portion 4 in the depth direction Z, but the above function can be achieved even if the n-type current diffusion region 16 faces only a portion of the lower surface of the p-type deep base portion 4. The n-type current diffusion region 16 is formed, for example, by ion implantation of n-type impurities into the bottom surface of the source trench 11 after the source trench 11 is formed and before the p-type deep base portion 4 is formed. The n-type current diffusion region 16 may be formed using a mask used to form the source trench 11.

[0062] For example, the n-type current diffusion region 16 may be formed by using a mask when ion implanting p-type impurities into the bottom surface of the source trench 11 to increase the thickness t2 of the p-type deep base portion 4. The n-type current diffusion region 16 is formed by ion implantation with a higher acceleration energy than the ion implantation for forming the p-type deep base portion 4, and is formed in a region deeper than the p-type deep base portion 4. + Since the p-type deep base portion 4 is formed at a deep position toward the drain region 1 side, it is relatively easy for the n-type current diffusion region 16 to diffuse in a direction parallel to the front surface of the semiconductor substrate 30. Therefore, by forming the p-type deep base portion 4 and the n-type current diffusion region 16 in a self-aligned manner, the n-type current diffusion region 16 can be formed over the entire area of ​​the lower surface of the p-type deep base portion 4, and the width of the n-type current diffusion region 16 can be made approximately the same as the width of the p-type deep base portion 4.

[0063] N-type current spreading region 16 is not provided in region 51b directly below gate pad 15, intermediate region 52, and edge termination region 53. As a result, when the SiC-MOSFET is off, avalanche breakdown can be intentionally caused only in region 51a directly below source trench 11 in region 51a directly below source electrode 13, and avalanche breakdown does not occur in region 51b directly below gate pad 15, intermediate region 52, and edge termination region 53. As a result, the breakdown voltage of intermediate region 52 and edge termination region 53 can be made higher than the breakdown voltage of active region 51, and the breakdown voltage of the entire silicon carbide semiconductor device 10 (semiconductor substrate 30) can be determined by the breakdown voltage of active region 51.

[0064] In the active region 51, a trench 21 filled with a buried insulating layer 22 (hereinafter referred to as an insulating trench) is provided in a region 51b directly below the gate pad 15. The insulating trench 21 and n - Between the active region 51 and the n-type drift region 2, the p-type base region 3 extends along the inner wall of the isolation trench 21 from the active region 51, and surrounds the entire bottom surface of the isolation trench 21. The lower surface of the portion 23 of the p-type base region 3 along the bottom surface of the isolation trench 21 (hereinafter referred to as the deep p-type base portion) is - In contact with the drift region 2, - The insulating trenches 21 are surrounded by the mold drift region 2. The insulating trenches 21 extend, for example, in a stripe shape in the second direction Y. The width w3 of the insulating trenches 21 in the first direction X and the interval w13 between adjacent insulating trenches 21 can be set appropriately.

[0065] The p-type base region 3 directly under the gate pad 15 has the function of suppressing the rise in potential of the region 51b directly under the gate pad 15 due to a sudden rise in the voltage applied to the drain electrode 14. By arranging the insulating trench 21 in the region 51b directly under the gate pad 15, the deep p-type base portion 23 at the bottom of the insulating trench 21 becomes n +The p-type deep base portion 23 is formed at a deep position toward the drain region 1. The thickness t3 of the p-type deep base portion 23 is, for example, approximately the same as the thickness t2 of the p-type deep base portion 4 at the bottom surface of the source trench 11. By making the depth d3 of the insulation trench 21 approximately the same as the depth d2 of the source trench 11, the p-type deep base portion 23 can be formed at approximately the same depth as the p-type deep base portion 4 at the bottom surface of the source trench 11.

[0066] The deep p-type base portions 23 at the bottom surfaces of the adjacent insulation trenches 21 are connected to each other, so that the lower surface of the p-type base region 3 is closer to the n-type base than the bottom surface of the insulation trench 21 in the entire region 51b directly below the gate pad 15. + The region 51b directly under the gate pad 15 has a substantially rectangular planar shape with dimensions substantially the same as or slightly larger than the gate pad 15, and faces the entire surface of the gate pad 15. The region 51b directly under the gate pad 15 may be substantially flat at a position deep on the p-type drain region 1 side. The region 51b directly under the gate pad 15 has a substantially rectangular planar shape with dimensions substantially the same as or slightly larger than the gate pad 15, and faces the entire surface of the gate pad 15. The region 51b may be substantially flat at a position deep on the p-type drain region 1 side. ++ Similarly to the p-type contact region 6, the p-type base ++ A mold contact region 24 may be provided.

[0067] The interlayer insulating film 12 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 9. A plurality of contact holes 12a to 12c are provided through the interlayer insulating film 12 in the depth direction Z. The contact holes 12a are connected to the source trench 11 and the n-type semiconductor substrate 30. + The p-type source region 5 is exposed through the contact hole 12b. The p-type base region 3 between the gate trench 7 and the insulating trenches 21, 41 adjacent to each other is exposed through the contact hole 12c. A gate polysilicon wiring layer 46, which will be described later, in the intermediate region 52 is exposed through the contact hole 12c. The source electrode 13 is buried in the source trench 11 through the contact hole 12a in the interlayer insulating film 12, and is connected to the p-type base region 3, n-type source region 5 on the inner wall of the source trench 11. + Type source region 5 and p ++ It contacts the mold contact region 6.

[0068] A gate pad 15 is provided on the interlayer insulating film 12 in the active region 51. The source electrode 13 and the gate pad 15 are provided on the same layer and are metal electrode layers electrically insulated from each other by the interlayer insulating film 12. The gate pad 15 faces the insulating trench 21, the buried insulating layer 22, and the deep p-type base 23 via the interlayer insulating film 12. All the gate electrodes 9 are electrically connected to the gate pad 15 via gate runners 48. The drain electrode (second electrode) 14 is connected to the back surface (n + The drain electrode 14 is in ohmic contact with the back surface of the semiconductor substrate 30 and is provided on the entire surface of the back surface of the semiconductor substrate 30. + Type drain region 1(n + The mold is electrically connected to the starting substrate 31).

[0069] The intermediate region 52 is provided with a gate trench 7 extending from the active region 51 and an insulating trench 41 in which a buried insulating layer 42 is buried. - Between the active region 51 and the n-type drift region 2, the p-type base region 3 extends along the inner wall of the isolation trench 41, surrounding the entire bottom surface of the isolation trench 41. The lower surface of the portion of the p-type base region 3 along the bottom surface of the isolation trench 41 (hereinafter referred to as the deep p-type base portion) 43 is - In contact with the drift region 2, - The insulating trenches 41 are surrounded by the mold drift region 2. The insulating trenches 41 extend, for example, in a stripe shape in the second direction Y. The width w4 of the insulating trenches 41 in the first direction X and the interval w14 between the adjacent gate trenches 7 and insulating trenches 41 can be set appropriately.

[0070] For example, the width w4 of the insulation trench 41 in the first direction X is approximately the same as the width w2 of the source trench 11 in the first direction X. The insulation trenches 41 are provided on a pair of opposite sides parallel to the first direction X of the intermediate region 52 that surrounds the periphery of the active region 51 in a substantially rectangular shape, facing the source trench 11 in the second direction Y, and are scattered across the gate trench 7 in the first direction X (FIG. 4). On the other hand, the insulation trenches 41 extend linearly (or in stripes) in the second direction Y across the entire area of ​​a pair of opposite sides parallel to the second direction Y of the intermediate region 52. do. At a pair of opposite sides of the intermediate region 52 parallel to the second direction Y, the entire area of ​​the insulation trench 41 faces in the depth direction Z a pair of opposite sides of the gate runner 48 parallel to the second direction Y.

[0071] By disposing the isolation trench 41 in the intermediate region 52, the p-type base deep portion 43 at the bottom of the isolation trench 41 becomes n + The p-type deep base portion 43 is formed at a deep position on the side of the drain region 1. The thickness t4 of the p-type deep base portion 43 is, for example, approximately the same as the thickness t2 of the p-type deep base portion 4 at the bottom surface of the source trench 11. By making the depth d4 of the insulation trench 41 approximately the same as the depth d2 of the source trench 11, the p-type deep base portion 43 can be formed at approximately the same depth as the p-type deep base portion 4 at the bottom surface of the source trench 11. ++ Similarly to the p-type contact region 6, the p-type base ++ A mold contact region 44 may be provided.

[0072] The p-type base region 3 in the intermediate region 52 surrounds the periphery of the active region 51 in a substantially rectangular shape along the boundary between the active regions 51 and the intermediate region 52. The p-type base region 3 in the intermediate region 52 functions to make the electric field uniform within the surface of the front surface of the semiconductor substrate 30 in the intermediate region 52. A field oxide film 45 is provided between the front surface of the semiconductor substrate 30 and the interlayer insulating film 12 in the intermediate region 52 and the edge termination region 53. The field oxide film 45 may extend between the front surface of the semiconductor substrate 30 in the active region 51 and the interlayer insulating film 12 so as to face the entire surface of the gate pad 15. A gate polysilicon wiring layer 46 is provided between the field oxide film 45 and the interlayer insulating film 12 in the intermediate region 52. The buried insulating layers 22 and 42 may be formed simultaneously with the field oxide film 45.

[0073] A gate electrode 9 is connected to the gate polysilicon wiring layer 46 at an end of the gate trench 7 in the longitudinal direction (second direction Y). A gate metal wiring layer 47 is provided on the gate polysilicon wiring layer 46 via a contact hole 12c in the interlayer insulating film 12. The gate metal wiring layer 47 is connected to the gate pad 15. The gate polysilicon wiring layer 46 and the gate metal wiring layer 47 form a gate runner 48 surrounding the active region 51. The gate runner 48 faces the p-type base region 3, the deep p-type base portion 43, the insulating trench 41, and the buried insulating layer 42 via insulating layers (field oxide film 45 and interlayer insulating film 12).

[0074] The operation of the silicon carbide semiconductor device 10 (SiC-MOSFET) according to the first embodiment will be described. When a positive voltage is applied to the drain electrode 14 with respect to the source electrode 13 (a forward bias is formed between the drain and source), p ++ The p-type contact region 6 and the p-type base region 3, and the n-type current diffusion region 16, - Type drift region 2 and n + A reverse bias is applied to the pn junction (main junction) between the gate electrode 9 and the gate-drain region 1. In this state, if the voltage applied to the gate electrode 9 is less than the gate threshold voltage, the SiC-MOSFET remains in the off state.

[0075] As described above, the main junction is reverse biased, so that the p-type deep base portion 4 (or the n-type current spreading region 16, or both) is depleted. Therefore, by appropriately setting the interval w12 between the adjacent gate trench 7 and source trench 11, the electric field applied to the gate insulating film 8 at the bottom of the gate trench 7 can be relaxed by the p-type deep base portion 4 at the bottom of the source trench 11, even without providing a p-type region for relaxing the electric field at the bottom of the gate trench 7.

[0076] Furthermore, the n-type current diffusion region 16 is provided in the depth direction Z so as to face the p-type base deep portion 4 at the bottom of the source trench 11, thereby concentrating an electric field near the bottom of the source trench 11 when the SiC-MOSFET is off. This allows avalanche breakdown to be intentionally caused near the bottom of the source trench 11 when the SiC-MOSFET is off, and the breakdown voltage can be lowered, thereby reducing the electric field strength near the bottom of the gate trench 7.

[0077] On the other hand, when a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 9 while a positive voltage relative to the source electrode 13 is applied to the drain electrode 14, a channel (n-type inversion layer) is formed in the p-type base region 3 along the sidewall of the gate trench 7. + Type drain region 1 to n - The n-type drift region 2, the JFET portion (the portion between the gate trench 7 and the p-type base deep portion 4 adjacent to each other) and the channel are connected. + A drift current (main current) flows toward the type source region 5, and the SiC-MOSFET turns on.

[0078] The n-type current diffusion region 16 is provided in the depth direction Z so as to face the p-type base deep portion 4 at the bottom of the source trench 11, and therefore the n-type impurity concentration is high near the bottom of the p-type base deep portion 4. Therefore, the n-type impurity concentration is increased near the bottom of the p-type base deep portion 4 from the reverse-biased main junction (pn junction). - The depletion layer is less likely to spread into the n-type drift region 2. This prevents the n-type drift region 2 from spreading when the SiC-MOSFET is in the on state.- This can prevent the path of the drift current flowing in the type drift region 2 from being narrowed by the depletion layer extending from the main junction, and can prevent the JFET resistance from increasing.

[0079] Furthermore, as described above, since the electric field strength near the bottom surface of the gate trench 7 can be reduced, even if the interval w12 between the adjacent gate trench 7 and source trench 11 is widened, the electric field relaxation effect near the bottom surface of the gate trench 7 by the deep p-type base portion 4 at the bottom surface of the source trench 11 can be obtained. Therefore, by widening the interval w12 between the adjacent gate trench 7 and source trench 11 and widening the width of the JFET section in the first direction X, the JFET resistance can be reduced.

[0080] As described above, according to the first embodiment, an n-type current diffusion region is provided facing the deep p-type base portion at the bottom of the source trench in the depth direction, thereby intentionally causing an avalanche breakdown near the bottom of the source trench when the SiC-MOSFET is turned off. This can lower the breakdown voltage and reduce the electric field strength near the bottom of the gate trench. Therefore, by widening the interval between adjacent gate trenches and source trenches and widening the width of the JFET section in the first direction X, the JFET resistance can be reduced, and the on-resistance can be reduced.

[0081] Furthermore, according to the first embodiment, by not arranging a p-type region for electric field relaxation at a position facing the bottom surface of the gate trench in the depth direction, the width of the JFET section is increased, and the JFET resistance is significantly reduced. Furthermore, even if a p-type region for electric field relaxation is not arranged at a position facing the bottom surface of the gate trench in the depth direction, the deep p-type base at the bottom surface of the source trench can relax the electric field applied to the gate insulating film at the bottom surface of the gate trench. Furthermore, according to the first embodiment, since the electric field strength near the bottom surface of the gate trench can be reduced as described above, the electric field relaxation effect near the bottom surface of the gate trench is higher than in the conventional structure (see FIG. 9 ) that does not have an n-type current diffusion region, and reliability can be improved.

[0082] Furthermore, according to the first embodiment, the n-type current diffusion region is provided facing the deep p-type base portion at the bottom of the source trench in the depth direction, thereby increasing the n-type impurity concentration near the bottom of the deep p-type base portion. - From the pn junction with the type drift region - This makes it difficult for the depletion layer to extend into the n-type drift region when the SiC-MOSFET is in the on-state. - The path of the drift current flowing in the n-type drift region is the deep p-type base, the n-type current diffusion region, and the n-type - This can prevent the gate electrode from being narrowed by the depletion layer extending from the pn junction with the type drift region, and can prevent the JFET resistance from increasing.

[0083] (Embodiment 2) The structure of a silicon carbide semiconductor device according to the second embodiment will be described. FIG. 6 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the second embodiment. The layout of a silicon carbide semiconductor device 60 according to the second embodiment, as viewed from the front surface side of the semiconductor substrate 30, is the same as that of the first embodiment (see FIG. 1). FIG. 6 corresponds to the cross-sectional structure taken along the line A-A' in FIG. 1. The silicon carbide semiconductor device 60 according to the second embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment (see FIGS. 1 to 5) in that, in addition to the n-type current diffusion region 16 immediately below the source trench, an n-type current diffusion region is also provided at a position facing the bottom surface of the gate trench 7 in the depth direction Z. - The n-type current diffusion region (fifth semiconductor region) 61 is provided in contact with the n-type drift region 2.

[0084] The n-type current diffusion region 61 has the function of increasing the n-type impurity concentration in the vicinity of the JFET section and reducing the JFET resistance. The n-type current diffusion region 61 may face the entire bottom surface of the gate trench 7, or may face only a portion of the bottom surface of the gate trench 7. The n-type current diffusion region 61 may be in contact with the gate insulating film 8 at the bottom surface of the gate trench 7, or may be provided away from the bottom surface of the gate trench 7. The n-type current diffusion region 61 is not provided in the region 51b directly below the gate pad 15 or in the intermediate region 52.

[0085] The thickness t21 of the n-type current diffusion region 61 may be substantially the same as the thickness t11 of the n-type current diffusion region 16. "Substantially the same thickness" means that the thicknesses are the same within a range that includes tolerances due to variations in the manufacturing process, for example, within ±5%. The impurity concentration of the n-type current diffusion region 61 is equal to or lower than the impurity concentration of the n-type current diffusion region 16 immediately below the source trench. The n-type current diffusion region 61 is formed, for example, by ion implantation of n-type impurities into the bottom surface of the gate trench 7 after the gate trench 7 is formed.

[0086] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, according to the second embodiment, by providing an n-type current diffusion region facing the bottom surface of the gate trench in the depth direction, it is possible to further reduce the on-resistance.

[0087] (Embodiment 3) The structure of a silicon carbide semiconductor device according to the third embodiment will be described. FIG. 7 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the third embodiment. The layout of a silicon carbide semiconductor device 70 according to the third embodiment, as viewed from the front surface side of the semiconductor substrate 30, is the same as that of the first embodiment (see FIG. 1). FIG. 7 corresponds to the cross-sectional structure taken along the line A-A' in FIG. 1. The silicon carbide semiconductor device 70 according to the third embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment (see FIGS. 1 to 5) in that the silicon carbide semiconductor device 70 according to the third embodiment has a structure in which a region between the p-type base region 3 and the n-type base region 4 is formed not only directly under the source trench 11 but also between the p-type base region 3 and the n-type base region 4. - The point is that an n-type current diffusion region (fourth semiconductor region) 71 is provided in contact with the n-type drift region 2 over the entire region between these regions.

[0088] The n-type current diffusion region 71 has the function of increasing the n-type impurity concentration in the vicinity of the JFET section and reducing the JFET resistance. - The n-type current diffusion region 71 is provided between the source trench 11 and the gate trench 7, extending from directly below the source trench 11 to directly below the gate trench 7, and is in contact with the entire p-type base region 3 (including the deep p-type base portion 4) and surrounds the p-type base region 3, and is in contact with the gate insulating film 8 over the entire bottom surface of the gate trench 7 and surrounds the bottom surface of the gate trench 7. The n-type current diffusion region 71 is in contact with the gate insulating film 8 at the bottom surface of the gate trench 7. The lower surface of the n-type current diffusion region 71 is, for example, a flat surface parallel to the front surface of the semiconductor substrate 30.

[0089] The n-type current diffusion region 71 is not provided in the region 51b directly below the gate pad 15, the intermediate region 52, or the edge termination region 53. The thickness t31 of the n-type current diffusion region 71 directly below the source trench 11 may be substantially the same as the thickness t11 (see FIG. 2) of the n-type current diffusion region 16 in the first embodiment. The portion of the n-type current diffusion region 71 between the adjacent gate trench 7 and the deep p-type base portion 4 becomes the JFET portion. The n-type current diffusion region 71 is formed, for example, by ion implantation of n-type impurities into the epitaxial layer 32 before the formation of the gate trench 7 and the source trench 11.

[0090] As described above, according to the third embodiment, it is possible to obtain the same effects as those of the first and second embodiments. Furthermore, according to the third embodiment, it is possible to obtain the same effects as those of the first and second embodiments. - By providing an n-type current diffusion region over the entire area between the n-type drift region and the n-type current diffusion region, the same effect as in the second embodiment can be obtained.

[0091] (Fourth embodiment) The structure of a silicon carbide semiconductor device according to the fourth embodiment will be described. FIG. 8 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. The layout of a silicon carbide semiconductor device 80 according to the fourth embodiment, viewed from the front surface side of the semiconductor substrate 30, is the same as that of the first embodiment (see FIG. 1). FIG. 8 corresponds to the cross-sectional structure taken along the cutting line A-A' in FIG. 1. The silicon carbide semiconductor device 80 according to the fourth embodiment differs from the silicon carbide semiconductor device 10 according to the first embodiment (see FIGS. 1 to 5) in that an n-type current diffusion region (fourth semiconductor region) 81 extends with approximately the same thickness t41 from directly below the source trench 11 to directly below the gate trench 7.

[0092] The n-type current diffusion region 81 has the function of increasing the n-type impurity concentration in the vicinity of the JFET section and reducing the JFET resistance. The n-type current diffusion region 81 is formed in the region 51a directly below the source electrode 13, and is connected to the p-type base region 3 and the n-type -The n-type current diffusion region 81 is provided between the p-type drift region 2 and the source trench 11, extending from the portion directly below the source trench 11 to the portion directly below the gate trench 7. The n-type current diffusion region 81 faces the entire p-type base region 3 (including the deep p-type base portion 4) in the depth direction Z, and also faces the entire bottom surface of the gate trench 7 in the depth direction Z.

[0093] The n-type current diffusion region 81 may be in contact with the p-type base region 3 (i.e., the deep p-type base portion 4) directly below the source trench 11, or may be disposed apart from the p-type base region 3 in the depth direction Z. The n-type current diffusion region 81 is disposed apart from the p-type base region 3 in the depth direction Z between the gate trench 7 and the deep p-type base portion 4 adjacent to each other. The n-type current diffusion region 81 is disposed apart from the bottom surface of the gate trench 7 in the depth direction Z. The n-type current diffusion region 81 and the gate trench 7 are separated from each other by an n-type current diffusion region. - The bottom surface of the gate trench 7 is an n-type drift region 2, as in the first embodiment. - It is surrounded by a type drift region 2.

[0094] The thickness t41 of the n-type current diffusion region 81 is uniform, and the upper surface (n + Both the surface (on the side of the n-type source region) and the bottom surface are flat surfaces parallel to the top surface of the semiconductor substrate 30. The thickness t41 of the n-type current diffusion region 81 may be substantially the same as the thickness t11 (see FIG. 2 ) of the n-type current diffusion region 16 of the first embodiment. The n-type current diffusion region 81 is formed, for example, by ion implantation of n-type impurities into the epitaxial layer 32 before the formation of the gate trench 7 and the source trench 11.

[0095] As described above, according to the fourth embodiment, it is possible to obtain the same effects as those of the first to third embodiments. Furthermore, according to the fourth embodiment, the bottom surface of the gate trench 7 is n - Being surrounded by the type drift region 2 makes it possible to reduce the electric field strength near the bottom surface of the gate trench 7.

[0096] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0097] As described above, the silicon carbide semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for SiC-MOSFETs in the high-voltage class of 1200 V or more. [Explanation of symbols]

[0098] 1n + Type drain region 2n - Type Drift Region 3 p-type base region 4,23,43 deep p-type base 5n + Type Source Area 6,24,44 p ++ Mold contact area 7 Gate Trench 8 Gate insulating film 9 Gate electrode 10,60,70,80 Silicon carbide semiconductor device 11 Source Trench 12 Interlayer insulating film 12a to 12c: contact holes in interlayer insulating film 13 Source electrode 14 Drain electrode 15 Gate Pad 16,61,71,81 n-type current diffusion region 21,41 Isolation trench 22,42 Buried insulating layer 30 Semiconductor substrate 31n + Starting substrate 32 Epitaxial layer 45 Field Oxide 46 Gate polysilicon wiring layer 47 Gate metal wiring layer 48 Gate Runner 49 pages - type area 51,51a, 51b active region 52 Intermediate area 53 Edge Termination Area X: the first direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction d1 Gate trench depth d2 Source trench depth d3,d4 Depth of insulation trench t1 Thickness of the p-type base region of the mesa t2~t4 Thickness of the deep p-type base t11,t21,t31,t41 Thickness of n-type current diffusion region w1 Width of the gate trench in the first direction w2 Width of source trench in the first direction w3, w4 Width of the insulation trench in the first direction w12: Distance between adjacent gate and source trenches w13, w14: Distance between adjacent insulation trenches

Claims

1. a semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided inside the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a first trench that penetrates the third semiconductor region and the second semiconductor region in a depth direction and reaches the first semiconductor region; a gate electrode provided inside the first trench via a gate insulating film; a second trench provided apart from the first trench, penetrating the third semiconductor region in a depth direction to a depth equal to or greater than the depth of the first trench, and surrounded by the second semiconductor region; a fourth semiconductor region of the first conductivity type, which is provided in a depth direction so as to face a portion of the second semiconductor region along a bottom surface of the second trench and has an impurity concentration higher than that of the first semiconductor region; a first electrode provided on the first main surface of the semiconductor substrate, embedded in the second trench, and in contact with the second semiconductor region and the third semiconductor region on an inner wall of the second trench; a second electrode provided on a second main surface of the semiconductor substrate; a fifth semiconductor region of the first conductivity type provided opposite to a bottom surface of the first trench in a depth direction, the fifth semiconductor region having an impurity concentration higher than that of the first semiconductor region and equal to or lower than that of the fourth semiconductor region; A silicon carbide semiconductor device comprising:

2. A semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided inside the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a first trench that penetrates the third semiconductor region and the second semiconductor region in a depth direction and reaches the first semiconductor region; a gate electrode provided inside the first trench via a gate insulating film; a second trench provided apart from the first trench, penetrating the third semiconductor region in a depth direction to a depth equal to or greater than the depth of the first trench, and surrounded by the second semiconductor region; a fourth semiconductor region of the first conductivity type, which is provided in a depth direction so as to face a portion of the second semiconductor region along a bottom surface of the second trench and has an impurity concentration higher than that of the first semiconductor region; a first electrode provided on the first main surface of the semiconductor substrate, embedded in the second trench, and in contact with the second semiconductor region and the third semiconductor region on an inner wall of the second trench; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with the fourth semiconductor region is provided across the entire area between the second semiconductor region and the first semiconductor region, faces a portion of the second semiconductor region along a bottom surface of the second trench in a depth direction, and faces a bottom surface of the first trench in a depth direction, away from the bottom surface of the first trench.

3. A semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided inside the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a first trench that penetrates the third semiconductor region and the second semiconductor region in a depth direction and reaches the first semiconductor region; a gate electrode provided inside the first trench via a gate insulating film; a second trench provided apart from the first trench, penetrating the third semiconductor region in a depth direction to a depth equal to or greater than the depth of the first trench, and surrounded by the second semiconductor region; a fourth semiconductor region of the first conductivity type, which is provided in a depth direction so as to face a portion of the second semiconductor region along a bottom surface of the second trench and has an impurity concentration higher than that of the first semiconductor region; a first electrode provided on the first main surface of the semiconductor substrate, embedded in the second trench, and in contact with the second semiconductor region and the third semiconductor region on an inner wall of the second trench; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with a first direction parallel to a first main surface of the semiconductor substrate, the first trenches being spaced apart from each other by a first trench between adjacent second trenches and the second trenches being spaced apart from each other by a first trench between adjacent second trenches without a first trench between them.

4. 4. The silicon carbide semiconductor device according to claim 3, wherein the fourth semiconductor region is provided across the entire area between the second semiconductor region and the first semiconductor region, faces a portion of the second semiconductor region along a bottom surface of the second trench in the depth direction, and faces a bottom surface of the first trench in the depth direction.

5. The silicon carbide semiconductor device according to claim 4 , wherein the fourth semiconductor region is in contact with the gate insulating film at a bottom surface of the first trench.

6. The silicon carbide semiconductor device according to claim 4 , wherein the fourth semiconductor region is provided away from a bottom surface of the first trench.

7. 7. The silicon carbide semiconductor device according to claim 2, wherein the fourth semiconductor region has a uniform thickness from a portion facing the bottom surface of the second trench to a portion facing the bottom surface of the first trench.

8. 7. The silicon carbide semiconductor device according to claim 1, wherein the fourth semiconductor region is in contact with a portion of the second semiconductor region that is along a bottom surface of the second trench.

9. 7. The silicon carbide semiconductor device according to claim 1, wherein a bottom surface of the first trench is surrounded by the first semiconductor region.

10. the second trenches are arranged at a predetermined pitch in a first direction parallel to the first main surface of the semiconductor substrate; 3 . The silicon carbide semiconductor device according to claim 1 , wherein a plurality of the first trenches are arranged at a predetermined pitch in the first direction between adjacent ones of the second trenches.

11. 3. The silicon carbide semiconductor device according to claim 1, wherein spaces between adjacent second trenches sandwiching a plurality of the first trenches and spaces between adjacent second trenches without sandwiching the first trenches are alternately and repeatedly formed in a first direction parallel to the first main surface of the semiconductor substrate.

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