Semiconductor Devices

Abstract

To provide a semiconductor device with high reliability including an oxide semiconductor, and a semiconductor device that has achieved miniaturization while keeping excellent electric characteristics using an oxide semiconductor.SOLUTION: A semiconductor device includes a first protection insulating layer 111, an oxide semiconductor layer 102 on the first protection insulating layer, a source electrode and a drain electrode 103 electrically connected to the oxide semiconductor layer, a gate insulating layer 104 existing on the source electrode and the drain electrode and overlapping with the oxide semiconductor layer, a gate electrode 105 overlapping with the oxide semiconductor layer through the gate insulating layer, and a second protection insulating layer 112 covering the source electrode, the drain electrode, and the gate electrode. In addition, the first protection insulating layer and the second protection insulating layer include an aluminum oxide film including an oxygen-excessive region, and include a region where these layers are in contact with each other in a region where the source electrode, the drain electrode, or the gate electrode does not exist.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed in this specification and the like relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including transistors, semiconductor circuits, arithmetic units, memory devices, imaging devices, and electro-optical devices. devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are semiconductor devices. This is one aspect of the arrangement. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is used in integrated circuits (ICs) and image display devices (simply called display devices). These are widely used in electronic devices such as semiconductors that can be applied to transistors. Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are in the spotlight.

[0004] For example, zinc oxide and In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, in order to improve the carrier mobility of transistors, the electron affinity (or conduction band A technique for stacking oxide semiconductor layers with different bottom energy levels has been disclosed (Patent Documents 3 and (See Patent Document 4). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-124360 [Patent Document 4] Japanese Patent Application Laid-Open No. 2011-138934 Summary of the Invention [Problem to be solved by the invention]

[0007] High reliability can be achieved in a semiconductor device including a transistor using an oxide semiconductor by: This is an important issue for commercialization. In particular, fluctuations and deterioration of the electrical characteristics of semiconductor devices can lead to low reliability. This is one of the factors that leads to a decline.

[0008] In view of the above problem, one embodiment of the present invention is a semiconductor device including an oxide semiconductor. An object of the present invention is to provide a highly reliable semiconductor device.

[0009] Furthermore, transistors are becoming faster, less power-consuming, less expensive, and more highly integrated. In order to achieve this, miniaturization of transistors is essential.

[0010] In view of the above, one embodiment of the present invention is a semiconductor device including an oxide semiconductor, which has good electrical characteristics. An object of the present invention is to provide a semiconductor device that achieves miniaturization while maintaining performance.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. It will be clear from the description of the specification, etc. that there are other problems than those mentioned above. It is possible to extract it. [Means for solving the problem]

[0012] A semiconductor device according to one embodiment of the present invention includes a first protective insulating layer and an oxide film formed on the first protective insulating layer. a semiconductor layer; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; a gate insulating layer located on the source electrode and the drain electrode and overlapping the oxide semiconductor layer; A gate electrode overlapping the oxide semiconductor layer via an insulating layer, a source electrode, a drain electrode, and and a second protective insulating layer covering the gate electrode. The protective insulating layer includes an aluminum oxide film having an oxygen excess region, and the source electrode, the drain electrode, and the like. The gate electrode and the gate electrode have a region where they contact each other in a region where they are not present.

[0013] The gate electrode covers the top and side surfaces of the oxide semiconductor layer via a gate insulating layer. It is preferable to have the following configuration.

[0014] The oxide semiconductor layer has a thickness that is 0.1 to 10 times the channel width. It is preferable that there is.

[0015] In the above, an oxide semiconductor insulating film is provided between the first protective insulating layer and the oxide semiconductor layer. a first oxide layer containing at least one metal element of the oxide semiconductor layer; The oxide semiconductor layer is provided between the gate insulating layer and the gate insulating layer, and the oxide semiconductor layer contains at least one metal element. and a second oxide layer formed on the first oxide layer. The energy of the conduction band minimum of the oxide layer is lower than that of the oxide semiconductor layer. It is also preferable that the potential be in the range of 0.05 eV to 2 eV, which is close to the vacuum level.

[0016] The upper surface of the second oxide layer is connected to the lower surface of the source electrode, the lower surface of the drain electrode, and the gate electrode. Alternatively, the insulating layer may be configured to be in contact with the lower surface of the insulating layer.

[0017] Alternatively, the lower surface of the second oxide layer is in contact with the upper surface of the source electrode, the upper surface of the drain electrode, and The upper surface of the oxide semiconductor layer in the region where the source electrode and the drain electrode are not provided and It may also be configured to contact the side surface.

[0018] Furthermore, a semiconductor device according to another embodiment of the present invention includes an insulating layer having a groove, and a side surface and a side surface of the groove. A first protective insulating layer is provided to cover the bottom surface, and a groove is embedded in the first protective insulating layer. and a source electrode and a gate electrode electrically connected to the oxide semiconductor layer. and a drain electrode, and a gate electrode positioned on the source electrode and the drain electrode and overlapping the oxide semiconductor layer. a gate insulating layer, a gate electrode overlapping the oxide semiconductor layer via the gate insulating layer, and a source electrode and a second protective insulating layer covering the first electrode, the drain electrode, and the gate electrode. Furthermore, the first protective insulating layer and the second protective insulating layer are made of aluminum oxide having an oxygen excess region. In the region including the aluminum film and not including the source electrode, the drain electrode, and the gate electrode, The electrodes have regions where they contact each other. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor is provided, which has high reliability. A conductor device can be provided.

[0020] According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor has good electrical conductivity. It is possible to provide a semiconductor device that achieves miniaturization while maintaining thermal properties. [Brief explanation of the drawings]

[0021] [Figure 1] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 2] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 3] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 4] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 5] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 6] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 7] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 8] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 9] 1A and 1B are a configuration example and a circuit diagram of a semiconductor device according to an embodiment; [Figure 10] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 11] 1A and 1B are diagrams illustrating band diagrams according to an embodiment. [Figure 12] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 13] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 14] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 15] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 16] 1A and 1B are a configuration example and a circuit diagram of a semiconductor device according to an embodiment; [Figure 17] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 18] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment. [Figure 19] 1 is a circuit diagram of a semiconductor device according to an embodiment. [Figure 20] 1 is a block diagram of a semiconductor device according to an embodiment; [Figure 21] FIG. 1 is a circuit diagram illustrating a memory device according to an embodiment. [Figure 22] 1. An electronic device according to an embodiment. [Figure 23] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 24] 1A and 1B are diagrams showing nanobeam electron diffraction patterns of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus; [Figure 25] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 26] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 27] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 28] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 29] 1 shows a configuration example of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0024] In each figure described in this specification, the size, layer thickness, or area of ​​each component is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0025] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limitation.

[0026] A transistor is a type of semiconductor device that controls the amplification of current and voltage, and conduction or non-conduction. In this specification, the transistor can be , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT) ) is included.

[0027] (Embodiment 1) In this embodiment, examples of the structure of a transistor and a semiconductor device according to one embodiment of the present invention will be described. An example of a manufacturing method thereof will be described with reference to the drawings.

[0028] When a transistor is manufactured using an oxide semiconductor, a carrier supply source of the oxide semiconductor One of the causes is oxygen vacancies. If there are many oxygen vacancies in the conductor, electrons are generated in the channel formation region, Normally-on transistor, increased leakage current, and threshold voltage fluctuation due to stress application This can cause poor electrical characteristics, such as shift.

[0029] In addition, in the oxide semiconductor layer, hydrogen, silicon, nitrogen, carbon, and a metal element other than the main component For example, some of the hydrogen in the oxide semiconductor layer forms a donor level, and Increase carrier density.

[0030] Therefore, in order to obtain stable electrical characteristics in a semiconductor device using an oxide semiconductor, By supplying sufficient oxygen to the oxide semiconductor layer, oxygen vacancies are reduced and impurities such as hydrogen are removed. It is necessary to take measures to reduce the concentration of substances.

[0031] In view of this, in a semiconductor device according to one embodiment of the present invention, an oxygen-excess region is formed so as to surround the oxide semiconductor layer. A protective insulating layer including an aluminum oxide film having the above structure is provided, and a channel is formed from the protective insulating layer. By supplying oxygen to the region, oxygen vacancies that may be formed in the channel formation region are compensated for. In addition, the protective insulating layer prevents oxygen from being released from the oxide semiconductor layer, thereby suppressing the formation of oxygen vacancies. do.

[0032] In one embodiment of the present invention, as a protective insulating layer for supplying oxygen to a channel formation region, In the above, an insulating layer having an aluminum oxide film containing excess oxygen is applied. The excess oxygen is, for example, oxygen contained in excess of the stoichiometric composition, or oxygen contained in excess of the stoichiometric composition when manufacturing a semiconductor device. This refers to the oxygen that can be released by heating at a temperature below the heat treatment temperature applied during the manufacturing process. As an aluminum oxide film containing excess oxygen, AlO x (x is greater than 3 / 2) Use a membrane The excess oxygen contained in the aluminum oxide film is released by heating, and the oxide Since it is possible to supply the insulating layer including such an aluminum oxide film to the semiconductor layer, By providing the layers above and below the oxide semiconductor layer, oxygen can be effectively supplied to the channel formation region. can be supplied.

[0033] The aluminum oxide film containing excess oxygen is formed by sputtering in an atmosphere containing oxygen, for example. It can be formed by film formation using a ring method or the like.

[0034] The aluminum oxide film can be used as an insulating layer such as a silicon oxide film or a silicon oxynitride film. is an insulating layer that is less permeable to oxygen and hydrogen than an oxide semiconductor layer. The aluminum oxide film is an insulating layer having a barrier property against oxygen and hydrogen. By providing an insulating layer containing It is possible to suppress the formation of hydrogen and hydrogen compounds from being mixed in.

[0035] In one embodiment of the present invention, the protective insulating layers provided above and below the oxide semiconductor layer are an oxide semiconductor layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; In other words, in the semiconductor device of one embodiment of the present invention, The semiconductor device has a configuration in which an aluminum oxide film is provided so as to enclose an oxide semiconductor layer. With this structure, the front channel side and the back channel side of the oxide semiconductor layer are In addition to the channel-side interface, oxygen desorption and / or hydrogen etc. on the side surface of the oxide semiconductor layer It is possible to suppress the inclusion of impurities and to supply oxygen. This suppresses fluctuations in the electrical characteristics of transistors in which channels are formed in the conductor layer, resulting in highly reliable semiconductors. It is possible to form a conductor device.

[0036] Therefore, in the semiconductor device of one embodiment of the present invention, oxygen vacancies in the channel formation region can be reduced. As a result, a highly reliable semiconductor is obtained that has good electrical characteristics and suppresses fluctuations in the electrical characteristics. The device can be realized.

[0037] The effect of the configuration according to one aspect of the present invention can be explained, for example, as follows.

[0038] A semiconductor device according to one embodiment of the present invention includes an insulating layer including an aluminum oxide film having excess oxygen. The aluminum oxide film is formed so as to surround the oxide semiconductor layer. An oxide semiconductor layer in which a channel is formed by heat treatment in a manufacturing process of a semiconductor device Furthermore, the aluminum oxide film has a barrier property against oxygen and hydrogen. Therefore, oxygen is released from the oxide semiconductor layer wrapped in the insulating layer including the aluminum oxide film, and In addition, it is possible to prevent impurities such as hydrogen from being mixed into the oxide semiconductor layer. The oxide semiconductor layer is supplied and the inclusion of impurities such as hydrogen is suppressed, and the oxide semiconductor layer is made highly purified and intrinsic. The oxide semiconductor layer is an oxide semiconductor layer.

[0039] In the semiconductor device, a gate insulating layer is formed between the oxide semiconductor layer and the gate insulating layer. The gate electrode is provided so as to overlap the side surface and the top surface of the channel formation region of the oxide semiconductor layer. With such a structure, the oxide semiconductor layer is preferably Since the electric field is applied from the direction perpendicular to the top surface, the threshold voltage of the transistor is effectively controlled. This allows for better control and an improved subthreshold coefficient (also called S value).

[0040] Here, in order to achieve high density (high integration) of semiconductor devices, the miniaturization of transistors is required. On the other hand, miniaturization of transistors leads to deterioration of their electrical characteristics. It is known that this is the case.

[0041] For example, in silicon transistors, shortening the channel length leads to subthreshold It is known that short channel effects such as deterioration of the stress coefficient (S value) and fluctuation of the threshold voltage occur. It is being done.

[0042] However, a transistor using an oxide semiconductor has an accumulation property in which electrons are the majority carriers. Since it is an inversion transistor, it has a short channel compared to an inversion transistor such as silicon. Drain-Induced Barrier Lowering (DIBL) occurs. A transistor using an oxide semiconductor is said to be resistant to the short-channel effect. This can also be rephrased.

[0043] Furthermore, there is a concern that reducing the channel width of a transistor may result in a decrease in on-state current. To improve flow, the active layer is thickened so that channels are formed on the sides of the active layer. However, the surface area where the channels are formed is increased, and the channel formation area is increased. The scattering of carriers at the interface between the gate insulating layer and the semiconductor region increases, so a sufficient improvement in on-current is not observed. It's not easy to get into.

[0044] However, in the transistor according to one embodiment of the present invention, the oxide film on which the channel is formed is The insulating layer includes an aluminum oxide film containing excess oxygen, and the insulating layer envelops the semiconductor layer. By this, excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, and Desorption of oxygen from the oxide semiconductor layer and inclusion of impurities such as hydrogen can be suppressed. For oxide semiconductor layers, oxygen vacancies and hydrogen are factors that generate carriers, so excess oxygen By providing an aluminum oxide film containing This can suppress possible scattering of carriers.

[0045] Therefore, even when the channel width is reduced, the thickness of the oxide semiconductor layer can be increased. By increasing the surface area overlapping with the gate electrode, the on-current can be improved sufficiently. In order to apply a sufficient electric field from the gate electrode to the side of the oxide semiconductor layer, The thickness of the oxide semiconductor layer is preferably equal to or larger than the channel width.

[0046] In addition, a metal oxide layer is provided in contact with the oxide semiconductor layer and includes at least one of the metal elements of the oxide semiconductor layer. By providing an oxide layer made of a material such as silicon dioxide, the scattering of carriers can be further suppressed. Therefore, it is effective.

[0047] Note that when the channel length and the channel width of a transistor are reduced, a resist mask is used. The end faces of wiring, semiconductor layers, etc. that are processed by this method may be rounded (have curved surfaces). A thin insulating layer (for example, a gate insulating layer) is formed so as to cover the oxide semiconductor layer. If the coating is too thick, it may cause a defect in the shape due to a decrease in coverage, and stable electrical characteristics may not be obtained. However, since the end face of the oxide semiconductor layer has a curved surface, the insulating film provided on the oxide semiconductor layer can be easily formed. This is preferable because it can improve the coverage of the layer.

[0048] In addition, part of the hydrogen in the oxide semiconductor layer is captured by oxygen vacancies, causing the oxide semiconductor layer to become an n-type Therefore, the Fermi level (Ef) approaches the bottom of the conduction band (Ec). The oxide semiconductor layer included in the On the other hand, if the oxide semiconductor layer is made intrinsic or substantially intrinsic, The Fermi energy of the oxide semiconductor layer is the mid-gap (energy In this case, the oxide semiconductor There is concern that a decrease in the number of carriers contained in the semiconductor layer may result in a decrease in field-effect mobility.

[0049] However, in the transistor of one embodiment of the present invention, the oxide semiconductor layer is In addition to the gate field from the top, a gate field from the side is applied. The gate electric field is applied to the entire semiconductor layer, and the current flows through the bulk of the oxide semiconductor layer. This allows for the suppression of fluctuations in electrical characteristics through high-purity intrinsic materials, while also reducing the This makes it possible to improve the field effect mobility of the transistor.

[0050] More specifically, for example, the following configuration can be adopted.

[0051] [Configuration example 1] FIG. 1A is a schematic top view of a transistor 100 illustrated in this configuration example. (B) and (C) are schematic cross-sectional views taken along the cutting lines AB and CD in Figure 1(A), respectively. In FIG. 1(A), some components are not shown for clarity.

[0052] The transistor 100 is provided on a substrate 101, and includes an island-shaped semiconductor layer 102 and a semiconductor layer a pair of electrodes 103 electrically connected to the semiconductor layer 102; a gate insulating layer 104 overlapping the semiconductor layer 102; and a semiconductor layer 102 located on the gate insulating layer 104. and a gate electrode 105 overlapping the gate electrode 104.

[0053] In addition, a first protective insulating layer 111 is provided between the substrate 101 and the semiconductor layer 102. In addition, a second protective insulating layer 112 is formed on the pair of electrodes 103 and the gate electrode 105. Furthermore, the first protective insulating layer 111 and the second protective insulating layer 112 are formed as a pair of The electrode 103 and the gate electrode 105 are provided in contact with each other in the region where they are not provided. It is being done.

[0054] The semiconductor layer 102 includes an oxide semiconductor. It is preferable that the alloy contains aluminum (In) or zinc (Zn). Alternatively, the alloy contains both In and Zn. More preferably, an In-M-Zn oxide (wherein M is Al, Ti, Ga, This includes oxides of metals such as Ge, Y, Zr, Sn, La, Ce or Hf.

[0055] One of the pair of electrodes 103 functions as a source electrode of the transistor 100, and the other In FIG. 1B, the pair of electrodes 103 are semiconductor The conductive layer 102 is provided in contact with the upper and side surfaces thereof.

[0056] The gate electrode 105 is connected to the upper and side surfaces of the semiconductor layer 102 via the gate insulating layer 104. It is set up to surround it.

[0057] Here, the channel length (L length) of a transistor is the distance between the opposing source and drain The channel width (W length) of a transistor is defined as the width in the direction perpendicular to the channel length direction. The width of the semiconductor layer in the transistor is Depending on the shape of the electrode and semiconductor layer, the channel length and width may vary depending on the region (position). In that case, the average or minimum value of these may be used as the transition It can be applied as the channel length or channel width of the gate.

[0058] The gate electrode 105 is provided so as to surround the side surfaces of the semiconductor layer 102. The side surface of the semiconductor layer 102 can also function as a channel forming region. The thickness of the semiconductor layer 102 is set to 0.05 times or more and 20 times or less, preferably, It is preferable that the ratio is 0.1 to 10 times. Even when the channel width is reduced, the decrease in on-current is suppressed, enabling finer and faster operation. This makes it possible to realize a transistor that can

[0059] In this way, the gate electrode surrounds the top and side surfaces of the semiconductor layer of the transistor. By actively using the channel formed near the side of the semiconductor layer, the on-state current can be reduced. The transistor structure with enhanced current is called the Surrounded Channel (SC) This can also be called a channel structure.

[0060] The first protective insulating layer 111 and the second protective insulating layer 112 have an oxygen excess region, and An insulating material that has the function of suppressing oxygen diffusion (also known as blocking properties against oxygen) For example, the first protective insulating layer 111 and the second protective insulating layer 112 can be As the insulating layer, a layer containing an aluminum oxide film can be used. , aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, nitrite oxide Yttrium nitride, hafnium oxide, hafnium oxynitride, yttria stabilized zirconia ( A film containing an insulating material containing oxygen, such as YSZ, can also be applied.

[0061] The insulating film having an oxygen excess region is, for example, an insulating film having an oxygen content exceeding the stoichiometric composition. It is preferable to use an oxide insulating film containing oxygen in an amount of 1000 to 15000 times lower than that containing oxygen in the stoichiometric composition. When an oxide insulating film contains a large amount of oxygen, some of the oxygen is released by heating.

[0062] The first protective insulating layer 111 and the second protective insulating layer 112 have an extremely low hydrogen content. For example, secondary ion mass spectroscopy (SIMS) is used. Hydrogen detected by Secondary Ion Mass Spectrometry The content of is 5×10 21 atoms / cm 3 Less than 2 x 10 21 atoms / cm 3 less than 1×10 21 atoms / cm 3 Absolute value including the area where Edge materials can be used.

[0063] The insulating material used for the first protective insulating layer 111 and the second protective insulating layer 112 is Therefore, it is also possible to use a material in which silicon oxide is contained in the above oxide. Silicon in the range of 0.1% by weight to 30% by weight (e.g., 5% by weight, 10% by weight, etc.) Aluminum oxide containing silicon oxide within this range can be used. By doing so, the blocking property against oxygen is not reduced and the compound is desorbed by heating. The amount of oxygen can be increased and the stress in the film can be reduced.

[0064] [About each component] Each component of the transistor 100 will now be described.

[0065] [Semiconductor layer] The oxide semiconductor contained in the semiconductor layer 102 has a wider band gap than silicon. When an oxide semiconductor having a low carrier density is used, the transistor can be turned off. This is preferable because it allows for a reduction in current.

[0066] The crystallinity of the semiconductor used for the semiconductor layer 102 may be an amorphous semiconductor or a crystalline semiconductor. Semiconductors (microcrystalline semiconductors, polycrystalline semiconductors, single-crystal semiconductors, or semiconductors that have crystalline parts in part or entirely) The semiconductor layer 102 may be formed of a crystalline semiconductor. This is preferable because it suppresses the deterioration of the transistor characteristics.

[0067] In particular, the semiconductor layer 102 has a plurality of crystal portions, and the crystal portions have a c-axis that is the same as that of the semiconductor layer 10 2 (the upper surface of the first protective insulating layer 111 in FIG. 1) or the upper surface of the semiconductor layer 102. It is preferable to use a layer that is oriented approximately perpendicular to the crystal grains and has no grain boundaries between adjacent crystal portions. It's nice.

[0068] By using such a material for the semiconductor layer 102, fluctuations in electrical characteristics are suppressed, A highly reliable transistor 100 can be realized.

[0069] The semiconductor layer 102 may have a single layer structure or a stacked structure of two or more layers. In this case, two or more oxide semiconductor films having different compositions may be combined.

[0070] The preferred form of the oxide semiconductor applicable to the semiconductor layer 102 and the method for forming it are as follows: This will be explained in detail in a later embodiment.

[0071] 〔substrate〕 There is no particular restriction on the material of the substrate 101, but it should be strong enough to withstand the heat treatment during the process. Use a material with high heat resistance. For example, a glass substrate, a ceramic substrate, a quartz substrate, a silicon substrate, A substrate such as a ferrite substrate or an yttria-stabilized zirconia (YSZ) substrate is used as the substrate 101. In addition, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate such as silicon or silicon carbide may be used. Substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can also be used. can.

[0072] In addition, various semiconductor substrates and SOI substrates on which semiconductor elements are provided are referred to as substrate 101. In this case, the transistor 100 may be mounted on the substrate 101 via an interlayer insulating layer. At this time, the transistor 10 is formed by the connection electrode embedded in the interlayer insulating layer. At least one of the pair of electrodes 103 and the gate electrode 105 of the semiconductor element 100 is electrically connected to the semiconductor element 100. The transistor 100 may be provided over a semiconductor element with an interlayer insulating layer interposed therebetween. By providing the transistor 100, the increase in area due to the addition of the transistor 100 can be suppressed. can be done.

[0073] [Gate electrode] The gate electrode 105 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above metals, or It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. One or more metals selected from the above may be used. Semiconductors such as doped polycrystalline silicon, silicides such as nickel silicide, The gate electrode 105 may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film; a two-layer structure in which a titanium film is laminated on a titanium nitride film; Two-layer structure with tungsten film stacked, tantalum nitride film or tungsten nitride film with tantalum A two-layer structure consisting of a titanium film and an aluminum film laminated on top of the titanium film. There are also three-layer structures, such as aluminum with a titanium film on top. , selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium An alloy film made of a combination of one or more metals, or a nitride film of these metals may also be used.

[0074] The gate electrode 105 is made of indium tin oxide, indium containing tungsten oxide, or the like. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide may also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0075] In addition, an In—Ga—Zn-based oxynitride is formed between the gate electrode 105 and the gate insulating layer 104. Semiconductor film, In-Sn oxynitride semiconductor film, In-Ga oxynitride semiconductor film, In-Zn Sn-based oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film ( These films may have a resistance of 5 eV or more, preferably 5.5 eV or more. Since the work function is greater than or equal to the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the conductor can be shifted to the positive side, so-called normal For example, an In-Ga-Zn oxynitride semiconductor When a conductive film is used, the nitrogen concentration is at least higher than that of the semiconductor layer 102, specifically, 7 atomic %. The above-mentioned In-Ga-Zn-based oxynitride semiconductor film is used.

[0076] [Gate insulating layer] The gate insulating layer 104 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminated layer or a single layer.

[0077] The gate insulating layer 104 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium Luminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. The use of -k materials can reduce gate leakage of transistors.

[0078] [Pair of electrodes] The pair of electrodes 103 is made of a conductive material such as aluminum, titanium, chromium, nickel, or copper. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten The metal or alloy containing it as the main component is used as a single layer or laminated structure. For example, a single layer structure of aluminum film containing silicon, titanium on aluminum film, Two-layer structure with copper film on titanium film, two-layer structure with copper film on titanium film, and titanium film on tungsten film Two-layer structure with a titanium film laminated on top, a copper film laminated on top of a copper-magnesium-aluminum alloy film Two-layer structure: titanium film or titanium nitride film and a layer on top of the titanium film or titanium nitride film An aluminum or copper film is laminated, and then a titanium or titanium nitride film is formed on top of that. The three-layer structure is a molybdenum film or molybdenum nitride film and a molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on the molybdenum film, and a molybdenum film is then formed on top of that. Alternatively, there is a three-layer structure in which a molybdenum nitride film is formed. Alternatively, a transparent conductive material containing zinc oxide may be used.

[0079] The above is a description of an example of the configuration of the transistor 100 and each of its components.

[0080] [Production method example 1] An example of a method for manufacturing the transistor 100 illustrated in FIG. 1 will be described below with reference to the drawings. 2A to 2C are schematic cross-sectional views illustrating each step in the fabrication method exemplified below.

[0081] [Formation of first protective insulating layer] First, a first protective insulating layer 111 is formed on a substrate 101 (FIG. 2(A)).

[0082] The first protective insulating layer 111 is formed by, for example, sputtering in an atmosphere containing oxygen. In addition, the film can be formed by chemical vapor deposition (CVD) in an atmosphere containing oxygen. al Vapor Deposition) method, MBE (Molecular Beam) Epitaxy) method, ALD (Atomic Layer Deposition) method or by PLD (Pulsed Laser Deposition) method, etc. That's fine.

[0083] For example, when an aluminum oxide film is used as the first protective insulating layer 111, the oxide Using aluminum as a sputtering target, film formation can be performed in an atmosphere containing oxygen. The deposition gas may contain an inert gas such as a rare gas. The oxygen flow rate is set to 20% or more, preferably 30% or more, more preferably 40% or more of the total flow rate. It is preferable that the reactivity of aluminum be as high as possible. The aluminum oxide film may be formed by sputtering. When used as a sputtering target, more oxygen can be contained in the film. Therefore, it is preferable.

[0084] [Formation of Semiconductor Layer] Next, a semiconductor film is formed on the first protective insulating layer 111. A resist mask is formed on the semiconductor film by a method such as etching, and unnecessary portions of the semiconductor film are etched. After that, the resist mask is removed, and the island-shaped semiconductor layer 102 can be formed (FIG. 2(B)).

[0085] Semiconductor films are formed by sputtering, CVD, MBE, ALD, or PLD. Alternatively, a liquid material such as a sol-gel method, a spray method, or a mist method can be used. A thin film formation technique using a material can also be used. As the sputtering method, RF sputtering, DC sputtering, etc. In particular, the use of a sputtering method, AC sputtering method, etc. can be used to prevent the generation of dust during film formation. DC sputtering is used because it can reduce the thickness and make the film thickness distribution uniform. is preferred.

[0086] After the semiconductor film is formed, heat treatment may be performed. Preferably, the temperature is 300°C or higher and 500°C or lower, and the inert gas atmosphere and the oxidizing gas are mixed for 10 minutes. The heat treatment can be carried out in an atmosphere containing at least ppm or under reduced pressure. After heat treatment in an oxidizing gas atmosphere, an oxidizing gas of 10 ppm or less is added to compensate for the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing the above-mentioned. Alternatively, oxygen is supplied to the semiconductor layer 102, and the oxide semiconductor included in the semiconductor layer 102 The heat treatment can reduce oxygen vacancies. This may be performed after the island-shaped semiconductor layer 102 is formed by processing the semiconductor film.

[0087] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6nm), H-line (wavelength 405nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Alternatively, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultraviolet) or X-rays may also be used. Instead of light used for exposure, electron beams can also be used. The use of an electron beam is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0088] Here, as shown in FIG. 2B, the first protective insulating layer 111 is removed during etching of the semiconductor film. In some cases, a part of the semiconductor layer 102 is etched away and thinned in the area that does not overlap with the semiconductor layer 102. The upper surface of the first protective insulating layer 111 around the semiconductor layer 102 is higher than the lower surface of the conductor layer 102. By lowering the surface, the gate electrode 105 to be formed later can be formed on the side surface of the semiconductor layer 102. As a result, the gate electrode can be formed so as to surround the lower part of the side surface of the semiconductor layer 102. The on-state current of the transistor 100 is increased by applying a sufficient electric field to the gate electrode 105. 26, the gate electrode 10 is located closer to the bottom surface of the semiconductor layer 102 than the bottom surface of the semiconductor layer 102. If a part of the first protective insulating layer 111 is etched so that the bottom surface of the insulating layer 5 becomes lower, the thickness of the insulating layer 5 becomes smaller. This is preferable because the on-current of the transistor 100 can be increased.

[0089] In addition, depending on the material used for the first protective insulating layer 111 and the etching conditions of the semiconductor film, In some cases, the first protective insulating layer 111 is not etched. This is preferable because it improves the coverage of the film formed on the substrate 2.

[0090] As shown in FIG. 2B, the upper corners of the semiconductor layer 102 are gently curved. In particular, when the semiconductor layer 102 is finely processed, By forming the semiconductor layer 102 into such a shape, Since the coverage of the film provided on the upper side of the transistor 100 is improved, the variation in the electrical characteristics of the transistor 100 is reduced. This is preferable because it can suppress noise and fluctuations.

[0091] [Formation of a pair of electrodes] Subsequently, a conductive film is formed on the first protective insulating layer 111 and the semiconductor layer 102. A resist mask is formed on the conductive film by photolithography or the like, and unnecessary portions of the conductive film are removed. The resist mask is then removed, revealing a pair of An electrode 103 can be formed (FIG. 2(C)).

[0092] The conductive film can be formed by, for example, sputtering, vapor deposition, CVD, etc. do.

[0093] Here, as shown in FIG. 2C, when the conductive film is etched, the upper part of the semiconductor layer 102 is A part of the film is etched, and the part that does not overlap with the pair of electrodes 103 may become thin. Therefore, the thickness of the semiconductor film that will become the semiconductor layer 102 must be predetermined in consideration of the etching depth. It is preferable to form it thicker.

[0094] Although not shown in the figure, the first protection layer is also used during etching of the conductive film in the same manner as described above. A part of the protective insulating layer 111 may be etched and thinned.

[0095] [Formation of gate insulating layer and gate electrode] Subsequently, an insulating film is formed on the semiconductor layer 102, the pair of electrodes 103, and the first protective insulating layer 111. Then, a conductive film is formed on the insulating film. A resist mask is formed on the conductive film using a resist mask, and unnecessary portions of the conductive film and the insulating film are etched. Thereafter, the resist mask is removed, thereby leaving the gate electrode 105 and Then, a gate insulating layer 104 can be formed (FIG. 2(D)).

[0096] The insulating film that becomes the gate insulating layer 104 can be formed by a sputtering method, a CVD method, an MBE method, or an ALD method. In particular, the insulating film can be formed by a CVD method, preferably a PLD method. Preferably, the film is formed by plasma CVD, which can improve the coating properties. Desirable.

[0097] The conductive film that becomes the gate electrode 105 can be formed by, for example, sputtering, vapor deposition, or CVD. The film can be formed by the following methods.

[0098] In this case, the gate insulating layer 104 is etched at the same time as the gate electrode 105 is formed. When the gate insulating layer 104 is processed to have the same top surface shape as the gate electrode 105, In this case, the gate insulating layer 104 extends beyond the gate electrode 105. Each of them may be processed individually to form the top surface shape. As exposure masks used in the lithography method, gray tone masks and half tone masks are used. The use of a multi-tone mask is preferable because it simplifies the process.

[0099] [Formation of second protective insulating layer] Next, the first protective insulating layer 111, the pair of electrodes 103, the gate insulating layer 104, and the gate insulating layer 106 are formed. A second protective insulating layer 112 is formed on the port electrode 105 (FIG. 2(E)).

[0100] The second protective insulating layer 112 is formed by the same method as the first protective insulating layer 111. can be done.

[0101] Here, the second protective insulating layer 112 is provided with a pair of electrodes 103 and a gate electrode 105. The insulating layer 111 is provided so as to be in contact with the first insulating layer 111 in the region where the insulating layer 111 is not provided. The semiconductor layer 102 is surrounded by the first protective insulating layer 111 and the second protective insulating layer 112. can be done.

[0102] Through the above steps, the transistor 100 can be manufactured.

[0103] [Heat Treatment] After the second protective insulating layer 112 is formed, heat treatment may be performed. Oxygen is supplied to the semiconductor layer 102 from the protective insulating layer 111 and the second protective insulating layer 112. This can reduce oxygen vacancies in the semiconductor layer 102. The insulating layer 111 and the second protective insulating layer 112 prevent oxygen from being released from the semiconductor layer 102. This can suppress the formation of oxygen vacancies in the semiconductor layer 102.

[0104] The above is a description of an example of a manufacturing process of the transistor 100.

[0105] [Modification of Configuration Example 1] Hereinafter, a transistor having a configuration partially different from that of the transistor illustrated in the above Configuration Example 1 will be described. The following describes an example of the configuration. Note that explanations of the same parts as above will be omitted, and only differences will be explained. In addition, even if the position or shape of the components differs, their functions will be explained in detail. In cases where the components are the same, the same reference numerals are used and the description thereof may be omitted.

[0106] [Variation 1] 3A and 3B are schematic cross-sectional views of the transistors exemplified below. The schematic diagram can be referred to in FIG. 1(A). The transistor shown in FIG. 3 mainly includes a semiconductor layer 102 and a It differs in that it has an insulating layer 106 between it and the first protective insulating layer 111 .

[0107] The insulating layer 106 provided under the semiconductor layer 102 is made of a material that releases oxygen when heated. The insulating layer 106 is preferably made of an oxide insulating material. Therefore, the heat generated during the heat treatment in the manufacturing process of the transistors causes more oxygen to be absorbed. It is possible to supply the insulating layer 106 and the semiconductor layer 102 with the same. The structure is surrounded by the first protective insulating layer 111 and the second protective insulating layer 112. The oxygen released from the insulating layer 106 flows to the outside (the substrate 101 side or the second protective insulating layer 112). Therefore, oxygen is more effectively supplied to the semiconductor layer 102. This can be done.

[0108] The insulating layer 106 may also be provided so as to cover the upper surface of the first protective insulating layer 111. However, as shown in FIG. 3, the semiconductor layer 102 and the insulating layer 106 are formed so that their top surfaces are substantially the same. It is preferable that the same resist mask is used for processing the first and second electrodes. As a result, the first protective insulating layer 111 and the second protective insulating layer 112 are in contact with the gate electrode 105 and Since the pair of electrodes 103 are in contact with each other in an area where they are not provided, the oxygen diffusion path is blocked and the Oxygen can be supplied to the semiconductor layer 102 .

[0109] The insulating layer 106 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable to use an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. When the film is heated, some oxygen is desorbed. The oxide insulating film containing In the ion spectroscopy analysis, the amount of oxygen released in terms of oxygen atoms was 1 .0×10 18 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 The oxide insulating film is as described above.

[0110] As the insulating layer 106, a silicon oxide film or a silicon oxynitride film is formed by plasma CVD. When forming the silicon nitride film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and thiazolinone. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and Nitric oxide, etc.

[0111] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180°C or higher. The temperature is kept at 260°C or lower, more preferably 200°C or higher and 240°C or lower, and raw material gas is introduced into the treatment chamber. By introducing gas, the pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably The pressure is between 100 Pa and 200 Pa, and the electrode installed in the processing chamber is set to 0.17 W / cm 2 Below Upper 0.5W / cm 2 or less, more preferably 0.25 W / cm 2 More than 0.35W / cm 2 Silicon oxide film or silicon oxynitride film is formed under the following conditions of supplying high frequency power. Complete.

[0112] As a film formation condition, high frequency power of the above power density is supplied in a processing chamber at the above pressure. This increases the decomposition efficiency of the source gas in the plasma, increases the number of oxygen radicals, and As a result, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is above this level, the bonding strength between silicon and oxygen is weak, so heating As a result, the oxygen content is greater than the stoichiometric ratio. In this case, an oxide insulating film from which part of oxygen is released by heating can be formed.

[0113] [Variation 2] FIG. 4 shows an example in which a capacitor 120 is formed adjacent to a transistor 100. In FIG.

[0114] The capacitor 120 is formed by connecting one of the pair of electrodes 103 of the transistor 100 and the gate electrode 10 5 is processed to form an electrode 125. The same conductive film as the gate insulating layer 104 is then formed between the electrode 125 and the gate insulating layer 104. The insulating film is processed to form a dielectric layer 124.

[0115] In this way, the capacitor element 120 is formed by processing the film used for manufacturing the transistor 100. By doing so, the capacitor 120 can be formed simultaneously with the transistor 100 without increasing the number of steps. It can be made.

[0116] 4, one of the pair of electrodes 103 of the transistor 100 is connected to the capacitor 120. Although the structure in which the capacitor is used as one electrode is shown, the present invention is not limited to this. As the electrodes 103 of the transistor 100, a different conductive film is formed by processing the same conductive film. Alternatively, the gate electrode 105, the electrode 125, and the gate insulating layer 1 may be formed of a material other than the insulating layer. At least one of the insulating layer 04 and the dielectric layer 124 may be formed as a continuous, integrated body and used in common. .

[0117] Here, the materials used for the insulating films that form the gate insulating layer 104 and the dielectric layer 124 are Aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide It is preferable to use a high dielectric constant material such as silicon dioxide, strontium titanate, or barium titanate. In addition, these materials may contain lanthanum, aluminum, yttrium, or tungsten. Materials containing metals such as silicon and oxides of these metals may also be used. It is also possible to use a laminate of films containing the same.

[0118] The insulating film is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. It is preferable to use such an insulating film. The heat generated during the heating process or the like supplies oxygen from the gate insulating layer 104 to the semiconductor layer 102. can be provided.

[0119] The above is a description of the modified example.

[0120] [Configuration example 2] Below, we will explain examples of transistor configurations that are partially different from the above Configuration Example 1, etc. Note that explanations of parts that overlap with those above may be omitted.

[0121] FIG. 5A is a schematic top view of a transistor 200 illustrated in this configuration example. (B) and (C) are schematic cross-sectional views taken along the cutting lines EF and GH in FIG. 5(A), respectively. In FIG. 5(A), some components are not shown for clarity.

[0122] The transistor 200 includes an insulating layer 207 having a groove formed on a substrate 201 and an insulating a semiconductor layer 202 provided on the layer 207 so as to fill the grooves; a pair of electrodes 203 provided on the semiconductor layer 202 and electrically connected to the semiconductor layer 202; a gate insulating layer 204 located on the semiconductor layer 203 and overlapping the semiconductor layer 202; and a gate electrode 205 positioned above and overlapping the semiconductor layer 202 .

[0123] Further, below the semiconductor layer 202, a layer is formed so as to cover the side and bottom surfaces of the groove of the insulating layer 207. The first protective insulating layer 211 is provided on the insulating layer 212. The first protective insulating layer 211 is formed as shown in FIG. As shown, the insulating layer 207 is provided so as to cover the upper surface of the region where no groove is provided. In addition, a second protective layer is preferably formed to cover the pair of electrodes 203 and the gate electrode 205. An insulating layer 212 is provided. Furthermore, a first protective insulating layer 211 and a second protective insulating layer 212 are provided. 2 means that the pair of electrodes 203 and the gate electrode 205 are not provided in the region where they are mutually connected. It is located adjacent to the

[0124] The semiconductor layer 202, the pair of electrodes 203, the gate insulating layer 204, the gate electrode 205, etc. The semiconductor layer 102, the pair of electrodes 103, the gate insulating layer 104, and the gate electrode 106 in the first configuration example are The same material as the protective insulating layer 211 and the protective insulating layer 105 can be used. The second protective insulating layer 212 is the same as the first protective insulating layer 111 and the second protective insulating layer 112 in the first configuration example. The same material as that of the insulating layer 112 can be used.

[0125] The first protective insulating layer 211 covers the side and bottom surfaces of the grooves provided in the insulating layer 207. Further, a semiconductor layer 202 is provided so as to be embedded in the groove. The side and bottom surfaces of the protective insulating layer 202 are surrounded by the first protective insulating layer 211. Therefore, the diffusion of impurities such as hydrogen from the insulating layer 207 to the semiconductor layer 202 is suppressed. In both cases, oxygen is prevented from being released from the semiconductor layer 202 toward the insulating layer 207. will be done.

[0126] In addition, the thickness of the semiconductor layer 202 can be increased by adjusting the depth of the grooves. , the on-current of the transistor 200 is increased, and the breakdown voltage between the source and drain is improved. For example, when a thick semiconductor layer is formed on a flat surface, the It becomes difficult for the film to cover the semiconductor layer, and the film may be divided or low density may be present in the film. On the other hand, in this configuration example, the semiconductor is formed so as to fill the grooves. The conductor layer 202 is provided, and the height of the upper surface of the conductor layer 202 and the height of the upper surface of the first protective insulating layer 211 are approximately equal to each other. Therefore, it does not adversely affect the coverage of the film provided on the upper layer. The semiconductor layer 202 can be formed thick without affecting the thickness.

[0127] The above is a description of an example of the configuration of the transistor 200.

[0128] [Production method example 2] An example of a method for manufacturing the transistor 200 illustrated in FIG. 5 will be described below with reference to the drawings. 6A to 6C are schematic cross-sectional views illustrating each step in the fabrication method exemplified below.

[0129] [Formation of insulating layer] First, an insulating layer 207 is formed on a substrate 201 .

[0130] The insulating layer 207 can be formed by a sputtering method, a CVD method, a vapor deposition method, or the like. do.

[0131] The insulating layer 207 may be made of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or silicon nitride. Silicon, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, Insulating materials such as yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride Edge materials can be used.

[0132] Alternatively, the insulating layer 207 may be formed by laminating films made of different insulating materials. By forming the layer 207 in a laminated structure, the film provided below can be prevented from being damaged during subsequent formation of the grooves. It can function as an etching stopper.

[0133] [Formation of Groove] Next, a resist mask is formed on the insulating layer 207 using a photolithography method or the like. Then, the upper part of the insulating layer 207 is removed by etching. As a result, a groove can be formed in the insulating layer 207.

[0134] Here, as described above, by making the insulating layer 207 a multi-layer structure made of different materials, Furthermore, the underlying layer can be easily etched. By using it as a topper, the bottom surface of the groove can be made flat, which is preferable.

[0135] In addition, when the depth of the groove is made deep, the resist mask disappears during etching. In that case, the insulating layer 207 may be etched away. a thin film made of a material that is difficult to separate (i.e., a material that has a high selectivity for the insulating layer 207 relative to the thin film) The thin film is then etched using a resist mask. The upper part of the insulating layer 207 may be etched using the mask to form a groove. If the thin film used as the hard mask is insulating, the hard mask is removed after the groove is formed. It may be left as it is.

[0136] [Formation of first protective insulating layer] Next, a first protective insulating layer 21 is formed on the insulating layer 207 so as to cover the side and bottom surfaces of the groove. Form 1 (Figure 6(A)).

[0137] The first protective insulating layer 211 was formed in the same manner as the first protective insulating layer 111 in the first manufacturing method. Formed in the same way.

[0138] [Formation of Semiconductor Layer] Subsequently, a semiconductor film is formed on the first protective insulating layer 211. The grooves are completely covered with the semiconductor film. When the semiconductor film is completely embedded, the height of the upper surface of the portion overlapping the groove portion of the semiconductor film is set to be equal to or greater than the height of the first protective insulating layer. It is preferable to form the film so that the height is equal to or greater than the height of the portion of 211 that does not overlap with the groove portion. It's nice.

[0139] The semiconductor film can be formed in the same manner as in the above-mentioned Manufacturing Method Example 1.

[0140] After the semiconductor film is formed, heat treatment may be performed. The heat treatment is performed in the same manner as in the above-described Example 1 of the manufacturing method. By the heat treatment, the semiconductor film (or the semiconductor Oxygen is supplied to the oxide semiconductor layer 202, and oxygen vacancies in the oxide semiconductor contained in the semiconductor layer 202 are reduced. The heat treatment may be performed immediately after the semiconductor film is formed, or after the semiconductor film is heated. This may be performed after the island-shaped semiconductor layer 202 is formed by the process.

[0141] Subsequently, a planarization process is performed so that the upper surface of the semiconductor film does not overlap the groove portion of the first protective insulating layer 211. By processing the semiconductor so that it matches the top surface of the missing part, the island-shaped semiconductor embedded in the groove is Layer 202 can be formed (FIG. 6(B)).

[0142] As a planarization process, for example, CMP (Chemical Mechanical Polishing) Polishing or etching may be used.

[0143] Here, aluminum oxide or the like is used as the first protective insulating layer 211, and a planarization process is performed. When a polishing process such as CMP is used, the first protective insulating layer 211 acts as an etching stopper. Therefore, the thickness of the semiconductor layer 202 can be reduced by the planarization process. This can prevent the thickness from increasing, and further reduce the variation in thickness.

[0144] [Formation of a pair of electrodes] Subsequently, a conductive film is formed on the first protective insulating layer 211 and the semiconductor layer 202. A resist mask is formed on the conductive film by photolithography or the like, and unnecessary portions of the conductive film are removed. The resist mask is then removed, revealing a pair of An electrode 203 can be formed (FIG. 6(C)).

[0145] The conductive film can be formed by, for example, sputtering, vapor deposition, CVD, etc. do.

[0146] Here, as shown in FIG. 6(C), when the conductive film is etched, the upper part of the semiconductor layer 202 A part of the film is etched, and the part that does not overlap with the pair of electrodes 203 may become thin. Therefore, the thickness of the semiconductor film that becomes the semiconductor layer 202 (i.e., the depth of the groove) is determined by etching. It is preferable to form the hole thick in advance, taking into consideration the depth to be cut.

[0147] Although not shown in the figure, a part of the first protective insulating layer 211 is removed during etching of the conductive film. The film may also be etched and thinned.

[0148] [Formation of gate insulating layer and gate electrode] Subsequently, an insulating film is formed on the semiconductor layer 202, the pair of electrodes 203, and the first protective insulating layer 211. Then, a conductive film is formed on the insulating film. A resist mask is formed on the conductive film, and unnecessary portions of the conductive film and the insulating film are etched. Thereafter, the resist mask is removed, thereby removing the gate electrode 205 and A gate insulating layer 204 can be formed (FIG. 6(D)).

[0149] The insulating film that becomes the gate insulating layer 204 and the conductive film that becomes the gate electrode 205 are formed by the above-mentioned method. It can be formed in the same manner as in 1.

[0150] In this case, the gate insulating layer 204 is etched at the same time as the gate electrode 205 is formed. When the gate insulating layer 204 is processed to have the same top surface shape as the gate electrode 205, The gate insulating layer 204 extends beyond the gate electrode 205. Each of them may be processed individually to form the top surface shape. As exposure masks used in the lithography method, gray tone masks and half tone masks are used. The use of a multi-tone mask is preferable because it simplifies the process.

[0151] [Formation of second protective insulating layer] Next, a first protective insulating layer 211, a pair of electrodes 203, a gate insulating layer 204, and a gate insulating layer 206 are formed. A second protective insulating layer 212 is formed on the port electrode 205 (FIG. 6(E)).

[0152] The second protective insulating layer 212 is formed by the same method as the first protective insulating layer 211. can be done.

[0153] Here, the second protective insulating layer 212 is provided with a pair of electrodes 203 and a gate electrode 205. The insulating layer 211 is provided so as to be in contact with the first insulating layer 211 in the region where the insulating layer 211 is not provided. The semiconductor layer 202 is surrounded by the first protective insulating layer 211 and the second protective insulating layer 212. can be done.

[0154] Through the above steps, the transistor 200 can be manufactured.

[0155] [Heat Treatment] After the second protective insulating layer 212 is formed, heat treatment may be performed. Oxygen is supplied to the semiconductor layer 202 from the protective insulating layer 211 and the second protective insulating layer 212. This can reduce oxygen vacancies in the semiconductor layer 202. The insulating layer 211 and the second protective insulating layer 212 prevent oxygen from being released from the semiconductor layer 202. This can suppress the formation of oxygen vacancies in the semiconductor layer 202.

[0156] This completes the description of the example manufacturing process of the transistor 200.

[0157] [Modification of Configuration Example 2] Hereinafter, a transistor having a configuration partially different from that of the transistor illustrated in the above Configuration Example 2 will be described. The following describes an example of the configuration. Note that explanations of the same parts as above will be omitted, and only differences will be explained. In addition, even if the position or shape of the components differs, their functions will be explained in detail. In cases where the components are the same, the same reference numerals are used and the description thereof may be omitted.

[0158] [Variation 1] 7A and 7B are schematic cross-sectional views of the transistors exemplified below. The schematic diagram can be seen in FIG. 5A. The transistor shown in FIG. 7 mainly comprises a semiconductor layer 202 and a It differs in that it has an insulating layer 206 between it and the first protective insulating layer 211 .

[0159] In the grooves formed in the insulating layer 207, the insulating layer 206 is The insulating layer 206 is provided to cover the side and top surfaces of the semiconductor layer 202. It is provided to cover the top and bottom surfaces.

[0160] The insulating layer 206 provided under the semiconductor layer 202 is made of a material that releases oxygen when heated. The insulating layer 206 is preferably made of an oxide insulating material. Therefore, the heat generated during the heat treatment in the manufacturing process of the transistors causes more oxygen to be absorbed. It is possible to supply the insulating layer 206 and the semiconductor layer 202. The structure is surrounded by the first protective insulating layer 211 and the second protective insulating layer 212. The oxygen released from the insulating layer 206 flows to the outside (the insulating layer 207 side or the second protective insulating layer 212 Therefore, oxygen is more effectively supplied to the semiconductor layer 202. It is possible.

[0161] The insulating layer 206 also covers the upper surface of the first protective insulating layer 211 in an area that does not overlap with the groove portion. However, it is processed so that it is provided inside the groove by a flattening process. With this configuration, the first protective insulating layer 211 and the second The protective insulating layer 212 is connected to the gate electrode 205 and the pair of electrodes 203 in a region where the gate electrode 205 and the pair of electrodes 203 are not provided. Therefore, the diffusion path of oxygen is blocked, and oxygen can be effectively supplied to the semiconductor layer 202. Cut.

[0162] The insulating layer 206, like the insulating layer 106, contains more oxygen than the stoichiometric composition. It is preferable to use an oxide insulating film containing oxygen.

[0163] [Variation 2] FIG. 8 shows an example in which a capacitor 220 is formed adjacent to a transistor 200 .

[0164] The capacitor 220 is formed by connecting one of the pair of electrodes 203 of the transistor 200 and the gate electrode 20 5 is processed to form an electrode 225. The same conductive film as the gate insulating layer 204 is then formed between the electrode 225 and the gate insulating layer 204. The insulating film is processed to form a dielectric layer 224.

[0165] In this way, the capacitor element 220 is formed by processing the film used to manufacture the transistor 200. By doing so, the capacitor 220 can be formed simultaneously with the transistor 200 without increasing the number of steps. It can be made.

[0166] 8, one of the pair of electrodes 203 of the transistor 200 is connected to the capacitor 220. However, the present invention is not limited to this. The pair of electrodes 203 of the transistor 200 are formed by processing the same conductive film. In addition, the gate electrode 205 and the electrode 225, as well as the gate insulating layer 204 and At least one of the dielectric layers 224 may be made into a continuous, integral body and used in common.

[0167] Here, the materials used for the insulating films that constitute the gate insulating layer 204 and the dielectric layer 224 are Aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide It is preferable to use a high dielectric constant material such as silicon dioxide, strontium titanate, or barium titanate. In addition, these materials may contain lanthanum, aluminum, yttrium, or tungsten. Materials containing metals such as silicon and oxides of these metals may also be used. It is also possible to use a laminate of films containing the same.

[0168] The insulating film is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. It is preferable to use such an insulating film. The heat generated during the heat treatment or the like causes oxygen to be introduced from the gate insulating layer 204 to the semiconductor layer 202. can be supplied.

[0169] [Variation 3] When multiple transistors are arranged on a substrate, one groove is provided for each transistor. Instead of providing a single groove for multiple transistors, This allows transistors to be integrated more densely.

[0170] As an example, in FIG. 9, when four transistors 200 are connected in series, In the case where four transistors 200 are formed above one groove portion provided in the insulating layer 207, 9(A) is a schematic top view, and FIG. 9(B) is a cross-sectional view of FIG. 9(A). FIG. 1 is a cross-sectional schematic view at IJ.

[0171] As shown in FIG. 9(B), four transistors are formed above one groove formed in the insulating layer 207. In addition, two adjacent transistors 200 are formed with a common The common electrode 203 connects the two transistors 200 in series. On the other hand, the gate electrodes 205 are provided independently for the respective transistors 200. are.

[0172] The first protective insulating layer 211 and the second protective insulating layer 212 are connected to the electrodes 203 provided on both ends. The transistors 200 are in contact with each other in an outer region and are provided so as to surround the four transistors 200.

[0173] An example of a circuit configuration to which such series-connected transistors 200 can be applied is shown in FIG. The circuit shown in FIG. 9(C) has four transistors and three capacitors. In two adjacent transistors, the source or drain of one transistor is connected to the other The source or drain of one of the transistors is electrically connected to form a node, and the node One electrode of the capacitor is electrically connected to the gate.

[0174] For example, the configuration of the capacitive element 220 illustrated in the second modification can be applied to the capacitive element. Cut.

[0175] The circuit shown in FIG. 9C operates as a shift register by applying the following potentials: It can function as.

[0176] A common potential is applied to the other electrodes of the three capacitance elements. The gates of the first and third transistors from the left are connected to the same clock signal. The gates of the second and fourth transistors are supplied with the same clock signal (CLK1). A signal (CLK2) is given. Also, one of the source or drain of the first transistor is The input terminal to which the input potential (IN) is applied, and the source or drain of the fourth transistor One of the inputs is the output terminal from which the output potential (OUT) is output. The potentials (e.g. high) that alternately turn on the transistors without overlapping each other are By using a clock signal that is equal to the input voltage, the voltage applied to the input terminal The information can be shifted from left to right.

[0177] The configuration shown in FIG. 9(D) is a circuit diagram of a plurality of readout circuits connected in series to the circuit of FIG. 9(C). Each of the transistors 260 is a capacitor element. The other electrode of each capacitor element is electrically connected to a node. By using this configuration, the circuit shown in FIG. The potential information held in the node to which one electrode of the capacitance element is connected can be read out at any time. It can function as a NAND type memory device. The transistor 0 may be a transistor including an oxide semiconductor, similar to the transistor 200. Alternatively, as exemplified in the following embodiments, transistors using different semiconductors may be used. It's fine.

[0178] The above is a description of the modified example.

[0179] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0180] (Embodiment 2) In this embodiment, a transistor having a configuration partially different from that of the transistor illustrated in Embodiment 1 is used. An example of the configuration of the transistor will be explained. Note that explanations of parts that overlap with the above will be omitted. In addition, even if the position or shape of the components differs, When the functions are the same, the same reference numerals are used and the description may be omitted.

[0181] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer and a gate electrode overlapping with the oxide semiconductor layer. Between the insulating layer and the protective insulating layer, at least one of the metal elements constituting the oxide semiconductor layer is formed. It is preferable to have an oxide layer containing one metal element as a constituent element. A trap level is formed at the interface between the oxide semiconductor layer and the insulating layer overlapping the oxide semiconductor layer. Since the above-mentioned phenomenon can be suppressed, deterioration of the electrical characteristics of the transistor can be suppressed. .

[0182] That is, in one embodiment of the present invention, at least the top surface and the bottom surface of the oxide semiconductor layer are made of an oxide semiconductor. The oxide layer acts as a barrier to prevent the formation of interface states in the carbon nanotube layer. The top and side surfaces of the oxide semiconductor layer in the panel width direction are connected to the gate electrode via the gate insulating layer. an insulating layer including an aluminum oxide film so as to be covered with the oxide semiconductor layer and to enclose the oxide semiconductor layer; It is more preferable that the oxide semiconductor layer The formation of oxygen vacancies and the incorporation of impurities, which are factors that cause carrier generation in the semiconductor and at the interface, are suppressed. Since this allows the oxide semiconductor layer to be highly purified and intrinsic, The oxidation means making the oxide semiconductor layer intrinsic or substantially intrinsic. This suppresses fluctuations in the electrical characteristics of transistors containing compound semiconductor layers, thereby providing highly reliable semiconductor devices. It will be possible to provide

[0183] Note that in this specification and the like, when the term "substantially intrinsic" is used, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 x 10 13 / cm 3 By making the oxide semiconductor layer highly purified and intrinsic, the transistor has stable electrical characteristics. Sex can be assigned.

[0184] More specifically, for example, the following configuration can be adopted.

[0185] [Configuration example 1] 10A and 10B are schematic cross-sectional views of a transistor 150, which will be described below. For a schematic top view, FIG. 1A can be used. The embodiment is different from the embodiment in that it mainly has a first oxide layer 151 and a second oxide layer 152. This is different from the transistor 100 illustrated in the first embodiment.

[0186] The first oxide layer 151 is provided between the first protective insulating layer 111 and the semiconductor layer 102. The second oxide layer 152 is provided between the semiconductor layer 102 and the gate insulating layer 104. It is being used.

[0187] More specifically, the second oxide layer 152 has an upper surface that faces the lower surfaces of the pair of electrodes 103 and The gate insulating layer 104 is provided in contact with the lower surface of the gate insulating layer 104 .

[0188] The first oxide layer 151 and the second oxide layer 152 are the same as the semiconductor layer 102. The oxides include oxides containing one or more of the above metal elements.

[0189] The boundary between the semiconductor layer 102 and the first oxide layer 151 or the boundary between the semiconductor layer 102 and the second oxide layer 152 is The boundary with the oxide layer 152 may be unclear.

[0190] For example, the first oxide layer 151 and the second oxide layer 152 contain In or Ga. Representative examples include In-Ga oxides, In-Zn oxides, and In-M-Zn oxides ( M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the semiconductor layer A material whose conduction band lower energy is closer to the vacuum level than 102 is used. The energy of the bottom of the conduction band of the first oxide layer 151 or the second oxide layer 152 and the energy of the bottom of the conduction band of the semiconductor The difference in energy between the lower end of the conduction band of the layer 102 and the lower end of the conduction band of the layer 103 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or more It is preferable to set it to 0.4 eV or less.

[0191] The first oxide layer 151 and the second oxide layer 152 are provided so as to sandwich the semiconductor layer 102. 52, an oxide having a higher Ga content that functions as a stabilizer compared to the semiconductor layer 102 By using the above, release of oxygen from the semiconductor layer 102 can be suppressed.

[0192] The semiconductor layer 102 may be formed by, for example, using an atomic ratio of In:Ga:Zn=1:1:1 or 3:1:2. When an In-Ga-Zn oxide having a numerical ratio is used, the first oxide layer 151 or the second oxide layer The material layer 152 may be, for example, In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1 In-Ga- with atomic ratios such as 1:6:4, 1:6:8, 1:6:10, or 1:9:6 Zn-based oxide can be used. The atomic ratios of the first oxide layer 151 and the second oxide layer 152 are each plus or minus the above atomic ratios as an error. The first oxide layer 151 and the second oxide layer 152 have a composition of The same material may be used, or materials of different compositions may be used.

[0193] In addition, when an In-M-Zn oxide is used as the semiconductor layer 102, the semiconductor layer 102 and The target used for forming the semiconductor film is a metal element contained in the target. When the atomic ratio is In:M:Zn=x1:y1:z1, the value of x1 / y1 is 1 / 3 or more. z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, preferably It is preferable to use an oxide having an atomic ratio of 1 or more and 6 or less. Note that by setting z1 / y1 to 6 or less, it becomes easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2, etc.

[0194] In addition, when an In-M-Zn-based oxide is used as the first oxide layer 151 and the second oxide layer 152, for forming the oxide films that become the first oxide layer 151 and the second oxide layer 152, the target used is such that when the atomic ratio of the metal elements contained in the target is In:M:Zn = x2:y2:z2, x2 / y2 < x1 / y1, and it is preferable to use an oxide having an atomic ratio of z2 / y2 of 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. Note that by setting z2 / y2 to 6 or less, it becomes easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:4, 1:3:6, 1:3:8, etc.

[0195] In addition, by using a material having an energy of the lower end of the conduction band closer to the vacuum level for the first oxide layer 151 and the second oxide layer 152 than for the semiconductor layer 102, a channel is mainly formed in the semiconductor layer 102, and the semiconductor layer 102 becomes the main current path. Thus, by sandwiching the semiconductor layer 102 in which the channel is formed with the first oxide layer 151 and the second oxide layer 152 containing the same metal element, the generation of these interface levels is suppressed, and the reliability in the electrical characteristics of the transistor is improved.

[0196] Note that it is not limited to these, and depending on the required semiconductor characteristics and electrical characteristics (field effect ​​​​​​It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of the transistor, the semiconductor layer 102, the first oxide layer 151, and the second oxide layer 152 are formed. The carrier density, impurity concentration, defect density, and atomic ratio of metal elements to oxygen in the oxide layer 152 of 2 It is preferable to make the interatomic distance, density, etc. appropriate.

[0197] Here, the thickness of the semiconductor layer 102 is at least thicker than that of the first oxide layer 151. The thicker the semiconductor layer 102, the higher the on-state current of the transistor. In addition, the first oxide layer 151 has the effect of suppressing the generation of interface states in the semiconductor layer 102. For example, the thickness of the semiconductor layer 102 is set to a value equal to or larger than the thickness of the first oxide layer. The thickness of the layer 151 is more than 1 time, preferably 2 times or more, more preferably 4 times or more. More preferably, it should be 6 times or more.

[0198] Similarly to the first oxide layer 151, the second oxide layer 152 also has a structure in which the interface of the semiconductor layer 102 is formed. The thickness may be such that the effect of suppressing the generation of levels is not lost. The thickness of the second oxide layer 152 may be equal to or less than that of the layer 151. Since the electric field from the gate electrode 105 may not reach the semiconductor layer 102 easily, It is preferable that the second oxide layer 152 is formed thinly. The thickness of 2 is determined by taking into consideration the withstand voltage of the gate insulating layer 104 and the voltage at which the transistor 150 is driven. It may be set appropriately depending on the situation.

[0199] 10(B), the oxide layer 151 is more porous than the oxide layer 151 on its periphery. The upper surface of the first protective insulating layer 111 in the surrounding area is lowered, and the gate electrode 105 is positioned above the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is surrounded. The electric field generated by the gate electrode 105 is sufficient up to the gate electrode 105, and the on-current of the transistor 150 is increased. Similarly, as shown in FIG. 27, the gate electrode 152 can be formed on the lower surface of the oxide layer 151. If the lower surface of the gate electrode 105 is lowered, the on-current of the transistor 150 can be increased. This is preferable because it is possible to

[0200] Here, the band structure in the channel formation region of the transistor 150 will be described. .

[0201] Figures 11(A) and (B) show the energy band structure in the thickness direction of the channel formation region. is shown schematically.

[0202] In Figure 11(A) and (B), EcI1, EcS1, EcS2, EcS3, and EcI2 are the first protective insulating layer 111, the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 153, respectively. The energy levels of the conduction band minimums of the oxide layer 152 and the gate insulating layer 104 are shown in FIG. For convenience, the thickness of each layer is not taken into consideration here.

[0203] Here, the difference between the vacuum level and the conduction band minimum (also called the electron affinity) is The energy difference between the potential and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap. Measurement can be performed using a HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was measured by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (e.g., P Measurements can be performed using a HI VersaProbe.

[0204] As shown in FIG. 11(A), a first oxide layer 151, a semiconductor layer 102, a second oxide layer In 152, the energy of the conduction band minimum changes continuously without any barrier between them. This is because the compositions of the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are similar to each other. This allows oxygen to diffuse between the two layers, forming a layer that can be called a mixed layer. This can be understood as being due to the

[0205] In FIG. 11A, the first oxide layer 151 and the second oxide layer 152 are formed in the same energy range. The case of oxide layers with different energy gaps has been shown. For example, if EcS3 is higher than EcS1, the oxide layer may have a large gap. At higher energies, a part of the band structure is shown in Figure 11(B). Although not shown, EcS1 may have higher energy than EcS3.

[0206] 11A and 11B, the semiconductor layer 102 forms a well in the channel formation region. ) and a channel is formed in the semiconductor layer 102. 151, the semiconductor layer 102, and the second oxide layer 152 have a continuous conduction band minimum energy. Because the well is changing dynamically, it can also be called a U-Shape Well. A channel formed in this manner can also be called a buried channel.

[0207] The first oxide layer 151 and the second oxide layer 152 are formed of metal elements constituting the semiconductor layer 102. Since the oxide layer 151 is an oxide containing one or more elements, the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are The laminated structure in which the oxide layer 152 is laminated is also called an oxide laminate in which the main component is laminated in common. (Hereinafter, the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are stacked.) The laminated structure is also called an oxide laminate. The layers are not simply stacked, but are connected in a continuous junction (here, the energy of the bottom of the conduction band is particularly It is possible to fabricate the material so that a U-shaped well structure is formed, in which the temperature changes continuously between layers. This is because defect levels such as trap centers and recombination centers are formed at the interfaces of the layers. When such impurities are mixed, the continuity of the energy band is lost and carriers are is lost due to trapping or recombination.

[0208] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each layer is deposited in succession using a device (such as a sputtering device) without being exposed to the atmosphere. Each chamber in the sputtering apparatus is preferably In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum evacuation (5×10 -7 Pa~1×10 -4 It is preferable to Alternatively, a turbomolecular pump and a cold trap can be combined to separate the chamber from the exhaust system. It is preferable to prevent backflow of gas into the bar.

[0209] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of sputtering gases. Oxygen gas and argon gas are used as sputtering gases. The dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using a gas highly purified by the above method, it is possible to minimize the incorporation of moisture and other substances into the oxide semiconductor. This can be prevented.

[0210] The first oxide layer 151 and the second oxide layer 152 are provided on the upper or lower layer of the semiconductor layer 102. Layer 152 acts as a barrier layer and protects the insulating layer (first protective insulating layer 111) from the oxide stack. The influence of trap states formed at the interface between the gate insulating layer 104 and the oxide stack is Extending to the semiconductor layer 102, which is the main carrier path of the transistor can be suppressed.

[0211] For example, oxygen vacancies in a semiconductor layer occur deep within the energy gap of an oxide semiconductor. This manifests as a localized level at the energy position. The reliability of the transistor is reduced by being trapped, so oxygen contained in the semiconductor layer is In the oxide stack, the oxide layer has a larger oxide content than the semiconductor layer 102. By providing oxide layers that are less likely to cause electron vacancies on the top and bottom of the semiconductor layer 102, For example, the semiconductor layer 102 can be used in a constant current measurement. Measured by the constant photocurrent method (CPM) The absorption coefficient due to the localized level is 1×10 -3 / cm, preferably less than 1×10 -4 / It can be less than cm.

[0212] In addition, the semiconductor layer 102 may be formed by forming an insulating layer having a different constituent element (for example, an insulating layer including a silicon oxide film). When a layer contacts a semiconductor, an interface state is formed at the interface between the two layers, and the interface state forms a channel. In such a case, a second transistor with a different threshold voltage appears, However, the apparent threshold voltage of the transistor may vary. In the present invention, the first oxide layer 151 contains one or more metal elements constituting the semiconductor layer 102. Therefore, an interface state is unlikely to be formed at the interface between the first oxide layer 151 and the semiconductor layer 102. Therefore, by providing the first oxide layer 151, the threshold voltage of the transistor and other This can reduce variations in electrical characteristics.

[0213] In addition, when a channel is formed at the interface between the gate insulating layer 104 and the semiconductor layer 102, the Interface scattering occurs at the interface, reducing the field-effect mobility of the transistor. In the oxide stack, the second oxide layer contains one or more metal elements constituting the semiconductor layer 102. Since the second oxide layer 152 is present, the carriers are not generated at the interface between the semiconductor layer 102 and the second oxide layer 152. This makes it difficult for electrons to scatter, and the field-effect mobility of the transistor can be increased.

[0214] [Configuration example 2] 12A and 12B are schematic cross-sectional views of a transistor 160, which will be described below. For a schematic top view, FIG. 1A can be used. The transistor 150 differs from the transistor 150 described above mainly in the shape of the second oxide layer 152. There are.

[0215] In the transistor 160, the second oxide layer 152 has a bottom surface that is in contact with the pair of electrodes 103. Furthermore, a pair of electrodes 103 is provided. The insulating film 104 is provided in contact with the upper surface and side surfaces of the semiconductor layer 102 in a region where the insulating film 104 is thin.

[0216] In the configuration shown in FIG. 12, the top surface shapes of the second oxide layer 152 and the gate insulating layer 104 are The same photomask is used to process the upper surface of the gate electrode 105 so that the upper surface of the gate electrode 105 roughly matches the upper surface of the gate electrode 105. In addition, the second protective insulating layer 112 is formed between the second oxide layer 152 and the gate insulating layer. The layer 104 is provided in contact with each end of the layer 104. By adopting such a configuration, The oxide is transferred from the semiconductor layer 102 through the second oxide layer 152 and the edge of the gate insulating layer 104. This can prevent the element from being released.

[0217] As shown in FIG. 12B, the semiconductor layer 102 of the transistor 160 has a top surface The semiconductor layer 152 is also in contact with the second oxide layer 152. The channel forming region of 102 is surrounded by a first oxide layer 151 and a second oxide layer 152. It is composed of:

[0218] With this structure, the second oxide film provided in contact with the side surface of the semiconductor layer 102 The layer 152 can also suppress the formation of interface states on the side surfaces of the semiconductor layer 102. As a result, when the channel formed near the side surface of the semiconductor layer 102 is actively used, Even if the transistor is turned on, the fluctuation of its electrical characteristics can be suppressed, resulting in a high on-state current and high signal quality. Therefore, it is possible to realize a transistor that has both high reliability and low power consumption.

[0219] 12(B), the oxide layer 151 is more porous than the oxide layer 151 on its periphery. The upper surface of the first protective insulating layer 111 in the surrounding area is lowered, and the gate electrode 105 is positioned above the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is surrounded. The electric field generated by the gate electrode 105 is sufficient up to the gate electrode 105, and the on-current of the transistor 160 is increased. Similarly, as shown in FIG. 28, the gate electrode 152 can be formed on the lower surface of the oxide layer 151. If the lower surface of the gate electrode 105 is lowered, the on-current of the transistor 160 can be increased. This is preferable because it is possible to

[0220] In addition, by using the insulating layer 106 that releases oxygen when heated, as exemplified in the first embodiment, It can also be done as follows.

[0221] 13A and 13B show a transistor 17 having a different configuration from the transistor 160. A cross-sectional schematic diagram of 0 is shown.

[0222] The transistor 170 is mainly formed between the first oxide layer 151 and the first protective insulating layer 111. It differs from the transistor 160 in that it has an insulating layer 106 .

[0223] As shown in FIGS. 13A and 13B, the semiconductor layer 102, the first oxide layer 151, and The insulating layer 106 is processed into islands, and a second oxide layer 152 is provided to cover the islands. By providing the first protective insulating layer 111 on the lower side, the oxygen released by the insulating layer 106 is reduced. It can be effectively supplied to the semiconductor layer 102 via the first oxide layer 151 .

[0224] 13B, the insulating layer 106 is more likely to be covered with a thin film than the bottom surface of the insulating layer 106. The upper surface of the first protective insulating layer 111 is lowered, and the gate electrode 105 is positioned on the side of the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is surrounded by the insulating film 104. The gate electrode 105 generates a sufficient electric field, increasing the on-current of the transistor 170. Similarly, as shown in FIGS. 29(A) and 29(B), the lower surface of the oxide layer 151 can be If the bottom surface of the gate electrode 105 is lowered, the on-current of the transistor 170 is further increased. This is preferable because it can

[0225] 13C and 13D show transistors having a partially different configuration from the transistor 170. 1 shows a cross-sectional schematic diagram of transistor 180. Transistor 180 is not processed as an island. The insulating layer 106 includes a first oxide layer 151 and a second oxide layer 152. The first oxide layer 151 and the second oxide layer 152 are made of a material having a sufficiently large band gap. Such a configuration can be realized by using

[0226] In the case of the transistor 180, the insulating layer 106 , the first oxide layer 151 and the second oxide layer 152 are etched to expose the first protective insulating layer. It is preferable to provide an area where the edge layer 111 and the second protective insulating layer 112 are in contact with each other. For example, A plurality of transistors are formed in the region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112. A configuration in which a star is provided may also be used.

[0227] 13(D), the periphery of the semiconductor layer 102 is thicker than the bottom surface of the semiconductor layer 102. The upper surface of the first protective insulating layer 111 in the surrounding area is lowered, and the gate electrode 105 is positioned above the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is surrounded. The electric field generated by the gate electrode 105 is sufficiently applied to the gate electrode 105, increasing the on-current of the transistor 180. Similarly, as shown in FIGS. 29(C) and 29(D), If the bottom surface of the gate electrode 105 is lower than the surface, the on-current of the transistor 180 is further increased. This is preferable because it can increase the

[0228] [Configuration example 3] 14A and 14B are schematic cross-sectional views of a transistor 250, which will be described below. For a schematic top view, FIG. 1A can be used. The embodiment is different from the embodiment in that it mainly has a first oxide layer 251 and a second oxide layer 252. This is different from the transistor 200 illustrated in the first embodiment.

[0229] The first oxide layer 251 is provided between the first protective insulating layer 211 and the semiconductor layer 202. The second oxide layer 252 is provided between the semiconductor layer 202 and the gate insulating layer 204. It is being used.

[0230] More specifically, in the grooves formed in the insulating layer 207, the first oxide layer 251 is The first oxide layer 211 is formed on the side and top surfaces of the first protective insulating layer 211. 51 is provided in contact with the bottom and side surfaces of the semiconductor layer 202 .

[0231] The second oxide layer 252 has a lower surface that is in contact with the upper surfaces of the pair of electrodes 203. Furthermore, in the region where the pair of electrodes 203 is not provided, It is provided on the top surface of layer 202 .

[0232] The first oxide layer 251 and the second oxide layer 252 are the same as the semiconductor layer 202. The oxides include oxides containing one or more of the above metal elements.

[0233] The boundary between the semiconductor layer 202 and the first oxide layer 251 or the boundary between the semiconductor layer 202 and the second oxide layer 252 is The boundary with the oxide layer 252 may be unclear.

[0234] The first oxide layer 251 and the second oxide layer 252 may be, for example, the above-mentioned first oxide layer. Similar materials can be used for layer 151 and second oxide layer 152 .

[0235] In the configuration shown in FIG. 14, the top surface shapes of the second oxide layer 252 and the gate insulating layer 204 are The same photomask is used to process the upper surface of the gate electrode 205 so that the upper surface of the gate electrode 205 roughly matches the upper surface of the gate electrode 205. In addition, the second protective insulating layer 212 is formed between the second oxide layer 252 and the gate insulating layer. The layer 204 is provided in contact with each end of the layer 204. The oxide is transferred from the semiconductor layer 202 through the second oxide layer 252 and the edge of the gate insulating layer 204. This can prevent the element from being released.

[0236] As shown in FIG. 14B, the semiconductor layer 202 of the transistor 250 has a lower surface In addition, the side surface of the semiconductor layer 202 is in contact with the first oxide layer 251. is provided in contact with the second oxide layer 252. That is, the channel of the semiconductor layer 202 The formation region is surrounded by a first oxide layer 251 and a second oxide layer 252. .

[0237] By adopting such a structure, in the channel forming region of the semiconductor layer 202, Therefore, the formation of the interface state can be suppressed. This can suppress the problem, thereby realizing a highly reliable transistor.

[0238] Here, the thickness of the semiconductor layer 202 is at least thicker than that of the first oxide layer 251. The thicker the semiconductor layer 202, the higher the on-state current of the transistor. In addition, the first oxide layer 251 has the effect of suppressing the generation of interface states in the semiconductor layer 202. For example, the thickness of the semiconductor layer 202 is set to a value equal to or larger than the thickness of the first oxide film. The thickness of the layer 251 is more than 1 time, preferably 2 times or more, more preferably 4 times or more. More preferably, it should be 6 times or more.

[0239] The depth of the grooves formed in the insulating layer 207 is determined by the thickness of the first protective insulating layer 211 and the first oxide layer 212. The thickness may be appropriately set in consideration of the thicknesses of the organic layer 251 and the semiconductor layer 202 after processing. The width of the groove is appropriately determined depending on the channel length and channel width of the transistor 250. Just set it.

[0240] Similarly to the first oxide layer 251, the second oxide layer 252 also has a structure in which the interface of the semiconductor layer 202 The thickness may be such that the effect of suppressing the generation of levels is not lost. The thickness of the second oxide layer 252 may be equal to or less than that of the layer 251. Since the electric field from the gate electrode 205 may not reach the semiconductor layer 202 easily, It is preferable that the second oxide layer 252 is formed thinly. The thickness of 2 is determined by taking into consideration the withstand voltage of the gate insulating layer 204 and the voltage at which the transistor 250 is driven. It may be set appropriately depending on the situation.

[0241] In addition, the insulating layer 206 that releases oxygen when heated, as exemplified in the first modification of the first embodiment, It can also be applied.

[0242] 14(C) and (D) show a transistor 27 having a different configuration from the transistor 250. A cross-sectional schematic diagram of 0 is shown.

[0243] The transistor 270 is mainly formed between the first oxide layer 251 and the first protective insulating layer 211. and the semiconductor layer 202 is provided to cover the groove portion. It is different from transistor 250.

[0244] In this way, by providing the first oxide layer 251 so as to fill the groove, the channel In the formation region, it is possible to increase the physical distance between the semiconductor layer 202 and the insulating layer 206. Therefore, in the channel formation region, the boundary formed at the interface of the semiconductor layer 202 The surface level can be further reduced.

[0245] FIG. 15 shows a transistor 28 having a different configuration from the transistors 250 and 270. 0 connected in series. The transistor 280 is mainly It differs from transistor 270 in that layer 251 is provided over the trench.

[0246] In this way, the insulating layer 206 is buried in the groove, and the first oxide layer 251 and the By providing the semiconductor layer 202, the volume of the insulating layer 206 can be easily increased. As a result, the amount of oxygen supplied to the semiconductor layer 202 can be increased. By adopting such a configuration, no step is formed on the upper surface of the insulating layer 206. The first oxide layer 251 and the semiconductor layer 202 are not covered with the insulating layer 201. Therefore, the insulating layer 206 can be formed thick.

[0247] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0248] (Embodiment 3) In this embodiment, an oxide semiconductor that can be suitably used in a semiconductor device of one embodiment of the present invention will be described. The conductor will now be described.

[0249] Oxide semiconductors have a large energy gap of 3.0 eV or more, making them suitable for The oxide semiconductor film obtained by processing under suitable conditions and sufficiently reducing the carrier density is applied. In a transistor with this structure, the leakage current between the source and drain in the off state (off current) can be made extremely low compared to conventional silicon-based transistors. .

[0250] As applicable oxide semiconductors, at least indium (In) or zinc (Zn ) is preferably contained. In particular, it is preferably contained In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to gallium (Ga), tin (Sn), hafnium (Hf), and zirconium (Zr) , titanium (Ti), scandium (Sc), yttrium (Y), lanthanides (e.g. , cerium (Ce), neodymium (Nd), gadolinium (Gd), or It is preferable that one or more types are contained.

[0251] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg acids oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO (also written as In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxides, In-Zr-Zn-based oxides, In-Ti-Zn-based oxides, In-Sc-Zn In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, I n-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga- Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, I n-Hf-Al-Zn oxides can be used.

[0252] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn does not matter. The metal elements may be included.

[0253] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer ) may be used, where M is selected from Ga, Fe, Mn and Co. It indicates one or more metal elements, or the above-mentioned stabilizer elements. In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials expressed as follows may also be used.

[0254] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A Or In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=2:1:3 and its composition It is preferable to use an oxide in the vicinity of

[0255] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors, generating electrons as carriers. Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove impurities to achieve high purity so that the impurities are not included as much as possible.

[0256] Note that dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film Oxygen may also decrease at the same time. A process of adding oxygen to an oxide semiconductor film to fill oxygen vacancies increased by oxidation. In this specification and the like, the case where oxygen is supplied to an oxide semiconductor film is preferably described as follows: This may be referred to as oxygen addition treatment, or oxygen contained in an oxide semiconductor film may be added to the oxide semiconductor film to obtain a stoichiometric composition. When the oxygen concentration is higher than this, it is sometimes referred to as hyperoxygenation treatment.

[0257] In this way, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies through oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is very close to i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that there are very few carriers derived from donors in the oxide semiconductor film. (close to zero), and the carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below It says something.

[0258] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 at room temperature (approximately 25°C). -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10 -24 A or below, or 85 1 x 10 at °C -15 A or less, preferably 1×10 -18 A or less, more preferably 1x 10 -21 A or less. Note that the transistor being in the off state is an n-channel In the case of a transistor of this type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. In general, if the gate voltage is 1V or more, 2V or more, or 3V or more less than the threshold voltage, , the transistor is turned off.

[0259] The structure of the oxide semiconductor film will be described below.

[0260] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0261] First, the CAAC-OS film will be described.

[0262] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it also includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°.

[0263] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0264] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0265] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron ​​microscope, clear boundaries between the crystals are observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0266] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0267] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0268] FIG. 23(a) is a cross-sectional TEM image of the CAAC-OS film. This is a cross-sectional TEM image of 23(a) enlarged, with the atomic arrangement emphasized for easier understanding. The key is displayed.

[0269] Figure 23(c) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 23(a). The local Fourier transform image of the area (nm) is shown in Figure 23(c). In addition, the c-axis orientation is different between A-O and O-A', so different graphs are formed. The c-axis angles between the A and A crystals are 14.3° and 16. 6°, 26.4°, and so on. Between these, the angle of the c-axis gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0270] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm on the top surface of the CAAC-OS film is observed. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See Figure 24(A)).

[0271] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0272] Most of the crystals in the CAAC-OS film are cubic crystals with sides of less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This also includes cases where the size fits within a cube of less than 5 nm, or less than 3 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a planar TEM image, 2 Over 5μm 2 or more than 1000μm 2 Crystal regions with more than this size may be observed.

[0273] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0274] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0275] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0276] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0277] Furthermore, the distribution of c-axis oriented crystals in the CAAC-OS film does not need to be uniform. For example, the crystalline part of the CAAC-OS film is grown from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has a crystal orientation that is more c-axis oriented than the region near the surface on which the crystal is formed. In addition, the CAAC-OS film containing impurities may have a high percentage of impurities. The region where the ZnO was added was transformed, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0278] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0279] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0280] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0281] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small number of carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) such that the threshold voltage is negative. It is also called "marine.") It is rare for it to become pure or substantially pure. An intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it is fixed. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0282] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0283] Next, a microcrystalline oxide semiconductor film will be described.

[0284] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less, or 1 nm to 3 nm. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called an oxide semiconductor film. In EM observation images, the grain boundaries may not be clearly visible.

[0285] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron diffraction (also called selected area electron diffraction) is performed using an electron beam (for example, 50 nm or larger). On the other hand, for the nc-OS film, Nanobeam electron circuit using an electron beam with a probe diameter close to or smaller than the size of the crystal part. When the nc-OS film was subjected to nanobeam electron diffraction, spots were observed. When the image is taken, a circular (ring-shaped) area of ​​high brightness may be observed. When nanobeam electron diffraction was performed on the c-OS film, multiple spots were observed within the ring-shaped region. It may be measured.

[0286] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0287] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of films.

[0288] When an oxide semiconductor film has multiple structures, the structure can be resolved by using nanobeam electron diffraction. analysis may be possible.

[0289] FIG. 24C shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and the optical system 12 below the optical system 12. a sample chamber 14, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, and an observation A transillumination system having a camera 18 installed in a chamber 20 and a film chamber 22 below the observation chamber 20. The figure shows a device for measuring electron diffraction. The camera 18 is installed facing the inside of the observation chamber 20. The room chamber 22 may not be provided.

[0290] FIG. 24(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 24(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 10 is irradiated onto a substance 28 placed in the sample chamber 14 via the optical system 12. The electrons are incident on a fluorescent screen 32 installed inside the observation chamber 20 via the optical system 16. On the light plate 32, a pattern appears according to the intensity of the incident electrons, which is called a transmission electron diffraction pattern. It is possible to measure the

[0291] The camera 18 is set facing the fluorescent screen 32 and captures the pattern that appears on the fluorescent screen 32. A line passing through the center of the lens of the camera 18 and the center of the fluorescent screen 32 is The angle between the line and the upper surface of the fluorescent screen 32 is, for example, 15° or more and 80° or less, or 30° or more. The angle is set to 75° or less, or 45° to 70°. The smaller the angle, the more accurate the image captured by the camera 18. However, if the angle is known in advance, the resulting transmission electron diffraction pattern will be distorted. If the data is corrected, it is possible to correct distortions in the obtained transmission electron diffraction pattern. In some cases, the camera 18 may be placed in the film chamber 22. The fluorescent screen may be installed in the room chamber 22 so as to face the direction of incidence of the electrons 24. A transmission electron diffraction pattern with little distortion can be taken from the backside of 32.

[0292] A holder for fixing a substance 28, which is a sample, is installed in the sample chamber 14. The holder is structured to be transparent to electrons passing through the material 28. The holder may have a function to move the object 28 along the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less The range of movement is 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance 28. That's fine.

[0293] Next, the transmission electron diffraction pattern of the substance is measured using the above-mentioned transmission electron diffraction measurement device. The method will be explained.

[0294] For example, as shown in FIG. 24(D), the irradiation position of the electron 24, which is a nanobeam, in the material By changing (scanning) the In this case, if the substance 28 is a CAAC-OS film, the film shown in FIG. Alternatively, if the material 28 is an nc-OS film, the diffraction pattern shown in Figure 24(B) is The diffraction pattern shown is observed.

[0295] By the way, even if material 28 is a CAAC-OS film, it may be partially composed of nc-OS films. Therefore, the quality of the CAAC-OS film can be determined by the diffraction pattern. , the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CAA For example, in a high-quality CAAC-OS film, If present, the CAAC conversion rate is 50% or more, preferably 80% or more, and more preferably 90% or more. The diffraction pattern is different from that of the CAAC-OS film. The area where this is observed is referred to as the non-CAAC rate.

[0296] As an example, immediately after film formation (denoted as as-sputtered), or in an atmosphere containing oxygen The top surface of each sample with the CAAC-OS film after the heat treatment at 450°C in air was scanned. Transmission electron diffraction patterns were acquired while scanning at a speed of 5 nm / s for 60 seconds. The diffraction pattern was observed while scanning, and the observed diffraction pattern was captured as a still image every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the probe diameter of 1n. The same measurement was carried out on six samples. The rate was calculated using the average value of six samples.

[0297] The CAAC conversion rate for each sample is shown in Figure 25(A). The AAC conversion rate was 75.7% (non-CAAC conversion rate was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC rate is reduced by heat treatment at a high temperature (for example, 400°C or higher). It can be seen that the CAAC conversion rate increases (the CAAC conversion rate increases). It can be seen that a CAAC-OS film with a high CAAC content can be obtained even with the SiO2 solution.

[0298] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment did not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the adjacent region influences the rearrangement and formation of CAAC. .

[0299] 25(B) and 25(C) show the CAAC- 25(B) and 25(C) are planar TEM images of the OS film. It can be seen that the CAAC-OS film after the heat treatment at 50°C has a more uniform film quality. It can be seen that the film quality of the CAAC-OS film is improved by heat treatment at a low temperature.

[0300] This measurement method makes it possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0301] (Fourth embodiment) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be explained with reference to the surface.

[0302] FIG. 16(A) shows a circuit diagram of the semiconductor device, and FIGS. 16(C) and 16(D) show cross-sectional views of the semiconductor device. 16(C) and 16(D) show the channel of the transistor 100 on the left side. The cross section in the longitudinal direction is shown on the right, and the cross section in the channel width direction is shown on the right. To clearly indicate that the transistor uses an oxide semiconductor, the word "OS" is used. It is attached.

[0303] The semiconductor device shown in FIGS. 16(C) and 16(D) has a transistor using a first semiconductor material in the lower part. 2200 and a transistor using a second semiconductor material on top. As a transistor using the second semiconductor material, the transistor exemplified in Embodiment 1 may be used. An example in which 100 is applied will be explained.

[0304] In addition, in Figures 17(A) and (B), a transistor using the second semiconductor material is implemented. 1 illustrates an example of a cross-sectional structure in which the transistor 200 illustrated in Embodiment 1 is used.

[0305] Here, the first semiconductor material and the second semiconductor material are materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon, ruthenium, silicon germanium, silicon carbide, or gallium arsenide, etc.), The second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors that use single crystal silicon as a non-conductor material are easy to operate at high speeds. On the other hand, a transistor including an oxide semiconductor has a low off-state current.

[0306] Here, the transistor 2200 is described as a p-channel transistor. However, it goes without saying that different circuits can be constructed using n-channel transistors. In addition, other than using the transistor using an oxide semiconductor as described in Embodiment 1, The specific configuration of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, is described below. There is no need to be limited to what is shown here.

[0307] The configurations shown in Figures 16(A), (C), and (D) are p-channel transistors and n-channel The so-called CM type transistors are connected in series and the gates of each transistor are connected. 1 shows an example of the configuration of an OS circuit.

[0308] The transistor including the oxide semiconductor of one embodiment of the present invention has increased on-state current. This allows the circuit to operate at high speed.

[0309] In the structure shown in FIG. 16C, a transistor 2200 is provided with an insulating layer 2201 therebetween. The transistor 100 is provided between the transistor 2200 and the transistor 1 A plurality of wirings 2202 are provided between the wirings 2200. The plugs 2203 electrically connect the wiring and electrodes provided on the upper and lower layers. In addition, an insulating layer 2204 covering the transistor 100 and a wiring layer 2206 on the insulating layer 2204 are formed. 2205 and a wiring 220 formed by processing the same conductive film as the pair of electrodes of the transistor. 6 and are provided.

[0310] In this way, stacking two transistors reduces the area occupied by the circuit, Multiple circuits can be arranged at higher density.

[0311] In FIG. 16C, one of the source and drain of the transistor 100 and the Either the source or the drain of the capacitor 2200 is electrically connected by a wiring 2202 or a plug 2203. The gate of the transistor 100 is electrically connected to the wiring 2205 and the wiring 220 6, via the plug 2203 and the wiring 2202, etc., to the gate of the transistor 2200 and is electrically connected.

[0312] In the structure shown in FIG. 16D, a plug 2203 is formed in the gate insulating layer of the transistor 100. An opening for embedding is provided, and the gate of the transistor 100 is connected to the plug 2203. This configuration not only makes it easier to integrate circuits, but also , the number and length of wiring and plugs to be passed through can be reduced compared to the configuration shown in FIG. 16(C). , the circuit can be operated at a higher speed.

[0313] Here, in the configurations shown in FIGS. 16(C) and 16(D), the transistor 100 and the transistor By changing the electrode connection configuration of the capacitor 2200, various circuits can be configured. For example, as shown in FIG. 16(B), the source and drain of each transistor are connected. By using a circuit configuration with this, it can function as a so-called analog switch. Cut.

[0314] Furthermore, the transistor exemplified in either the first or second embodiment can be used to A semiconductor device having an image sensor function for reading information can be manufactured.

[0315] FIG. 18 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0316] The photodiode 602 has one electrode connected to a photodiode reset signal line 658, The other electrode is electrically connected to the gate of transistor 640. 0 indicates that either the source or the drain is connected to the photosensor reference signal line 672, and The other terminal is electrically connected to one of the source and drain of the transistor 656 . The transistor 656 has a gate connected to a gate signal line 659 and a drain connected to a floating gate. It is electrically connected to the photo sensor output signal line 671 .

[0317] The photodiode 602 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance ( A pin type in which a semiconductor layer having an i-type conductivity and a semiconductor layer having an n-type conductivity are stacked A photodiode of the type described above can be applied.

[0318] By detecting the light incident on the photodiode 602, information on the detected object is read. When reading the information of the detected object, a light source such as a backlight is used. You can be there.

[0319] The transistor 640 and the transistor 656 may be the same as those in either of the first and second embodiments. A transistor in which a channel is formed in an oxide semiconductor, as shown in the example above, can be used. In FIG. 18, the transistor 640 and the transistor 656 include an oxide semiconductor. To make this clear, the transistor symbol is marked with "OS."

[0320] The transistor 640 and the transistor 656 are the same as the transistors shown as examples in the above embodiment. The oxide semiconductor layer in which the channel is formed is made of aluminum oxide containing excess oxygen. The oxide semiconductor layer is covered with an insulating layer including an aluminum film. Therefore, the transistor 640 and the transistor The transistor 656 is an electrically stable transistor in which fluctuations in electrical characteristics are suppressed. By including a transistor, a semiconductor device having an image sensor function as shown in FIG. A highly reliable semiconductor device can be provided.

[0321] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0322] (Embodiment 5) In this embodiment, a transistor according to one embodiment of the present invention is used, and a power supply is not supplied. A semiconductor device (memory) that can retain its memory contents even under certain circumstances and has no limit on the number of times it can be written. An example of the device will be described with reference to the drawings.

[0323] FIG. 19 shows a circuit diagram of the semiconductor device.

[0324] The semiconductor device shown in FIG. 19 includes a transistor 3200 using a first semiconductor material and a second The semiconductor device includes a transistor 3300 and a capacitor 3400 made of a semiconductor material. The transistor 3300 may be any of the transistors described in the above embodiments. can be done.

[0325] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 3300 has a small off-state current, so that It is possible to retain the stored contents for a longer period of time, i.e., no refresh operation is required. A semiconductor memory device that does not require refresh operations or requires extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0326] In FIG. 19, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain electrode of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the gate electrodes of the transistor 3300. The gate electrode of the transistor 3200 and the The other of the source electrode and the drain electrode of the transistor 3300 is connected to the electrode of the capacitor 3400. The fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400. are actively connected.

[0327] In the semiconductor device shown in FIG. 19, the potential of the gate electrode of the transistor 3200 can be maintained. By utilizing this feature, it is possible to write, store, and read information as follows.

[0328] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitor element 3400. That is, the gate electrode of the transistor 3200 is A predetermined charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning the transistor 3300 to the off state, the The charge applied to the gate electrode is retained (retention).

[0329] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrode is maintained for a long period of time.

[0330] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. Generally, if the transistor 3200 is an n-channel type, the transistor 320 The apparent threshold voltage V when a high level charge is applied to the gate electrode of th_ H is the state when a low level charge is applied to the gate electrode of transistor 3200. Threshold V th_L Here, the apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H), then transistor 3200 is " When a low level charge is applied, the fifth wiring 3005 is in the "ON state." The potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0331] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. Alternatively, depending on the state of the gate electrode, The potential at which transistor 3200 remains "on," i.e., V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0332] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By applying transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is not required or the refresh operation is Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0333] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem of element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, the problem of deterioration of the gate insulating layer does not occur at all. In this device, there is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory. Reliability will be dramatically improved. Furthermore, the on / off state of the transistor determines the information Since the data is written in the memory, high-speed operation can be easily achieved.

[0334] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0335] (Embodiment 6) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the previous embodiment will be described.

[0336] FIG. 20 shows a CPU that uses the transistor described in the first embodiment at least in part. FIG. 10 is a block diagram showing the configuration of an example.

[0337] The CPU shown in FIG. 20 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 20 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their use. For example, the CPU or the configuration including the arithmetic circuit shown in FIG. 20 is regarded as one core, and the core is divided into multiple It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a calculation circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0338] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0339] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0340] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals that control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generator generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0341] In the CPU shown in FIG. 20, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0342] In the CPU shown in FIG. 20, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0343] FIG. 21 is a circuit diagram of an example of a storage element that can be used as the register 1196. The memory element 700 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a circuit 702 in which stored data is volatilized when the power is cut off. A circuit 702 in which data is not volatile, a switch 703, a switch 704, and a logic element 706 The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708 includes a transistor 709 and a transistor 710. The element 700 may further include other elements such as diodes, resistors, and inductors as needed. It may also have

[0344] Here, the memory device described in the above embodiment can be used for the circuit 702. When the supply of the power supply voltage to the memory element 700 is stopped, the gate of the transistor 709 in the circuit 702 The ground potential (0V) or the potential at which the transistor 709 is turned off is continuously input to the output. For example, the gate of the transistor 709 is grounded via a load such as a resistor. It is completed.

[0345] The switch 703 is implemented by using a transistor 713 of one conductivity type (for example, n-channel type). The switch 704 is configured to have a transistor of a conductivity type opposite to one conductivity type (for example, a p-channel type). Here, the first terminal of the switch 703 is a transistor 714. The second terminal of the switch 703 corresponds to one of the source and drain of the transistor 713. The switch 703 corresponds to the other of the source and drain of the transistor 713. The control signal RD input to the gate of the transistor 3 controls the conduction or non-conduction between the first and second terminals. The switch 713 is turned off (i.e., the transistor 713 is turned on or off). The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714. The second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714. The first terminal of the switch 704 is turned on by a control signal RD input to the gate of the transistor 714. Conduction or non-conduction between the first terminal and the second terminal (i.e., the on or off state of transistor 714) OFF state) is selected.

[0346] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. and the gate of the transistor 710. The node M2 ​​is connected to one of the source and drain of the transistor 710. The other is electrically connected to a wiring (for example, a GND line) that can be connected to the switch 703 The first terminal (one of the source and the drain of the transistor 713) is electrically connected to the first terminal of the transistor 713. The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is connected to the 704 (one of the source and drain of the transistor 714) The second terminal of the switch 704 (the other of the source and drain of the transistor 714) is electrically connected to a wiring that can supply a power supply potential VDD. The second terminal (the other of the source and drain of the transistor 713) and the first terminal of the switch 704 terminal (one of the source and drain of the transistor 714) and the input terminal of the logic element 706 is electrically connected to one of the pair of electrodes of the capacitor 707. The other of the pair of electrodes of the capacitor 707 is a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential ( VDD or the like) can be input to one of the pair of electrodes of the capacitor 707. The other is electrically connected to a wiring that can supply low-potential power (for example, a GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, when a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input, The other of the pair of electrodes of the capacitor 708 is connected to a low potential power supply. It is electrically connected to a wiring that can supply power (for example, a GND line).

[0347] The capacitors 707 and 708 are formed by accumulating parasitic capacitances of transistors and wirings. It is possible to omit it by using it sparingly.

[0348] A control signal WE is input to the first gate (first gate electrode) of the transistor 709. The switches 703 and 704 are controlled by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by the When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no electrical continuity between the terminals.

[0349] The other of the source and drain of the transistor 709 is connected to a data held in the circuit 701. In FIG. 21, the signal output from the circuit 701 is input to the transistor The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other terminal (the other of the source and drain of transistor 713) is input to logic element 7 The logic value is inverted by 06 to become an inverted signal, and is sent to the circuit 701 via the circuit 720. is entered.

[0350] In FIG. 21, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input is transmitted to the circuit 70 via the logic element 706 and the circuit 720. 1 is shown as an example, but is not limited to this. The signal output from the other of the source and drain of the transistor 713 is inverted in logic value. For example, the input from the input terminal may be input to the circuit 701 without being input to the circuit 701. When there is a node where a signal whose logic value is inverted from the signal inputted to the switch 70 is held, 3 (the other of the source and drain of the transistor 713) It can be input to the node.

[0351] The transistor 709 in FIG. 21 is the transistor described in Embodiment 1. In addition, the second gate ( It is preferable that the first gate electrode has a control signal WE. The first gate can be input with a control signal WE2, and the second gate can be input with a control signal WE3. The constant potential may be, for example, a ground potential GND or a transistor potential. The control signal WE2 is a potential smaller than the source potential of the transistor 709. is a potential signal for controlling the threshold voltage of the transistor 709, and Ic The transistor 709 can be further reduced by using a transistor having a second gate. It is also possible to use a transistor that does not have a gate.

[0352] In addition, in FIG. 21, among the transistors used in the memory element 700, The transistors other than the transistor 709 are formed on a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon layer or The memory element 7 can be a transistor in which the channel is formed in the silicon substrate. All the transistors used in 00 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 700 may include a transistor other than the transistor 709. The other transistor may include a transistor in which the channel is formed of an oxide semiconductor layer. The transistor is a transistor in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be a transistor.

[0353] For example, a flip-flop circuit can be used as the circuit 701 in FIG. The logic element 706 may be, for example, an inverter or a clocked inverter. This can be done.

[0354] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 700, The data stored in the circuit 701 is transferred to the capacitor 708 in the circuit 702. It can be held by

[0355] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer increases depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using this transistor as the transistor 709, the memory element 7 The signal held in the capacitor 708 is maintained for a long time even while power supply voltage is not supplied to the capacitor 700. In this way, the storage element 700 maintains its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold

[0356] Furthermore, by providing the switches 703 and 704, the precharge operation Since the memory element is characterized by performing the above, after the power supply voltage is restarted, the circuit 701 returns to the original state. This reduces the time required to re-store data.

[0357] In the circuit 702, the signal held by the capacitor 708 is 10. Therefore, the supply of the power supply voltage to the memory element 700 is resumed. After that, the signal held by the capacitor 708 is transferred to the transistor 710 in the ON state ( or OFF state) and can be read out from the circuit 702. Even if the potential corresponding to the signal held in 708 fluctuates slightly, the original signal can be read accurately. It is possible to do this.

[0358] Such a storage element 700 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0359] In this embodiment, the storage element 700 is used as a CPU. 00 is a DSP (Digital Signal Processor), custom LS I, LSI such as PLD (Programmable Logic Device), RF -Can also be applied to ID (Radio Frequency Identification) It is Noh.

[0360] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0361] (Embodiment 7) In this embodiment, the transistor, the memory device, or the CPU described in the above embodiment (including DSP, custom LSI, PLD, RF-ID) An example of an electronic device that can do this will be described below.

[0362] The transistors, memory devices, CPUs, and the like exemplified in the above embodiments can be used in various applications. It can be applied to sub-devices (including gaming machines). Electronic devices include televisions, monitors, etc. display devices, lighting devices, personal computers, word processors, image reproduction devices, portable audio players, radios, tape recorders, stereos, telephones, cordless telephones Telephones, mobile phones, car phones, transceivers, radios, game consoles, calculators, personal digital assistants, Child notebooks, e-books, electronic translators, voice input devices, video cameras, digital still cameras, Electric shavers, IC chips, microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, Vacuum cleaners, air conditioning equipment such as air conditioners, dishwashers, dish dryers, clothes dryers Washers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, radiation Radiation measuring devices, dialysis machines, X-ray diagnostic equipment, and other medical equipment. Examples of alarm devices include heat detectors, gas alarms, and burglar alarms. Traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems In addition, fuel-powered engines and power generation from non-aqueous secondary batteries are also examples of industrial equipment. Mobile objects propelled by electric motors using force are also included in the category of electronic devices. Examples of the above-mentioned vehicles include electric vehicles (EVs), hybrid vehicles that combine internal combustion engines and electric motors, and Hybrid electric vehicles (HEV), plug-in hybrid electric vehicles (PHEV), and these tire and wheel Tracked vehicles converted to limit tracks, motorized bicycles including electrically assisted bicycles, motorcycles, electric vehicles Wheelchairs, golf carts, small or large boats, submarines, helicopters, aircraft, rockets These include computers, satellites, space probes, planetary probes, and spacecraft. A specific example is shown in FIG.

[0363] A television set 8000 shown in FIG. 22A includes a housing 8001 and a display unit 8002. The display unit 8002 displays images and the speaker unit 8003 outputs sounds. The transistors described in the above embodiments can be incorporated into the housing 8001. The semiconductor laser diode can be used in a driver circuit or pixel for operating the display portion 8002. .

[0364] The display unit 8002 is a light-emitting device having a light-emitting element such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display device, DMD (Digital Micromirror Device) ce), PDP (Plasma Display Panel), etc. You can be there.

[0365] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via (from sender to receiver) or two-way (between sender and receiver, or between receivers) It is also possible to do so.

[0366] The television device 8000 also includes a CPU 8004 for performing information communication, a memory The CPU 8004 and the memory may include the transistors shown in the above embodiments. , storage device, or CPU can be used to reduce power consumption.

[0367] The alarm device 8100 shown in FIG. 22(A) is a residential fire alarm, and is used to detect smoke or heat. 8 is an example of an electronic device using a microcomputer 8101 and a power supply 8102. The computer 8101 may include a transistor, a memory device, or a CP shown in the above embodiment. Contains U.

[0368] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. The sensor may be a device including a transistor, a memory device, a CPU, or the like shown in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a In FIG. 22A, the CPU 8203 controls the indoor unit 8200. 8203 is provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The transistor shown in the above embodiment may be used as a CP of an air conditioner. By using U, power consumption can be reduced.

[0369] An electric refrigerator-freezer 8300 shown in FIG. 22(A) is the same as the transformer shown in the previous embodiment. This is an example of an electronic device that includes a register, a memory device, or a CPU. The storage room 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, and a CPU 83 In FIG. 22A, a CPU 8304 is provided inside a housing 8301. The transistor described in the above embodiment is used in the CPU 830 of the electric refrigerator-freezer 8300. By using 4, power saving can be achieved.

[0370] 22(B) and (C) show an example of an electric vehicle, which is an example of an electronic device. The circuit 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is supplied to the circuit 9 The output is adjusted by 702 and supplied to a driver 9703. The processor 9704 has a ROM, RAM, CPU, etc. By using the transistor shown in the embodiment in the CPU of the electric vehicle 9700, power saving can be achieved. This will help to strengthen our capabilities.

[0371] The drive unit 9703 is a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 is configured by combining the operations of the driver of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., information about the drive wheels) The circuit 970 outputs a control signal to the circuit 9702 based on input information (such as load information). 2 is a secondary battery 9701 supplied with electric energy in response to a control signal from a processing device 9704. The output of the drive unit 9703 is controlled by adjusting the gear ratio. Although not shown, an inverter for converting direct current to alternating current is also built in.

[0372] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done. [Explanation of symbols]

[0373] 100 transistors 101 Substrate 102 Semiconductor layer 103 Electrode 104 Gate insulating layer 105 gate electrode 106 Insulating layer 111 Protective insulating layer 112 Protective insulating layer 120 Capacitor 124 dielectric layer 125 electrode 150 transistors 151 Oxide layer 152 oxide layer 160 transistors 170 transistors 180 transistors 200 transistors 201 Substrate 202 Semiconductor layer 203 Electrode 204 Gate insulating layer 205 gate electrode 206 Insulating layer 207 Insulating layer 211 Protective insulating layer 212 Protective insulating layer 220 Capacitive element 224 Dielectric Layer 225 Electrode 250 transistors 251 Oxide layer 252 oxide layer 260 transistors 270 transistors 280 transistors 602 Photodiode 640 transistors 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 700 memory elements 701 circuits 702 circuits 703 Switch 704 Switch 706 Logic Elements 707 Capacitor 708 Capacitor 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 circuits 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 transistors 2201 Insulation layer 2202 Wiring 2203 Plug 2204 Insulation layer 2205 Wiring 2206 Wiring 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detector 8200 indoor unit 8201 Case 8202 Ventilation outlet 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicle 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing equipment

Claims

1. a first insulating layer, an oxide semiconductor layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer; the oxide semiconductor layer has a region disposed above a first insulating layer; the oxide semiconductor layer has a channel formation region of a transistor, the first conductive layer has a region disposed above the oxide semiconductor layer; the first conductive layer functions as a source electrode or a drain electrode of the transistor; the second insulating layer has a region disposed above the oxide semiconductor layer; the second insulating layer functions as a gate insulating layer of the transistor; the second conductive layer overlaps with the oxide semiconductor layer via the second insulating layer; the second conductive layer functions as a gate electrode of the transistor; a semiconductor device, wherein the third insulating layer has a region disposed above the second conductive layer, the third insulating layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with a side surface of the second insulating layer, a region in contact with an upper surface of the first conductive layer, a region in contact with a side surface of the first conductive layer, and a region in contact with an upper surface of the first insulating layer; a surface of the first insulating layer having a recess, and the oxide semiconductor layer having a region disposed inside the recess, in a cross-sectional view taken along a channel length direction of the transistor.

2. a first insulating layer, an oxide semiconductor layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer; the oxide semiconductor layer has a region disposed above a first insulating layer; the oxide semiconductor layer has a channel formation region of a transistor, the first conductive layer has a region disposed above the oxide semiconductor layer; the first conductive layer functions as a source electrode or a drain electrode of the transistor; the second insulating layer has a region disposed above the oxide semiconductor layer; the second insulating layer functions as a gate insulating layer of the transistor; the second conductive layer overlaps with the oxide semiconductor layer via the second insulating layer; the second conductive layer functions as a gate electrode of the transistor; a semiconductor device, wherein the third insulating layer has a region disposed above the second conductive layer, the third insulating layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with a side surface of the second insulating layer, a region in contact with an upper surface of the first conductive layer, a region in contact with a side surface of the first conductive layer, and a region in contact with an upper surface of the first insulating layer; In a cross-sectional view of a cross section cut along a channel length direction of the transistor, a surface of the first insulating layer has a recess, and the oxide semiconductor layer has a region disposed inside the recess, a region of the oxide semiconductor layer that is in contact with the second insulating layer and a region of the first insulating layer that is in contact with the first conductive layer, the region of the oxide semiconductor layer being in contact with the second insulating layer and a region of the first insulating layer being in contact with the first conductive layer, the ...

3. In claim 1 or claim 2, The semiconductor device, wherein the oxide semiconductor layer contains indium.

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