Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing the generation of noise even when a plurality of semiconductor devices are connected in parallel and used at the same time, with a simple structure.SOLUTION: A semiconductor device includes: a plurality of transistor cells 18 formed in a SiC epitaxial layer 28; a gate pad 4 for electrical connection for controlling the plurality of transistor cells; a pad peripheral part 12 formed around the gate pad so as to continuously surround the gate pad; a built-in resistor 21 partially disposed below the gate pad, made of polysilicon, and electrically connecting the gate pad and the pad peripheral portion; and a plurality of source pads 6 for electrical connection. The gate pad is physically separated from the pad peripheral pad in the same layer so that a space is formed between the gate pad part and the pad periphery, and is formed around an edge of the epitaxial layer. The connection part to which the connection member is connected is selectively formed on the surface of the gate pad.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device Place Regarding. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a gate pad, a gate connecting wiring made of polysilicon, and a gate metal wiring formed on the gate connecting wiring and integrally connected to the gate pad. When a voltage is applied to the gate pad, power is supplied to a MOSFET formed in an active region via the gate metal wiring and the gate connecting wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-238885 Summary of the Invention [Problem to be solved by the invention]

[0004] In practice, modules containing multiple semiconductor devices (chips) connected in parallel are often used. The module is provided with a gate terminal electrically connected to the gates of each chip. By applying a control voltage to the gate terminal, voltage is simultaneously applied to the gates of each built-in chip, causing switching operations.

[0005] However, such modules have the problem of being prone to noise generation when turned on. This is because there is variation in gate resistance among multiple chips, and current concentrates in chips with relatively low gate resistance at the beginning of turn-on control. Furthermore, the variation in gate resistance is caused by variations in processing accuracy (etching dimensions, etc.) when manufacturing chips, so it is difficult to eliminate this variation.

[0006] On the other hand, an external gate resistor having a resistance value greater than the gate resistor in each chip may be provided for each chip, but this would result in a complex module structure and would make assembly difficult, which would be another problem.

[0007] Book The object of the invention is to New structure of Semiconductor Equipment Place The purpose is to provide. [Means for solving the problem]

[0008] One embodiment of the present invention comprises: a gate electrode facing a channel region of the transistor cell in which a channel is formed when the transistor cell is turned on; a gate metal exposed at the outermost surface for electrical connection with the outside, the gate metal including a gate pad that is physically separated from the gate electrode but electrically connected to the gate electrode; and a built-in resistor that electrically connects the gate metal and the gate electrode and is made of a material having a resistance value greater than that of the gate metal; and a p-type semiconductor layer formed in a region other than the cell region in the active region and a p-type semiconductor layer formed in a surface region of the SiC semiconductor layer. - A type region is formed, and the p - The surface of the type region is p + A type region is formed, and the p + The p-type region is formed in a region of the SiC semiconductor layer facing the built-in resistor. - p in the type domain - The mold portion is selectively exposed on the SiC surface. A semiconductor device is provided.

[0009] In one embodiment of the present invention, The built-in resistors are arranged symmetrically with each other in a plan view seen from the normal direction of the SiC semiconductor layer.

[0010] In one embodiment of the present invention, The built-in resistor is made of polysilicon.

[0011] In one embodiment of the present invention, The gate metal is selectively disposed in the center of one side of the active region.

[0012] In one embodiment of the present invention, The transistor cell is p + a p-type body contact region, the semiconductor device including a source metal, + The body contact region is fixed to the ground potential together with the source metal.

[0013] In one embodiment of the present invention, The transistor cell is p - the source metal includes a source pad; + type region and the p - The source metal is formed so as to extend below the source pad, and the p + the body contact region and the p - It is integrally connected to the mold body region.

[0014] In one embodiment of the present invention, The semiconductor device further includes gate fingers extending from the gate metal, the gate metal being selectively formed in a portion of the periphery of the active region near the boundary with the termination region, the gate fingers extending from the formation position of the gate pad in a direction along the periphery of the active region and in a direction toward the inside of the active region, and an inner cell region and an outer cell region are formed in the active region in a portion partitioned by the multiple gate fingers extending in different directions across the gate metal and in an outer region of the gate fingers, respectively.

[0015] In one embodiment of the present invention, The area facing the built-in resistor is 1×10 19 cm -3 The p having the following impurity concentration - It is a type domain.

[0016] In one embodiment of the present invention, A source metal is included, the source metal being formed to cover substantially the entire inner cell region and the outer cell region.

[0017] In one embodiment of the present invention, The gate electrode and the built-in resistor are both made of p-type polysilicon.

[0018] In one embodiment of the present invention, The cell region includes an annular outer cell region formed along the periphery of the active region.

[0019] In one embodiment of the present invention, The above p + The impurity concentration and depth of the p-type region are + The impurity concentration and depth of the body contact region are the same as those of the p - The impurity concentration and depth of the p-type region are - The impurity concentration and depth are the same as those of the mold body region.

[0022] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG. [Figure 3] 3a and 3b are enlarged views of the area surrounded by the two-dot chain line III in FIG. 2, with FIG. 3a showing a plan view and FIG. 3b showing a cross-sectional view of the semiconductor device taken along the cutting line IIIb-IIIb in FIG. 3a. [Figure 4] FIG. 4 is a diagram showing a modified example of the cell structure. [Figure 5] FIG. 5 is an electric circuit diagram showing an electric circuit of a module to which a semiconductor device according to one embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] Fig. 1 is a schematic plan view of a semiconductor device 1 according to one embodiment of the present invention. For clarity, in Fig. 1, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

[0026] The semiconductor device 1 is a semiconductor device that employs SiC, and is formed, for example, in the shape of a square chip when viewed from a plane (hereinafter simply referred to as "plan view") when the outermost surface is viewed from the normal direction.

[0027] The semiconductor device 1 has an active region 2 and a termination region 3 surrounding the active region 2. In this embodiment, the active region 2 is formed in an inner region of the semiconductor device 1 in a generally rectangular shape in plan view, but the shape is not particularly limited. A guard ring (not shown) may be formed between the active region 2 and the termination region 3 to improve the breakdown voltage of the semiconductor device 1.

[0028] A gate metal 44 as an example of a control pad of the present invention, a source metal 43, and a gate finger 5 as an example of a finger of the present invention are formed in the active region 2. A passivation film 40 is formed on the outermost surface of the semiconductor device 1 so as to cover these. Openings 41 and 42 are formed in the passivation film 40 to expose a portion of the gate metal 44 and a portion of the source metal 43 as the gate pad 4 and the source pad 6, respectively. On the other hand, the gate finger 5 is entirely covered with the passivation film 40.

[0029] The gate metal 44, the gate finger 5, and the source metal 43 are made of metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), Cu (copper), or the like.

[0030] By configuring the gate fingers 5 with metal wiring that has lower resistance than polysilicon, it is possible to supply gate current in a short time even to transistor cells 18 (see FIG. 2) that are located relatively far from the gate metal 44. Furthermore, Al has good processability (is easy to process), which simplifies the process of forming these wirings. On the other hand, AlCu can improve the power cycle resistance of the semiconductor device 1 compared to when Al is used, and can also improve the bonding strength of the bonding wire with respect to the gate pad 4. When Cu is used, it has the advantage of being able to reduce resistivity compared to when Al and AlCu are used.

[0031] Gate metal 44 is selectively formed in part of the periphery of active region 2 (near the boundary with termination region 3). Gate fingers 5 extend from the position where gate pad 4 is formed, splitting into two directions: along the periphery of active region 2 and toward the inside of active region 2. As a result, cell regions 7 and 45 are formed in the active region 2 in the area partitioned by multiple gate fingers 5 extending in different directions with gate metal 44 between them, and in the area outside the gate fingers 5.

[0032] More specifically, in this embodiment, the gate metal 44 is formed in a rectangular shape in a plan view, and is selectively disposed in the center of one side 8 of the active region 2. The sides of the active region 2 other than the side 8 (the side on which the gate metal 44 is disposed) are the side 9 opposite the side 8, and sides 10 and 11 continuing to both ends of these sides 8 and 9, respectively.

[0033] The gate finger 5 includes a pad periphery 12 that surrounds the gate metal 44 with a gap therebetween, and a first finger 13 and a second finger 14 that extend from the pad periphery 12 in a direction along the side 8 of the active area 2 and in a direction perpendicular to the side 8, respectively.

[0034] The pad peripheral portion 12 is formed in a quadrangular ring shape in plan view along the periphery of the gate metal 44 .

[0035] A pair of first fingers 13 are formed along side 8 in the direction toward side 10 and the opposite side 11 relative to pad peripheral portion 12 .

[0036] The second finger 14 includes a linear main portion 15 that crosses the active area 2 in a direction perpendicular to the first finger 13 up to the side 9, and a plurality of branch portions 16 that are integrally connected to the main portion 15 and extend from the connection point along the first finger 13. In this embodiment, the branch portions 16 are connected to two points, the tip end and the middle part of the main portion 15, to form a total of two pairs of branch portions 16, but the number is not particularly limited.

[0037] Thus, cell regions 7 and 45 are defined in the active region 2 by the first finger 13 and the second finger 14 (main portion 15 and branch portion 16). In this embodiment, a total of four inner cell regions 7 are formed, one at each corner of the intersection formed by the main portion 15 of the second finger 14 and the central branch portion 16. In addition, an annular outer cell region 45 is formed along the periphery of the active region 2 between the periphery of the active region 2 and the gate finger 5.

[0038] The source metal 43 is formed so as to cover almost the entire inner and outer cell regions 7, 45. A total of four openings 42 are formed in the passivation film 40 so that one source pad 6 is disposed in each of the inner cell regions 7.

[0039] In addition, a recess 17 corresponding to the shape of the gate metal 44 is formed in the source metal 43. The gate metal 44 is set back toward the inside of the active region 2 with respect to the first finger 13, and the recess 17 is a depression formed to avoid this gate metal 44.

[0040] 2 is an enlarged view of the area surrounded by the dashed-dotted line II in FIG. 1. That is, it is an enlarged view of the gate pad 4 and its surrounding area of ​​the semiconductor device 1. For clarity, in FIG. 2, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

[0041] As shown in FIG. 2, a plurality of transistor cells 18 are arranged in inner and outer cell regions 7, 45 defined by the gate finger 5 (pad peripheral portion 12, first finger 13, and second finger 14).

[0042] In this embodiment, the plurality of transistor cells 18 are arranged in a matrix in plan view in each of the inner and outer cell regions 7, 45. Near the gate finger 5, the plurality of transistor cells 18 are aligned to match the shape of the gate finger 5. For example, the plurality of transistor cells 18 are aligned in a curved manner to match the shape of the corners of the pad peripheral portion 12, and are aligned in a straight manner to match the shape of the main portion 15 of the linear second finger 14. The source metal 43 is formed to cover the plurality of transistor cells 18.

[0043] 2, for clarity, only a portion of the plurality of transistor cells 18 covered with the source metal 43 is shown. The arrangement of the plurality of transistor cells 18 is not limited to a matrix, and may be, for example, a stripe pattern, a staggered pattern, etc. The planar shape of each transistor cell 18 is not limited to a quadrangle, and may be, for example, a circle, a triangle, a hexagon, etc.

[0044] Gate electrodes 19, which are an example of control electrodes of the present invention, are formed between adjacent transistor cells 18. In the inner and outer cell regions 7, 45, the gate electrodes 19 are arranged between each of the matrix-arranged transistor cells 18, and are formed in a lattice shape in plan view as a whole. Meanwhile, the gate electrodes 19 are formed not only in the inner and outer cell regions 7, 45 but also in the regions where the gate fingers 5 are arranged, and the lower portions of the gate fingers 5 are in contact with the gate fingers 5.

[0045] In this embodiment, a portion of the gate electrode 19 is formed in a region below the first finger 13 and the second finger 14 and faces the first finger 13 and the second finger 14 as a contact portion. In FIG. 2, for clarity, the portion of the gate electrode 19 formed in the region below is represented by a hatched region. As a result, the gate electrodes 19 of adjacent inner cell regions 7 are continuous via the gate electrode 19 crossing the second finger 14 below. This continuity of the gate electrodes 19 is also the same between the inner cell region 7 and the outer cell region 45 adjacent to the gate metal 44. In other words, the gate electrodes 19 in these regions are continuous via the gate electrode 19 crossing the first finger 13 below.

[0046] Each of the first finger 13 and the second finger 14 is connected to a gate electrode 19 disposed in a region below the first finger 13 and the second finger 14 by a gate contact 20. The gate contact 20 is formed linearly along the longitudinal direction of each of the first finger 13 and the second finger 14 in the center of the finger, spaced apart from each side edge of the finger.

[0047] In this embodiment, multiple built-in resistors 21 are arranged below the gate metal 44. It is preferable to arrange the multiple built-in resistors 21 at positions that are approximately equidistant from each other from the center of gravity of the planar shape of the gate metal 44, thereby providing symmetry in the arrangement of the multiple built-in resistors 21. In this embodiment, the multiple built-in resistors 21 are arranged one at each corner of the gate metal 44 that is equidistant from the center of gravity G of the gate metal 44 that has a rectangular shape in a planar view. This provides symmetry to the four built-in resistors 21.

[0048] Various such symmetrical patterns are conceivable, and for example, two built-in resistors 21 may be arranged, one at each of two diagonally opposite corners of gate metal 44, or may be arranged, one at each of two opposite sides of gate metal 44, facing each other. Furthermore, for example, when gate metal 44 has a circular shape in plan view, two built-in resistors 21 may be arranged, one at each end of the diameter of gate metal 44, or when gate metal 44 has a triangular shape in plan view, three built-in resistors 21 may be arranged, one at each of three corners of gate metal 44.

[0049] Each built-in resistor 21 is formed across the annular gap region 26 between the gate metal 44 and the gate finger 5 (pad peripheral portion 12) so as to straddle them. As a result, the built-in resistor 21 faces each of the gate metal 44 and the gate finger 5. The gate metal 44 and the gate finger 5 (pad peripheral portion 12) are connected to the built-in resistor 21 arranged in the region below them by a pad-side contact 22 and a cell-side contact 23, which are an example of the contact via of the present invention.

[0050] In this embodiment, four built-in resistors 21 extend from below peripheral edge portions 24 of two opposing sides of gate metal 44 in an outward direction perpendicular to those sides to below pad peripheral portion 12. Each built-in resistor 21 is formed in a quadrangular shape in a plan view and has a size of, for example, 200 μm square or less (200 μm × 200 μm or less). In practice, if the size of each built-in resistor 21 is 200 μm square or less, the area of ​​the region on SiC epitaxial layer 28 (see FIG. 3b) sacrificed for built-in resistor 21 can be reduced, thereby saving space.

[0051] The pad-side contacts 22 and the cell-side contacts 23 are formed in parallel linear shapes along the sides of the gate metal 44 and the pad peripheral portion 12, respectively.

[0052] The built-in resistor 21 is disposed below the peripheral portion 24 avoiding the central portion of the gate metal 44, and furthermore, the region above the region where the built-in resistor 21 is disposed is covered with the passivation film 40, thereby ensuring the gate pad 4 as the wire region of the present invention surrounded by the built-in resistor 21 in the central portion of the gate metal 44. The gate pad 4 is the region to which the bonding wire is connected.

[0053] That is, in this embodiment, each corner of the gate metal 44, where the built-in resistor 21 is disposed, is selectively covered with the passivation film 40, and the remaining portion of the gate metal 44 is exposed through the opening 41. As a result, the gate pad 4, which is rectangular in plan view and has each corner recessed inward, is exposed on the outermost surface of the semiconductor device 1. In this way, by covering the region above the region where the built-in resistor 21 is disposed with the passivation film 40, it is possible to prevent the bonding wire from being erroneously bonded to the portion of the gate metal 44 that overlaps with the built-in resistor 21 when bonding the bonding wire. As a result, it is possible to prevent the built-in resistor 21 from being damaged or destroyed by an impact such as ultrasonic waves when bonding the bonding wire.

[0054] 3a and 3b are enlarged views of the area surrounded by the two-dot chain line III in FIG. 2, where FIG. 3a shows a plan view and FIG. 3b shows a cross-sectional view of the semiconductor device 1 taken along the line IIIb-IIIb in FIG. 3a. Note that, for clarity, the scale of each component in FIGS. 3a and 3b may differ from that in FIGS. 1 and 2, and the scale of each component may also differ between FIGS. 3a and 3b. Also, for clarity, in FIGS. 3a and 3b, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

[0055] Next, the detailed configuration of the built-in resistor 21 and its surrounding area will be described together with the cross-sectional structure of the semiconductor device 1.

[0056] The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The SiC epitaxial layer 28 is stacked on the SiC substrate 27, and this stacked structure is shown as an example of the SiC semiconductor layer of the present invention.

[0057] The SiC substrate 27 and the SiC epitaxial layer 28 are each n + type and n - It is a type of SiC. + The impurity concentration of the SiC substrate 27 is, for example, 1×10 17 cm -3 ~1×10 21 cm -3 On the other hand, n - The impurity concentration of the SiC epitaxial layer 28 is, for example, 1×10 14 cm -3 ~1×10 17 cm -3 As the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used (the same applies hereinafter).

[0058] In the inner cell region 7, a plurality of transistor cells 18 are formed on the surface of the SiC epitaxial layer 28. The plurality of transistor cells 18 are p - Type body region 29 and p -n selectively formed in an inner region spaced from the periphery of the mold body region 29 + a source region 30 and an n + selectively formed in an inner region spaced apart from the periphery of the p-type source region 30. + The SiC epitaxial layer 28 includes an n-type body contact region 31. - The mold portion serves as a common drain region for multiple transistor cells 18 .

[0059] As shown in FIG. 3a, in plan view, except for the transistor cells 18 along the pad periphery 12 (gate fingers 5), + The n-type body contact region 31 is surrounded by + A source region 30 is formed, and further, an n + The p type source region 30 is surrounded by - A mold body region 29 is formed. - In the type body region 29, n + The annular region surrounding the type source region 30 is a channel region 32 in which a channel is formed when the semiconductor device 1 is turned on. Although not shown in Figures 3a and 3b, the multiple transistor cells 18 in the outer cell region 45 also have a similar configuration.

[0060] On the other hand, in the transistor cells 18 along the pad periphery 12 (gate finger 5), p - Type body region 29 and p + The body contact regions 31 are p - Type region 34 and p + It is electrically connected to the mold region 33 .

[0061] p - The impurity concentration of the body region 29 is, for example, 1×10 14 cm -3 ~1×10 19 cm -3 and n + The impurity concentration of the source region 30 is, for example, 1×10 17 cm -3 ~1×10 21 cm-3 and p + The impurity concentration of the body contact region 31 is, for example, 1×10 19 cm -3 ~1×10 21 cm -3 is.

[0062] To form these regions 29 to 31, for example, p - The p body region 29 is then formed. - By sequentially implanting n-type impurities and p-type impurities into the surface of the body region 29, n + type source region 30 and p + A p-type body contact region 31 is formed. This forms a transistor cell 18 made up of regions 29 to 31. As the p-type impurity, for example, B (boron), Al (aluminum), etc. can be used (the same applies hereinafter).

[0063] In the active region 2, in the region other than the inner and outer cell regions 7 and 45, specifically, in the region below the gate metal 44, the gate finger 5 and the gap region 26, p is formed on the surface of the SiC epitaxial layer 28. - A mold region 34 is formed. - The surface of the mold region 34 is + A mold region 33 is formed.

[0064] p + The SiC epitaxial layer 28 has a p-type region 33 in a region facing the built-in resistor 21. - p in type region 34 - The mold part is selectively exposed on the SiC surface, and in other areas, the p + The mold portion is formed over almost the entire area below the gate metal 44, etc., so that the mold portion is selectively exposed on the SiC surface. That is, the gate metal 44 and the gate finger 5 are p - In most other areas, p +It faces the mold part. + Type region 33 and p - The type regions 34 are formed so as to extend to below the source metal 43, and below the source metal 43 (in this embodiment, the portion outside the source pad 6), p + The body contact region 31 and the p - 3a, the p-type body region 29 of the transistor cell 18 along the pad periphery 12 (gate finger 5) is integrally connected to the p-type body region 29. + type body contact region 31 and p + The mold region 33 is represented by the hatched region. + The body contact region 31 is fixed to the ground potential together with the source metal 43, thereby + The gate metal 44 and the gate fingers 5 are mostly p-type regions 33, which are stable at 0 V. + It is preferable to place it opposite the mold area 33.

[0065] p + Type region 33 and p - The type regions 34 are respectively p + The body contact region 31 and the p - It is formed in the same process as the mold body region 29, and has the same impurity concentration and depth.

[0066] A gate insulating film 35, which is an example of an insulating film of the present invention, is formed on the surface of the SiC epitaxial layer 28. The gate insulating film 35 is made of an insulating material such as silicon oxide and has a thickness of, for example, 0.001 μm to 1 μm. The gate insulating film 35 is a common insulating film for insulating the gate electrode 19 and the built-in resistor 21 from the SiC epitaxial layer 28.

[0067] A gate electrode 19 and an internal resistor 21 are formed on the gate insulating film 35. The gate electrode 19 is formed to face the channel region 32 of each transistor cell 18 with the gate insulating film 35 interposed therebetween. -Exposure p of mold region 34 - The gate insulating film 35 is formed on the mold portion so as to face each other.

[0068] Both gate electrode 19 and built-in resistor 21 may be made of p-type polysilicon and formed in the same process. In this embodiment, gate electrode 19 and built-in resistor 21 contain B (boron) as a p-type impurity. B (boron)-containing polysilicon has a higher resistivity than phosphorus (P)-containing polysilicon, which is commonly used in Si semiconductor devices. Therefore, boron-containing polysilicon (built-in resistor 21) requires a smaller area than phosphorus-containing polysilicon to achieve the same resistance value. This allows the area occupied by built-in resistor 21 on SiC epitaxial layer 28 to be reduced, thereby enabling more effective use of space.

[0069] The concentration of p-type impurities contained in the polysilicon can be appropriately changed according to the design resistance values ​​of gate electrode 19 and built-in resistor 21. In this embodiment, the concentration is set so that built-in resistor 21 has a sheet resistance of 10 Ω / □ or more. In practice, if the sheet resistance of built-in resistor 21 is 10 Ω / □ or more, the overall resistance of built-in resistor 21 can be easily made larger than the resistance variation among multiple semiconductor devices 1 without increasing the area of ​​built-in resistor 21. For example, when the resistance variation is 0.1 Ω to 20 Ω, the resistance of built-in resistor 21 can be set to 2 Ω to 40 Ω with a small area. As a result, the area of ​​the region on SiC epitaxial layer 28 sacrificed for built-in resistor 21 can be reduced, thereby minimizing the impact on the layout of other elements. In this case, the total resistance value of gate electrode 19 and built-in resistor 21 is preferably 4 Ω to 50 Ω.

[0070] Furthermore, the thickness of gate electrode 19 and built-in resistor 21 is preferably 2 μm or less. By making the thickness of built-in resistor 21 2 μm or less, the resistance value of the entire built-in resistor 21 can be easily made larger than the variation in resistance value among multiple semiconductor devices 1. Conversely, if built-in resistor 21 is too thick, its resistance value becomes too low, which is not preferable.

[0071] An interlayer film 36 is formed on the gate insulating film 35 so as to cover the gate electrode 19 and the built-in resistor 21. The interlayer film 36 is made of an insulating material such as silicon oxide, and has a thickness of, for example, 0.1 μm to 5 μm.

[0072] Moreover, interlayer film 36 is formed so as to extend into a region (first region) on gate insulating film 35 where gate electrode 19 and built-in resistor 21 are not arranged. This allows the distance (insulating film thickness T) between SiC epitaxial layer 28 and gate metal 44 to be increased in the region where built-in resistor 21 is not arranged, thereby reducing the capacitance therebetween.

[0073] The pad-side contact 22 and the cell-side contact 23 are formed to penetrate this interlayer film 36. The pad-side contact 22 and the cell-side contact 23 are made of metal vias formed integrally with the gate metal 44 and the gate finger 5 (pad peripheral portion 12), respectively.

[0074] The interlayer film 36 contains n + type source region 31 and p + A source contact 46 for making contact from the source metal 43 to the mold body contact region 31 is formed penetrating the body contact region 31. The source contact 46 is made of a metal via formed integrally with the source metal 43.

[0075] On the interlayer film 36, a gate metal 44, a gate finger 5, and a source metal 43 are formed at intervals from one another.

[0076] A passivation film 40 is formed on the interlayer film 36 so as to cover the gate metal 44, the gate fingers 5, and the source metal 43. Openings 41 and 42 that expose portions of the gate metal 44 and the source metal 43 are formed in the passivation film 40.

[0077] 3a and 3b, in the semiconductor device 1, the polysilicon resistor (built-in resistor 21) is interposed between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). In other words, the built-in resistor 21 is interposed in the middle of the current path extending from the outside to the plurality of transistor cells 18.

[0078] By adjusting the resistance value of built-in resistor 21, the resistance value of built-in resistor 21 can be made dominant in the resistance value (gate resistance) which is the sum of the resistance values ​​of gate electrode 19 and built-in resistor 21. Therefore, even when multiple semiconductor devices 1 having gate electrodes 19 with variations in resistance value are connected in parallel for use, by making the resistance value of built-in resistor 21 larger than the variations, it is possible to limit the flow of current into semiconductor device 1 having gate electrodes 19 with relatively low resistance values. As a result, it is possible to reduce noise generation during use.

[0079] Moreover, the polysilicon that constitutes built-in resistor 21 is a material whose resistance value can be easily controlled by implanting impurities or the like, and its processing has also been established using conventional semiconductor manufacturing technology. Therefore, the introduction of built-in resistor 21 can avoid the structure of semiconductor device 1 itself and the module including it from becoming complicated.

[0080] As with gate electrode 19, variations in size and thickness of built-in resistor 21 may occur due to variations in processing accuracy (etching dimensions, etc.) when manufacturing semiconductor device 1, but the processing dimensions are smaller than those of gate electrode 19. Therefore, variations in built-in resistor 21 rarely cause noise generation.

[0081] Furthermore, since the built-in resistor 21 is connected to the gate metal 44 below the gate metal 44, it is possible to limit the flow of gate current at the entrance of the current path leading from the outside to the plurality of transistor cells 18. This makes it possible to prevent inrush current from flowing only to a specific transistor cell 18.

[0082] 2, consider a case where built-in resistor 21 is formed in the middle of first finger 13 or second finger 14 of gate finger 5 as a detour for these fingers 13 and 14. In this case, on the side closer to gate metal 44 than built-in resistor 21, an inrush current may flow from fingers 13 and 14 to gate electrode 19 via gate contact 20 before reaching built-in resistor 21. In contrast, if the gate current can be limited at the entrance of the current path as in this embodiment, it is possible to reduce variations in switching speed among multiple transistor cells 18.

[0083] Furthermore, the built-in resistors 21 are arranged symmetrically as shown in Figure 2. This feature also makes it possible to reduce variations in switching speed among the plurality of transistor cells 18.

[0084] As shown in FIGS. 3a and 3b, the region of the SiC epitaxial layer 28 facing the built-in resistor 21 has a thickness of 1×10 19 cm -3 p with impurity concentration below - The p-type region 34 is therefore capable of effectively suppressing the dielectric breakdown of the gate insulating film 35. - Since the p-type region is less likely to accumulate carriers than the n-type region, the built-in resistor 21 and the p-type region, which face each other with the gate insulating film 35 interposed therebetween, - The capacitance between the mold region 34 can also be reduced.

[0085] 3a and 3b, the gate metal 44 and the built-in resistor 21 are connected by a pad-side contact 22 made of a metal via. Therefore, the resistance value contributed by the built-in resistor 21 in the current path extending from the outside to the plurality of transistor cells 18 can be easily adjusted by processing such as changing the position of the pad-side contact 22 along the surface of the SiC epitaxial layer 28 or changing the diameter of the via.

[0086] For example, as with pad-side contact 37 shown by the dashed line in FIG. 3b, simply by moving the pad-side contact 37 closer to the pad peripheral area 12 than the pad-side contact 22, the distance from the contact position for the built-in resistor 21 to the pad peripheral area 12 can be easily shortened from D1 to D2. This reduces the resistance of the built-in resistor 21. Conversely, by moving the pad-side contact 37 farther from the pad peripheral area 12, the resistance of the built-in resistor 21 can be increased. Also, as with pad-side contact 38 shown by the dashed line in FIG. 3a, the resistance of the current path toward the built-in resistor 21 can be increased simply by making the via diameter smaller than that of the pad-side contact 22. Conversely, by increasing the via diameter, the resistance of the path can be reduced.

[0087] Furthermore, when forming the pad-side contacts 22 (vias), these processes only require the use of a mask that matches the distance design and via diameter design, which prevents the manufacturing process from becoming complicated.

[0088] Although the embodiment of the present invention has been described above, the present invention can also be embodied in other forms.

[0089] For example, in the above-described embodiment, the transistor cells 18 are MOSFET cells with a planar gate structure, but the transistor cells 18 may be MOSFET cells with a trench gate structure as shown in Fig. 4. In this case, the gate electrodes 19 are embedded in gate trenches 39 formed between the plurality of transistor cells 18 via gate insulating films 35.

[0090] The transistor cell 18 may also be an IGBT cell with a planar gate structure or a trench gate structure. + Instead of the SiC substrate 27, + A type SiC substrate 27 may be used.

[0091] Furthermore, built-in resistor 21 does not need to be embedded in interlayer film 36 below gate metal 44; for example, polysilicon wiring connecting gate metal 44 and gate finger 5 may be formed on the surface of interlayer film 36 as the built-in resistor of the present invention.

[0092] Furthermore, instead of polysilicon, built-in resistor 21 may be made of a material (for example, metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), or Cu (copper)) having a resistance value equal to or greater than that of gate metal 44 and gate finger 5. Even if built-in resistor 21 is made of metal, the distance between gate metal 44 and gate finger 5 can be increased, and therefore the total resistance value of gate electrode 19 and built-in resistor 21 can be increased.

[0093] Furthermore, the built-in resistor 21 does not need to be formed below the gate metal 44, and may be formed below the gate finger 5, for example.

[0094] The built-in resistor 21 may be linear and extend along a portion of the peripheral edge 24 of the gate metal 44 , or may be annular and extend along the entire periphery of the peripheral edge 24 of the gate metal 44 .

[0095] It is also possible to employ a configuration in which the conductivity types of the semiconductor portions of the aforementioned semiconductor device 1 are reversed. For example, in the semiconductor device 1, the p-type portions may be n-type, and the n-type portions may be p-type.

[0096] FIG. 5 is an electric circuit diagram showing an electric circuit of a module to which a semiconductor device according to one embodiment of the present invention is applied.

[0097] The module 100 includes a plurality of semiconductor devices (chips) 101 to 104, a drain terminal 105, a source terminal 106, and a gate terminal 107. Each of the semiconductor devices 101 to 104 is configured from the semiconductor device 1 shown in FIGS. 1 to 3. Each of the semiconductor devices 101 to 104 may be configured from the semiconductor device shown in FIG. 4. The plurality of semiconductor devices 101 to 104 are connected in parallel.

[0098] Each of the semiconductor devices 101 to 104 includes a plurality of transistor cells 18 connected in parallel (see FIGS. 2, 3a, and 3b) and four built-in resistors 41 connected in parallel (see FIGS. 2, 3a, and 3b). In FIG. 5, the plurality of transistor cells 18 connected in parallel are represented by one transistor cell Tr, and the four built-in resistors 41 connected in parallel are represented by one resistor R.

[0099] The gate electrode of each of the semiconductor devices 101 to 104 is connected to a gate terminal 107 of the module 100 via an internal resistor R built into the semiconductor device. The drain electrode of each of the semiconductor devices 101 to 104 is connected to a drain terminal 105 of the module 100. The source electrode of each of the semiconductor devices 101 to 104 is connected to a source terminal 106 of the module 100.

[0100] In this module 100, each of the semiconductor devices 101 to 104 has a built-in resistor R having a resistance value greater than the gate resistance in the semiconductor devices 101 to 104. Therefore, in this module 100, the structure is simpler than when each of the semiconductor devices 101 to 104 is provided with an external gate resistor having a resistance value greater than the gate resistance in the semiconductor devices 101 to 104.

[0101] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0102] This application corresponds to Patent Application No. 2013-246474 filed with the Japan Patent Office on November 28, 2013, the entire disclosure of which is incorporated herein by reference.

[0103] Further features can be extracted from this specification as follows:

[0104] "A1" SiC semiconductor layer, a plurality of transistor cells formed on the surface side of the SiC semiconductor layer, the transistor cells being on / off controlled by receiving a control voltage input to a control pad at a control electrode thereof; a built-in resistor that is disposed closer to the SiC semiconductor layer than the control pad, electrically connects the control pad and the control electrode, and reduces variations in on-resistance values ​​of the plurality of transistor cells; a first wire region is selectively formed on the surface of the control pad, the first wire region being exposed from a surface insulating film formed on the outermost surface and to which a bonding wire is connected; the built-in resistor is selectively arranged in a region avoiding the first wire region in a plan view seen from a normal direction of the SiC semiconductor layer; a main electrode pad, which is connected to one main electrode of each of the plurality of transistor cells and is different from the control pad, is disposed above the plurality of transistor cells; A second wire region, which is exposed from the surface insulating film and to which a bonding wire is connected, is selectively formed on the surface of the main electrode pad.

[0105] This configuration includes an internal resistor disposed closer to the SiC semiconductor layer than the control pad, electrically connecting the control pad and the control electrode, and reducing variations in the on-resistance values ​​of the multiple transistor cells. By adjusting the resistance value of this internal resistor, the resistance value of the internal resistor can be made dominant over the total resistance value (control resistance) of the control electrode and the internal resistor. Therefore, even when multiple semiconductor devices with varying control electrode resistances are connected in parallel, setting the resistance value of the internal resistor larger than the variations can limit current flow to semiconductor devices with relatively low control electrode resistances. As a result, noise generation during use can be reduced.

[0106] "A2" The control pad is formed independently and surrounded by the surface insulating film, The semiconductor device according to "A1", wherein the built-in resistor is arranged in a region below the control pad, outside the first wire region, via an interlayer film.

[0107] This configuration limits the flow of control current below the control pad, i.e., at the entrance of the current path leading from the outside to multiple cells. This prevents inrush current from flowing only to specific transistor cells, thereby reducing variations in switching speed among multiple transistor cells.

[0108] "A3" A part of the built-in resistor is arranged in the area below the control pad, The semiconductor device according to "A2", wherein the interlayer film is buried in a first region below the control pad where the built-in resistor is not arranged.

[0109] "A4" further includes an insulating film disposed between the built-in resistor and the SiC semiconductor layer, The semiconductor device according to "A3", wherein in the first region, a film consisting of an extension of the insulating film is arranged between the interlayer film and the SiC semiconductor layer.

[0110] According to this configuration, in the first region where no built-in resistor is arranged, the distance (thickness of the insulating film) between the SiC semiconductor layer and the control pad can be increased, thereby reducing the capacitance therebetween.

[0111] "A5" In the SiC semiconductor layer, in the region facing the built-in resistor across the insulating film, 1×10 19 cm -3 A semiconductor device according to "A4", in which an impurity region having the following concentration is selectively formed.

[0112] According to this configuration, the concentration of the impurity region facing the built-in resistor is 1×10 19 cm -3 In this case, the SiC semiconductor layer is an n-type SiC semiconductor layer, and the semiconductor layer has a thickness of 1×10 in the region facing the built-in resistor across the insulating film. 19 cm -3 The following p - It is preferable that the polymorphic region has a polymorphic structure. - Since it is more difficult for carriers to accumulate in the p-type region than in the n-type region, the built-in resistor and the p-type region, which face each other with an insulating film in between, - The capacitance between the mold area can also be reduced.

[0113] "A6" The portion of the built-in resistor is disposed below the peripheral edge of the control pad, The semiconductor device according to any one of "A1" to "A5", wherein the first wire region is formed in the center of the control pad surrounded by the peripheral edge portion.

[0114] [A7] The semiconductor device according to any one of [A2] to [A5], including a contact via that penetrates the interlayer film and electrically connects the control pad and the built-in resistor.

[0115] With this configuration, the resistance value contributed by the built-in resistor in the current path leading from the outside to multiple transistor cells can be easily adjusted by processing to change the position of the contact via along the surface of the SiC semiconductor layer, processing to change the diameter of the via, etc. Moreover, these processing steps only require the use of a mask that matches the distance design and via diameter design when forming the contact via, which prevents the manufacturing process from becoming complicated.

[0116] "A8" The semiconductor device according to any one of "A1" to "A7", wherein the built-in resistors are arranged symmetrically with respect to each other in a plan view seen from the normal direction of the SiC semiconductor layer.

[0117] According to this configuration, it is possible to prevent an inrush current from flowing only through a specific transistor cell, thereby reducing variations in switching speed among a plurality of transistor cells.

[0118] [A9] The semiconductor device according to any one of [A1] to [A8], wherein the control electrode is made of p-type polysilicon.

[0119] [A10] The semiconductor device according to [A9], wherein the control electrode contains B (boron) as a p-type impurity.

[0120] B (boron)-containing polysilicon has a higher resistivity than P (phosphorus)-containing polysilicon, which is commonly used in Si semiconductor devices. Therefore, boron-containing polysilicon (built-in resistor) requires a smaller area than phosphorus-containing polysilicon to achieve the same resistance value. This allows the built-in resistor to occupy a smaller area on the SiC semiconductor layer, thereby enabling more efficient use of space.

[0121] [A11] The semiconductor device according to any one of [A1] to [A10], wherein the resistance value of the built-in resistor is 2Ω to 40Ω.

[0122] [A12] The semiconductor device according to any one of [A1] to [A11], wherein the total resistance value of the control electrode and the built-in resistor is 4Ω to 50Ω.

[0123] [A13] The semiconductor device according to any one of [A1] to [A12], wherein the sheet resistance of the built-in resistor is 10 Ω / □ or more.

[0124] In practice, if the sheet resistance of the built-in resistor is 10 Ω / □ or more, the resistance value of the entire built-in resistor can be easily made larger than the variation in resistance value among multiple semiconductor devices without increasing the area of ​​the built-in resistor. As a result, the area of ​​the region on the SiC semiconductor layer that is sacrificed for the built-in resistor can be reduced, thereby minimizing the impact on the layout of other elements.

[0125] [A14] The semiconductor device according to any one of [A1] to [A13], wherein the size of each of the built-in resistors is 200 μm square or less in a plan view seen from the normal direction of the SiC semiconductor layer.

[0126] In practice, if the size of each built-in resistor is 200 μm square or less, the area of ​​the region on the SiC semiconductor layer that is sacrificed for the built-in resistor can be reduced, thereby saving space.

[0127] "A15" The semiconductor device according to any one of claims 1 to 14, wherein the thickness of the built-in resistor is 2 µm or less.

[0128] By making the thickness of the built-in resistor 2 μm or less, the resistance value of the entire built-in resistor can be easily made larger than the variation in resistance value among multiple semiconductor devices. Conversely, if the built-in resistor is too thick, its resistance value will be too low, which is not desirable.

[0129] "A16" further includes fingers arranged on the front surface side of the semiconductor device similarly to the control pads and extending from the control pads so as to divide the plurality of transistor cell regions into a plurality of regions; The semiconductor device according to any one of "A1" to "A15," wherein the built-in resistor electrically connects the control pad and the finger.

[0130] In this way, the features of the present invention can be effectively applied to devices in which fingers extend from the control pads.

[0131] [A17] The semiconductor device according to [A16], wherein the finger has a portion arranged to surround the periphery of the control pad.

[0132] [A18] The semiconductor device according to [A16], wherein the fingers are made of metal wiring. By configuring the fingers with metal wiring having lower resistance than polysilicon, it is possible to supply a control current in a short time even to cells located relatively far from the control pad.

[0133] [A19] The semiconductor device according to [A17], wherein the metal wiring is made of one of Al, AlCu, and Cu.

[0134] When the metal wiring is made of Al, Al is easy to process, so the finger formation process can be simplified. When the metal wiring is made of AlCu, power cycle resistance can be improved compared to when the fingers are made of Al wiring. When the metal wiring is made of Cu, resistivity can be reduced compared to when the fingers are made of Al wiring or AlCu wiring.

[0135] "A20" The transistor cell constitutes a MOSFET cell, the control pad is connected to a control electrode of the MOSFET cell; the main electrode pad is connected to the source electrode of the MOSFET cell; The semiconductor device according to any one of "A1" to "A19", further comprising a drain electrode formed on a back surface side of the SiC semiconductor layer.

[0136] [A21] The semiconductor device according to [A20], wherein the MOSFET cell includes a planar gate structure.

[0137] [A22] The semiconductor device according to [A20], wherein the MOSFET cell includes a trench gate structure.

[0138] "A23" The transistor cell constitutes an IGBT cell, the control pad is connected to a control electrode of the IGBT cell; the main electrode pad is connected to the emitter electrode of the IGBT cell; The semiconductor device according to any one of "A1" to "A19", further comprising a collector electrode formed on a back surface side of the SiC semiconductor layer.

[0139] [A24] The semiconductor device according to any one of [A1] to [A23], wherein the plurality of transistor cells are arranged in a lattice pattern.

[0140] "A25" semiconductor layer, a plurality of transistor cells formed on the surface side of the semiconductor layer, the transistor cells being controlled to be on / off by receiving a control voltage input to a control pad at a control electrode; a finger extending from the control pad so as to divide the area in which the plurality of transistor cells are formed into a plurality of areas, and electrically connected to the control pad; a built-in resistor disposed closer to the semiconductor layer than the control pad and the finger, electrically connecting the control pad and the finger, and made of a material having a resistance value the same as but greater than that of the finger; a first wire region is selectively formed on the surface of the control pad, the first wire region being exposed from a surface insulating film formed on the outermost surface and to which a bonding wire is bonded; the built-in resistor is selectively disposed in a region avoiding the first wire region in a plan view seen from a normal direction of the semiconductor layer; a main electrode pad, which is connected to one main electrode of each of the plurality of transistor cells and is different from the control pad, is disposed above the plurality of transistor cells; A second wire region, which is exposed from the surface insulating film and to which a bonding wire is connected, is selectively formed on the surface of the main electrode pad.

[0141] [A26] The semiconductor device according to [A25], wherein the built-in resistor is made of metal.

[0142] [A27] A semiconductor module comprising a plurality of semiconductor devices according to any one of [A1] to [A26] connected in parallel. [Explanation of symbols]

[0143] 1. Semiconductor device 2. Active Area 4 Gate Pad 5 Gate Finger 7 Inner cell area 12 Pad periphery 13 First Finger 14 Second Finger 15 Main parts 16 Branch 18 transistor cells 19 Gate electrode 20 gate contacts 21 Built-in resistor 22 Pad side contact 23 Cell side contact 24 Periphery 27 SiC substrate 28 SiC epitaxial layer 29 pages - Type Body Area 30n + Type Body Area 31 pages + Mold body contact area 32 channel region 33 pages + type area 34 pages -type area 35 Gate insulating film 36 Interlayer Film 37 Pad side contact 38 Pad side contact 39 Gate Trench 44 Gate Metal

Claims

1. a SiC semiconductor layer including an active region and a termination region surrounding the active region; a plurality of transistor cells formed in a cell region of an active region of the SiC semiconductor layer and controlled to be turned on / off by a predetermined control voltage; a gate electrode facing a channel region of the transistor cell in which a channel is formed when the transistor cell is turned on; a gate metal including a gate pad exposed on the outermost surface for electrical connection to the outside, the gate pad being physically separated from the gate electrode but electrically connected to the gate electrode; a built-in resistor electrically connecting the gate metal and the gate electrode and made of a material having a resistance value greater than that of the gate metal; In the region other than the cell region in the active region, p is formed on the surface portion of the SiC semiconductor layer. － A type region is formed, and the p － The surface of the mold region is ＋ A mold region is formed, The p ＋ The p-type region is formed in a region of the SiC semiconductor layer facing the built-in resistor. － p in the type domain － The mold portion is selectively exposed on the SiC surface, The semiconductor device, wherein the built-in resistors are arranged symmetrically with respect to each other in a plan view seen from a normal direction of the SiC semiconductor layer.

2. a SiC semiconductor layer including an active region and a termination region surrounding the active region; a plurality of transistor cells formed in a cell region of an active region of the SiC semiconductor layer and controlled to be turned on / off by a predetermined control voltage; a gate electrode facing a channel region of the transistor cell in which a channel is formed when the transistor cell is turned on; a gate metal including a gate pad exposed on the outermost surface for electrical connection to the outside, the gate pad being physically separated from the gate electrode but electrically connected to the gate electrode; a built-in resistor electrically connecting the gate metal and the gate electrode and made of a material having a resistance value greater than that of the gate metal; a source metal; In the region other than the cell region in the active region, p is formed on the surface portion of the SiC semiconductor layer. － A type region is formed, and the p － The surface of the mold region is ＋ A mold region is formed, The p ＋ The p-type region is formed in a region of the SiC semiconductor layer facing the built-in resistor. － p in the type domain － The mold portion is selectively exposed on the SiC surface, The transistor cell is p ＋ a mold body contact region; The semiconductor device, wherein the p + -type body contact region and the source metal are fixed to a ground potential.

3. a SiC semiconductor layer including an active region and a termination region surrounding the active region; a plurality of transistor cells formed in a cell region of an active region of the SiC semiconductor layer and controlled to be turned on / off by a predetermined control voltage; a gate electrode facing a channel region of the transistor cell in which a channel is formed when the transistor cell is turned on; a gate metal including a gate pad exposed on the outermost surface for electrical connection to the outside, the gate pad being physically separated from the gate electrode but electrically connected to the gate electrode; a built-in resistor electrically connecting the gate metal and the gate electrode and made of a material having a resistance value greater than that of the gate metal; In the region other than the cell region in the active region, p is formed on the surface portion of the SiC semiconductor layer. － A type region is formed, and the p － The surface of the mold region is ＋ A mold region is formed, The p ＋ The p-type region is formed in a region of the SiC semiconductor layer facing the built-in resistor. － p in the type domain － The mold portion is selectively exposed on the SiC surface, further comprising a gate finger extending from the gate metal; the gate metal is selectively formed in a portion of the periphery of the active region near the boundary with the termination region, the gate finger extends from a position where the gate pad is formed in a direction along a periphery of the active area and in a direction toward an inside of the active area; In the active region, an inner cell region and an outer cell region are formed in a portion partitioned by a plurality of the gate fingers extending in different directions with the gate metal sandwiched therebetween, and in an outer region of the gate fingers, respectively.

4. a SiC semiconductor layer including an active region and a termination region surrounding the active region; a plurality of transistor cells formed in a cell region of an active region of the SiC semiconductor layer and controlled to be turned on / off by a predetermined control voltage; a gate electrode facing a channel region of the transistor cell in which a channel is formed when the transistor cell is turned on; a gate metal including a gate pad exposed on the outermost surface for electrical connection to the outside, the gate pad being physically separated from the gate electrode but electrically connected to the gate electrode; a built-in resistor electrically connecting the gate metal and the gate electrode and made of a material having a resistance value greater than that of the gate metal; In the region other than the cell region in the active region, p is formed on the surface portion of the SiC semiconductor layer. － A type region is formed, and the p － The surface of the mold region is ＋ A mold region is formed, The p ＋ The p-type region is formed in a region of the SiC semiconductor layer facing the built-in resistor. － p in the type domain － The mold portion is selectively exposed on the SiC surface, The semiconductor device, wherein the gate electrode and the built-in resistor are both made of p-type polysilicon.

5. a SiC semiconductor layer including an active region and a termination region surrounding the active region; a plurality of transistor cells formed in a cell region of an active region of the SiC semiconductor layer and controlled to be turned on / off by a predetermined control voltage; a gate electrode facing a channel region of the transistor cell in which a channel is formed when the transistor cell is turned on; a gate metal including a gate pad exposed on the outermost surface for electrical connection to the outside, the gate pad being physically separated from the gate electrode but electrically connected to the gate electrode; a built-in resistor electrically connecting the gate metal and the gate electrode and made of a material having a resistance value greater than that of the gate metal; In the region other than the cell region in the active region, p is formed on the surface portion of the SiC semiconductor layer. － A type region is formed, and the p － The surface of the mold region is ＋ A mold region is formed, The p ＋ The p-type region is formed in a region of the SiC semiconductor layer facing the built-in resistor. － p in the type domain － The mold portion is selectively exposed on the SiC surface, The cell region includes an outer annular cell region formed along the periphery of the active region.

6. The semiconductor device according to any one of claims 2 to 5, wherein the built-in resistors are arranged symmetrically with each other in a plan view seen from a normal direction of the SiC semiconductor layer.

7. 7. The semiconductor device according to claim 1, wherein the built-in resistor is made of polysilicon.

8. 8. The semiconductor device according to claim 1, wherein the gate metal is selectively disposed in a center portion of one side of the active region.

9. The transistor cell is p ＋ a mold body contact region; the semiconductor device includes a source metal; The p ＋ 6. The semiconductor device according to claim 1, wherein a body contact region is fixed to a ground potential together with the source metal.

10. The transistor cell is p － including a type body region, the source metal includes a source pad; The p ＋ type region and the p － The p-type regions are formed so as to extend to below the source metal, and below a portion of the source metal that is outward from the source pad. ＋ the body contact region and the p － 10. The semiconductor device according to claim 2, wherein the first and second gate electrodes are integrally connected to the first and second body regions.

11. further comprising a gate finger extending from the gate metal; the gate metal is selectively formed in a portion of the periphery of the active region near the boundary with the termination region, the gate finger extends from a position where the gate pad is formed in a direction along a periphery of the active area and in a direction toward an inside of the active area; 6. The semiconductor device according to claim 1, wherein an inner cell region and an outer cell region are formed in the active region in a portion partitioned by a plurality of the gate fingers extending in different directions with the gate metal therebetween and in an outer region of the gate fingers, respectively.

12. The area facing the built-in resistor is 1×10 １９ cm －３ The p having the following impurity concentration － The semiconductor device according to any one of claims 1 to 11, which is a mold region.

13. 12. The semiconductor device according to claim 3, further comprising a source metal, the source metal being formed so as to cover substantially the entire inner cell region and the outer cell region.

14. 6. The semiconductor device according to claim 1, wherein said gate electrode and said built-in resistor are both made of p-type polysilicon.

15. 5. The semiconductor device according to claim 1, wherein said cell region includes an outer annular cell region formed along a periphery of said active region.

16. The p ＋ The impurity concentration and depth of the p-type region are ＋ The impurity concentration and depth of the p-type body contact region are the same as those of the p-type body contact region. － The impurity concentration and depth of the p-type region are － 11. The semiconductor device according to claim 10, wherein the impurity concentration and depth of the second body region are the same as those of the first body region.

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