Semiconductor Devices

Abstract

To provide a semiconductor device that can be mass-produced even in a configuration that has a gate electrode on the rear surface side.SOLUTION: A semiconductor device includes: a first control electrode and a second control electrode for switching which are provided on a first principal surface and a second principal surface of a semiconductor substrate; a first control electrode pad which is electrically connected to the first control electrode; a first through via which penetrates the semiconductor substrate in the thickness direction and has a conductor therein that electrically connects between the first principal surface and the second principal surface; and a second control electrode pad which is provided on the first principal surface and is electrically connected to the second control electrode through the first through via.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a double gate structure. [Background technology]

[0002] In order to improve the switching performance of an insulated gate bipolar transistor (IGBT), a double-gate IGBT has been developed in which a double-gate structure as disclosed in Patent Document 1 is applied to the IGBT.

[0003] The double-gate IGBT has a structure in which a gate electrode is formed on the main surface on the emitter electrode side, and a control gate electrode is formed on the main surface on the opposite side, on the collector electrode side. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-34506 Summary of the Invention [Problem to be solved by the invention]

[0005] In the double-gate IGBT disclosed in Patent Document 1, a control gate electrode pad electrically connected to the control gate electrode is exposed on the back surface, which is the collector electrode side.

[0006] However, the technique of connecting wiring to the control gate electrode pad on the back surface by wire bonding has the problem that it is not suitable for mass production, although it is suitable for small-scale production.

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can be mass-produced even in a configuration in which a gate electrode is provided on the back surface side. [Means for solving the problem]

[0008] A semiconductor device according to the present disclosure is a semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface opposing each other, and includes: a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first main surface; a third semiconductor layer of the first conductivity type selectively provided on the first main surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided between the first semiconductor layer and the second main surface; a fifth semiconductor layer of the first conductivity type selectively provided on the second main surface side of the fourth semiconductor layer; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a first control electrode that switches conduction and non-conduction between the first semiconductor layer and the third semiconductor layer in response to a first control signal; a second control electrode that switches conduction and non-conduction between the first semiconductor layer and the fifth semiconductor layer in response to a second control signal; a first control electrode pad that is provided on the first main surface and electrically connected to the first control electrode; a voltage-resistant structure that is provided in a termination region that surrounds an area where the first main electrode and the first control electrode pad are provided; a first through via that penetrates the semiconductor substrate in a thickness direction and has a conductor therein that electrically connects the first main surface and the second main surface; and a second control electrode pad that is provided on the first main surface and electrically connected to the second control electrode via the first through via. The first through via is provided in a peripheral region closer to a side surface of the semiconductor substrate than the breakdown voltage holding structure in the termination region, and the second control electrode pad is provided so as to surround the peripheral region. do. [Effects of the Invention]

[0009] According to the semiconductor device of the present disclosure, only the second main electrode is exposed on the second main surface of the semiconductor substrate, and the second control electrode pad is provided on the first main surface. Therefore, the electrode pattern on the second main surface is the same as that of conventional semiconductor devices, and wiring can be performed using conventional soldering and wire bonding techniques, making mass production possible. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view showing a front surface pattern of a double-gate RC-IGBT according to a first embodiment of the present disclosure. [Figure 2] 1 is a plan view showing a rear surface pattern of a double-gate RC-IGBT according to a first embodiment of the present disclosure. [Figure 3] 1 is a partial cross-sectional view of a double-gate RC-IGBT according to a first embodiment of the present disclosure. [Figure 4] FIG. 10 is a plan view showing a front surface pattern of a double-gate RC-IGBT according to a second embodiment of the present disclosure. [Figure 5] FIG. 10 is a partially enlarged view of a front surface pattern of a double-gate RC-IGBT according to a second embodiment of the present disclosure. [Figure 6] FIG. 10 is a plan view showing a front surface pattern of a double-gate RC-IGBT according to a modification of the second embodiment of the present disclosure. [Figure 7] FIG. 10 is a partially enlarged view of a front surface pattern of a double-gate RC-IGBT according to a modification of the second embodiment of the present disclosure. [Figure 8] FIG. 11 is a plan view showing a front surface pattern of a double-gate RC-IGBT according to a third embodiment of the present disclosure. [Figure 9] FIG. 11 is a partial cross-sectional view of a double-gate RC-IGBT according to a third embodiment of the present disclosure. [Figure 10] FIG. 11 is a plan view showing a rear surface pattern of a double-gate RC-IGBT according to a third embodiment of the present disclosure. [Figure 11] FIG. 10 is a plan view showing a front surface pattern of a double-gate RC-IGBT according to a fourth embodiment of the present disclosure. [Figure 12]FIG. 11 is a partial cross-sectional view of a double-gate RC-IGBT according to a fourth embodiment of the present disclosure. [Figure 13] FIG. 11 is a plan view showing a rear surface pattern of a double-gate RC-IGBT according to a fourth embodiment of the present disclosure. [Figure 14] FIG. 11 is a plan view showing a front surface pattern of a double-gate RC-IGBT according to a fifth embodiment of the present disclosure. [Figure 15] FIG. 11 is a partially enlarged view of a front surface pattern of a double-gate RC-IGBT according to a fifth embodiment of the present disclosure. [Figure 16] FIG. 11 is a partially enlarged view of a front surface pattern of a double-gate RC-IGBT according to a fifth embodiment of the present disclosure. [Figure 17] FIG. 11 is a partial cross-sectional view of a double-gate RC-IGBT according to a fifth embodiment of the present disclosure. [Figure 18] FIG. 11 is a partial cross-sectional view of a double-gate RC-IGBT according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - The n type indicates that the impurity concentration is lower than that of the n type. + The p type indicates that the impurity concentration is higher than that of the n type. - The impurity concentration is lower than that of p-type, and p + The type indicates that the impurity concentration is higher than that of the p-type.

[0012] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0013] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0014] In the following description, "outside" refers to the direction toward the outer periphery of the semiconductor substrate, and "inside" refers to the opposite direction to "outside".

[0015] In the following explanation, a double-gate RC-IGBT in which a double-gate IGBT is provided in the IGBT region will be used as an example of a reverse conducting IGBT (RC-IGBT) in which the IGBT and free wheeling diode (FWD) are provided on a common semiconductor substrate. However, the application of the present disclosure is not limited to this, and can also be applied to a double-gate IGBT in which the IGBT is provided alone on a semiconductor substrate, and to a double-gate metal-oxide semiconductor field effect transistor (MOSFET).

[0016] Furthermore, in this disclosure, the diode region in which the freewheeling diode is provided is not relevant to the present disclosure, and therefore is not shown in the drawings.

[0017] In addition, the following describes an example of a double-gate RC-IGBT having trench gate electrodes as the gate electrode and the control gate electrode, but the application of the present disclosure is not limited to this, and the present disclosure can also be applied to a configuration in which one or both of the gate electrode and the control gate electrode are planar gate electrodes.

[0018] <First Embodiment> FIG. 1 is a plan view showing a front pattern 101 on which an emitter electrode 6 (first main electrode) of a double-gate RC-IGBT 100 according to a first embodiment of the present disclosure is arranged.

[0019] As shown in FIG. 1 , a pad region 40, which is a pad arrangement region, is provided adjacent to the IGBT region 10 on the lower side of the page. The pad region 40 is an area where a control pad 41 for controlling the double-gate RC-IGBT 100 is provided. The IGBT region 10 and a diode region (not shown) are collectively referred to as the cell region. A termination region 30 is provided around the combined area of ​​the cell region and pad region 40 to maintain the breakdown voltage of the double-gate RC-IGBT 100. A well-known breakdown voltage maintenance structure can be appropriately selected and provided in the termination region 30. For example, the breakdown voltage maintenance structure can be configured by providing a field limiting ring (FLR) on the first main surface side, which is the front side of the double-gate RC-IGBT 100, in which the cell region is surrounded by a p-type termination well layer of a p-type semiconductor, and a variation of lateral doping (VLD) on which the cell region is surrounded by a p-type well layer with a concentration gradient.

[0020] The control pads 41 may include, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting the current flowing in the cell region, and is electrically connected to some IGBT cells or diode cells in the cell region so that when a current flows in the cell region, a current that is one fraction to one tens of thousands of the current flowing in the entire cell region flows.

[0021] The Kelvin emitter pad 41b and gate pad 41c (first control electrode pad) are control pads to which a gate drive voltage is applied to control the on / off state of the double-gate RC-IGBT 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the double-gate RC-IGBT 100. The temperature of the double-gate RC-IGBT 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0022] In the termination region 30, a plurality of termination electrodes 6a are provided concentrically as a breakdown voltage holding structure outside the combined region of the cell region and pad region 40. In the peripheral region further outside the termination electrodes 6a, a final back surface gate pad 42f (second control electrode pad) is provided so as to surround the peripheral region, and a through silicon via 44 (first through via) is provided below one corner of the final back surface gate pad 42f. Note that the through silicon via 44 is covered by the final back surface gate pad 42f and cannot be seen from above, but is shown by a dashed line for convenience.

[0023] 2 is a plan view showing a back surface pattern 102 on which a collector electrode 7 (second main electrode) of a double-gate RC-IGBT 100 is arranged, and is a plan view when viewed from the front side, omitting everything other than the collector electrode 7. Note that all of the plan views of the back surface pattern 102 below are plan views when viewed from the front side, omitting everything other than the collector electrode 7. As shown in FIG. 2, a through-silicon via 44 is provided in a portion corresponding to one corner of the collector electrode 7.

[0024] 3 shows a cross-sectional view of the double-gate RC-IGBT 100 taken along the dashed line EE shown in FIG. 1. In FIG. 3, the double-gate RC-IGBT 100 is an n-type IGBT made of a semiconductor substrate. - The n-type drift layer 1 (first semiconductor layer) is- The type drift layer 1 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 is.

[0025] <IGBT region> As shown in FIG. 3, in the IGBT region 10, a plurality of active trench gates 11 are provided in a stripe shape with a gap therebetween on the first main surface side which is the upper surface of the semiconductor substrate.

[0026] The active trench gate 11 is configured by providing a gate trench electrode 11a (first control electrode) via a gate trench insulating film 11b in a trench formed in the semiconductor substrate. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c (first gate pad) shown in FIG. 1, and a gate signal G1 (first control signal) is supplied to the gate trench electrode 11a.

[0027] n + type source layer 13 (third semiconductor layer) is provided in contact with the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. n + type source layer 13 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 is.

[0028] Also, as shown in FIG. 3, in the IGBT region 10, on the first main surface side of the n - type drift layer 1, an n - type carrier accumulation layer 2 having a higher concentration of n-type impurity than the n 13 / cm 3 ~1.0×1017 / cm 3 By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The combined layer and the type drift layer 1 can also be called a drift layer.

[0029] A p-type base layer 15 (second semiconductor layer) is provided on the first principal surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, there is provided an n-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11. + A type source layer 13 is provided. + The source layer 13 forms a first major surface of the semiconductor substrate.

[0030] In Figure 3, n + Only the source layer 13 is connected to the emitter electrode 6, but the p + The mold contact layer is connected to the emitter electrode 6 .

[0031] The gate trench electrode 11a is connected to the n-type gate electrode 11b via the gate trench insulating film 11b. - The gate trench insulating film 11b of the active trench gate 11 faces the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0032] An interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. The interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11, and is insulated from the emitter electrode 6 for input of the gate signal G1.

[0033] A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), and may be, for example, titanium nitride or TiSi, which is an alloy of titanium and silicon (Si). The barrier metal 5 may be n + ohmic contact with the n-type source layer 13, + The emitter electrode 6 is electrically connected to the n-type source layer 13. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or it can be an electrode composed of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating can be, for example, a nickel (Ni) plating film. Furthermore, if there are fine regions, such as between adjacent interlayer insulating films 4, where the emitter electrode 6 cannot be satisfactorily embedded, tungsten, which has better embedding properties than the emitter electrode 6, can be disposed in the fine regions, and the emitter electrode 6 can be provided on the tungsten. Note that, in the case where the barrier metal 5 is not provided, it is also possible to form an n-type source layer 13 on the tungsten. + An emitter electrode 6 can be provided on the n-type source layer 13. + The barrier metal 5 can be provided only on the n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 can be collectively called an emitter electrode.

[0034] As shown in FIG. 3, a plurality of active trench gates 18 (second gates) are provided in a stripe pattern at intervals on the second main surface side, which is the lower surface of the semiconductor substrate.

[0035] The active trench gate 18 is configured by providing a gate trench electrode 18a (second control electrode) via a gate trench insulating film 18b in a trench formed in a semiconductor substrate. The gate trench electrode 18a of the active trench gate 18 is electrically connected to a final backside gate pad 42f provided in the termination region 30 on the first main surface side, and a gate signal G2 (second control signal) is supplied to the gate trench electrode 18a.

[0036] As shown in FIG. 3, in the IGBT region 10, n - The second main surface side of the n-type drift layer 1 is + A p-type collector layer 19 (fifth semiconductor layer), a p-type collector layer 16 (fourth semiconductor layer), and an n-type buffer layer 3 are provided in this order from the second main surface of the semiconductor substrate, and these impurity layers are in contact with the gate trench insulating film 18b on both sides in the width direction of the active trench gate 18. The bottom of the active trench gate 18 is an n-type - The electrode extends into the drift layer 1.

[0037] The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 toward the second main surface from punching through when the double-gate RC-IGBT 100 is in an off state. The n-type buffer layer 3 is formed by doping, for example, phosphorus (P) or protons (H + ) can be implanted, or it can be formed by implanting both phosphorus and protons. The concentration of n-type impurities in the n-type buffer layer 3 is 1.0×10 12 / cm 3 ~1.0×10 18 / cm 3 is.

[0038] The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate.

[0039] n + The n-type collector layer 19 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 is.

[0040] In Figure 3, n + Only the p-type collector layer 19 is connected to the collector electrode 7, but the p-type collector layer 16 is connected to the collector electrode 7 in the depth direction of the drawing (not shown).

[0041] An interlayer insulating film 4 is provided on the gate trench electrode 18a of the active trench gate 18. The interlayer insulating film 4 is formed on the gate trench electrode 18a of the active trench gate 18, and is insulated from the collector electrode 7 for input of the gate signal G2.

[0042] A barrier metal 5 is formed on the region of the second main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4.

[0043] <Terminal area> As shown in FIG. 3, in the termination region 30, n - The termination region 30 has a first main surface and a second main surface which are flush with the first main surface and the second main surface of the IGBT region 10, respectively. - The n-type drift layer 1 is formed in the IGBT region 10. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0044] n - The first main surface side of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate, and - A p-type termination well layer 31 is provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×1014 / cm 3 ~1.0×10 19 / cm 3 A plurality of p-type termination well layers 31 are provided concentrically surrounding the cell region including the IGBT region 10. The number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the double gate RC-IGBT 100. In addition, p + A p-type contact layer 32 is provided. + The p-type contact layer 32 surrounds the p-type termination well layer 31 .

[0045] n - Between the n-type drift layer 1 and the second main surface of the semiconductor substrate, an n-type buffer layer 3, a p-type collector layer 16, and an n-type + A collector layer 19 is provided extending from the IGBT region 10, + The mold collector layer 19 only extends to the area in the termination region 30 where the active trench gate 18 is partially located.

[0046] At the boundary between the IGBT region 10 and the termination region 30, a plurality of dummy trench gates 12 having a cross section similar to that of the active trench gate 11 are provided on the first main surface side of the semiconductor substrate. The dummy trench gates 12 are provided in a stripe pattern similar to the active trench gates 11. At least one of the dummy trench gates 12 is provided in the p-type termination well layer 31.

[0047] The tops of the multiple dummy trench gates 12 are covered with a continuous interlayer insulating film 4, and the multiple dummy trench gates 12 are electrically connected to the emitter electrode 6 via contacts that penetrate the interlayer insulating film 4 in a portion not shown.

[0048] In the termination region 30, an emitter electrode 6 continuing from the IGBT region 10 and a plurality of termination electrodes 6a separated from the emitter electrode 6 are provided. The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 can be formed of, for example, sinSiN (semi-insulating silicon nitride). The termination electrode 6a, the p-type termination well layer 31, and the p + The emitter electrode 6 is electrically connected to the mold contact layer 32 via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the termination region 30. In addition, a termination protective film 34 is provided in the termination region 30 to cover the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33. The termination protective film 34 can be made of, for example, polyimide.

[0049] In the outer peripheral region outside the end face of the termination protective film 34, a final back surface gate pad 42f is provided in the same layer as the emitter electrode 6, and the final back surface gate pad 42f is electrically connected to a silicon through via 44 that penetrates the semiconductor substrate in the thickness direction.

[0050] Termination area 30 So An interlayer insulating film 4 is continuously provided on the second main surface of the semiconductor substrate, and the interlayer insulating film 4 is covered with a barrier metal 5. A through-silicon via 44 is provided to penetrate the barrier metal 5 and the interlayer insulating film 4.

[0051] The through silicon via 44 is composed of a through silicon via insulating film 44b that covers the inner surface of a via hole that penetrates the semiconductor substrate in the thickness direction, and a through silicon via electrode 44a that covers the inner surface of the through silicon via insulating film 44b, and on the second main surface side, the through silicon via electrode 44a is provided so as to also cover the barrier metal 5 around the via hole. The through silicon via electrode 44a that covers the barrier metal 5 around the via hole can be called a backside gate pad 46.

[0052] The gate trench electrode 18a of the active trench gate 18 is electrically connected to the through-silicon via electrode 44a via a contact (not shown) that penetrates the interlayer insulating film 4. The through-silicon via electrode 44a is connected to the barrier metal 5 on the first main surface side and electrically connected to the final backside gate pad 42f via the barrier metal 5, so that a gate signal G2 is supplied to the gate trench electrode 18a.

[0053] The through silicon via 44 and the back surface gate pad 46 around it are covered with an interlayer insulating film 4a and are electrically isolated from the collector electrode 7 covering thereon.

[0054] 3, the through silicon via electrode 44a covers the inner surface of the through silicon via insulating film 44b and is not filled into the through silicon via 44, leaving the inside of the through silicon via 44 hollow, but this is not limiting. For example, the through silicon via 44 can be filled with the through silicon via electrode 44a, or the through silicon via 44 can be filled with an insulator or a semiconductor. As long as the through silicon via 44 is electrically connected to the final back surface gate pad 42f via the through silicon via electrode 44a, the inside of the through silicon via 44 can be filled with something or hollow.

[0055] The material of the through-silicon via electrode 44a is not limited as long as it is a low-resistance conductor, and examples thereof include polysilicon, doped polysilicon, and metals such as copper and aluminum. Also, examples of the manufacturing method that can be used include plating, CVD (chemical vapor deposition), evaporation, and sputtering.

[0056] As shown in FIG. 3, the gate trench electrode 18a of the active trench gate 18 is electrically connected to a final back surface gate pad 42f provided on the first main surface side via a silicon through via 44, and only the collector electrode 7 is exposed on the back surface of the double-gate RC-IGBT 100.

[0057] This prevents short circuits between the back gate and collector electrode, which can occur when mounting a double-gate RC-IGBT chip, and therefore the circuit pattern of the circuit-patterned ceramic substrate on which the double-gate RC-IGBT chip is mounted can avoid restrictions imposed by the back pattern on the chip side.

[0058] Furthermore, since the wiring path from the back surface gate pad 46 to the final back surface gate pad 42f is formed by the through-silicon via electrode 44a, its length is approximately the thickness of the semiconductor substrate, and the wiring path is short, resulting in small parasitic inductance and enabling high-speed control.

[0059] In double-gate RC-IGBTs, injection carrier control, which controls the amount of carriers in the semiconductor using the gate on the back side, i.e., the control gate, can be performed with a pulse waveform of a few microseconds or less, so the double-gate RC-IGBT100, which allows high-speed control, is extremely advantageous.

[0060] In addition, the back surface pattern of the double gate RC-IGBT100 has only the collector electrode exposed, just like conventional RC-IGBTs, so chip wiring can be done using conventional soldering and wire bonding techniques, eliminating the need for new equipment and enabling mass production.

[0061] Furthermore, since through silicon via 44 is provided in the peripheral region that becomes the collector potential portion, the thickness of through silicon via insulating film 44b can be made thin. Also, since it is not between the main electrodes, leakage current can be kept small.

[0062] Furthermore, as shown in FIG. 1, since the through silicon via 44 is provided below one corner of the final back surface gate pad 42f, the diameter of the through silicon via 44 can be increased, which reduces the wiring resistance and improves reliability.

[0063] Furthermore, by providing the through silicon via 44 below the final back surface gate pad 42f, the final back surface gate pad 42f and the through silicon via 44 can be connected in the shortest distance, thereby reducing the wiring resistance.

[0064] The electrical resistance of the through silicon via 44 can be set arbitrarily by selecting the material of the through silicon via electrode 44a. That is, the through silicon via 44 can be used as a resistor. Therefore, by setting the electrical resistance of the wiring path connecting to the final back surface gate pad 42f via the through silicon via 44 to 1 Ω or more and 100 Ω or less, it becomes unnecessary to connect an external gate resistor to the active trench gate 18.

[0065] <Embodiment 2> 4 is a plan view showing a front surface pattern 101 on which an emitter electrode 6 of a double-gate RC-IGBT 200 according to a second embodiment of the present disclosure is arranged. In the double-gate RC-IGBT 100 shown in FIG. 1, a through-silicon via 44 is provided under one corner of the final back surface gate pad 42f, and this corner has the same size as the other three corners. difference On the other hand, in the double-gate RC-IGBT 200 shown in FIG. 4, the corner of the final back surface gate pad 42f where the through silicon via 44 is provided has a larger area than the other three corners. This makes it possible to increase the diameter of the through silicon via 44 or to provide space around the through silicon via 44. Furthermore, by increasing the size of the corner of the final back surface gate pad 42f where the through silicon via 44 is provided, the area for wire bonding becomes larger, making wire bonding easier.

[0066] Fig. 5 is an enlarged view of a corner of final backside gate pad 42f provided with through silicon via 44 in Fig. 4. Note that through silicon via 44 is covered by final backside gate pad 42f and cannot be seen from above, but is shown by a dashed line for convenience.

[0067] 6 is a plan view showing a front surface pattern 101 on which an emitter electrode 6 of a double-gate RC-IGBT 201 according to a modification of the second embodiment of the present disclosure is arranged. In the double-gate RC-IGBT 201 shown in FIG. 6, the through silicon via 44 is provided in a part of one side of the final back surface gate pad 42f that is enlarged. This allows the diameter of the through silicon via 44 to be increased, or allows for more space to be provided around the through silicon via 44.

[0068] Fig. 7 is an enlarged view of a portion of one side of the final back surface gate pad 42f provided with the through silicon via 44 in Fig. 6. Note that the through silicon via 44 is covered by the final back surface gate pad 42f and cannot be seen from above, but is shown by a dashed line for convenience.

[0069] <Third Embodiment> 8 is a plan view showing a front surface pattern 101 on which an emitter electrode 6 of a double-gate RC-IGBT 300 according to a third embodiment of the present disclosure is arranged. As shown in FIG. 8, in the double-gate RC-IGBT 300, through-silicon vias 44 are provided at the bottoms of two diagonally opposite corners of a final back surface gate pad 42f.

[0070] Two diagonally opposite corners of the final back surface gate pad 42f are connected to each other by the final back surface gate pad 42f that goes around the outer periphery of the termination region 30, resulting in a low resistance and highly reliable connection.

[0071] Fig. 9 shows a cross-sectional view taken along dashed line FF of the double-gate RC-IGBT 300 shown in Fig. 8. The cross-sectional view taken along dashed line EE in Fig. 9 is the same as that in Fig. 3, but the cross-section taken along dashed line FF is a cross-section at the boundary between the pad region 40 and the termination region 30, and as shown in Fig. 9, no active trench gate 11 is provided in the pad region 40. The cross-section of the termination region 30 is the same as that of the termination region 30 shown in Fig. 3.

[0072] FIG. 10 is a plan view showing the rear surface pattern 102 on which the collector electrode 7 of the double-gate RC-IGBT 300 is arranged. 10 As shown in Fig. 8, the two through-silicon vias 44 are electrically connected to each other by a backside gate wiring 43 that is provided so as to surround the outer peripheral region of the termination region 30 (Fig. 8). The backside gate wiring 43 not only surrounds the outer peripheral region of the termination region 30 but also crosses the cell region, resulting in low resistance and high reliability. By increasing the number of parallel wirings, the resistance of the backside gate wiring 43 can be further reduced.

[0073] The location where the silicon through via 44 is provided is not limited to the bottom of two diagonally opposite corners of the final back surface gate pad 42f, but can also be provided in each of the enlarged portions of two sides of the final back surface gate pad 42f.

[0074] Furthermore, the number of through silicon vias 44 is not limited to 2. Increasing the number of through silicon vias 44 can reduce wiring resistance and increase reliability.

[0075] <Fourth Embodiment> 11 is a plan view showing a front surface pattern 101 on which an emitter electrode 6 of a double-gate RC-IGBT 400 according to a fourth embodiment of the present disclosure is arranged. In the double-gate RC-IGBT 400 as shown in FIG. 11 , a through silicon via 44 is provided under one corner of a final back surface gate pad 42 f, but a through silicon via 44 is not provided under the corner diagonally opposite to the corner in question, and the final back surface gate pad 42 f in that portion is used as a wire bonding region 47.

[0076] Fig. 12 shows a cross section of the double-gate RC-IGBT 400 shown in Fig. 11 taken along dashed line GG. As shown in Fig. 12, no through silicon via 44 is provided below the final back surface gate pad 42f.

[0077] The portion where the through silicon via 44 is provided is structurally weak, and differences in the configuration of the film formed on the semiconductor substrate may result in a difference in thickness between the portion where the through silicon via 44 is provided and other portions. Therefore, by designating the region other than the portion where the through silicon via 44 is provided as wire bonding region 47, it is possible to prevent cracks and the like from occurring during bonding.

[0078] 13 is a plan view showing a back surface pattern 102 on which a collector electrode 7 of a double-gate RC-IGBT 400 is arranged. As shown in Fig. 13, the through silicon via 44 is electrically connected to the back surface gate wiring 43 provided so as to surround the outer peripheral region of the termination region 30 (Fig. 11), and the back surface gate wiring 43 is also provided so as to cross the cell region. Therefore, as long as the through silicon via 44 and the wire bonding region 47 do not overlap, their relative positions can be freely set, and they can be provided, for example, at the same corner but at different positions.

[0079] <Fifth Embodiment> 14 is a plan view showing a front surface pattern 101 on which an emitter electrode 6 of a double-gate RC-IGBT 500 according to a fifth embodiment of the present disclosure is arranged. As shown in FIG. 14, in the double-gate RC-IGBT 500, a collector sense pad 42g (main electrode pad) is provided in an outer peripheral region further outside the termination electrode 6a, and a through silicon via 45 (second through via) is provided below a part of one side of the collector sense pad 42g. Note that the through silicon via 45 is covered by the collector sense pad 42g and cannot be seen from above, but is shown by a dashed line for convenience.

[0080] Furthermore, a final back surface gate pad 42f is provided at one corner of the double-gate RC-IGBT chip, and a through silicon via 44 is provided below the final back surface gate pad 42f. Note that the through silicon via 44 is covered by the final back surface gate pad 42f and cannot be seen from above, but is shown by a dashed line for convenience.

[0081] Fig. 15 is an enlarged view of a corner where the final rear surface gate pad 42f is provided in Fig. 14. The final rear surface gate pad 42f is electrically isolated from the collector sense pad 42g, and the collector sense pad 42g is electrically isolated from the termination electrode 6a.

[0082] Fig. 16 is an enlarged view of a part of one side of the collector sense pad 42g in Fig. 14. The collector sense pad 42g is electrically connected to the collector electrode 7 through a silicon through via 45, and therefore the collector voltage C The wiring for monitoring the collector voltage C can be provided on the front surface of the double gate RC-IGBT chip, making it easy to monitor the collector voltage C.

[0083] Furthermore, since through silicon via 45 is provided in the peripheral region that becomes the collector potential portion, the thickness of through silicon via insulating film 45b can be made thin. Also, since it is not between the main electrodes, leakage current can be kept small.

[0084] A cross-sectional view of the double-gate RC-IGBT 500 shown in Fig. 14 taken along dashed line HH is shown in Fig. 17, and a cross-sectional view of the double-gate RC-IGBT 500 taken along dashed line II is shown in Fig. 18. The cross-sectional configuration shown in Fig. 17 is the same as the cross-sectional configuration of the double-gate RC-IGBT 100 shown in Fig. 3.

[0085] 18, through silicon via 45 is composed of through silicon via insulating film 45b covering the inner surface of a via hole that penetrates the semiconductor substrate in the thickness direction, and through silicon via electrode 45a covering the inner surface of through silicon via insulating film 45b, and through silicon via electrode 45a covering the inner surface of through silicon via insulating film 45b on the second main surface side. Through silicon via electrode 45a is connected to barrier metal 5 on the first main surface side, and is electrically connected to collector sense pad 42g via barrier metal 5.

[0086] The through silicon via electrode 45a covering the barrier metal 5 around the via hole can be called a backside collector pad .

[0087] The through silicon via 45 and the surrounding back surface collector pad 48 are covered with a collector electrode 7, and the collector electrode 7 is electrically connected to a collector sense pad 42g via a through silicon via electrode 45a.

[0088] <Other application examples> In the first to fifth embodiments described above, through silicon vias 44 and through silicon vias 45 are formed in the termination region. 30 However, these may also be provided in pad region 40. Pad region 40 is an area where external wiring is connected to the double-gate RC-IGBT chip, so by arranging final back surface gate pad 42f and collector sense pad 42g together with through silicon vias 44 and through silicon vias 45, external wiring becomes easy.

[0089] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0090] The present disclosure described above will be summarized as an appendix.

[0091] (Appendix 1) A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface opposed to each other, a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first major surface; a third semiconductor layer of a first conductivity type selectively provided on the first principal surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second main surface; a fifth semiconductor layer of a first conductivity type selectively provided on the second principal surface side of the fourth semiconductor layer; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer and the fifth semiconductor layer; a first control electrode that switches between conduction and non-conduction between the first semiconductor layer and the third semiconductor layer in response to a first control signal; a second control electrode that switches between conduction and non-conduction between the first semiconductor layer and the fifth semiconductor layer in response to a second control signal; a first control electrode pad provided on the first main surface and electrically connected to the first control electrode; a breakdown voltage holding structure provided in a termination region surrounding an area where the first main electrode and the first control electrode pad are disposed; a first through via that penetrates the semiconductor substrate in a thickness direction and has a conductor therein that electrically connects the first main surface and the second main surface; a second control electrode pad provided on the first main surface and electrically connected to the second control electrode through the first through via.

[0092] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the first through via is provided in a peripheral region in the termination region that is closer to a side surface of the semiconductor substrate than the breakdown voltage holding structure.

[0093] (Appendix 3) The first through via is 3. The semiconductor device according to claim 2, wherein the semiconductor device is provided at a position corresponding to a corner of the semiconductor substrate.

[0094] (Appendix 4) The first through via is 3. The semiconductor device according to claim 2, wherein the termination region is provided at a plurality of positions.

[0095] (Appendix 5) The first through via is 3. The semiconductor device according to claim 2, wherein the second control electrode pad is provided below the second control electrode pad.

[0096] (Appendix 6) The second control electrode pad is 6. The semiconductor device according to claim 5, further comprising a wire bonding region in a region below where the first through via is not provided.

[0097] (Appendix 7) The second control electrode pad is 3. The semiconductor device according to claim 2, wherein the semiconductor device is provided so as to surround the outer periphery region.

[0098] (Appendix 8) The first through via is 3. The semiconductor device according to claim 2, wherein the second main surface is electrically connected to a wiring provided around the outer periphery region.

[0099] (Appendix 9) a second through via that penetrates the semiconductor substrate in a thickness direction and has a conductor therein that electrically connects the first main surface and the second main surface; 2. The semiconductor device according to claim 1, further comprising: a main electrode pad provided on the first main surface and electrically connected to the second main electrode via the second through via.

[0100] (Appendix 10) 10. The semiconductor device according to claim 9, wherein the second through via is provided in a peripheral region in the termination region that is closer to a side surface of the semiconductor substrate than the breakdown voltage holding structure.

[0101] (Appendix 11) 11. The semiconductor device according to claim 1, wherein the electrical resistance of a wiring path from the second control electrode through the first through via to the second control electrode pad is 1 Ω or more and 100 Ω or less. [Explanation of symbols]

[0102] 1n - 6 emitter electrode; 6a termination electrode; 7 collector electrode; 11a, 18a gate trench electrodes; 13 n +15 p-type source layer, 15 p-type base layer, 16 p-type collector layer, 19 n + Collector layer, 30 termination area, 40 pad area, 41c gate pad, 42f final backside gate pad, 42g collector sense pad, 43 backside gate wiring, 44, 45 through silicon vias, 47 wire bonding area.

Claims

1. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface opposed to each other, a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first major surface; a third semiconductor layer of a first conductivity type selectively provided on the first principal surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second major surface; a fifth semiconductor layer of a first conductivity type selectively provided on the second principal surface side of the fourth semiconductor layer; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer and the fifth semiconductor layer; a first control electrode that switches between conduction and non-conduction between the first semiconductor layer and the third semiconductor layer in response to a first control signal; a second control electrode that switches between conduction and non-conduction between the first semiconductor layer and the fifth semiconductor layer in response to a second control signal; a first control electrode pad provided on the first main surface and electrically connected to the first control electrode; a breakdown voltage holding structure provided in a termination region surrounding an area where the first main electrode and the first control electrode pad are disposed; a first through via that penetrates the semiconductor substrate in a thickness direction and has a conductor therein that electrically connects the first main surface and the second main surface; a second control electrode pad provided on the first main surface and electrically connected to the second control electrode via the first through via; the first through-via is provided in an outer periphery region in the termination region that is closer to a side surface of the semiconductor substrate than the breakdown voltage holding structure; The second control electrode pad is The semiconductor device is provided so as to surround the outer peripheral region.

2. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first major surface; a third semiconductor layer of a first conductivity type selectively provided on the first principal surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second major surface; a fifth semiconductor layer of a first conductivity type selectively provided on the second principal surface side of the fourth semiconductor layer; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer and the fifth semiconductor layer; a first control electrode that switches between conduction and non-conduction between the first semiconductor layer and the third semiconductor layer in response to a first control signal; a second control electrode that switches between conduction and non-conduction between the first semiconductor layer and the fifth semiconductor layer in response to a second control signal; a first control electrode pad provided on the first main surface and electrically connected to the first control electrode; a breakdown voltage holding structure provided in a termination region surrounding an area where the first main electrode and the first control electrode pad are disposed; a first through via that penetrates the semiconductor substrate in a thickness direction and has a conductor therein that electrically connects the first main surface and the second main surface; a second control electrode pad provided on the first main surface and electrically connected to the second control electrode via the first through via; the first through-via is provided in an outer periphery region in the termination region that is closer to a side surface of the semiconductor substrate than the breakdown voltage holding structure; The first through via is The semiconductor device is electrically connected to wiring provided on the second main surface so as to surround the outer peripheral region.

3. The first through via is 3. The semiconductor device according to claim 1, wherein the contact hole is provided at a position corresponding to a corner of the semiconductor substrate.

4. The first through via is 3. The semiconductor device according to claim 1, wherein the termination region is provided at a plurality of positions.

5. The first through via is 3. The semiconductor device according to claim 1, wherein the second control electrode pad is provided below the second control electrode pad.

6. The second control electrode pad is 6. The semiconductor device according to claim 5, further comprising a wire bonding region in a region below which said first through via is not provided.

7. a second through via that penetrates the semiconductor substrate in a thickness direction and has a conductor therein that electrically connects the first main surface and the second main surface; 3. The semiconductor device according to claim 1, further comprising: a main electrode pad provided on said first main surface and electrically connected to said second main electrode through said second through via.

8. 8. The semiconductor device according to claim 7, wherein said second through via is provided in an outer peripheral region in said termination region that is closer to a side surface of said semiconductor substrate than said breakdown voltage holding structure.

9. 9. The semiconductor device according to claim 1, wherein an electrical resistance of a wiring path from the second control electrode to the second control electrode pad via the first through via is 1 Ω or more and 100 Ω or less.

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