Semiconductor Devices

Abstract

To provide a semiconductor device capable of preferably reducing a turn-on power loss.SOLUTION: A semiconductor device comprises: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a higher doping concentration than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first storage region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a higher doping concentration than the drift region; a plurality of trench parts provided through the emitter region, the base region, and the first storage region from an upper surface of the semiconductor substrate and provided with a conductive part therein; and a capacitance addition unit provided below the first storage region and adding a gate-collector capacitance.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Documents 1 to 3). Patent Document 1: Japanese Patent Application Laid-Open No. 2007-311627 Patent Document 2 Special Publication No. 2014-61075 Patent Document 3: JP 2015-138884 A Summary of the Invention [Problem to be solved by the invention]

[0003] In the semiconductor device, Relief of electric field concentration It is preferable to do so. [Means for solving the problem]

[0004] A first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include a first semiconductor region of the first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region. The semiconductor device may include a second semiconductor region of a second conductivity type provided between the first semiconductor region and the drift region. The semiconductor device may include a plurality of trench portions arranged along a first direction on the front surface side of the semiconductor substrate and having extension portions extending along a second direction perpendicular to the first direction. The semiconductor device may include a mesa portion sandwiched between two trench portions. At least one of the plurality of trench portions may have a first tapered portion, above a depth position of a lower surface of the second semiconductor region, whose width in the first direction decreases toward the upper side. The semiconductor device may include an emitter region of a first conductivity type provided above a drift region within the semiconductor substrate and having a doping concentration higher than that of the drift region. The semiconductor device may include a base region of a second conductivity type provided between the emitter region and the drift region within the semiconductor substrate. The semiconductor device may include a first accumulation region of the first conductivity type provided between the base region and the drift region within the semiconductor substrate and having a doping concentration higher than that of the drift region. The semiconductor device may include a plurality of trench portions provided from the upper surface of the semiconductor substrate through the emitter region, the base region, and the first accumulation region, and having conductive portions provided therein. The semiconductor device may include a capacitance adding portion provided below the first accumulation region and adding gate-collector capacitance.

[0005] The capacitance adding portion may have an accumulation region of a first conductivity type provided below the first accumulation region between the two trench portions and having a doping concentration higher than that of the drift region. The capacitance adding portion may have a plurality of accumulation regions of the first conductivity type in a depth direction of the semiconductor substrate, each having a doping concentration higher than that of the drift region. At least one accumulation region formed below the first accumulation region may have a doping concentration higher than that of the first accumulation region.

[0006] The peak position of the doping concentration distribution of the lowest accumulation region in the depth direction of the semiconductor substrate may be located above the lower end of the trench portion. The lower end of the lowest accumulation region may be located above the lower end of the trench portion. The peak position of the doping concentration distribution of the lowest accumulation region in the depth direction of the semiconductor substrate may be located below the center of the trench portion.

[0007] In the accumulation regions other than the first accumulation region, the lower accumulation regions may have a higher doping concentration than the upper accumulation regions.

[0008] In a depth direction of the semiconductor substrate, a distance between the first accumulation region and the accumulation region arranged next to the first accumulation region may be greater than a distance between the lowest accumulation region and the second lowest accumulation region, and a doping concentration in a region between the first accumulation region and the accumulation region arranged next to the first accumulation region may be higher than a doping concentration in the drift region.

[0009] The minimum doping concentration in the region between the first accumulation region and the next accumulation region may be 1 / 10 or less of the peak doping concentration of the first accumulation region. The first accumulation region may contain phosphorus as a dopant, and the accumulation regions other than the first accumulation region may contain hydrogen as a dopant.

[0010] The trench portion may include a trench extending from the upper surface of the semiconductor substrate through the emitter region, the base region, and the first accumulation region, and an insulating film formed on the inner wall of the trench and surrounding the conductive portion. At least a portion of the insulating film below the first accumulation region may be thinner than the insulating film above the first accumulation region. The insulating film below the first accumulation region may function as a capacitance adding portion.

[0011] The trench portion may include a trench extending from the upper surface of the semiconductor substrate through the emitter region, the base region, and the first accumulation region, and an insulating film formed on the inner wall of the trench and surrounding the conductive portion. At least a portion of the insulating film below the first accumulation region may have a higher dielectric constant than the insulating film above the first accumulation region. The insulating film below the first accumulation region may function as a capacitance adding portion.

[0012] The semiconductor device may include a high concentration region of a first conductivity type provided in the semiconductor substrate below the plurality of trench portions and having a doping concentration higher than that of the drift region. The doping concentration of the high concentration region may be lower than that of the first accumulation region. The semiconductor device may include a bottom region of a second conductivity type provided between the lowermost accumulation region and the drift region.

[0013] At least one of the plurality of trenches may have a first tapered portion whose width in a direction parallel to the upper surface of the semiconductor substrate decreases toward the upper side, and the first tapered portion may be disposed above a depth position of a boundary between the first accumulation region and the base region.

[0014] At least one trench portion may have a second tapered portion whose width increases toward the bottom, and the second tapered portion may be located below a depth position of a boundary between the first accumulation region and the base region.

[0015] At least one trench portion may have a third tapered portion whose width decreases toward the bottom. The third tapered portion may be located below a depth position of a boundary between the first accumulation region and the base region.

[0016] At least one trench portion may have a maximum width portion between the first tapered portion and the third tapered portion, and any one of the accumulation regions may be located at the same depth as the maximum width portion.

[0017] The multiple trench portions may include trenches extending from the upper surface of the semiconductor substrate through the emitter region, the base region, and the first accumulation region. The multiple trench portions may include an insulating film formed on the inner wall of the trench and surrounding the conductive portion. At least one of the multiple trench portions may have a lower portion including the bottom of the trench portion. The trench portion may include a thin film portion located above the lower portion, the insulating film being thinner than the insulating film of the lower portion. The uppermost accumulation region may be disposed opposite the thin film portion.

[0018] A second aspect of the present invention provides a semiconductor device including a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include a first semiconductor region of the first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region. The semiconductor device may include a second semiconductor region of a second conductivity type provided between the first semiconductor region and the drift region. The semiconductor device may include a plurality of trench portions arranged along a first direction on the front surface side of the semiconductor substrate and having extension portions extending along a second direction perpendicular to the first direction. The semiconductor device may include a mesa portion sandwiched between two trench portions. The semiconductor device may include a first top surface electrode and a second top surface electrode provided separately from each other. The semiconductor device may include an interlayer insulating film provided below the first top surface electrode and the second top surface electrode. The plurality of trench portions may include a first trench portion having a first insulating film provided on an inner wall of the trench and a first conductive portion provided inside the trench further inward than the first insulating film and connected to the first upper surface electrode, and a second trench portion having a second insulating film provided on an inner wall of the trench and a second conductive portion provided inside the trench further inward than the second insulating film and connected to the second upper surface electrode. At least one of the first conductive portion and the second conductive portion may have a portion above a depth position of the lower surface of the second semiconductor region, the width of which in the first direction decreases toward the upper side. The semiconductor device may include an emitter region of a first conductivity type provided above a drift region within the semiconductor substrate and having a doping concentration higher than that of the drift region. The semiconductor device may include a base region of a second conductivity type provided between the emitter region and the drift region within the semiconductor substrate. The semiconductor device may include an accumulation region of the first conductivity type provided between the base region and the drift region within the semiconductor substrate and having a doping concentration higher than that of the drift region. The semiconductor device may include a plurality of trench portions extending from the upper surface of the semiconductor substrate through the emitter region, the base region, and the accumulation region, and having a conductive portion provided therein. At least one of the plurality of trench portions may include a first tapered portion provided above a depth position of a boundary between the accumulation region and the base region. The width of the first tapered portion in a plane parallel to the upper surface of the semiconductor substrate may decrease toward the upper side. The trench portion may include a third tapered portion provided below a depth position of a boundary between the accumulation region and the base region. The width of the third tapered portion may decrease toward the lower side. The trench portion may have a maximum width portion between the first tapered portion and the third tapered portion, and the accumulation region may be located at the same depth as the maximum width portion.

[0019] In the depth direction of the semiconductor substrate, when the distance from the top end of the first accumulation region to the bottom end of the lowest accumulation region is defined as L1 and the distance from the bottom end of the lowest accumulation region to the bottom end of the trench portion is defined as L2, the distance L2 may be two or more and three or less times the distance L1. The capacitance adding portion may have only one accumulation region of the first conductivity type. The doping concentration of the accumulation region of the first conductivity type may be higher than the doping concentration of the first accumulation region.

[0020] A third aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having a drift region of a first conductivity type. The semiconductor device may include a first semiconductor region of the first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region. The semiconductor device may include a second semiconductor region of a second conductivity type provided between the first semiconductor region and the drift region. The semiconductor device may include a plurality of trench portions arranged along a first direction on the front surface side of the semiconductor substrate and having extension portions extending along a second direction perpendicular to the first direction. The semiconductor device may include a bottom region of the second conductivity type provided in the first direction from the bottom of one adjacent trench portion to the bottom of the other adjacent trench portion. At least one of the plurality of trench portions may have a first tapered portion, above a depth position of a lower surface of the second semiconductor region, whose width in the first direction decreases toward the upper side. A method for manufacturing a semiconductor device is provided. The method may include an emitter region forming step of forming an emitter region of a first conductivity type provided above a drift region of a first conductivity type within a semiconductor substrate having the drift region, the emitter region having a doping concentration higher than that of the drift region. The method may include a base region forming step of forming a base region of a second conductivity type provided between the emitter region and the drift region within the semiconductor substrate. The method may include a first accumulation region forming step of forming a first accumulation region of the first conductivity type provided between the base region and the drift region within the semiconductor substrate, the first accumulation region having a doping concentration higher than that of the drift region. The method may include a trench forming step of forming a plurality of trench portions extending from an upper surface of the semiconductor substrate through the emitter region, the base region, and the first accumulation region, the trench portions having conductive portions therein. The method may include a capacitance adding portion forming step of forming a capacitance adding portion provided below the first accumulation region and adding gate-collector capacitance.

[0021] In the capacitance adding portion forming step, protons may be implanted from the upper surface side of the semiconductor substrate to form an accumulation region of the first conductivity type having a doping concentration higher than that of the drift region below the first accumulation region.

[0022] The above summary of the invention does not list all of the features of the present invention. Subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing an example of a cross section taken along line aa' in FIG. [Figure 3] FIG. 3 is a diagram showing an example of a doping concentration distribution in the cc' cross section of FIG. [Figure 4] FIG. 10 is a diagram showing an example of the waveform of the collector current Ic at the time of turn-on. [Figure 5] 3 is a diagram showing another example of the doping concentration distribution in the cc' cross section of FIG. 2. FIG. [Figure 6] 3 is a diagram showing another example of the doping concentration distribution in the cc' cross section of FIG. 2. FIG. [Figure 7] FIG. 2 is a diagram showing another example of the aa' cross section in FIG. [Figure 8] 1 is a diagram showing an example of the arrangement of a first accumulation region 16, a second accumulation region 26, and a third accumulation region 28. FIG. [Figure 9] 1 is a flowchart showing an example of a method for manufacturing the semiconductor device 100. [Figure 10] FIG. 2 is a diagram showing another example of the aa' cross section in FIG. [Figure 11] 2 is a diagram showing another example of the aa' cross section of the semiconductor device 100 in FIG. [Figure 12] 12 is a diagram showing an example of a doping concentration distribution in the cc' cross section of the semiconductor device 100 shown in FIG. [Figure 13] 10 is a diagram showing an example of paths through which electron current and displacement current flow near a mesa portion 61 in a comparative example having only a first accumulation region 16. FIG. [Figure 14]1 is a diagram showing electron current and displacement current at turn-on in a semiconductor device 100 including a first accumulation region 16, a second accumulation region 26, and a third accumulation region 28. FIG. [Figure 15] FIG. 2 is a diagram showing an example of the time waveforms of the gate voltage Vg and the collector-emitter voltage Vce at the time of turn-on. [Figure 16] FIG. 2 is a diagram showing another example of the aa' cross section in FIG. [Figure 17] FIG. 17 is a diagram showing an example of a doping concentration distribution in the dd' cross section of FIG. [Figure 18] FIG. 10 is a diagram showing the relationship between turn-off loss Eoff and distance L2 under conditions of room temperature and low current. [Figure 19] FIG. 10 is a diagram showing the relationship between turn-on loss Eon and distance L2 under room temperature and low current conditions. [Figure 20] FIG. 10 is a diagram showing the relationship between the sum Eon+Err of the turn-on loss and the reverse recovery loss and the distance L2 under the conditions of room temperature and low current. [Figure 21] FIG. 10 is a diagram showing the relationship between turn-off loss Eoff and distance L2 under high temperature and large current conditions. [Figure 22] FIG. 10 is a diagram showing the relationship between turn-on loss Eon and distance L2 under high temperature and large current conditions. [Figure 23] FIG. 10 is a diagram showing the relationship between the sum Eon+Err of the turn-on loss and the reverse recovery loss and the distance L2 under high temperature and large current conditions. [Figure 24] 10 is a diagram showing the trade-off relationship between switching loss and the sum of the on-voltage of the transistor section 70 and the forward voltage of the diode section 80 under room temperature and low current conditions. FIG. [Figure 25] 10 is a diagram showing the trade-off relationship between switching loss and the sum of the on-voltage of the transistor section 70 and the forward voltage of the diode section 80 under high temperature and large current conditions. FIG. [Figure 26] 17 is a diagram showing another example of the doping concentration distribution in the dd' cross section of FIG. 16. FIG. [Figure 27]FIG. 2 is a diagram showing another example of the aa' cross section in FIG. [Figure 28] FIG. 2 is a view partially illustrating the top surface of a semiconductor device 300 according to another embodiment of the present invention. [Figure 29] 29 is a cross-sectional view taken along line aa' of FIG. 28. [Figure 30] 29 is another example of the cross-sectional view taken along line aa' in FIG. 28. [Figure 31] 29 is another example of the cross-sectional view taken along line aa' in FIG. 28. [Figure 32] FIG. 10 is a diagram showing an example of a cross section of a semiconductor device 400 according to another embodiment of the present invention. [Figure 33] FIG. 10 is a diagram showing another example of the semiconductor device 400. [Figure 34] FIG. 10 is a view partially illustrating the top surface of a semiconductor device 500 according to another embodiment of the present invention. [Figure 35] This is a cross-sectional view taken along line aa' in FIG. [Figure 36] 2 is a diagram illustrating the cross-sectional shape of a gate trench portion 40. FIG. [Figure 37] 10 is a diagram showing another example of the cross-sectional shape of the gate trench portion 40. FIG. [Figure 38] 35 is a cross-sectional view taken along the line bb' in FIG. 34. [Figure 39] 39A to 39C are diagrams illustrating an example of a process for forming the gate trench portion 40 illustrated in FIGS. 35 to 38. FIG. [Figure 40] 10 is a diagram showing another example of the cross-sectional shape of the gate trench portion 40. FIG. [Figure 41] 2 is a diagram illustrating the cross-sectional shape of a gate trench portion 40. FIG. [Figure 42] 10 is a diagram showing an example of the relationship between the depth position of the maximum width portion 98 of the gate trench portion 40 and the first accumulation region 16. FIG. [Figure 43] 35 is another example of a cross-sectional view taken along line aa' in FIG. 34. [Figure 44] 44 is a diagram showing an example of the relationship between the depth position of the maximum width portion 98 of the gate trench portion 40 and the first accumulation region 16 in the example of FIG. 43. FIG. [Figure 45]10A to 10C are diagrams illustrating an example of a process for forming a gate trench portion 40 having a first tapered portion 45 and a third tapered portion 47. [Figure 46] 10 is a diagram showing another example of the cross-sectional shape of the gate trench portion 40. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 of this example is a semiconductor chip having a transistor section 70 including a transistor such as an IGBT, and a diode section 80 including a diode such as an FWD (Free Wheel Diode). The diode section 80 is formed adjacent to the transistor section 70 on the top surface of a semiconductor substrate. FIG. 1 shows the top surface of the chip around the edge of the chip, and omits other regions.

[0026] 1 shows an active region of the semiconductor substrate of semiconductor device 100, but semiconductor device 100 may have an edge termination structure surrounding the active region. The active region refers to the region through which current flows when semiconductor device 100 is controlled to an on state. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these.

[0027] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 formed inside the upper surface side of a semiconductor substrate. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate electrode 50 provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate electrode 50 are provided separately from each other. The gate trench portion 40 and the dummy trench portion 30 are examples of trench portions.

[0028] An interlayer insulating film is formed between the emitter electrode 52 and the gate electrode 50 and the upper surface of the semiconductor substrate, but is not shown in Fig. 1. In this example, contact holes 56, 58, 49, and 54 are formed in the interlayer insulating film so as to penetrate the interlayer insulating film.

[0029] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56 and a contact hole 58. Between the emitter electrode 52 and the dummy conductive portion, a connection portion 21 and a connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided. The connection portion 21 and the connection portion 25 are formed on the upper surface of the semiconductor substrate. An insulating film such as a thermal oxide film is formed between the connection portion 21 and the connection portion 25 and the semiconductor substrate.

[0030] The gate electrode 50 contacts the gate wiring 48 through the contact hole 49. The gate wiring 48 is formed of impurity-doped polysilicon or the like. An insulating film such as a thermal oxide film is formed between the gate wiring 48 and the semiconductor substrate. The gate wiring 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. The gate wiring 48 is not connected to the dummy conductive portion in the dummy trench portion 30. In this example, the gate wiring 48 is formed from below the contact hole 49 to the tip portion 41 of the gate trench portion 40. The tip portion 41 is the end portion of the gate trench portion 40 closest to the gate electrode 50. At the tip portion of the gate trench portion 40, the gate conductive portion is exposed to the upper surface of the semiconductor substrate and contacts the gate wiring 48.

[0031] The emitter electrode 52 and the gate electrode 50 are formed of a material containing metal. For example, at least a portion of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0032] The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (short side direction) in the region of the transistor portion 70. In the transistor portion 70, the one or more gate trench portions 40 and the one or more dummy trench portions 30 may be formed alternately along the arrangement direction.

[0033] The gate trench portion 40 of this example may have two extension portions 39 (portions of the trench that are linear along the extension direction) that extend along an extension direction (longitudinal direction) perpendicular to the arrangement direction, and a tip portion 41 that connects the two extension portions. It is preferable that at least a portion of the tip portion 41 is formed in a curved shape. In the two extension portions 39 of the gate trench portion 40, the tip portions 41 connect the ends that are linear along the extension direction, thereby alleviating electric field concentration at the ends of the extension portions 39. The gate wiring 48 may be connected to the gate conductive portion at the tip portion 41 of the gate trench portion 40.

[0034] The dummy trench portions 30 of this example are provided between the extension portions 39 of the gate trench portions 40. These dummy trench portions 30 may have a linear shape extending in the extension direction.

[0035] The transistor section 70 has an intermediate region 90 at the boundary adjacent to the diode section 80, where no emitter region is formed on the surface. Furthermore, in the transistor section 70, a plurality of dummy trench sections 30 may be continuously arranged in the portion adjacent to the intermediate region 90. The dummy trench section 30 formed in the portion adjacent to the intermediate region 90 may also have an extension portion 29 and a tip portion 31. The tip portion 31 and the extension portion 29 have the same shapes as the tip portion 41 and the extension portion 39. The dummy trench section 30 having the tip portion 31 and the linear dummy trench section 30 may have the same length in the extension direction.

[0036] The number of dummy trenches 30 arranged continuously at the boundary with the diode section 80 may be greater than the number of dummy trenches 30 arranged continuously inside the transistor section 70 away from the diode section 80. The number of trenches refers to the number of extensions of the trenches arranged in the arrangement direction.

[0037] 1, a dummy trench portion 30 having a tip portion 31 and an extension portion 29 is provided in the transistor portion 70 at the boundary with the diode portion 80 (i.e., the intermediate region 90 and its adjacent portion). In the example of FIG. 1, two extension portions 29 connected via the tip portion 31 are continuously arranged in an arrangement direction perpendicular to the extension direction of the extension portions 29. In contrast, inside the transistor portion 70, extension portions 39 of the gate trench portion 40 and linear dummy trench portions 30 are arranged alternately one by one.

[0038] The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is formed in a predetermined range away from the longitudinal end of the contact hole 54 in the active region on the side where the gate electrode 50 is provided. The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Partial regions of the gate trench portion 40 and the dummy trench portion 30 on the gate electrode 50 side are formed in the well region 11. The ends of the linear dummy trench portion 30 in the extension direction and the bottom of the tip portion 31 of the dummy trench portion 30 may be covered by the well region 11.

[0039] A base region 14 is formed in a mesa portion 61 sandwiched between each trench portion. The mesa portion 61 is a region of the semiconductor substrate sandwiched between the trench portions, located above the deepest bottom of the trench portion. The base region 14 is of the second conductivity type, which has a lower doping concentration than the well region 11. The well region 11 is of the second conductivity type. In this example, the base region 14 is of P- type, and the well region 11 is of P+ type.

[0040] A contact region 15 of a second conductivity type having a higher doping concentration than the base region 14 is formed on the upper surface of the base region 14 of the mesa portion 61. In this example, the contact region 15 is P+ type. The well region 11 may be formed away from the contact region 15 in the active region that is located at the end most in the extension direction of the trench portion, in the direction of the gate electrode 50. In the transistor portion 70, an emitter region 12 of a first conductivity type having a higher doping concentration than the semiconductor substrate is selectively formed on part of the upper surface of the contact region 15. In this example, the emitter region 12 is N+ type.

[0041] Each of the contact regions 15 and the emitter regions 12 is formed from one adjacent trench portion to the other adjacent trench portion. One or more contact regions 15 and one or more emitter regions 12 of the transistor portion 70 are formed so as to be exposed on the top surface of the mesa portion 61 alternately along the extension direction of the trench portions.

[0042] In another example, the contact region 15 and the emitter region 12 may be formed in a stripe shape along the extension direction in the mesa portion 61 of the transistor section 70. For example, the emitter region 12 is formed in a region adjacent to the trench portion, and the contact region 15 is formed in a region sandwiched between the emitter regions 12.

[0043] The mesa portion 61 of the diode portion 80 does not need to have an emitter region 12 formed therein. Furthermore, a contact region 15 is formed in a region of the mesa portion 61 of the intermediate region 90 (referred to as the intermediate mesa portion 60 in this specification) that faces at least one contact region 15 in the transistor portion 70, with the dummy trench portion 30 sandwiched therebetween. Furthermore, a contact region 15 may also be formed on the outermost surface of the intermediate mesa portion 60 that faces the emitter region 12 of the adjacent transistor portion 70 across the dummy trench portion 30. In this case, the contact region 15 may be continuously formed, sandwiched between the base regions 14 exposed at both ends of the intermediate mesa portion 60 in the trench extension direction.

[0044] In the transistor section 70, the contact holes 54 are formed above the contact regions 15 and the emitter regions 12. The contact holes 54 are not formed in the regions corresponding to the base region 14 and the well region 11.

[0045] In the diode section 80, the contact hole 54 is formed above the contact region 15 and the base region 14. In this example, the contact hole 54 is not formed in the base region 14 closest to the gate electrode 50 among the multiple base regions 14 in the mesa portion 61 of the diode section 80. In this example, the contact hole 54 in the transistor section 70 and the contact hole 54 in the diode section 80 have the same length in the extension direction of each trench portion.

[0046] In the diode section 80, an N+ type cathode region 82 is formed in a region adjacent to the lower surface of the semiconductor substrate. In Fig. 1, the region where the cathode region 82 is formed is indicated by a dotted line. A P+ type collector region may be formed in the region adjacent to the lower surface of the semiconductor substrate where the cathode region 82 is not formed.

[0047] Figure 2 is a diagram showing an example of the a-a' cross section in Figure 1. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38.

[0048] The collector electrode 24 is formed on the lower surface of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a conductive material such as metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0049] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. A P-type base region 14 is formed on the upper surface side of the semiconductor substrate 10 in this cross section.

[0050] In this cross section, on the upper surface side of the transistor section 70, an N+ type emitter region 12, a P- type base region 14, and an N+ type first accumulation region 16 are formed in this order from the upper surface side of the semiconductor substrate 10.

[0051] In this cross section, a P-type base region 14 is formed on the upper surface side of the diode section 80. The first accumulation region 16 is not formed in the diode section 80. In addition, a contact region 15 is formed on the upper surface of the intermediate mesa section 60 adjacent to the transistor section 70.

[0052] In the transistor section 70, an N-type drift region 18 is formed on the lower surface of the first accumulation region 16. By providing the first accumulation region 16, which has a higher concentration than the drift region 18, between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced.

[0053] The first accumulation region 16 is formed in each mesa portion 61 of the transistor portion 70. The first accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 61. In the diode portion 80, a drift region 18 is formed on the lower surface of the base region 14. In both the transistor portion 70 and the diode portion 80, an N+ type buffer region 20 is formed on the lower surface of the drift region 18.

[0054] The buffer region 20 is formed on the lower surface side of the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0055] In the transistor section 70, a P+ type collector region 22 is formed on the lower surface of the buffer region 20. In the diode section 80, an N+ type cathode region 82 is formed on the lower surface of the buffer region 20. Note that the diode section 80 is the region on the lower surface of the active region that coincides with the cathode region 82. Alternatively, the diode section 80 may be the projection region of the cathode region 82 projected onto the upper surface of the semiconductor substrate 10 in a direction perpendicular to the lower surface of the semiconductor substrate 10. In the active region, the transistor section 70 is the projection region of the collector region 22 projected onto the upper surface of the semiconductor substrate in a direction perpendicular to the lower surface of the semiconductor substrate 10, and in which predetermined unit components including the emitter region 12 and the contact region 15 are regularly arranged.

[0056] One or more gate trench portions 40 and one or more dummy trench portions 30 are formed on the upper surface side of the semiconductor substrate 10. Each trench portion extends from the upper surface of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In regions where at least one of the emitter region 12, the contact region 15, and the first accumulation region 16 is provided, each trench portion also extends through these regions to reach the drift region 18. The trench portion extending through the doped region does not necessarily mean that the trench portion is formed after the doped region is formed. The trench portion extending through the doped region also includes a trench portion formed after the trench portion is formed.

[0057] The ends of the first accumulation region 16 in the extension direction of the trench portion may be located inside the contact regions 15 (below the contact regions 15 in the depth direction of the semiconductor substrate 10) that are arranged at both ends in the extension direction of the trench portion in the plan view shown in Figure 1. Furthermore, the ends of the first accumulation region 16 in the extension direction of the trench portion may be located closer to the gate electrode 50 than the emitter region 12 and closer to the emitter region 12 than the ends of the contact hole 54 in the extension direction.

[0058] The gate trench portion 40 has a gate trench formed on the upper surface side of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, more inward than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0059] The gate conductive portion 44 includes a region facing at least the adjacent base region 14 in the depth direction, with the gate insulating film 42 sandwiched therebetween. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 38 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0060] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the upper surface side of the semiconductor substrate 10. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44. The dummy trench portion 30 in the cross section is covered by an interlayer insulating film 38 on the upper surface of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0061] The semiconductor device 100 further includes a capacitance adding portion that is provided below the first accumulation region 16 in the mesa portion 61 and that adds gate-collector capacitance. That is, the capacitance adding portion increases the transient gate-collector capacitance between the gate conductive portion 44 and the collector electrode 24 at turn-on, compared to when no capacitance adding portion is provided. The semiconductor device 100 in the example of FIG. 2 includes a second accumulation region 26 as the capacitance adding portion.

[0062] The second accumulation region 26 is provided between two trench portions and below the first accumulation region 16. At least one of the two trench portions adjacent to the second accumulation region 26 may be a gate trench portion 40. The second accumulation region 26 may also be provided between two dummy trench portions 30. The second accumulation region 26 is of N+ type with a higher doping concentration than the drift region 18.

[0063] Alternatively, three or more accumulation regions may be provided between the two trench portions. In the example of Fig. 2, a third accumulation region 28 is provided between the first accumulation region 16 and the second accumulation region 26. The third accumulation region 28 is an N+ type with a higher doping concentration than the drift region 18.

[0064] FIG. 3 is a diagram showing an example of the doping concentration distribution in the c-c' cross section of FIG. 2. FIG. 3 shows the doping concentration distribution from the emitter region 12 to the upper end of the drift region 18 in the transistor section 70. As in FIG. 3, the vertical axis of the diagram showing the doping concentration is a logarithmic axis. Each division on the vertical axis represents 10 times. In this specification, the doping concentration refers to the concentration of impurities (dopants) that have become donors or acceptors. The impurity concentration shown in FIG. 3 corresponds to the concentration difference between the donor and acceptor (net doping concentration).

[0065] The doping concentration distribution in the depth direction has peaks in the first accumulation region 16, the third accumulation region 28, and the second accumulation region 26. The first accumulation region 16, the third accumulation region 28, and the second accumulation region 26 may be formed by implanting impurities from the top or bottom surface of the semiconductor substrate 10.

[0066] As an example, the peak value Dc of the doping concentration in the first accumulation region 16, the peak value D2 of the doping concentration in the third accumulation region 28, and the peak value D1 of the doping concentration distribution in the second accumulation region 26 are the same. However, these peak values ​​may have an error of about ±10%.

[0067] As an example, the peak position P3 of the doping concentration in the first accumulation region 16, the peak position P2 of the doping concentration in the third accumulation region 28, and the peak position P1 of the doping concentration distribution in the second accumulation region 26 are arranged at equal intervals in the depth direction. However, these peak positions may have an error of about ±10%. The distance between the peak position P3 and the peak position P1 may be greater than the width of the first accumulation region 16 in the depth direction. The distance between the peak position P3 and the peak position P2 may also be greater than the width of the first accumulation region 16 in the depth direction. Here, the width of the first accumulation region 16 in the depth direction may be, for example, the full width at half maximum (FWHM) of the peak concentration, or may be the width between the positions where the doping concentration is minimal before and after the peak position, as indicated by the double-headed arrow 88 in FIG. 3 .

[0068] Furthermore, the lowest accumulation region among the plurality of accumulation regions (the second accumulation region 26 in this example) is preferably provided near the lower end of the adjacent trench portion and in the mesa portion 61. However, it is preferable that the peak position P1 of the lowest accumulation region among the plurality of accumulation regions (the second accumulation region 26 in this example) be located above the position Pt of the lower end of the adjacent gate trench portion 40. Furthermore, it may be located above the boundary Pt2 where the trench sidewall changes from a substantially linear shape to a curved surface. By providing the second accumulation region 26 in the region sandwiched between the trench portions, the transient gate-collector capacitance at turn-on can be increased.

[0069] Furthermore, the position Pb of the lower end of the accumulation region formed at the lowest position among the multiple accumulation regions (the second accumulation region 26 in this example) may be located above the position Pt of the lower end of the adjacent gate trench portion 40. Furthermore, it may be located above the boundary Pt2 where the trench sidewall changes from a substantially linear shape to a curved surface. The lower end of the second accumulation region 26 may be a position below the peak P1 of the second accumulation region 26 where the doping concentration is 10 times the doping concentration Dd of the drift region 18.

[0070] The doping concentration in the region between the first accumulation region 16 and the accumulation region next to the first accumulation region 16 (the third accumulation region 28 in this example) may be higher than the doping concentration of the drift region Dd. In other words, the minimum value D3 of the doping concentration distribution at the boundary between the first accumulation region 16 and the third accumulation region 28 may be higher than the doping concentration Dd of the drift region. The minimum values ​​of the doping concentration distribution at the boundaries between accumulation regions other than the first accumulation region 16 may also be higher than the doping concentration Dd of the drift region.

[0071] However, if the minimum value D3 of the doping concentration distribution at the boundary between the first accumulation region 16 and the accumulation region next to the first accumulation region 16 (the third accumulation region 28 in this example) is too close to the peak value Dc of the doping concentration in the first accumulation region 16, the first accumulation region 16 and the third accumulation region 28 will function as a single accumulation region. As a result, the accumulation region provided below the first accumulation region 16 will not function as a capacitance-adding region. In other words, the doping concentration between the first accumulation region 16 and the adjacent accumulation region serving as a capacitance-adding region (the second accumulation region 26 in this example) may be lower than the peak concentration of the first accumulation region 16 by a predetermined percentage. As an example, the minimum value D3 of the doping concentration distribution at the boundary between the first accumulation region 16 and the third accumulation region 28 may be 1 / 10 or less of the peak value Dc of the doping concentration of the first accumulation region 16. The minimum value D3 may be 1 / 100 or less of the peak value Dc.

[0072] Furthermore, the peak position P1 of the accumulation region formed at the lowest position among the multiple accumulation regions (in this example, the second accumulation region 26) may be located below the center of the adjacent gate trench portion 40. Furthermore, the peak position P2 of the accumulation region located next to the first accumulation region 16 (in this example, the third accumulation region 28) may also be located below the center of the adjacent gate trench portion 40.

[0073] Furthermore, the peak position P1 of the accumulation region formed at the lowest position among the multiple accumulation regions (in this example, the second accumulation region 26) may be located in the lower ¼ range or the lower ⅛ range of the adjacent gate trench portion 40. By providing the second accumulation region 26 near the bottom of the gate trench portion 40, it is possible to increase the transient gate-collector capacitance at turn-on.

[0074] The minimum concentration of the portion where the doping concentration distribution takes on a valley shape between the second accumulation region 26 and the third accumulation region 28 may be lower than the minimum concentration of the portion where the doping concentration distribution takes on a valley shape between the first accumulation region 16 and the second accumulation region 26. This makes it possible to efficiently increase the transient gate-collector capacitance at turn-on.

[0075] If the accumulation region is located near the base region 14, the negative capacitance increases, and it is not possible to increase the transient positive capacitance between the gate and collector. In contrast, by adjusting the position of each accumulation region, for example, as described above, it is possible to increase the transient positive capacitance between the gate and collector.

[0076] 4 is a diagram showing an example of the waveform of the collector current Ic at turn-on. Waveform 93 shows the collector current Ic when none of the first accumulation region 16, second accumulation region 26, and third accumulation region 28 is provided.

[0077] Waveform 94 shows the collector current Ic when the first accumulation region 16 is provided but the second accumulation region 26 and the third accumulation region 28 are not. The first accumulation region 16 is provided near the base region 14, which increases the negative capacitance between the gate and the collector. This increases the di / dt of the collector current Ic at turn-on. The provision of the first accumulation region 16 can improve the trade-off between on-voltage and turn-off loss, but since the di / dt at turn-on increases, increasing the gate resistance to suppress the increase in di / dt results in increased turn-on loss.

[0078] Waveform 91 shows the collector current Ic when the first accumulation region 16 and the second accumulation region 26 are provided. The second accumulation region 26 is located away from the base region 14, which increases the capacitance between the gate and the collector. This reduces the di / dt of the collector current Ic at turn-on. This allows for a reduction in turn-on loss while improving the trade-off between on-voltage and turn-off loss.

[0079] Waveform 92 shows the collector current Ic when the first accumulation region 16, the second accumulation region 26, and the third accumulation region 28 are provided. The provision of the third accumulation region 28 further increases the capacitance between the gate and the collector. This allows for a further reduction in turn-on loss while improving the trade-off between on-voltage and turn-off loss.

[0080] FIG. 5 shows another example of the doping concentration distribution in the c-c' cross section of FIG. 2. In this example, among the accumulation regions other than the first accumulation region 16, the lower accumulation region has a higher doping concentration than the upper accumulation region. More specifically, the peak value D1 of the doping concentration of the second accumulation region 26 is higher than the peak value D2 of the doping concentration of the third accumulation region 28. The peak value D1 of the doping concentration of the second accumulation region 26 may be higher than the peak value Dc of the doping concentration of the first accumulation region 16. For example, the peak value D1 of the doping concentration of the second accumulation region 26 may be approximately three to seven times the peak value Dc of the doping concentration of the first accumulation region 16. This configuration mitigates the effect of increased negative capacitance due to the first accumulation region 16, thereby reducing the di / dt of the collector current Ic at turn-on. Therefore, by increasing the doping concentration of the second accumulation region 26, the accumulation effect due to the IE effect is further enhanced, thereby improving the trade-off between on-voltage and turn-off loss, and further reducing turn-on loss by reducing the turn-on di / dt.

[0081] Furthermore, the peak value D1 of the doping concentration of the lowermost second accumulation region 26 may be smaller than the peak values ​​D2, Dc of the doping concentrations of the first accumulation region 16 and the third accumulation region 28. By reducing the doping concentration of the accumulation region that is farthest from the base region 14, the amount of capacitance added between the gate and collector can be efficiently reduced.

[0082] Fig. 6 is a diagram showing another example of the doping concentration distribution in the c-c' cross section of Fig. 2. In this example, in the depth direction of the semiconductor substrate 10, the distance P2-P3 between the first accumulation region 16 and the accumulation region arranged next to the first accumulation region 16 (the third accumulation region 28 in this example) is larger than the distance P1-P2 between the lowest accumulation region (the second accumulation region 26 in this example) and the second lowest accumulation region (the third accumulation region 28 in this example).

[0083] The distance P2-P3 may be 1.5 times or more, or even twice or more, the distance P1-P2. The distance between the accumulation regions may be constant. Forming an accumulation region near the base region 14 may increase the negative capacitance between the gate and collector. However, the above-described configuration allows the additional capacitance to be increased efficiently without increasing the negative capacitance between the gate and collector.

[0084] 7 is a diagram showing another example of the a-a' cross section in FIG. 1. In this example, the number of accumulation regions in the intermediate region 90 and in the mesa portion 61 adjacent to the intermediate region 90 across the dummy trench portion 30 in the transistor portion 70 is smaller than the number of accumulation regions in the mesa portion 61 inside the transistor portion 70. The number of accumulation regions in the mesa portion 61 of the transistor portion 70 may decrease as it approaches the intermediate region 90.

[0085] 7, the mesa portion 61 adjacent to the intermediate region 90 across the dummy trench portion 30 has the third accumulation region 28 formed therein, but the second accumulation region 26 is not formed therein. The mesa portion 61 adjacent to the mesa portion 61 on the opposite side from the intermediate region 90 has the second accumulation region 26 and the third accumulation region 28 formed therein. With this configuration, the number of accumulation regions can be gradually changed, and electric field concentration at the boundary portion can be alleviated.

[0086] The first accumulation region 16 may also be formed in the mesa portion 61 (intermediate mesa portion 60) of the intermediate region 90. No other accumulation regions are formed in the intermediate mesa portion 60. A contact region 15 may be formed in the intermediate mesa portion 60 near the upper surface of the semiconductor substrate 10. Unlike the intermediate mesa portion 60, the mesa portion 61 of the diode portion 80 does not have any of the first accumulation region 16, second accumulation region 26, or third accumulation region 28 formed therein. With this configuration, the number of N+ type regions formed below the base region 14 can be gradually changed.

[0087] 8 is a diagram showing an example of the arrangement of the first accumulation region 16, the third accumulation region 28, and the second accumulation region 26. In Fig. 8, the horizontal axis represents the depth direction of the semiconductor substrate 10, and the vertical axis represents the doping concentration. Furthermore, the length of the gate trench portion 40 that protrudes downward from the lower end of the base region 14 is denoted as α, and the interval between the peak positions of each accumulation region is denoted as β.

[0088] In addition, the interval between positions where the doping concentration distribution of each accumulation region is 1 / 10 of the peak concentration is defined as γ. For example, the interval between the position below the peak position in the doping concentration distribution of the first accumulation region 16 where the concentration is 1 / 10 of the peak concentration and the position above the peak position in the doping concentration distribution of the third accumulation region 28 where the concentration is 1 / 10 of the peak concentration is defined as γ1. Similarly, the interval between the position below the peak position in the doping concentration distribution of the third accumulation region 28 where the concentration is 1 / 10 of the peak concentration and the position above the peak position in the doping concentration distribution of the second accumulation region 26 where the concentration is 1 / 10 of the peak concentration is defined as γ2.

[0089] The interval βk (k = 1, 2, ... toward the bottom surface) between the respective peak positions is approximately 0.3α or more and 0.9α or less. As mentioned above, β1 may be greater than β2. Furthermore, the interval γk between the respective peak positions is approximately 0.2βk or more and 0.8βk or less. The doping concentration distribution in FIG. 8 is a Gaussian distribution, but in other examples, the doping concentration distribution may have a shape such as a rectangle. For example, if each region is formed by ion implantation, the doping concentration distribution is approximated by a Gaussian distribution, and if each region is formed by epitaxial growth, the doping concentration distribution is approximated by a rectangle. If the doping concentration distribution is rectangular, the peak position is the center of the section where the doping concentration shows its maximum value.

[0090] βk may become smaller as the depth of the semiconductor substrate 10 increases toward the lower surface side. Alternatively, βk may become larger as the depth of the semiconductor substrate 10 increases toward the lower surface side. Furthermore, γk may become larger as the depth of the semiconductor substrate 10 increases toward the lower surface side. Alternatively, γk may become smaller as the depth of the semiconductor substrate 10 increases toward the lower surface side.

[0091] The number of accumulation regions on the trench bottom side may be greater than the number of accumulation regions on the base region 14 side relative to the depth of the midpoint between the base region 14 and the trench bottom. Alternatively, the number of accumulation regions on the trench bottom side may be smaller than the number of accumulation regions on the base region 14 side relative to the depth of the midpoint between the base region 14 and the trench bottom.

[0092] 9 is a flowchart showing an example of a method for manufacturing the semiconductor device 100. First, in step S1200, the structure of the upper surface of the semiconductor device 100 is formed. Step S1200 includes a doping region formation step for forming the emitter region 12 and the base region 14. The base region 14 may be formed by implanting doping such as phosphorus. Step S1200 also includes a trench formation step for forming each trench portion after the doping region formation step. Step S1200 also includes an interlayer insulating film formation step for forming the interlayer insulating film 38 that covers each trench portion.

[0093] Next, in step S1202, a barrier metal is formed over the entire upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38. Next, in step S1204, protons are implanted from the upper surface of the semiconductor substrate 10 to form the first accumulation region 16 and other accumulation regions (e.g., the second accumulation region 26 and the third accumulation region 28). In step S1204, protons are implanted multiple times with different proton implantation ranges. Some of the implanted protons become donors to form each accumulation region. In this case, hydrogen is contained as an impurity in the first accumulation region 16 and other accumulation regions. Alternatively, in step S1204, protons may be implanted from the lower surface of the semiconductor substrate 10. After the proton implantation, the protons may be activated by heat treatment at a temperature of approximately 350°C to 450°C.

[0094] Protons can be implanted deeper than phosphorus ions and the like, with less variation in the implantation position. By forming an accumulation region with protons, it is possible to easily form an accumulation region at a deep position. Furthermore, since the peak of the doping concentration distribution in the accumulation region can be formed steeply, it is easy to form an accumulation region with a narrow width, and the gate-collector capacitance can be easily increased. Furthermore, by implanting protons from the upper surface side of the semiconductor substrate 10 after forming the barrier metal, it is possible to prevent protons or hydrogen from escaping from the upper surface side of the semiconductor substrate 10.

[0095] Next, in step S1206, the emitter electrode 52 is formed. The temperature for forming the emitter electrode 52 is approximately 350°C to 450°C. The heat treatment after the proton implantation may be omitted, and the protons may be activated when the emitter electrode 52 is formed. The order of steps S1204 and S1206 may be reversed. By implanting protons after forming the emitter electrode 52, it is possible to further prevent the protons from escaping from the upper surface of the semiconductor substrate 10. Furthermore, after forming the emitter electrode 52, the semiconductor substrate 10 may be irradiated with an electron beam to adjust the carrier lifetime.

[0096] Next, in step S1208, the underside of the semiconductor substrate 10 is ground to adjust the thickness of the semiconductor substrate 10. The thickness of the semiconductor substrate 10 is set according to the breakdown voltage or rated voltage that the semiconductor device 100 should have. Here, the breakdown voltage may be, for example, the applied voltage when a predetermined value of avalanche current flows.

[0097] Next, in step S1210, a structure on the underside of the semiconductor device 100 is formed. The structure on the underside is, for example, the collector region 22 and the cathode region 82. Next, in step S1212, protons are implanted from the underside of the semiconductor substrate 10 to form the buffer region 20. Next, in step S1214, a heat treatment is performed to activate the protons implanted in the buffer region 20.

[0098] Protons may be implanted multiple times into the buffer region 20 at different depth positions. This results in multiple peaks in the doping concentration distribution in the depth direction of the buffer region 20. In the doping concentration distribution of the buffer region 20, the peak value at the deepest position as viewed from the bottom surface of the semiconductor substrate 10 is greater than the peak value at the next deepest position. By this method, the semiconductor device 100 can be manufactured.

[0099] In another example manufacturing method, the impurity of the first accumulation region 16 may be phosphorus. In this case, an impurity may be implanted into the first accumulation region 16 in step S1200. The first accumulation region 16 is formed at a relatively shallow position, and therefore can be formed with phosphorus. In contrast, the other accumulation regions (e.g., the second accumulation region 26 and the third accumulation region 28) are formed at relatively deep positions. By using hydrogen as the impurity of the accumulation regions other than the first accumulation region 16, as described above, the accumulation regions other than the first accumulation region 16 can be easily formed, and the width of the accumulation regions other than the first accumulation region 16 can be narrowed.

[0100] In another example of the manufacturing method, the impurity of at least one of the accumulation regions other than the first accumulation region 16 may be phosphorus. For example, the impurity of the shallowest accumulation region (third accumulation region 28) of the accumulation regions other than the first accumulation region 16 may be phosphorus. In this case, in step S1200, the impurity may be implanted into the accumulation region. In step S1200, after implanting phosphorus into the base region 14, heat treatment at about 1150° C. may be performed for about three hours.

[0101] Next, phosphorus is implanted into the first accumulation region 16 and one or more other accumulation regions. At this time, the valence of the phosphorus ions implanted at deeper positions may be made higher. This allows phosphorus ions to be implanted at deeper positions without significantly increasing the acceleration voltage. After phosphorus is implanted into the first accumulation region 16 and other accumulation regions, heat treatment is performed at a lower temperature than the base region 14 for a shorter time. For example, heat treatment is performed at about 1000°C for about 30 minutes. Other steps are the same as those shown in FIG. 9.

[0102] 10 is a diagram showing another example of the a-a' cross section in FIG. 1. The semiconductor device 100 of this example has a capacitance adding portion 33 in the insulating film of each trench portion. In each trench portion of FIG. 10, at least a portion of the insulating film below the first accumulation region 16 is formed to be thinner than the insulating film above the first accumulation region 16. In this example, the insulating film with a smaller thickness below the first accumulation region 16 functions as the capacitance adding portion 33.

[0103] By forming the insulating film below the first accumulation region 16 to be thin, it is possible to increase the transient gate-collector capacitance at turn-on below the first accumulation region 16. The upper end of the capacitance adding portion 33 (i.e., the upper end of the insulating film with a small thickness) is formed away from the lower end of the first accumulation region 16 in the depth direction. The distance in the depth direction between the upper end of the capacitance adding portion 33 and the lower end of the first accumulation region 16 may be 0.5 times or more, or may be 1 time or more, the length of the first accumulation region 16 in the depth direction.

[0104] In another example, in each trench portion, at least a portion of the insulating film below the first accumulation region 16 is formed to have a higher dielectric constant than the insulating film above the first accumulation region 16. The portion of the insulating film with a higher dielectric constant functions as the capacitance adding portion 33. The insulating film functioning as the capacitance adding portion 33 may be formed of a different material from the other insulating film portions. Furthermore, the insulating film functioning as the capacitance adding portion 33 may be formed under different temperature conditions from the other insulating film portions. This configuration also makes it possible to increase the transient gate-collector capacitance at turn-on.

[0105] 1 to 9 may be applied to any of the semiconductor devices 100 shown in Fig. 1 to 9. That is, a plurality of accumulation regions may be further formed while forming the capacitance adding portion 33 in the insulating film in each trench portion. The peak position of the doping concentration of the second accumulation region 26 at the deepest position may be provided in a depth range facing the capacitance adding portion 33.

[0106] Fig. 11 is a diagram showing another example of the a-a' cross section of the semiconductor device 100 in Fig. 1. The semiconductor device 100 of this example further includes an N+ type high concentration region 19 having a doping concentration higher than that of the drift region 18, in addition to the configuration of the semiconductor device 100 of any of the aspects described with reference to Figs.

[0107] The high concentration region 19 is provided inside the semiconductor substrate 10 below the multiple trench portions and above the buffer region 20. The high concentration region 19 may be located above the midpoint in the depth direction of the semiconductor substrate 10. The high concentration region 19 may be provided away from the multiple trench portions. A drift region 18 may be provided between the high concentration region 19 and each trench portion.

[0108] The high-concentration region 19 is provided in at least a portion of the transistor section 70. In the example of FIG. 11 , the high-concentration region 19 is provided in the entire active region of the transistor section 70 (the entire region where the emitter regions 12 are regularly formed). For example, in a plane parallel to the upper surface of the semiconductor substrate 10, the high-concentration region 19 may be provided so as to overlap the entire collector region 22. In this plane, the end of the high-concentration region 19 may be positioned so as to overlap the end of the collector region 22. Furthermore, the end of the high-concentration region 19 may be positioned closer to the transistor section 70 than the end of the collector region 22, or may be positioned closer to the diode section 80.

[0109] Furthermore, the high-concentration region 19 is not provided in at least a portion of the diode section 80. However, it is preferable that at least a portion of the mesa section 61 (intermediate mesa section 60) of the intermediate region 90 is not covered with the high-concentration region 19. A contact region 15 is provided in the intermediate mesa section 60. This makes it possible to maintain extraction of holes from the intermediate mesa section 60. In the example of FIG. 11 , the high-concentration region 19 is not provided in the entire diode section 80 or the intermediate region 90.

[0110] In the semiconductor device 100, current concentration may occur in regions other than the active region, reducing breakdown resistance (turn-off resistance) during turn-off. In particular, as the semiconductor device 100 is miniaturized, the breakdown voltage in the active region increases, making avalanche breakdown more likely to occur in regions other than the active region. If avalanche breakdown occurs in regions other than the active region, the turn-off resistance of the semiconductor device 100 will decrease. In response to this, providing a high-concentration region 19 in the transistor section 70 reduces the breakdown voltage in the transistor section 70. Therefore, avalanche breakdown can occur in the entire transistor section 70, which has a relatively large area, before avalanche breakdown occurs in regions other than the active region, thereby improving the resistance of the semiconductor device 100.

[0111] FIG. 12 is a diagram showing an example of a doping concentration distribution in the c-c' cross section of the semiconductor device 100 shown in FIG. 11. As described above, the high-concentration region 19 is provided at a position P19 deeper than the lower end position Pt of the gate trench portion 40. The doping concentration D19 (e.g., peak concentration) of the high-concentration region 19 is lower than the doping concentration Dc of the first accumulation region 16. The doping concentration D19 of the high-concentration region 19 may be lower than the doping concentrations of any of the accumulation regions. The doping concentration D19 of the high-concentration region 19 may be equal to or less than half of the smallest doping concentration among the doping concentrations of the multiple accumulation regions. Furthermore, the doping concentration D19 of the high-concentration region 19 may be equal to or less than 1 / 10 of the largest doping concentration among the doping concentrations of the multiple accumulation regions. The high-concentration region 19 may be formed by implanting protons or the like from the upper surface side of the semiconductor substrate 10.

[0112] 2 and other figures, the semiconductor device 100 having multiple accumulation regions has a different path through the mesa portion 61 than a semiconductor device having one or less accumulation regions. This also enables the semiconductor device 100 to reduce loss at turn-on.

[0113] 13 is a diagram showing an example of the paths through which electron current and displacement current flow near the mesa portion 61 in a comparative example having only the first accumulation region 16. FIG. 13 shows the current paths during turn-on. During turn-on, the voltage of the gate conductive portion 44 gradually rises from 0 [V]. As a result, negative charges are induced near the gate trench portion 40 of the base region 14, forming a channel.

[0114] The main current in the initial stage of turn-on is electron current, not hole current. The initial stage is the period from just before the gate voltage Vge reaches the threshold voltage until before the Miller period, during which Vge remains constant at approximately the threshold voltage. When Vge approaches the threshold voltage, the channel begins to open and electrons begin to be injected into the drift region.

[0115] 13, electrons flowing downward from the channel may flow once in the first accumulation region 16 in the arrangement direction (the X-axis direction, or the direction from the vicinity of the gate trench portion 40 toward the center of the mesa portion 61). However, in the drift region 18 below the first accumulation region 16, an electron accumulation layer has already been formed near the gate trench portion 40 (the threshold voltage at which the electron accumulation layer of the N-type region is formed is much lower than the threshold voltage of the inversion layer of the P-type region), so the electron current flows mainly near the gate trench portion 40.

[0116] When the electrons reach the collector region 22 on the back surface, holes start to be injected from the collector region 22 into the buffer region 20 and the drift region 18. As a result, holes are accumulated near the bottom end of the trench portion. As an example, holes are accumulated at a rate of 1E+16 cm from near the bottom end of the gate trench portion 40 to the side of the dummy trench portion 30 below the first accumulation region 16. -3 ] exists in the order of

[0117] Holes gather at the bottom end of the gate trench portion 40 and the bottom end of the dummy trench portion 30. In particular, because the dummy conductive portion 34 has the same potential as the emitter electrode 52, a hole inversion layer is likely to form on the sidewall of the dummy trench portion 30. Holes injected from the collector region 22 gather near this hole inversion layer. Holes are continuously distributed from the dummy trench portion 30 to the bottom end of the gate trench portion 40. Due to this hole distribution, a large displacement current flows near the bottom end of the gate trench portion 40 when the device is turned on.

[0118] The displacement current caused by the accumulation of holes causes charging of the gate conductive portion 44, which faces the gate insulating film 42. This charging of the gate conductive portion 44 causes an instantaneous increase in the gate electrode Vge. The larger the displacement current, the more the gate conductive portion 44 is charged, and therefore the more quickly the potential of the gate conductive portion 44 rises. As a result, the potential of the gate conductive portion 44 instantaneously exceeds the gate threshold.

[0119] This initiates a large injection of electrons and holes, increasing the collector-emitter current. The rate of voltage decrease (dV / dt) of the collector-emitter voltage increases in accordance with the rate of change of the collector-emitter current. The larger the displacement current, the larger the dV / dt. In particular, the less the accumulated holes flow to the emitter electrode 52, the larger the displacement current and the larger the instantaneous increase in the potential of the gate conductive portion 44. Therefore, in the comparative example of FIG. 13, dV / dt is relatively large, and electromagnetic noise is also relatively large.

[0120] 14 is a diagram showing electron current and displacement current at turn-on in a semiconductor device 100 including a first accumulation region 16, a second accumulation region 26, and a third accumulation region 28. In this example, too, electrons that have passed through the channel tend to travel in the arrangement direction (X-axis direction) in the first accumulation region 16. However, in this example, the third accumulation region 28 and the second accumulation region 26 are provided below the first accumulation region 16.

[0121] In this example, the impedance for electron current is lower for the path that flows directly from the first accumulation region 16 to the third accumulation region 28 than for the path that flows from near the center of the first accumulation region 16 back to near the gate trench portion 40 and then to the third accumulation region 28. Similarly, the impedance for electron current is lower for the path that flows directly from the third accumulation region 28 to the second accumulation region 26 than for the path that flows from near the center of the third accumulation region 28 back to near the gate trench portion 40 and then to the second accumulation region 26.

[0122] Of the areas below each accumulation region, holes tend to accumulate in the high-hole concentration region adjacent to the gate trench portion 40. Furthermore, since the electron current flows near the center of the mesa portion 61 rather than near the gate trench portion 40, the accumulation of holes in the high-hole concentration region is promoted. This promotes the flow of the electron current near the center of the mesa portion 61. Although FIG. 14 schematically shows the high-hole concentration region in which holes are accumulated, the high-hole concentration region may exist only near the boundary between the gate trench portion 40 and the semiconductor substrate 10.

[0123] As described above, the electron current in this example does not return to the vicinity of the gate trench portion 40, but travels downward near the center of the mesa portion 61 sandwiched between the gate trench portion 40 and the dummy trench portion 30. In other words, the electron current in this example flows near the center of the mesa portion 61, not near the gate trench portion 40. The effect of the electron current flowing near the center of the mesa portion 61 is achieved by arranging multiple accumulation regions in the depth direction.

[0124] When the electron current flows near the center of the mesa portion 61, the hole distribution near the bottom of the mesa portion 61 is split near the center of the mesa portion 61. Therefore, holes on the dummy trench portion 30 side of the electron current path do not flow toward the gate trench portion 40 side. This split of the hole distribution at the center of the mesa portion 61 suppresses the accumulation of holes at the bottom end of the gate trench portion 40. As a result, the displacement current can be reduced in the example of FIG. 14 compared to the example of FIG. 13. Because the displacement current can be reduced, the charging of the gate conductive portion 44 is also reduced, and the instantaneous increase in the gate electrode Vge is also suppressed. This also suppresses the voltage decrease rate (dV / dt) of the collector-emitter voltage.

[0125] The inventors of the present invention have confirmed through simulations that holes are distributed mainly at the bottom end of the gate trench portion 40 and the bottom end and side portions of the dummy trench portion 30, and are hardly distributed at the center of the mesa portion 61. As an example, the concentration of holes near the bottom end of the gate trench portion 40 and the bottom end of the dummy trench portion 30 is 1E+13 [cm -3 ], and the comparative example in FIG. -3 ] is much lower than 1E+13. 13 This is what I mean.

[0126] Although not limited to the following reasons, it is believed that the hole distribution in the example of Fig. 14 is caused by the hole distribution being divided by an electron current between the gate trench portion 40 and the dummy trench portion 30. Furthermore, due to this hole distribution, a smaller displacement current flows from the vicinity of the bottom end of the dummy trench portion 30 to the vicinity of the bottom end of the gate trench portion 40 at the time of turn-on than in the comparative example of Fig. 13.

[0127] 13, the displacement current is smaller in this example than in the comparative example of FIG. 13, and therefore dV / dt is smaller, and electromagnetic noise can also be reduced, compared to the comparative example of FIG. 13. Furthermore, in this example, it is not necessary to connect an additional gate resistor Rg to the gate conductive portion 44 in order to suppress a rapid rise in the potential of the gate conductive portion 44. Alternatively, connecting a small gate resistor Rg to the gate conductive portion 44 can suppress a rapid rise in the potential of the gate conductive portion 44. Therefore, power loss at turn-on can be reduced compared to the comparative example of FIG. 13.

[0128] The second accumulation region 26 and the third accumulation region 28 do not have to be in direct contact with the dummy trench portion 30. In this case, holes can exist from the lower end of the dummy trench portion 30 to immediately below the first accumulation region 16 on the side of the dummy trench portion 30. This can facilitate extraction of holes into the emitter electrode 52 at the time of turn-off.

[0129] Fig. 15 is a diagram showing an example of the time waveforms of the gate voltage Vg and the collector-emitter voltage Vce at turn-on, in which the characteristics of the semiconductor device 100 shown in Fig. 14 are indicated by a solid line, and the characteristics of the comparative example shown in Fig. 13 are indicated by a dotted line 200.

[0130] 15, in the semiconductor device 100, the gate voltage Vge and the collector-emitter voltage Vce fluctuate more slowly during turn-on than in the comparative example. This reduces turn-on loss. As an example, the semiconductor device 100 can reduce turn-on loss by 30% or more compared to the comparative example.

[0131] The reduction in turn-on loss described with reference to FIGS. 13 to 15 becomes more pronounced when the semiconductor device 100 is miniaturized. As the semiconductor device 100 is miniaturized and the trench pitch becomes smaller, the hole density near the bottom of each mesa portion 61 increases. This makes it easier for a displacement current to flow to the gate trench portion 40. On the other hand, by providing multiple accumulation regions as in the semiconductor device 100 and causing the electron current at turn-on to flow to the center of the mesa portion 61, the hole distribution near the bottom of the mesa portion 61 can be separated, thereby suppressing the displacement current flowing to the gate trench portion 40. Therefore, even when the semiconductor device 100 is miniaturized, the turn-on loss can be suppressed.

[0132] 16 is a diagram showing another example of the a-a' cross section in FIG. 1. In this example, in the mesa portion 61 of the transistor portion 70, the capacitance adding portion has only one accumulation region. That is, in addition to the first accumulation region 16, only one second accumulation region 26 is provided in the mesa portion 61 of the transistor portion 70. Moreover, no accumulation regions are provided in the mesa portion 61 of the diode portion 80. In the intermediate mesa portion 60, the first accumulation region 16 is provided, and no other accumulation regions are provided.

[0133] Fig. 17 is a diagram showing an example of the doping concentration distribution in the dd' cross section of Fig. 16. The dd' cross section is a cross section perpendicular to the upper surface of the semiconductor substrate 10 in the mesa portion 61 of the transistor section 70. As described above, the first accumulation region 16 and the second accumulation region 26 are provided in the mesa portion 61.

[0134] In the depth direction of the semiconductor substrate 10, the distance from the upper end of the first accumulation region 16 to the lower end of the accumulation region arranged at the lowest position (in this example, the second accumulation region 26) is defined as L1. In this example, the upper end of the first accumulation region 16 refers to the boundary between the first accumulation region 16 and the base region 14. As described above, the lower end of the second accumulation region 26 may be located below the peak P1 of the second accumulation region 26, at a position where the doping concentration is 10 times the doping concentration Dd of the drift region 18.

[0135] Furthermore, the distance from the bottom end of the lowest accumulation region (the second accumulation region 26 in this example) to the bottom end of the trench portion (the gate trench portion 40 in this example) is defined as L2. Distance L2 is preferably two to three times the distance L1. This allows for reduced switching loss in the semiconductor device 100.

[0136] 18 to 23 are diagrams showing the relationship between the switching loss and the distance L2 in the semiconductor device 100 shown in FIG. 16. In FIGS. 18 to 23, the distance L2 is normalized by the distance L1. In the examples of FIGS. 18 to 23, the position of the lower end of the lowest accumulation region is fixed (i.e., L1 is fixed), and the position of the lower end of the gate trench portion 40 is changed. As an example, the position of the lower end of the lowest accumulation region is approximately 2.0 μm or more and 3.0 μm or less from the upper surface of the semiconductor substrate 10, and the position of the lower end of the gate trench portion 40 is approximately 4 μm or more and 8 μm or less from the upper surface of the semiconductor substrate.

[0137] FIG. 18 shows the results when the ambient temperature is 25 degrees and the operating current of the semiconductor device 100 is 10 A / cm 2 19 is a diagram showing the relationship between turn-off loss Eoff and distance L2 under the conditions (referred to as room temperature, low current conditions). Fig. 19 is a diagram showing the relationship between turn-on loss Eon and distance L2 under the conditions of room temperature, low current. Fig. 20 is a diagram showing the relationship between the sum of turn-on loss and reverse recovery loss Eon+Err and distance L2 under the conditions of room temperature, low current.

[0138] FIG. 21 shows the results when the ambient temperature is 150° C. and the operating current of the semiconductor device 100 is 400 A / cm 2 Fig. 21 is a diagram showing the relationship between turn-off loss Eoff and distance L2 under conditions of approximately the same temperature and large current (referred to as high temperature and large current conditions). Fig. 22 is a diagram showing the relationship between turn-on loss Eon and distance L2 under high temperature and large current conditions. Fig. 23 is a diagram showing the relationship between the sum of turn-on loss and reverse recovery loss Eon+Err and distance L2 under high temperature and large current conditions.

[0139] 18 to 23, by setting the distance L2 to be between two and three times the distance L1, the switching loss of the semiconductor device 100 can be reduced. In particular, the turn-on loss and reverse recovery loss can be reduced under room temperature and low current conditions. Furthermore, by setting the distance L2 to be about 2.5 times the distance L1, the switching loss of the semiconductor device 100 can be minimized. The distance L2 may be between 2.25 and 2.75 times the distance L1.

[0140] Increasing distance L2 in the region where distance L2 is less than 2.5 times distance L1 increases the time change in collector-emitter voltage dV / dt at turn-on, reducing turn-on loss. However, if distance L2 is increased too much, the Miller capacitance between the gate and collector increases, increasing turn-on loss. As shown in Figures 18 to 23, by appropriately setting distance L2, switching loss can be minimized.

[0141] Fig. 24 is a diagram showing the trade-off relationship between switching loss (Eoff+Eon+Err) and the sum (Von+Vf) of the on-voltage of the transistor section 70 and the forward voltage of the diode section 80 under room temperature and low current conditions. Fig. 24 shows the characteristics when the number of accumulation regions in the mesa section 61 is one, two, and three. In this example, the distance L2 is about 2.5 times the distance L1.

[0142] 24, by setting the number of storage regions in the mesa portion 61 to two (for example, two stages consisting of the first storage region 16 and the second storage region 26), the trade-off between switching loss and on-voltage, etc. When the number of storage regions is one, the trade-off is relatively good, but the negative capacitance parasitic on the gate increases, and the change in voltage over time in the gate conductive portion 44 becomes too steep.

[0143] Furthermore, if the number of storage regions is three, the concentration of carriers stored below the storage regions becomes too high. This results in a very large turn-off loss, which increases switching loss. It is preferable that the number of storage regions provided in the mesa portion 61 be two (i.e., the number of storage regions in the capacitance adding portion is one).

[0144] 25 is a diagram showing the trade-off relationship under high temperature and large current conditions between switching loss (Eoff+Eon+Err) and the sum (Von+Vf) of the on-voltage of the transistor section 70 and the forward voltage of the diode section 80. As shown in FIG. 25, by providing two storage regions, the trade-off is improved compared to when the storage regions are provided in three stages.

[0145] 26 is a diagram showing another example of the doping concentration distribution in the d-d' cross section of FIG. 16. As in the example shown in FIG. 5, the doping concentration D1 of the second accumulation region 26 may be higher than the doping concentration Dc of the first accumulation region 16. The doping concentration D1 of the second accumulation region 26 may be higher than the doping concentration of the base region 14. Moreover, the doping concentration D1 of the second accumulation region 26 may be lower than the doping concentration Dc of the first accumulation region 16.

[0146] 27 is a diagram showing another example of the a-a' cross section in FIG. 1. In the semiconductor device 100 of this example, the intermediate mesa portion 60 and the mesa portion 61 of the diode portion 80 also have a structure similar to the mesa portion 61 of the transistor portion 70 shown in FIG. 16. That is, the mesa portion 61 and the intermediate mesa portion 60 each have a first accumulation region 16 and a second accumulation region 26. This structure also reduces the turn-on loss of the semiconductor device 100 and improves the trade-off between switching loss and on-voltage, etc.

[0147] 28 is a diagram partially illustrating the top surface of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 differs from the semiconductor device 100 in that an intermediate region 90B is newly provided between the intermediate region 90A and the diode section 80. The intermediate region 90A in the semiconductor device 300 corresponds to the intermediate region 90 in the semiconductor device 100. The other structures are the same as those of the semiconductor device 100 according to any of the aspects described with reference to FIGS. 1 to 27.

[0148] In the intermediate region 90B, contact regions 15 are provided only at both ends in the extension direction of the contact hole 54. Furthermore, the base region 14 is exposed on the upper surface of the semiconductor substrate between the contact regions 15 at both ends in the extension direction. The area of ​​the exposed base region 14 on the upper surface of the intermediate region 90B may be 5 times or more, 10 times or more, or 20 times or more the area of ​​the contact region 15.

[0149] Furthermore, the number of intermediate mesas 60 in the intermediate region 90B may be equal to or greater than the number of intermediate mesas 60 in the intermediate region 90A. Here, the number of intermediate mesas 60 refers to the number of intermediate mesas 60 sandwiched between trench portions in the arrangement direction. In this example, the number of intermediate mesa portions 60 in the intermediate region 90A is one, and the number of intermediate mesa portions 60 in the intermediate region 90B is two.

[0150] FIG. 29 is a cross-sectional view taken along the line a-a' in FIG. 28. The collector region 22 of the intermediate region 90A may be extended to form an extension on the underside of the semiconductor substrate 10 directly below the intermediate region 90B. In this example, the first accumulation region 16, the second accumulation region 26, and the third accumulation region 28 are not formed in the intermediate region 90A or the intermediate region 90B. When the diode section 80 is conducting in the forward direction, holes flow from the intermediate region 90A of the transistor section 70 toward the cathode region 82 of the diode section 80. Since the contact region 15 is formed over almost the entire surface of the intermediate region 90A, a large amount of holes are injected. By providing the intermediate region 90B, the distance between the intermediate region 90A and the cathode region 82 is increased, thereby suppressing the amount of holes injected from the intermediate region 90A to the diode section 80.

[0151] FIG. 30 is another example of the a-a' cross-sectional view of FIG. 28. In this example, the number of stages of accumulation regions provided in each mesa portion decreases from the transistor portion 70 toward the diode portion 80. The other structures are the same as those of the semiconductor device 300 shown in FIG. 29. In the example shown in FIG. 30, the mesa portion 61 of the transistor portion 70 is formed with the first accumulation region 16 and the second accumulation region 26, and the mesa portion 61 of the transistor portion 70 adjacent to the intermediate region 90A is formed with only the first accumulation region 16. No accumulation regions are formed in the mesa portions of the diode portion 80, the intermediate region 90A, and the intermediate region 90B. In this example, too, by providing the intermediate region 90B, the distance between the intermediate region 90A and the cathode region 82 is increased, thereby suppressing the amount of holes injected from the intermediate region 90A into the diode portion 80.

[0152] FIG. 31 is another example of the a-a' cross-sectional view of FIG. 28. In this example, accumulation regions are formed in the mesa portions of the transistor portion 70 and intermediate region 90A, but not in the mesa portions of the diode portion 80 and intermediate region 90B. In the example shown in FIG. 31, a first accumulation region 16 and a second accumulation region 26 are formed in each mesa portion of the transistor portion 70 and intermediate region 90A. In this example, too, providing intermediate region 90B increases the distance between intermediate region 90A and cathode region 82, thereby reducing the amount of holes injected from intermediate region 90A into diode portion 80.

[0153] 32 is a diagram showing an example of a cross section of a semiconductor device 400 according to another embodiment of the present invention. In addition to the configuration of the semiconductor device described with reference to FIGS. 1 to 31, semiconductor device 400 further includes a bottom region 17. The configuration other than bottom region 17 is the same as that of the semiconductor device of any of the aspects described with reference to FIGS. 1 to 31. FIG. 32 shows a configuration in which bottom region 17 is added to the configuration of the a-a' cross section of FIG. 2.

[0154] The bottom region 17 is a region doped with impurities of the second conductivity type. In this example, the bottom region 17 is P-type. The peak value of the doping concentration of the bottom region 17 may be smaller than, larger than, or the same as the peak value of the doping concentration of the base region 14.

[0155] The bottom region 17 is provided in each mesa of the transistor section 70 between the accumulation region formed at the lowest position (the second accumulation region 26 in the example of FIG. 32 ) and the drift region 18. The bottom region 17 may be provided adjacent to the trench portions on both sides of each mesa. The bottom region 17 may not be provided in the intermediate region 90 and the diode section 80.

[0156] The bottom region 17 may be electrically floating with respect to the base region 14 and the emitter electrode 52. In another example, the bottom region 17 may be connected to the base region 14 or the emitter electrode 52 via a P-type region.

[0157] The bottom region 17 may be provided in a range facing the gate conductive portion 44 in the depth direction of the semiconductor substrate 10. The bottom region 17 may also be located higher than the bottom of the adjacent trench portion. In another example, the bottom region 17 may cover at least a portion of the bottom of the adjacent trench portion.

[0158] Providing the bottom region 17 can alleviate electric field concentration in each mesa portion 61, improving the breakdown voltage. In particular, in a mesa portion 61 provided with multiple accumulation regions, the electric field tends to concentrate in the mesa portion 61. The bottom region 17 may be provided in a mesa portion 61 provided with multiple accumulation regions. The bottom region 17 does not need to be provided in a mesa portion 61 with only one accumulation region or with no accumulation region. In the depth direction of the semiconductor substrate 10, the areas between the multiple accumulation regions 16, 26, 28 may be N-type doped with a lower doping concentration than the peak concentrations of the multiple accumulation regions 16, 26, 28.

[0159] Alternatively, the P-type regions between the multiple accumulation regions 16, 26, 28 in the depth direction of the semiconductor substrate 10 may be P-type. In this case, the doping concentration of the P-type regions between the multiple accumulation regions 16, 26, 28 may be equal to or less than the maximum doping concentration of the base region 14 and equal to or greater than the maximum doping concentration of the bottom region 17, or may be equal to or less than the maximum doping concentration of the bottom region 17. In particular, if the doping concentration of the P-type regions between the multiple accumulation regions 16, 26, 28 is equal to or less than the maximum doping concentration of the bottom region 17, electron current tends to flow near the center of the mesa portion 61.

[0160] As an example, the buffer region 20 in the semiconductor device 400 has multiple peaks 13 in the doping concentration distribution in the depth direction. However, the doping concentration distribution in the buffer region 20 may have a single peak or may have a substantially uniform concentration throughout. The semiconductor device 400 shown in FIG. 32 has four peaks in the buffer region 20. The uppermost peak 13-1 may have a higher concentration than the next upper peak 13-2.

[0161] Fig. 33 is a diagram showing another example of a semiconductor device 400. Fig. 33 shows a configuration in which a bottom region 17 is added to the configuration of the a-a' cross section of Fig. 7. The other configuration is the same as that of the semiconductor device 100 shown in Fig. 7.

[0162] In the semiconductor device 400 of this example, the mesa portion 61 in which two or more accumulation regions are formed is provided with a bottom region 17. The other mesas are not provided with a bottom region 17.

[0163] Furthermore, the depth position of the lower end of the bottom region 17 may be the same even in mesa portions 61 with different numbers of accumulation region steps. In other words, the thickness in the depth direction of the bottom region 17 of a mesa portion 61 with a fewer number of accumulation region steps may be greater than the thickness of the bottom region 17 of a mesa portion 61 with a larger number of accumulation region steps. In another example, the thickness of each bottom region 17 may be constant regardless of the number of accumulation region steps. This structure also alleviates electric field concentration in each mesa portion 61, improving the breakdown voltage.

[0164] 34 is a diagram partially illustrating the top surface of a semiconductor device 500 according to another embodiment of the present invention. The semiconductor device 500 differs from any of the semiconductor devices described in FIGS. 1 to 33 in the cross-sectional shape of the trench portion. The other structures may be the same as any of the semiconductor devices described in FIGS. 1 to 33.

[0165] 34 differs from the semiconductor device described in FIGS. 1 to 33 in that it does not include gate wiring 48 and contact hole 49. In the semiconductor device 500 shown in FIG. 34, the gate electrode 50 is disposed at a position overlapping with the tip portion 41 of the gate trench portion 40. The gate electrode 50 passes through a contact hole 59 formed in the interlayer insulating film 38 and is directly connected to the gate conductive portion 44 of the gate trench portion 40. However, the semiconductor device 500 may include gate wiring 48 and contact hole 49, similar to the semiconductor devices in FIGS. 1 to 33.

[0166] Fig. 35 is a cross-sectional view taken along line a-a' in Fig. 34. As described above, semiconductor device 500 differs from the semiconductor devices of Figs. 1 to 33 in the cross-sectional shape of the trench portion. In the example of Fig. 35, mesa portion 61 is provided with first accumulation region 16 and second accumulation region 26, while intermediate mesa portion 60 and diode portion 80 are not provided with accumulation regions. However, the number of stages of accumulation regions in each mesa portion may be the same as the number of stages of accumulation regions in any of the semiconductor devices described in Figs. 1 to 33.

[0167] The gate trench 40 of this example has a tapered portion whose width in a direction parallel to the upper surface of the semiconductor substrate 10 (i.e., the width in a direction perpendicular to the extension direction of the gate trench 40) becomes smaller toward the upper side. The dummy trench 30 may have the same shape as the gate trench 40, or may have the same shape as the gate trench 40 described with reference to FIGS. 1 to 33.

[0168] 36 is a diagram illustrating the cross-sectional shape of the gate trench portion 40. In this example, the boundary position is the boundary between the base region 14 and the first accumulation region 16 in the depth direction of the semiconductor substrate 10. The boundary position may be the boundary position between the base region 14 and the first accumulation region 16 in the region that contacts the gate trench portion 40.

[0169] The gate trench portion 40 has a first tapered portion 45 above the boundary position, the width of which in a direction parallel to the upper surface of the semiconductor substrate 10 decreases toward the upper side (i.e., toward the upper surface of the semiconductor substrate 10). The first tapered portion 45 may be formed over the entire region between the boundary position and the upper surface of the semiconductor substrate 10, or may be formed only in a portion of the region. The first tapered portion 45 may be formed over a range wider than the base region 14, or may be formed over half or more of the region between the boundary position and the upper surface of the semiconductor substrate 10.

[0170] The width W1 of the gate trench portion 40 on the upper surface of the semiconductor substrate 10 may be smaller than the width W10 of the gate trench portion 40 at the boundary position. Furthermore, the width W1 of the gate trench portion 40 may be smaller than the width W2 at the bottom of the gate trench portion 40. By reducing the width W1 of the gate trench portion 40 on the upper surface of the semiconductor substrate 10, the distance between the gate trench portion 40 and the contact hole 54 can be increased. Therefore, even when the semiconductor device 500 is miniaturized, the distance between the gate trench portion 40 and the contact hole 54 can be secured, and the distance between the gate trench portion 40 and the emitter electrode 52 can be secured. This makes it easier to miniaturize the semiconductor device 500.

[0171] The gate trench portion 40 of this example has a second tapered portion 46 below the boundary position, the width of which increases as it goes downward. The second tapered portion 46 may be formed over the entire region between the boundary position and the trench bottom, or may be formed only in a portion of the region. The second tapered portion 46 may be formed over a range wider than the region from the top end of the uppermost accumulation region (first accumulation region 16 in this example) to the bottom end of the lowermost accumulation region (second accumulation region 26 in this example), or may be formed over more than half of the region between the boundary position and the trench bottom.

[0172] This structure makes it easy to reduce the width W1 of the gate trench portion 40 on the upper surface of the semiconductor substrate 10. Furthermore, since the gate trench portion 40 has the second tapered portion 46, the mesa width W5 between the gate trench portion 40 and the dummy trench portion 30 at the trench bottom is reduced. This facilitates the flow of the displacement current shown in FIGS. 13 and 14 . In contrast, according to the semiconductor device 500, multiple accumulation regions are provided in the mesa portion 61, which facilitates the flow of electron current near the center of the mesa portion 61, as shown in FIG. 14 . This allows the hole distribution near the trench bottom to be separated at the center of the mesa portion 61, thereby suppressing the displacement current.

[0173] The width W1 of the gate trench portion 40 on the upper surface of the semiconductor substrate 10 may be 0.8 times or less, or may be 0.7 times or less, the maximum width W2 (in this example, the width at the trench bottom) of the gate trench portion 40. The width W1 of the gate trench portion 40 may be smaller than the maximum width W3 of the mesa portion 61 (in this example, the mesa width at the substrate upper surface), may be smaller than the minimum width W5 of the mesa portion 61 (in this example, the mesa width at the trench bottom), and may be smaller than the width W4 of the contact hole 54.

[0174] The maximum width W2 of the gate trench portion 40 may be greater than the minimum width W5 of the mesa portion 61. The maximum width W2 of the gate trench portion 40 may be greater than the maximum width W3 of the mesa portion 61. The angle θ1 of the sidewall of the first tapered portion 45 and the angle θ2 of the sidewall of the second tapered portion 46 with respect to a plane parallel to the top surface of the semiconductor substrate 10 may be the same or different. The angle θ1 may be greater or smaller than θ2. In this example, the angles θ1 and θ2 are equal. Note that the angles θ1 and θ2 may be the maximum angles between the tangents to the sidewalls of each tapered portion and the top surface of the substrate. Furthermore, the angles θ1 and θ2 may be the angles of the tangents to the sidewalls at the center positions in the depth direction of each tapered portion.

[0175] FIG. 37 is a diagram showing another example of the cross-sectional shape of the gate trench 40. The gate trench 40 of this example has curved corners at the bottom of the trench. Other structures may be the same as those of the gate trench 40 shown in FIG. 36. This structure can reduce the electric field at the corners at the bottom of the trench. In addition, the distance between the gate trench 40 and the dummy trench 30 at the bottom of the trench can be increased, suppressing displacement current.

[0176] FIG. 38 is a cross-sectional view taken along the line b-b' in FIG. 34. As described above, the gate electrode 50 in this example is directly connected to the gate conductive portion at the tip 41 of the gate trench portion 40 via the contact hole 59. In contrast, when the gate conductive portion and the gate electrode 50 are connected via the gate wiring 48 as shown in FIG. 1, charges flowing parallel to the upper surface of the substrate through the gate wiring 48 flow in the depth direction of the substrate in the gate conductive portion. In this case, if the connection point between the gate wiring 48 and the gate conductive portion has a sharp corner, charges will undesirably concentrate at the corner. Therefore, to reduce the connection angle between the gate wiring 48 and the gate conductive portion, the gate trench portion 40 preferably has an inverse tapered structure near the upper surface of the semiconductor substrate 10, in which the width increases as it approaches the upper surface of the semiconductor substrate 10. However, if the upper end of the gate trench portion 40 has an inverse tapered structure, the distance between the gate trench portion 40 and the contact hole 54 will be reduced in the cross section shown in FIG. 36.

[0177] In this example, since the gate electrode 50 is directly connected to the gate conductive portion, the upper end of the gate trench portion 40 does not need to have an inverted tapered structure. For this reason, as shown in Figure 36 etc., a first tapered portion 45 is provided in the gate trench portion 40, which makes it easy to reduce the width W1 of the gate trench portion 40 on the upper surface of the substrate.

[0178] 38, it becomes relatively difficult to align the gate electrode 50 with the gate trench portion 40. For this reason, it is preferable that the width W6 of the upper end of the gate trench portion 40 in the portion that contacts the gate electrode 50 is larger than the width W1 of the upper end of the gate trench portion 40 in the portion that does not contact the gate electrode 50. For example, the width W6 of the gate trench portion 40 in the portion that contacts the gate electrode 50 is larger than the width W1 of the extension portion 39 of the gate trench portion 40.

[0179] FIG. 39 is a diagram showing an example of a process for forming the gate trench portion 40 shown in FIGS. 35 to 38. First, in S550, shallow trenches 502 are formed in the upper surface 501 of the semiconductor substrate 10. The trenches 502 can be formed by forming a mask of a predetermined pattern on the upper surface 501 of the semiconductor substrate 10 and etching the upper surface 501 of the semiconductor substrate 10. Each trench in FIG. 39 may be formed by anisotropic etching or isotropic etching. After the trenches 502 are formed, a protective film 503 such as a nitride film is formed on the side walls of the trenches 502.

[0180] In S552, the bottom surface of the trench 502 is etched to form a trench 504. The width of the trench 504 is greater than the width of the trench 502. After the trench 504 is formed, a protective film 503 is formed on the sidewall of the trench 504. In S554, the formation of the trenches is repeated. The number of steps of the trench may be adjusted depending on the depth of the trench to be formed. The protective film 503 is not formed on the sidewall of the last formed trench 505.

[0181] In S555, after forming the grooves 505, the protective films 503 are removed, thereby forming tapered trenches 506. After removing the protective films 503, the entire inner wall of the trench 506 may be isotropically etched to make the inner wall of the trench 506 smooth.

[0182] 40 is a diagram showing another example of the cross-sectional shape of the gate trench portion 40. Aside from the cross-sectional shape of the gate trench portion 40, the semiconductor device 500 may have the same structure as the examples described in FIGS.

[0183] FIG. 41 is a diagram illustrating the cross-sectional shape of the gate trench portion 40. The gate trench portion 40 of this example has a first tapered portion 45 and a third tapered portion 47. The first tapered portion 45 is similar to the first tapered portion 45 described with reference to FIGS. 35 to 38. However, while the sidewalls of the first tapered portion 45 shown in FIG. 35 have a substantially linear shape, the sidewalls of the first tapered portion 45 of this example have an outwardly convex curved shape. Note that the sidewalls of the first tapered portion 45 in the example of FIG. 35 and this example may have either a linear shape or a curved shape.

[0184] The third tapered portion 47 is provided below the boundary position, and its width decreases as it goes downward. The third tapered portion 47 may be formed over the entire region between the boundary position and the trench bottom, or may be formed only in a portion thereof. The third tapered portion 47 may be formed over more than half of the region between the boundary position and the trench bottom. The sidewall of the third tapered portion 47 may have a linear shape or a curved shape. In the example of FIG. 41, the sidewall of the third tapered portion 47 has an outwardly convex curved shape.

[0185] The gate trench portion 40 has the first tapered portion 45 and the third tapered portion 47, so that the width W8 of the gate trench portion 40 on the upper surface of the substrate can be reduced while increasing the distance between the gate trench portion 40 and the dummy trench portion 30 at the trench bottom. This makes it possible to easily miniaturize the semiconductor device 500 and suppress displacement current.

[0186] The gate trench portion 40 has a maximum width portion 98, where the width of the gate trench portion 40 is greatest, between the first tapered portion 45 and the third tapered portion 47. The maximum width portion 98 may be located below the boundary between the base region 14 and the first accumulation region 16. The width W7 of the gate trench portion 40 at the maximum width portion 98 may be 1.2 times or more, or 1.3 times or more, the width of the gate trench portion 40 at the upper surface of the substrate.

[0187] The angle of the sidewall of the first tapered portion 45 relative to a plane parallel to the top surface of the semiconductor substrate 10 is defined as θ1, and the angle of the sidewall of the second tapered portion 46 relative to the plane parallel to the top surface of the semiconductor substrate 10 is defined as θ2. If angle θ1 is an acute angle, angle θ3 is an obtuse angle. That is, θ1 and θ3 may have a relationship in which one of them is an acute angle and the other is an obtuse angle. The angles θ1 and θ3 may be the maximum angles formed between the tangent to the sidewall of each tapered portion and the top surface of the substrate. Furthermore, angle θ1 may be an acute angle at any position in the depth direction of the first tapered portion 45. The angle θ3 may be an obtuse angle at any position in the depth direction of the third tapered portion 47. Furthermore, the angles θ1 and θ2 may be the angles of the tangent to the sidewall at the center of the depth direction of each tapered portion. The sidewall of the first tapered portion 45 may have a convex shape on the upward side. The sidewall of the third tapered portion 47 may have a convex shape on the downward side.

[0188] Either of the accumulation regions may be disposed at the same depth as the maximum width portion 98. In the example of FIG. 41, the first accumulation region 16 is disposed at the same depth as the maximum width portion 98. The width of the mesa portion 61 is narrower in the region where the maximum width portion 98 is provided. By providing an accumulation region at this position, holes are accumulated in a narrow region, and the concentration of holes accumulated by the accumulation region can be increased.

[0189] 42 is a diagram showing an example of the relationship between the depth position of the maximum width portion 98 of the gate trench portion 40 and the first accumulation region 16. As described above, the first accumulation region 16 is disposed at the same depth position as the maximum width portion 98. In this example, the range R1 of the first accumulation region 16 is defined as the range from the boundary between the base region 14 and the first accumulation region 16 to the boundary between the first accumulation region 16 and the second accumulation region 26. The position of the maximum width portion 98 (maximum width position) may be disposed within the range R1 of the first accumulation region 16.

[0190] Furthermore, the maximum width portion 98 may be located in a range R2 of the half-width of the doping concentration distribution in the depth direction of the first accumulation region 16. Furthermore, the peak position of the doping concentration distribution in the depth direction of the first accumulation region 16 may overlap with the depth position of the maximum width portion 98.

[0191] Figure 43 is another example of the cross-sectional view taken along the line a-a' in Figure 34. The semiconductor device 500 of this example differs from the semiconductor device 500 described with reference to Figures 40 to 42 in the number of stages of the accumulation region in the mesa portion 61. The other structures are the same as those of the semiconductor device 500 described with reference to Figures 40 to 42.

[0192] The semiconductor device 500 of this example has only one accumulation region in the mesa portion 61 (first accumulation region 16 in this example). The gate trench portion 40 of this example has a small width at the trench bottom, so the distance between the trench bottom and the dummy trench portion 30 is large. This makes it possible to suppress displacement current. Therefore, even if there is only one accumulation region, a large displacement current does not flow.

[0193] FIG. 44 is a diagram showing an example of the relationship between the depth position of the maximum width portion 98 of the gate trench portion 40 and the first accumulation region 16 in the example of FIG. 43. In this example, the first accumulation region 16 may also be located at the same depth position as the maximum width portion 98. In this example, the range R1 of the first accumulation region 16 is defined as the range from the boundary between the base region 14 and the first accumulation region 16 to the boundary between the first accumulation region 16 and the drift region 18. The position of the maximum width portion 98 (maximum width position) may be located within the range R1 of the first accumulation region 16.

[0194] Furthermore, the maximum width portion 98 may be located in a range R2 of the half-width of the doping concentration distribution in the depth direction of the first accumulation region 16. Furthermore, the peak position of the doping concentration distribution in the depth direction of the first accumulation region 16 may overlap with the depth position of the maximum width portion 98.

[0195] 45 is a diagram showing an example of a process for forming a gate trench 40 having a first tapered portion 45 and a third tapered portion 47. Steps S550 and S552 are similar to the process in FIG. 39. Depending on the depth to which the gate trench 40 is to be formed, step S552 may be repeated to form multiple grooves 504 whose widths gradually increase.

[0196] In S556, the protective film 503 of each trench is removed. In S557, the entire sidewall and bottom surface of each trench is isotropically etched to form trenches 510. This allows the first tapered portion 45 to be formed in the region where the trench was formed, and the third tapered portion 47 to be formed below the trench.

[0197] 46 is a diagram showing another example of the cross-sectional shape of the gate trench portion 40. The gate trench portion 40 of this example has a lower portion 86 that includes the bottom of the gate trench portion 40, and a thin film portion 84 that is provided above the lower portion 86 and in which the gate insulating film 42 is thinner than the gate insulating film 42 of the lower portion 86. By making the gate insulating film 42 thicker at the trench bottom, it is possible to increase the breakdown voltage of the gate insulating film 42 at the trench bottom where an electric field is likely to concentrate.

[0198] An intermediate portion 87, in which the thickness of the gate insulating film 42 changes continuously, may be provided between the thin film portion 84 and the lower portion 86. The thickness of the gate insulating film 42 in the thin film portion 84 may be approximately constant. The thickness of the gate insulating film 42 in the lower portion 86 may be approximately constant. The gradient of the change in thickness of the gate insulating film 42 in the intermediate portion 87 is greater than the gradient of the change in thickness of the gate insulating film 42 in the thin film portion 84 and the lower portion 86.

[0199] In the present example, a plurality of accumulation regions are provided in the mesa portion 61. In the example of FIG. 46, a first accumulation region 16 and a second accumulation region 26 are provided. Of the accumulation regions, the first accumulation region 16, which is arranged at the uppermost position, may be arranged opposite the thin film portion 84. The first accumulation region 16 facing the thin film portion 84 means that the peak position of the doping concentration distribution in the depth direction of the first accumulation region 16 is arranged opposite the thin film portion 84. The entire first accumulation region 16 may be arranged opposite the thin film portion 84.

[0200] Among the accumulation regions, the second accumulation region 26, which is located at the bottom, also functions as a capacitance adding portion. The second accumulation region 26 may be located opposite at least one of the intermediate portion 87 and the lower portion 86. The second accumulation region 26 may be located such that the peak position of the doping concentration distribution in the depth direction faces the lower portion 86, or the entire second accumulation region 26 may be located opposite the lower portion 86. It is preferable that the second accumulation region 26 increase the gate-collector capacitance to an extent that can compensate for the decrease in gate-collector capacitance caused by thickening the gate insulating film 42 in the lower portion 86. The peak value of the doping concentration of the second accumulation region 26 may be higher than the peak value of the doping concentration of the first accumulation region 16.

[0201] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0202] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0203] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 first accumulation region, 17 bottom region, 18 drift region, 19 high concentration region, 20 buffer region, 21 connection portion, 22 collector region, 24 collector electrode, 25 connection portion, 26 second accumulation region, 28 Third accumulation region, 29 Extension portion, 30 Dummy trench portion, 31 Tip portion, 32 Dummy insulating film, 33 Capacitive adding portion, 34 Dummy conductive portion, 38 Interlayer insulating film, 39 Extension portion, 40 Gate trench portion, 41 Tip portion, 42 Gate insulating film, 44 Gate conductive portion, 45 First tapered portion, 46 Second tapered portion, 4 7...Third tapered portion, 48...Gate wiring, 49...Contact hole, 50...Gate electrode, 52...Emitter electrode, 54...Contact hole, 56, 58, 59...Contact holes, 60...Intermediate mesa portion, 61...Mesa portion, 70...Transistor portion, 80...Diode portion, 82...Cathode region, 84...Thin film portion, 86...Lower portion, 87... Intermediate portion, 88... double arrow, 90... intermediate region, 91, 92, 93, 94... waveform, 98... maximum width portion, 100... semiconductor device, 200... dotted line, 300... semiconductor device, 400... semiconductor device, 500... semiconductor device, 501... upper surface, 502... groove portion, 503... protective film, 504... groove portion, 505... groove portion, 506... trench, 510... trench

Claims

1. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the transistor region are separated from each other; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the mesa portion including a plurality of first conductivity type emitter regions provided in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with The separation region is a semiconductor device in which the drift region or the accumulation region is in contact with the lower surface of the base region.

2. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the transistor region are separated from each other; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the mesa portion including a plurality of first conductivity type emitter regions provided in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with In the separation region, the bottom region is not provided below a portion of the base region that contacts the well region.

3. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the transistor region are separated from each other; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the mesa portion including a plurality of first conductivity type emitter regions provided in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with The semiconductor device wherein an end of the accumulation region in the first direction is located inside the transistor region in a plan view.

4. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the transistor region are separated from each other; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the mesa portion including a plurality of first conductivity type emitter regions provided in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with the trench portion includes a gate trench portion having a gate conductive portion as the conductive portion, and a dummy trench portion having a dummy conductive portion as the conductive portion, the mesa portion includes a first mesa portion disposed adjacent to the gate trench portion, in which a channel is formed in the base region therein when a predetermined gate voltage is applied to the gate conductive portion, and a second mesa portion disposed adjacent to the dummy trench portion, in which a channel is not formed in the base region therein even when a predetermined gate voltage is applied to the gate conductive portion; The bottom region of the semiconductor device has different thicknesses between the first mesa portion and the second mesa portion.

5. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the transistor region are separated from each other; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the mesa portion including a plurality of first conductivity type emitter regions provided in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with The transistor region is provided away from the well region, and includes a contact hole having a longitudinal direction in the first direction.

6. The contact hole is provided to an outer side of the emitter region closest to the well region in the first direction. The semiconductor device according to claim 5 .

7. The contact hole is not formed in the separation region.

7. The semiconductor device according to claim 5.

8. The bottom region is provided between the accumulation region and the drift region, and is provided from one of the trench portions adjacent to the mesa portion to the other of the trench portions. The semiconductor device according to claim 1 .

9. The bottom region covers at least a portion of the bottom of the adjacent trench portion. The semiconductor device according to claim 1 .

10. The mesa portion where the accumulation region is not provided has a region where the bottom region is not provided. The semiconductor device according to claim 1 .

11. The transistor region includes a region where the bottom region is not provided. The semiconductor device according to claim 1 .

12. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; an emitter region of a first conductivity type provided above the base region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the emitter region are spaced apart; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the emitter regions being provided in plurality in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with the separation region separates the well region from the emitter region that is provided closest to the well region among the plurality of emitter regions included in the transistor region; The separation region is a region where the drift region or the accumulation region is in contact with the lower surface of the base region. Semiconductor device.

13. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; an emitter region of a first conductivity type provided above the base region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the emitter region are spaced apart; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the emitter regions being provided in plurality in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with the separation region separates the well region from the emitter region that is provided closest to the well region among the plurality of emitter regions included in the transistor region; In the separation region, the bottom region is not provided below a portion of the base region that contacts the well region. Semiconductor device.

14. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; an emitter region of a first conductivity type provided above the base region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the emitter region are spaced apart; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the emitter regions being provided in plurality in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with the separation region separates the well region from the emitter region that is provided closest to the well region among the plurality of emitter regions included in the transistor region; the trench portion includes a gate trench portion having a gate conductive portion as the conductive portion, and a dummy trench portion having a dummy conductive portion as the conductive portion, the mesa portion includes a first mesa portion disposed adjacent to the gate trench portion, in which a channel is formed in the base region therein when a predetermined gate voltage is applied to the gate conductive portion, and a second mesa portion disposed adjacent to the dummy trench portion, in which a channel is not formed in the base region therein even when a predetermined gate voltage is applied to the gate conductive portion; The bottom region has different thicknesses between the first mesa portion and the second mesa portion. Semiconductor device.

15. A semiconductor device including a transistor region, which is a region in which predetermined unit structures are regularly arranged on a semiconductor substrate, and an edge termination structure surrounding the transistor region, a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region in the semiconductor substrate; an emitter region of a first conductivity type provided above the base region in the semiconductor substrate; a plurality of trenches provided on the front surface side of the semiconductor substrate and having conductive portions therein; a well region of a second conductivity type provided on the side of the edge termination structure; a separation region in which the well region and the emitter region are spaced apart; Including, The transistor region is a mesa portion of the semiconductor substrate sandwiched between the trench portions and having a longitudinal direction in a first direction, the emitter regions being provided in plurality in the first direction; an accumulation region of a first conductivity type and a bottom region of a second conductivity type provided in the mesa portion below the plurality of emitter regions and provided in this order from the front surface side of the semiconductor substrate; Equipped with the separation region separates the well region from the emitter region that is provided closest to the well region among the plurality of emitter regions included in the transistor region; The transistor region is provided apart from the well region and includes a contact hole having a longitudinal direction in the first direction. Semiconductor device.

16. The contact hole is provided to an outer side of the emitter region closest to the well region in the first direction. The semiconductor device according to claim 15.

17. The contact hole is not formed in the separation region.

17. The semiconductor device according to claim 15 or 16.

18. the transistor region is provided in the mesa portion and includes a contact region of a second conductivity type having a doping concentration higher than that of the base region; The transistor region is a region in which the emitter regions and the contact regions are regularly arranged. The semiconductor device according to claim 1 .

19. At least a portion of the accumulation region is provided at the same depth as the bottom region. The semiconductor device according to claim 1 .

20. The accumulation region has a higher doping concentration than the drift region. The semiconductor device according to claim 1 .

21. The accumulation region has a plurality of peaks in the doping concentration distribution in the depth direction. The semiconductor device according to any one of claims 1 to 20.

22. The bottom region has a lower peak doping concentration than the base region. The semiconductor device according to any one of claims 1 to 21.

23. The bottom region is electrically floating The semiconductor device according to claim 1 .

24. The separation region is a region where the drift region is in contact with the lower surface of the base region.

24. The semiconductor device according to claim 1.

25. The semiconductor device is a semiconductor chip having a diode portion provided on the semiconductor substrate.

25. The semiconductor device according to claim 1.

26. At least one of the plurality of trench portions is a first tapered portion, the first tapered portion being located above a depth position of the lower surface of the base region and having a width in a second direction perpendicular to the first direction that decreases toward the upper side; a second tapered portion, the width of which increases downward, located below a depth position of the lower surface of the base region; The accumulation region is the trench portion is provided between a depth position of the lower surface of the base region and a depth position of the bottom of the trench portion in a depth direction of the semiconductor substrate, deeper than the center of the depth of the trench portion, At least the mesa portion is provided on the front surface side of the lower end of the trench portion.

26. The semiconductor device according to claim 1.

27. At least one of the plurality of trench portions is a first tapered portion, the first tapered portion being located above a depth position of the lower surface of the base region and having a width in a second direction perpendicular to the first direction that decreases toward the upper side; a third tapered portion, the width of which decreases downward, located below a depth position of the lower surface of the base region; The accumulation region is the trench portion is provided between a depth position of the lower surface of the base region and a depth position of the bottom of the trench portion in a depth direction of the semiconductor substrate, deeper than the center of the depth of the trench portion, At least the mesa portion is provided on the front surface side of the lower end of the trench portion.

26. The semiconductor device according to claim 1.

28. a first upper surface electrode and a second upper surface electrode provided separately from each other; an interlayer insulating film provided below the first upper surface electrode and the second upper surface electrode; Equipped with The second upper electrode is in contact with the emitter region through a contact hole provided in the interlayer insulating film.

28. The semiconductor device according to claim 26 or 27.

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