Semiconductor Devices

Abstract

To provide a semiconductor device having an excellent electric field relaxation effect while reducing on-resistance.SOLUTION: Provided is a semiconductor device including: a gate electrode at least partially embedded in a semiconductor layer; a deep p layer at least partially embedded in the semiconductor layer at the same depth as an embedded lower end of the gate electrode or to a position deeper than the embedded lower end; and a channel layer. The channel layer contains, as main components, a first p-type oxide semiconductor, and the deep p layer contains, as main components, a second p-type oxide semiconductor different from the first p-type oxide semiconductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device useful as a power device or the like, and a semiconductor system including the same. [Background technology]

[0002] Semiconductor devices using gallium oxide (Ga2O3), which has a wide band gap, are attracting attention as a next-generation crystalline oxide semiconductor material that can achieve high voltage resistance, low loss, and high heat resistance. Semiconductor devices containing crystalline oxide semiconductors are expected to be used as switching elements in power semiconductor devices such as inverters. In addition, due to their wide band gap, they are also expected to be used in light-emitting and receiving devices such as LEDs and sensors.

[0003] Gallium oxide is known to have five crystal structures: α, β, γ, δ, and ε (Non-Patent Document 1). However, since the most stable phase of gallium oxide is the β gallium structure, there is a problem that it is difficult to form a crystalline film containing gallium oxide having, for example, a corundum structure, which is a metastable phase, without using a special film formation method. In response to this, several studies are currently being conducted on the formation of crystalline oxide semiconductor films containing gallium oxide and / or its mixed crystals, including the formation of crystalline semiconductors having a corundum structure.

[0004] For example, Patent Document 1 describes that gallium oxide can be mixed with indium and aluminum, either individually or in combination, to control the band gap, and describes it as an InAlGaO-based semiconductor. X Al Y Ga ZO3 (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5 to 2.5), and can be viewed as the same material family containing gallium oxide. Patent Document 2 also describes a semiconductor device that includes an n-type semiconductor layer containing a crystalline oxide semiconductor (α-Ga2O3, etc.) with a corundum structure as its main component, and an electric field shielding layer and a gate electrode that are stacked on the n-type semiconductor layer, in which a p-type oxide semiconductor is used for the electric field shielding layer.

[0005] While semiconductor devices containing gallium oxide can achieve high breakdown voltage, low loss, and high heat resistance, they are still not satisfactory in fully utilizing the semiconductor properties of gallium oxide. For example, there are problems such as the gate insulating film becoming prone to breakdown due to a high electric field. Therefore, there has been a long awaited development of a semiconductor device that can fully utilize the semiconductor properties of gallium oxide, in particular a semiconductor device that can achieve high breakdown voltage while reducing on-resistance. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2014 / 050793 [Patent Document 2] International Publication No. 2019 / 098298 [Non-patent literature]

[0007] [Non-Patent Document 1] R. Roy VG Hill, and EF Osborn: J. Am. Chem. Soc. 74 (1952) 719 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a semiconductor device that has a reduced on-resistance and an excellent electric field relaxation effect. [Means for solving the problem]

[0009] As a result of intensive research into achieving the above-mentioned object, the inventors have found that a semiconductor device including a gate electrode at least partially buried in a semiconductor layer, a deep p layer at least partially buried in the semiconductor layer to a depth equal to or deeper than a buried lower end of the gate electrode, and a channel layer, wherein the deep p layer is made of a crystalline oxide semiconductor and the carrier concentration of the deep p layer is higher than the carrier concentration of the channel layer, can obtain an electric field relaxation effect while reducing on-resistance. Furthermore, after obtaining the above findings, the present inventors conducted further studies and have now completed the present invention.

[0010] That is, the present invention relates to the following inventions. [1] A semiconductor device including: a gate electrode at least partially buried in a semiconductor layer; a deep p-layer at least partially buried in the semiconductor layer to a position equal to or deeper than a buried lower end of the gate electrode; and a channel layer, A semiconductor device characterized in that the channel layer contains a first p-type oxide semiconductor as a main component, and the deep p-layer contains a second p-type oxide semiconductor different from the first p-type oxide semiconductor as a main component. [2] The semiconductor device according to [1], wherein the first and / or second p-type oxide semiconductor has a corundum structure or a β-gallium structure. [3] The semiconductor device according to [1] or [2], wherein the first p-type oxide semiconductor is gallium oxide or an alloy thereof. [4] The semiconductor device according to any one of [1] to [3] above, wherein a band offset of the conduction band between the channel layer and the semiconductor layer is 1.5 eV or less. [5] The semiconductor device according to [4], wherein the band offset is 1.0 eV or less. [6] The semiconductor device according to any one of [1] to [5], wherein the band gap of the second p-type oxide semiconductor is smaller than the band gap of the first p-type oxide semiconductor. [7] The semiconductor device according to any one of [1] to [6], wherein the second p-type oxide semiconductor is iridium oxide or an alloy thereof. [8] The semiconductor device according to any one of [1] to [7], wherein an i-type semiconductor layer is provided between the deep p-layer and the semiconductor layer. [9] The semiconductor device according to [8], wherein the carrier density of the i-type semiconductor layer is lower than the carrier density of the semiconductor layer.

[10] The semiconductor device according to any one of [1] to [9] above, which is a power device.

[11] A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [1] to

[10] above. [Effects of the Invention]

[0011] According to the semiconductor device of the present invention, it is possible to obtain an excellent electric field relaxation effect while reducing the on-resistance. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic perspective cross-sectional view of a preferred semiconductor device according to the present invention; [Figure 2] 1 is a perspective cross-sectional view schematically showing a preferred example of a semiconductor device of the present invention; [Figure 3] FIG. 1 is a diagram schematically illustrating a preferred example of a power supply system. [Figure 4] FIG. 1 is a diagram schematically illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 5] FIG. 1 is a diagram schematically illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 6] FIG. 1 is a schematic diagram of a film forming apparatus (mist CVD apparatus) that is preferably used in the present invention. [Figure 7] FIG. 1 is a schematic diagram of a film forming apparatus (mist CVD apparatus) that is preferably used in the present invention. [Figure 8] FIG. 1 is a diagram schematically illustrating a preferred example of a power card. [Figure 9]1 is a cross-sectional view schematically showing a preferred semiconductor device according to the present invention. [Figure 10] 1 is a cross-sectional view schematically showing a preferred semiconductor device according to the present invention. [Figure 11] 1 is a cross-sectional view schematically showing a preferred semiconductor device according to the present invention. [Figure 12] FIG. 10 is a diagram showing the results of a device simulation according to the present invention. [Figure 13] FIG. 10 is a diagram showing the results of a device simulation according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] The semiconductor device of the present invention includes a gate electrode at least partially buried in a semiconductor layer, a deep p-layer at least partially buried in the semiconductor layer to the same depth as a buried lower end of the gate electrode or deeper than the buried lower end, and a channel layer, wherein the channel layer contains a first p-type oxide semiconductor as a main component, and the deep p-layer contains a second p-type oxide semiconductor different from the first p-type oxide semiconductor as a main component.

[0014] The "buried lower end of the gate electrode" refers to the entire or part of the bottom of the gate electrode. The gate electrode is not particularly limited as long as it is an electrode that can control the flow of main current, and includes a semiconductor region, a diffusion region, an electrode, and the like.

[0015] The material of the gate electrode is not particularly limited as long as it can be used as a gate electrode, and may be a conductive inorganic material or a conductive organic material. In the present invention, the material of the gate electrode is preferably a metal, a metal compound, a metal oxide, or a metal nitride. Suitable examples of the metal include at least one metal selected from Groups 4 to 11 of the periodic table. Examples of metals in Group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals in Group 6 of the periodic table include one or more metals selected from chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals in Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). Examples of metals in Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au).

[0016] The gate electrode can be formed by known methods, such as a dry method, a wet method, etc. Dry methods include known methods such as sputtering, vacuum deposition, and CVD. Wet methods include screen printing and die coating.

[0017] The channel layer is not particularly limited as long as it is in contact with the gate electrode directly or via another layer and is located between the source electrode (emitter electrode) and the drain electrode (collector electrode). In the present invention, the channel layer contains a first p-type oxide semiconductor as a main component. The first p-type oxide semiconductor preferably contains a d-block metal and / or a Group 13 metal of the periodic table, more preferably a Group 9 metal and / or a Group 13 metal of the periodic table, and most preferably contains at least a Group 13 metal of the periodic table. The term "main component" means that the first p-type oxide semiconductor preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more, of the total components of the channel layer, in atomic ratio, and may even be 100%. For example, when the first p-type oxide semiconductor is α-Ga2O3 containing a p-type dopant, the atomic ratio of gallium among all metal elements in the channel layer may be 0.5 or more. In the present invention, the band gap of the first p-type oxide semiconductor is preferably 5.0 eV or more. In the present invention, the first p-type oxide semiconductor is preferably crystalline. In this case, the first p-type oxide semiconductor may be single crystal or polycrystalline. In addition, the first p-type oxide semiconductor preferably has a corundum structure or a β-gallium structure, and more preferably has a corundum structure.

[0018] In the present invention, the first p-type oxide semiconductor is preferably a crystalline or mixed crystal of a metal oxide containing gallium, and more preferably gallium oxide or a mixed crystal thereof (e.g., α-Ga2O3 or a mixed crystal thereof). In this case, the first p-type oxide semiconductor usually contains a p-type dopant. The p-type dopant is not particularly limited, but examples thereof include Mg, Zn, Ca, H, Li, Na, K, Rb, Cs, Fr, Be, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Cd, Hg, Tl, Pb, N, P, and elements such as two or more of these. The concentration of the dopant is not particularly limited. In the present invention, the carrier concentration is preferably lower than that of the deep p-layer. The dopant concentration is, for example, about 1 × 10 16 / cm 3 ~1×10 22 / cm 3 In the present invention, the concentration of the dopant may be, for example, about 1×10 18 / cm 3 The following low concentrations are preferred:

[0019] The "periodic table" refers to the periodic table established by the International Union of Pure and Applied Chemistry (IUPAC). The "d block" refers to elements having electrons filling the 3d, 4d, 5d, and 6d orbitals. Examples of the d block metals include scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), lutetium (Lu), hafnium (Hf), and chromium (Cu). Examples of suitable metals include ruthenium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), lawrencium (Lr), rutherfordium (Rf), dubnium (Db), seaborgium (Sg), bohrium (Bh), hassium (Hs), meitnerium (Mt), darmstadtium (Ds), roentgenium (Rg), copernicium (Cn), and two or more of these metals.

[0020] The deep p-type layer is not particularly limited as long as it contains, as a main component, a second p-type oxide semiconductor different from the first p-type oxide semiconductor. In the present invention, the second p-type oxide semiconductor preferably contains a d-block metal and / or a Group 13 metal of the periodic table, more preferably a Group 9 metal and / or a Group 13 metal of the periodic table, and most preferably a Group 9 metal and a Group 13 metal of the periodic table. In the present invention, the second p-type oxide semiconductor is preferably a crystal or mixed crystal of a metal oxide containing iridium, and more preferably iridium oxide or a mixed crystal thereof (e.g., α-Ir2O3 or a mixed crystal thereof). An example of the second p-type oxide semiconductor being a mixed crystal of α-Ir2O3 is α-(IrGa)2O3. In this case, the atomic ratio of Ir to Ga in α-(IrGa)2O3 in the second p-type oxide semiconductor is not particularly limited. In an embodiment of the present invention, the atomic ratio of Ir to the total of Ir and Ga in α-(IrGa)O is, for example, within the range of 1% to 95%. The term "main component" means that the second p-type oxide semiconductor preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the deep p-layer, and may even be 100%. Specifically, for example, when the second p-type oxide semiconductor is α-IrO, it is sufficient that the atomic ratio of iridium to all metal elements in the deep p-layer is 0.5 or more. For example, when the second p-type oxide semiconductor is α-(IrGa)O, it is sufficient that the total atomic ratio of iridium and gallium to all metal elements in the deep p-layer is 0.5 or more. Furthermore, in the present invention, it is preferable that the second p-type oxide semiconductor be crystalline. In this case, the second p-type oxide semiconductor preferably has a corundum structure or a β-gallium structure, more preferably a corundum structure. The deep p-layer may contain a p-type dopant.The p-type dopant is not particularly limited, but examples thereof include Mg, Zn, Ca, H, Li, Na, K, Rb, Cs, Fr, Be, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Cd, Hg, Tl, Pb, N, P, and the like, and two or more elements thereof. The dopant concentration is usually higher than the carrier concentration of the channel layer. The carrier concentration of the deep p-layer is, for example, about 1×10. 16 / cm 3 ~1×10 22 / cm 3 In the present invention, the carrier concentration of the deep p-layer is 1×10 17 / cm 3 It is preferable that the density is equal to or greater than 1×10 18 / cm 3 More preferably, it is equal to or greater than this.

[0021] The semiconductor layer is not particularly limited as long as it is a semiconductor layer made of a semiconductor, but is preferably an n-type semiconductor layer (including an n+-type semiconductor layer and an n--type semiconductor layer). In the present invention, the semiconductor layer is preferably a crystalline oxide semiconductor layer. In addition, in the present invention, it is preferable that the breakdown field strength of the semiconductor layer is 5 MV / cm or more, since better semiconductor characteristics can be exhibited. In addition, in the present invention, it is preferable that the semiconductor layer has a corundum structure or a β-gallium structure, and it is also preferable that it contains gallium oxide or an alloy thereof. The thickness of the semiconductor layer is not particularly limited as long as it does not impede the object of the present invention. In the present invention, the thickness of the semiconductor layer is preferably 50 μm or less, more preferably 30 μm or less, and most preferably 10 μm or less. It is also preferable to set the thickness of the deep p-layer to at least half the thickness of the semiconductor layer (e.g., n-type semiconductor layer). By setting such a preferable thickness, the electric field relaxation effect of the second p-type oxide semiconductor can be further improved and better semiconductor characteristics (including miniaturization) can be exhibited.

[0022] The crystalline oxide semiconductor layer typically contains an oxide semiconductor as a main component. The oxide semiconductor preferably contains gallium, more preferably gallium oxide or a mixed crystal thereof. The crystalline structure of the crystalline oxide semiconductor layer is not particularly limited. Examples of the crystalline structure of the crystalline oxide semiconductor layer include a corundum structure, a β-gallium structure, and a hexagonal structure (e.g., an ε-type structure). In the present invention, the crystalline oxide semiconductor layer preferably has a corundum structure or a β-gallium structure, more preferably a corundum structure. The oxide semiconductor is not particularly limited, but preferably contains at least one or more metals from periods 3 to 6 of the periodic table, more preferably at least one selected from gallium, indium, rhodium, iridium, and aluminum. An n-type oxide semiconductor preferably contains at least gallium. Examples of the oxide semiconductor containing gallium include α-Ga2O3 or a mixed crystal thereof. A crystalline oxide semiconductor layer containing such a preferred oxide semiconductor as a main component can exhibit superior crystallinity and heat dissipation, and can also exhibit even more excellent semiconductor properties. The term "main component" refers to a crystalline oxide semiconductor layer containing 50% or more of the oxide semiconductor, preferably 70% or more, and more preferably 90% or more of the oxide semiconductor, in terms of composition. For example, when the oxide semiconductor is α-Ga2O3, the crystalline oxide semiconductor layer may contain α-Ga2O3 at an atomic ratio of gallium in the metal elements of the crystalline oxide semiconductor layer of 0.5 or more. In the present invention, the atomic ratio of gallium in the metal elements of the crystalline oxide semiconductor layer is preferably 0.7 or more, more preferably 0.8 or more. The oxide semiconductor may be single-crystalline or polycrystalline. The oxide semiconductor is typically in the form of a film, but is not particularly limited thereto as long as it does not impede the objectives of the present invention. It may be in the form of a plate, a sheet, a layer, or a laminate including multiple layers.

[0023] The oxide semiconductor may contain a dopant. The dopant is not particularly limited as long as it does not impede the object of the present invention. It may be an n-type dopant or a p-type dopant. Examples of the n-type dopant include tin, germanium, silicon, titanium, zirconium, vanadium, and niobium. Examples of the p-type dopant include the p-type dopants described above. The concentration of the dopant may be set appropriately, and specifically, for example, about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the dopant concentration may be, for example, about 1×10 17 / cm 3 Furthermore, according to the present invention, the dopant may be present in a concentration as low as about 1×10 20 / cm 3 It may be contained in a concentration higher than this.

[0024] In the present invention, the conduction band offset between the channel layer and the semiconductor layer (drift layer) is preferably 1.5 eV or less, more preferably 1.0 eV or less. This preferred configuration enables the semiconductor device to achieve an electric field relaxation effect while further reducing the on-resistance. A preferred combination of the channel layer and the deep p-layer is, for example, a combination in which the channel layer contains, as a main component, α-Ga2O3 containing a p-type dopant, and the deep p-layer contains, as a main component, α-Ir2O3 or a mixed crystal thereof (e.g., a mixed crystal of iridium oxide and gallium oxide). In this case, the on-resistance can be further reduced by using, as the semiconductor layer (drift layer), α-Ga2O3 containing an n-type dopant. In this case, it is also preferable that an i-type semiconductor layer be provided between the deep p-layer and the semiconductor layer (drift layer). The i-type semiconductor layer is not particularly limited as long as it has a lower carrier density than the semiconductor layer (drift layer). The i-type semiconductor layer may be, for example, a semiconductor layer whose main component is the same material as the main component of the semiconductor layer (drift layer) and / or the deep p-layer. The carrier density of the i-type semiconductor layer may be, for example, 2.0×10 16 / cm 3 By using an i-type semiconductor layer in this way, it is possible to suppress the electric field applied to the deep p-layer, even if the deep p-layer is made of a material with a lower band gap than the semiconductor layer (drift layer).

[0025] The first and second p-type oxide semiconductors, the crystalline oxide semiconductor, and the oxide semiconductor (hereinafter collectively referred to as "the crystalline oxide semiconductors") can be obtained by epitaxial crystal growth using, for example, a mist CVD method or a mist epitaxy method.

[0026] <Crystal substrate> The crystalline substrate is not particularly limited as long as it does not impede the object of the present invention, and may be a known substrate. It may be an insulating substrate, a conductive substrate, or a semiconductor substrate. It may be a single crystal substrate or a polycrystalline substrate. An example of the crystalline substrate is a substrate containing a crystalline material having a corundum structure as a main component. The term "main component" refers to a substrate containing 50% or more of the crystalline material, preferably 70% or more, and more preferably 90% or more, in terms of composition ratio in the substrate. Examples of the crystalline substrate having a corundum structure include a sapphire substrate and an α-type gallium oxide substrate.

[0027] In the present invention, the crystal substrate is preferably a sapphire substrate. Examples of the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, and an r-plane sapphire substrate. The sapphire substrate may have an off-angle. The off-angle is not particularly limited and may be, for example, 0.01° or more, preferably 0.2° or more, and more preferably 0.2° to 12°. The sapphire substrate preferably has a crystal growth plane that is an a-plane, an m-plane, or an r-plane, and is also preferably a c-plane sapphire substrate with an off-angle of 0.2° or more. The thickness of the crystal substrate is not particularly limited, but is usually 10 μm to 20 mm, and more preferably 10 to 1000 μm.

[0028] The crystal substrate may have a shape including at least a first crystal axis and a second crystal axis, or may have grooves formed therein corresponding to the first crystal axis and the second crystal axis. Suitable shapes of the crystal substrate include, for example, a circle, a triangle, a square (for example, a rectangle or a trapezoid), a polygonal shape such as a pentagon or a hexagon, and a fan shape.

[0029] In the present invention, other layers such as a buffer layer or a stress relaxation layer may be provided on the crystal substrate. Examples of the buffer layer include a layer made of a metal oxide having the same crystal structure as the crystal substrate or the crystalline oxide semiconductor. Examples of the stress relaxation layer include an ELO mask layer.

[0030] The method for growing the epitaxial crystal is not particularly limited and may be any known method as long as it does not impede the object of the present invention. Examples of the epitaxial crystal growth method include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD. In the present invention, the epitaxial crystal growth is preferably performed using mist CVD or mist epitaxy.

[0031] In the mist CVD method or mist epitaxy method, a raw material solution containing a metal is atomized (atomization process), the droplets are suspended, the resulting atomized droplets are transported to the vicinity of the crystal substrate by a carrier gas (transportation process), and then the atomized droplets are thermally reacted (film formation process).

[0032] (Raw material solution) The raw material solution contains a metal as a film-forming raw material, and is not particularly limited as long as it can be atomized, and may contain an inorganic material or an organic material. The metal may be a simple metal or a metal compound, and is not particularly limited as long as it does not impede the object of the present invention. Examples of the metal include gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), Examples of suitable metals include one or more metals selected from lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). In the present invention, the metal preferably includes at least one or more metals from periods 3 to 6 of the periodic table, more preferably at least one selected from gallium, indium, rhodium, iridium, and aluminum, and most preferably at least gallium. Furthermore, in the present invention, the metal preferably includes gallium, indium, and / or aluminum. By using such preferred metals, it is possible to form the crystalline oxide semiconductor film, which can be more suitably used in semiconductor devices and the like.

[0033] In the present invention, the raw material solution can be suitably prepared by dissolving or dispersing the metal in the form of a complex or salt in an organic solvent or water. Examples of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of the salt include organic metal salts (e.g., metal acetates, metal oxalates, and metal citrates), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, and metal iodides).

[0034] The solvent for the raw material solution is not particularly limited as long as it does not impair the object of the present invention, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the solvent preferably contains water.

[0035] The raw material solution may also contain additives such as hydrohalic acids and oxidizing agents. Examples of hydrohalic acids include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Examples of oxidizing agents include peroxides such as hydrogen peroxide (HO), sodium peroxide (NaO), barium peroxide (BaO), and benzoyl peroxide (CHCO)O, as well as hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

[0036] The raw material solution may contain a dopant. The dopant is not particularly limited as long as it does not impede the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, and p-type dopants such as magnesium or calcium. The dopant concentration is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the dopant concentration may be, for example, about 1×10 17 / cm 3 Furthermore, according to the present invention, the dopant may be present in a concentration as low as about 1×10 20 / cm 3 It may be contained in a concentration higher than this.

[0037] (Atomization process) The atomization step involves preparing a raw material solution containing a metal, atomizing the raw material solution, suspending the droplets, and generating atomized droplets. The blending ratio of the metal is not particularly limited, but is preferably 0.0001 mol / L to 20 mol / L relative to the total raw material solution. The atomization method is not particularly limited as long as it can atomize the raw material solution, and any known atomization method may be used. However, in the present invention, an atomization method using ultrasonic vibration is preferred. The mist used in the present invention is airborne, and is preferably a mist that floats in space with an initial velocity of zero and can be transported as a gas, rather than being sprayed like a spray. The droplet size of the mist is not particularly limited, and may be droplets of about several mm, but is preferably 50 μm or less, more preferably 1 to 10 μm.

[0038] (Transportation process) In the transport step, the atomized droplets are transported to the substrate by the carrier gas. The type of carrier gas is not particularly limited as long as it does not impede the object of the present invention, and suitable examples include oxygen, ozone, an inert gas (e.g., nitrogen, argon, etc.), or a reducing gas (e.g., hydrogen gas, forming gas, etc.). The type of carrier gas may be one type, or two or more types. A dilution gas with a different carrier gas concentration (e.g., a 10-fold dilution gas, etc.) may also be used as a second carrier gas. The number of carrier gas supply locations may be one or more. The flow rate of the carrier gas is not particularly limited, but is preferably 1 LPM or less, and more preferably 0.1 to 1 LPM.

[0039] (Film forming process) In the film-forming step, the atomized droplets are reacted to form a film on the crystal substrate. The reaction is not particularly limited as long as it forms a film from the atomized droplets, but a thermal reaction is preferred in the present invention. The thermal reaction may be any reaction that heats the atomized droplets to react, and the reaction conditions are not particularly limited as long as they do not impede the objectives of the present invention. In this step, the thermal reaction is typically carried out at a temperature equal to or higher than the evaporation temperature of the solvent in the raw material solution, but is preferably not too high, more preferably 650°C or lower. The thermal reaction may be carried out under any of the following conditions: vacuum, oxygen-free, reducing gas, and oxygen, as long as it does not impede the objectives of the present invention. Furthermore, the thermal reaction may be carried out under any of the following conditions: atmospheric pressure, pressurized, and reduced pressure. However, in the present invention, atmospheric pressure is preferred because it simplifies the calculation of the evaporation temperature and simplifies the equipment. The film thickness can be set by adjusting the film-forming time.

[0040] The semiconductor device of the present invention typically includes a source electrode (emitter electrode) and a drain electrode (collector electrode). Known electrode materials may be used for the source electrode (emitter electrode) and the drain electrode (collector electrode), and are not particularly limited as long as they do not impede the object of the present invention. Suitable materials include, for example, metals from Group 4 or Group 11 of the periodic table. Suitable metals from Group 4 or Group 11 of the periodic table used for the source electrode (emitter electrode) and the drain electrode (collector electrode) may be the same as the metal contained in the gate electrode. The source electrode (emitter electrode) and the drain electrode (collector electrode) may be a single metal layer or may include two or more metal layers. The means for forming the source electrode (emitter electrode) and the drain electrode (collector electrode) are not particularly limited, and examples thereof include known methods such as vacuum deposition and sputtering. The metals constituting the source electrode and the drain electrode may be alloys.

[0041] A semiconductor device suitable for use in the present invention is shown in FIG. 1. The semiconductor device in FIG. 1 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and includes an n+ type semiconductor layer 1, an n- type semiconductor layer (drift layer) 2, a p+ type semiconductor layer (deep p layer) 6, a p- type semiconductor layer (channel layer) 7, an n+ type semiconductor layer 11, a gate insulating film 13, a gate electrode 3, a p+ type semiconductor layer 16, a source electrode 24, an interlayer insulating film 25, and a drain electrode 26. At least a portion of the p+ type semiconductor layer (deep p layer) 6 is buried in the n- type semiconductor layer 2 to a position deeper than the buried lower end 3a of the gate electrode 3. When a voltage is applied between the source electrode 24 and the drain electrode 26 and a positive voltage is applied to the gate electrode 3 with respect to the source electrode 24, a channel is formed at the interface between the p- type semiconductor layer 7 and the gate insulating film 13, causing the device to turn on. When the voltage of the gate electrode 3 is set to 0 V, no channel is formed and the device turns off. 1, the p+ type semiconductor layer 6 is buried deeper in the n- type semiconductor layer 2 than the gate electrode 3. This configuration can alleviate the electric field near the bottom of the gate electrode, and improve the electric field distribution in the gate insulating film and the n- type semiconductor layer. In the present invention, the carrier density of the n- type semiconductor layer 2 is 1.4×10 in the case of a breakdown voltage of 600V. 17 / cm 3 It is preferable that the resistance is 6.9×10 or less in the case of 1200V withstand voltage. 16 / cm 3 The depth of the deep p-layer 6 (D in FIG. 1) is preferably 1.0 μm or more, and more preferably 1.5 μm or more, since this further relaxes the electric field. The relationship between the depth D of the deep p-layer 6 and the drift layer concentration is y≧2.67×10 in the case of a 600V breakdown voltage. -17 x-0.83 (where y represents the depth of the deep p-layer 6 and x represents the concentration of the drift layer (n-type semiconductor layer 2)). In the case of a breakdown voltage of 1200 V, y≧1.89×10 -17Preferably, the n-type semiconductor layer 6 has a thickness of 0.5 μm or less, and the n-type semiconductor layer 6 has a thickness of 0.5 μm or less. ... In the present invention, the p-type semiconductor layer 7 has a thickness of 0.5 μm or less, and the p+ type semiconductor layer 6 has a thickness of 0.5 μm or less.

[0042] The material of the gate insulating film (interlayer insulating film) is not particularly limited and may be a known material. Examples of the material for the gate insulating film include SiO2 film, phosphorus-doped SiO2 film (PSG film), boron-doped SiO2 film, and phosphorus-boron-doped SiO2 film (BPSG film). Examples of methods for forming the gate insulating film include CVD, atmospheric pressure CVD, plasma CVD, and mist CVD. In an embodiment of the present invention, the method for forming the gate insulating film is preferably mist CVD or atmospheric pressure CVD. The material for the gate electrode is not particularly limited and may be a known electrode material. Examples of materials for the gate electrode include the aforementioned materials for the source electrode. The method for forming the gate electrode is not particularly limited. Specific examples of methods for forming the gate electrode include dry methods and wet methods. Examples of dry methods include sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating. The materials for the n+-type semiconductor layer 1 and the n--type semiconductor layer 2 may be the same as the materials for the semiconductor layers described above. Furthermore, the main component of the p+ type semiconductor layer 16 is preferably different from the main component of the p- type semiconductor layer (channel layer) 7. In the present invention, the main component of the p+ type semiconductor layer 16 may be the same as that of the second p type oxide semiconductor.

[0043] 1 may be formed by any known method as long as it does not impede the object of the present invention. For example, a film may be formed by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or by direct patterning using printing techniques. In the present invention, the mist CVD method is preferred.

[0044] The film forming apparatus for the mist CVD method will be described below. 6 includes a carrier gas unit 622a that supplies a carrier gas, a flow rate control valve 623a that controls the flow rate of the carrier gas discharged from the carrier gas unit 622a, a carrier gas (dilution) unit 622b that supplies a carrier gas (dilution), a flow rate control valve 623b that controls the flow rate of the carrier gas (dilution) discharged from the carrier gas (dilution) unit 622b, a mist generation source 624 that contains a raw material solution 624a, a container 625 that contains water 625a, an ultrasonic vibrator 626 attached to the bottom of the container 625, a film formation chamber 630, a quartz supply pipe 627 that connects the mist generation source 624 to the film formation chamber 630, and a hot plate (heater) 628 installed in the film formation chamber 630. A substrate 603 is placed on the hot plate 628.

[0045] 6, raw material solution 624a is placed in mist source 624. Next, substrate 603 is placed on hot plate 628, and hot plate 628 is operated to increase the temperature inside film formation chamber 630. Next, flow rate control valves 623 (623a, 623b) are opened to supply carrier gas from carrier gas sources (carrier gas device 622a and carrier gas (dilution) device 622b) into film formation chamber 630. After the atmosphere inside film formation chamber 630 is sufficiently replaced with the carrier gas, the flow rates of the carrier gas and the carrier gas (dilution) are adjusted. Next, ultrasonic vibrator 626 is vibrated, and the vibrations are propagated to raw material solution 624a through water 625a, thereby atomizing raw material solution 624a and generating atomized droplets 624b. The atomized droplets 624b are introduced into the film-forming chamber 630 by the carrier gas and carried to the substrate 603. Then, the atomized droplets 624b undergo a thermal reaction in the film-forming chamber 630 under atmospheric pressure, forming a film on the substrate 603.

[0046] It is also preferable to use a mist CVD apparatus (film formation apparatus) 602 shown in Fig. 7. The mist CVD apparatus 602 in Fig. 7 includes a susceptor 621 on which a substrate 603 is placed, a carrier gas supply unit 622a for supplying a carrier gas, a flow rate control valve 623a for adjusting the flow rate of the carrier gas sent from the carrier gas supply unit 622a, a carrier gas (dilution) supply unit 622b for supplying a carrier gas (dilution), a flow rate control valve 623b for adjusting the flow rate of the carrier gas sent from the carrier gas (dilution) supply unit 622b, a mist generating source 624 that contains a raw material solution 624a, a container 625 that contains water 625a, an ultrasonic vibrator 626 attached to the bottom of the container 625, a supply pipe 627 made of a quartz tube with an inner diameter of 40 mm, a heater 628 installed around the supply pipe 627, and an exhaust port 629 for discharging mist, droplets, and exhaust gas after the thermal reaction. The susceptor 621 is made of quartz, and the surface on which the substrate 603 is placed is inclined from the horizontal. By making both the supply pipe 627, which serves as the film formation chamber, and the susceptor 621 out of quartz, impurities originating from the apparatus are prevented from being mixed into the film formed on the substrate 603. This mist CVD apparatus 602 can be used in the same way as the above-mentioned film formation apparatus 601.

[0047] By using the suitable film formation apparatus, the crystalline oxide semiconductor can be more easily formed on the crystal growth surface of the crystal substrate. The crystalline oxide semiconductor is usually formed by epitaxial crystal growth. The semiconductor device can be fabricated from the crystalline oxide semiconductor by known means.

[0048] Another preferred embodiment of the semiconductor device of the present invention is shown in FIG. 2. The semiconductor device of FIG. 2 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and includes an n+ type semiconductor layer 1, an n- type semiconductor layer (drift layer) 2, a p+ type semiconductor layer (deep p layer) 6, a gate insulating film 13, a gate electrode 3, a source electrode 24, an interlayer insulating film 25, and a drain electrode 26. The semiconductor device of FIG. 2 also includes a p- type semiconductor layer (channel layer) 7, an n+ type semiconductor layer 11, and a p+ type semiconductor layer 16. At least a portion of the p+ type semiconductor layer (deep p layer) 6 is buried in the semiconductor layer to a position deeper than the buried lower end 3a of the gate electrode 3. The semiconductor device of FIG. 2 differs from the semiconductor device of FIG. 1 in that the p+ type semiconductor layer 6 is provided so as to be perpendicular to the gate electrode 3. Such a semiconductor device is also preferred and can exhibit an excellent electric field relaxation effect.

[0049] In the semiconductor device of the present invention, the thickness of the semiconductor layer is preferably 50 μm or less, more preferably 30 μm or less, and most preferably 10 μm or less, so as to more effectively alleviate the electric field in the crystalline oxide semiconductor and to achieve better semiconductor characteristics (including miniaturization). The thickness of the deep p-layer is preferably set to at least half the thickness of the semiconductor layer (e.g., n-type semiconductor layer).

[0050] FIG. 9 shows an example of a preferred semiconductor device of the present invention. The semiconductor device of FIG. 9 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and includes an n+ type semiconductor layer (drain layer) 1, an n- type semiconductor layer (drift layer) 2, a p+ type semiconductor layer (deep p layer) 6, a p- type semiconductor layer (channel layer) 7, an n+ type semiconductor layer (n+ source layer) 11, a gate insulating film 13, a gate electrode 3, a p+ type semiconductor layer 16, a source electrode 24, and a drain electrode 26. At least a portion of the p+ type semiconductor layer (deep p layer) 6 is buried in the n- type semiconductor layer 2 to a position deeper than the buried lower end of the gate electrode 3. In the on-state of the semiconductor device of FIG. 9, when a voltage is applied between the source electrode 24 and the drain electrode 26 and a positive charge is applied to the gate electrode 3 with respect to the source electrode 24, a channel is formed at the interface between the p- type semiconductor layer 7 and the gate insulating film 13, and the device is turned on. In the off-state, when the voltage of the gate electrode 3 is set to 0 V, no channel is formed and the device is turned off. 9, the p+-type semiconductor layer 6 is buried deeper in the n--type semiconductor layer 2 than the gate electrode 3. This configuration can alleviate the electric field near the bottom of the gate electrode, improving the electric field distribution in the gate insulating film and the n--type semiconductor layer. In the present invention, the p+-type semiconductor layer (deep p-layer) 6 preferably contains an oxide semiconductor containing iridium as a main component. Examples of oxide semiconductors containing iridium include α-Ir2O3 and its mixed crystals (e.g., mixed crystals of iridium oxide and gallium oxide). By using such a preferred oxide semiconductor for the p+-type semiconductor layer (deep p-layer) 6, a sufficient amount of space charge can be secured in the depletion layer, resulting in a more effective electric field alleviation effect.

[0051] In the semiconductor device shown in Figure 9, a simulation was performed to examine the influence of the band offset ΔEc (conduction band offset) at the interface between the p-type semiconductor layer (channel layer) 7 and the n-type semiconductor layer (drift layer) 2 on the Id-Vd characteristics of the semiconductor device. The simulation model is shown in Figure 12(a). The simulation was performed with the carrier density of the n+ type semiconductor layer set to 1.0 x 10 19 / cm 3 , the depth is 0.1 μm, and the carrier density of the p-type semiconductor layer (channel layer) is 1.0 × 10 17 / cm 3 , the thickness is 0.7 μm, and the carrier density of the n-type semiconductor layer (drift layer) is 1.0 × 10 17 / cm 3 , the thickness is 3 μm, and the carrier density of the n+ type semiconductor layer (drain layer) is 1.0 × 10 19 / cm 3 The trench gate had a depth of 1 μm, a width of 0.4 μm, and a gate oxide film with a side thickness of 80 nm and a bottom thickness of 120 nm. The results are shown in FIG. 12(b). As is clear from FIG. 12(b), the band offset ΔEc at the interface between the p-type semiconductor layer (channel layer) and the n-type semiconductor layer (drift layer) is preferably 1.0 eV or less, and more preferably 0 eV or less. By using such a preferable combination of the p-type semiconductor layer (channel layer) and the n-type semiconductor layer (drift layer), a semiconductor device with reduced on-resistance can be obtained. A preferable combination of the p-type semiconductor layer (channel layer) and the n-type semiconductor layer (drift layer) is, for example, a combination in which α-Ga2O3 containing a p-type dopant is used as the p-type semiconductor layer (channel layer) and α-Ga2O3 containing an n-type dopant is used as the n-type semiconductor layer (drift layer).

[0052] Figure 10 shows another example of a suitable semiconductor device of the present invention. The semiconductor device of Figure 10 is a metal oxide semiconductor field effect transistor (MOSFET) and differs from the semiconductor device of Figure 9 in that an i-type semiconductor layer 28 is provided between a p+-type semiconductor layer (deep p-layer) 6 and an n-type semiconductor layer (drift layer) 2. The i-type semiconductor layer is not particularly limited as long as it has a lower carrier density than the n-type semiconductor layer. In the present invention, it is preferable that the main component of the i-type semiconductor layer is the same as the main component of the n-type semiconductor layer.

[0053] A simulation was carried out to confirm the effect of the i-type semiconductor layer 28 in the semiconductor device shown in Fig. 10. The simulation model is shown in Fig. 13(a). The simulation was carried out with the carrier concentration of the p+-type semiconductor layer (deep p layer) set to 1.0 × 10 18 / cm 3 , the thickness is 1.0 μm, and the carrier density of the n-type semiconductor layer (drift layer) is 1.0 × 10 17 / cm 3 , the thickness is 2 μm, and the carrier density of the n+ type semiconductor layer (drain layer) is 1.0 × 10 19 / cm 3 The thickness was set to 1 μm. In this simulation, IrGaO (band gap 3 eV) was used as the p+ type semiconductor layer (deep p layer), Ga2O3 was used as the i type semiconductor layer and n type semiconductor layer, the band offset ΔEc (conduction band offset) of the IrGaO / Ga2O3 junction was set to 1.04 eV, and the band offset ΔEv (valence band offset) was set to 3.34 eV. When there is no i type semiconductor layer ((1) in Figure 13(b)), the carrier density of the i type semiconductor layer is 1.0 × 10 14 / cm 3 , when the thickness is 0.6 μm ((2) in Figure 13(b)), the carrier density of the i-type semiconductor layer is 1.0 × 10 14 / cm 3 FIG. 13(b) shows the electric field strength distribution when a reverse voltage of 1000 V is applied for the cases of a 1 μm thick film ((3) in FIG. 13(b)). As is clear from FIG. 13(b), by providing an i-type semiconductor layer, even when IrGaO (a mixed crystal of iridium oxide and gallium oxide) is used as the p+-type semiconductor layer, the electric field in IrGaO can be reduced to below the breakdown field.

[0054] Fig. 11 shows another example of a suitable semiconductor device of the present invention. The semiconductor device of Fig. 11 is a metal oxide semiconductor field effect transistor (MOSFET) and differs from the semiconductor device of Fig. 10 in that it includes a p-type semiconductor layer 27 near the bottom of the gate. The p-type semiconductor layer 27 preferably contains, as its main component, a p-type oxide semiconductor different from the p-type oxide semiconductor that is the main component of the p-type semiconductor layer (channel layer) 7. In the present invention, the main component of the p-type semiconductor layer 27 may be the same as the second p-type oxide semiconductor.

[0055] Simulations were performed to compare the Id-Vd characteristics (Vg = 20 V) of the semiconductor devices shown in Figures 9, 10, and 11. Table 1 shows the results of the electric field and on-resistance (Vg = 20 V, Vd = 2 V) applied to the IrGaO (p+-type semiconductor layer: deep p layer) and gate oxide film when 1000 V was applied. As is clear from Table 1, the structure of Figure 10 can reduce the electric field applied to the IrGaO and the oxide film more than the structure of Figure 9. It can also be seen that the structure of Figure 11 can reduce the electric field applied to the gate oxide film more than the structure of Figure 10.

[0056] [Table 1]

[0057] The semiconductor device is particularly useful as a power device, and is particularly suitable for use as a normally-off semiconductor device. In the present invention, the crystalline oxide semiconductor can be peeled off from the crystalline substrate by known methods, if desired, and used in a semiconductor device, preferably as a vertical device. The semiconductor device can be used as either a horizontal device in which an electrode is formed on one side of the semiconductor layer, or a vertical device in which electrodes are formed on both the front and back sides of the semiconductor layer. In the present invention, however, vertical devices are preferred. Suitable examples of the semiconductor device include metal semiconductor field-effect transistors (MESFETs), high electron mobility transistors (HEMTs), metal oxide semiconductor field-effect transistors (MOSFETs), static induction transistors (SITs), junction field-effect transistors (JFETs), and insulated gate bipolar transistors (IGBTs). In the present invention, insulated gate semiconductor devices (e.g., MOSFETs or IGBTs) or semiconductor devices with Schottky gates (e.g., MESFETs) are preferred, with MOSFETs or IGBTs being more preferred.

[0058] In addition to the above features, the semiconductor device of the present invention can be suitably used as a power module, inverter, or converter using a known method, and further suitably used in, for example, a semiconductor system using a power supply device. The power supply device can be fabricated from or as the semiconductor device by connecting it to a wiring pattern using a known method. FIG. 3 shows a power supply system 170 configured using multiple power supply devices 171 and 172 and a control circuit 173. As shown in FIG. 4, the power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182. FIG. 5 shows an example of a power supply circuit diagram for a power supply device. FIG. 5 shows the power supply circuit of the power supply device, which is composed of a power circuit and a control circuit. DC voltage is switched at high frequency by an inverter 192 (comprising MOSFETs A to D) to convert it to AC, then insulated and transformed by a transformer 193, rectified by rectifying MOSFETs 194 (A to B'), smoothed by a DCL 195 (smoothing coils L1 and L2) and a capacitor, and output as a DC voltage. At this time, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and rectifying MOSFET 194 so as to obtain a desired output voltage.

[0059] In the present invention, the semiconductor device is preferably a power card, including a cooler and an insulating member. More preferably, the coolers are provided on both sides of the semiconductor layer, with at least the insulating member interposed between them. Most preferably, heat dissipation layers are provided on both sides of the semiconductor layer, with the coolers provided on the outer sides of the heat dissipation layers, with at least the insulating member interposed between them. Figure 8 shows a power card according to a preferred embodiment of the present invention. The power card shown in Figure 8 is a double-sided cooled power card 201, and includes a refrigerant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin portion 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal portion) 302b, a heat sink and electrode 303, a metal heat transfer plate (protruding terminal portion) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The thickness-direction cross section of the refrigerant tube 202 has a number of flow paths 222 separated by a number of partition walls 221 extending in the flow path direction at predetermined intervals. Such a suitable power card can achieve higher heat dissipation and satisfy higher reliability.

[0060] Semiconductor chip 301a is joined to the inner main surface of metal heat transfer plate (protruding terminal portion) 302b with solder layer 304, and metal heat transfer plate (protruding terminal portion) 303b is joined to the remaining main surface of semiconductor chip 301a with solder layer 304, thereby connecting the collector electrode surface and emitter electrode surface of the IGBT with the anode electrode surface and cathode electrode surface of the flywheel diode in a so-called anti-parallel configuration. Metal heat transfer plates (protruding terminal portions) 302b and 303b can be made of, for example, Mo or W. Metal heat transfer plates (protruding terminal portions) 302b and 303b have a thickness difference that compensates for the thickness difference of semiconductor chip 301a, and as a result, the outer surfaces of metal heat transfer plates 302b and 303b are flat.

[0061] Resin sealing portion 209 is made of, for example, epoxy resin and is molded to cover the side surfaces of metal heat transfer plates 302b and 303b, and semiconductor chip 301a is molded in resin sealing portion 209. However, the outer main surfaces, i.e., the contact heat-receiving surfaces, of metal heat transfer plates 302b and 303b are completely exposed. Metal heat transfer plates (protruding terminal portions) 302b and 303b protrude from resin sealing portion 209 to the right in Fig. 8, and control electrode terminal 305, which is a so-called lead frame terminal, connects the gate (control) electrode surface of semiconductor chip 301a, on which, for example, an IGBT is formed, to control electrode terminal 305.

[0062] The insulating spacer, insulating plate 208, is made of, for example, aluminum nitride film, but may be made of other insulating films. Insulating plate 208 completely covers and adheres to metal heat transfer plates 302b and 303b. However, insulating plate 208 and metal heat transfer plates 302b and 303b may simply be in contact with each other, or may be coated with a good heat transfer material such as silicone grease, or may be joined by various methods. Alternatively, an insulating layer may be formed by ceramic spraying, or insulating plate 208 may be joined to the metal heat transfer plate, or may be joined or formed on the refrigerant tube.

[0063] The refrigerant tubes 202 are fabricated by cutting aluminum alloy plates formed by pultrusion or extrusion to the required length. The cross section of the refrigerant tubes 202 in the thickness direction has numerous flow paths 222 separated by numerous partition walls 221 extending in the flow path direction at predetermined intervals. The spacers 203 may be soft metal plates such as solder alloys, or may be films formed by coating on the contact surfaces of the metal heat transfer plates 302b and 303b. The surface of this soft spacer 203 easily deforms to conform to the minute irregularities and warping of the insulating plate 208 and the refrigerant tubes 202, thereby reducing thermal resistance. The surfaces of the spacers 203 may be coated with a known high-thermal-conductivity grease, or the spacers 203 may be omitted. [Industrial Applicability]

[0064] The semiconductor device of the present invention can be used in a wide range of fields, such as compound semiconductor electronic devices, electronic components and electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful in power devices including oxide semiconductor layers. [Explanation of symbols]

[0065] 1 n+ type semiconductor layer 2 n-type semiconductor layer (drift layer) 3. Gate electrode 3a Buried lower end 6 p+ type semiconductor layer (deep p layer) 7 p-type semiconductor layer (channel layer) 11 n+ type semiconductor layer 13 Gate insulating film 16 p+ type semiconductor layer 24 Source electrode 25 Interlayer insulating film 26 Drain electrode 27 p-type semiconductor layer 28 i-type semiconductor layer 170 Power System 171 Power supply 172 Power supply 173 Control Circuit 180 System Unit 181 Electronic circuit 182 Power System 192 inverter 193 Trans 194 Rectifier MOSFET 195 DCL 196 PWM control circuit 197 Voltage Comparator 201 Double-sided cooled power card 202 Refrigerant tube 203 Spacer 208 Insulating plate (insulating spacer) 209 Sealing resin part 221 Bulkhead 222 Channel 301a Semiconductor chip 302b Metal heat transfer plate (protruding terminal part) 303 Heat sink and electrode 303b Metal heat transfer plate (protruding terminal part) 304 solder layer 305 Control electrode terminal 308 Bonding Wire 601 Mist equipment (film forming equipment) 602 Mist equipment (film forming equipment) 603 Substrate 621 Susceptor 622a Carrier gas supply device 622b Carrier gas (dilution) supply device 623a Flow control valve 623b Flow control valve 624 Mist Source 624a Raw material solution 625 Container 625a water 626 Ultrasonic vibrator 627 Supply pipe 628 Heater 629 Exhaust port 630 Deposition chamber

Claims

1. A semiconductor device including: a gate electrode at least partially buried in a semiconductor layer; a deep p-layer at least partially buried in the semiconductor layer to a position equal to or deeper than a buried lower end of the gate electrode; and a channel layer, a channel layer including a first p-type oxide semiconductor as a main component, and a deep p-layer including a second p-type oxide semiconductor different from the first p-type oxide semiconductor as a main component;

2. 2. The semiconductor device according to claim 1, wherein the first and / or second p-type oxide semiconductor has a corundum structure or a β-gallium structure.

3. 3. The semiconductor device according to claim 1, wherein the first p-type oxide semiconductor is gallium oxide or a mixed crystal thereof.

4. 4. The semiconductor device according to claim 1, wherein a band offset of the conduction band between the channel layer and the semiconductor layer is 1.5 eV or less.

5. 5. The semiconductor device according to claim 4, wherein the band offset is 1.0 eV or less.

6. 6. The semiconductor device according to claim 1, wherein the band gap of the second p-type oxide semiconductor is smaller than the band gap of the first p-type oxide semiconductor.

7. 7. The semiconductor device according to claim 1, wherein the second p-type oxide semiconductor is iridium oxide or an alloy thereof.

8. 8. The semiconductor device according to claim 1, wherein an i-type semiconductor layer is provided between the deep p-layer and the semiconductor layer.

9. 9. The semiconductor device according to claim 8, wherein the carrier density of the i-type semiconductor layer is lower than the carrier density of the semiconductor layer.

10. 10. The semiconductor device according to claim 1, which is a power device.

11. A semiconductor system comprising a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 10.

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