Image sensor and image pickup device

Abstract

To increase a time from the transfer of charges to the reading of pixel signals as the number of pixels increase, and increase or decrease the charges to easily add noise to the pixel signals.SOLUTION: An imaging element includes a plurality of imaging units in which a plurality of unit blocks in which multiple pixels are arranged in a matrix are arranged in a matrix, at least one A / D conversion unit provided for each of the unit blocks, and converting a pixel signal from a pixel included in the corresponding unit block into a digital signal, and a reading unit that sequentially reads digital signals of pixels included in the imaging unit across the plurality of unit blocks.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an imaging element and an imaging device. [Background technology]

[0002] In some image sensors in which pixels are arranged in a matrix, a global shutter is electronically realized by transferring charges all at once using a memory circuit consisting of transistors and storage capacitors (see, for example, Patent Document 1). Patent Document 1: JP 2011-119950 Summary of the Invention [Problem to be solved by the invention]

[0003] However, after the charges are transferred all at once, the pixel signals based on the charges are read sequentially. Therefore, the more pixels there are, the longer the time it takes from when the charges are transferred until the pixel signals are read, and the more likely it is that the charges will increase or decrease, causing noise in the pixel signals. [Means for solving the problem]

[0004] In a first aspect of the present invention, a first block includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first photoelectric conversion unit in the column direction, and a third photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first photoelectric conversion unit in the row direction; a fourth photoelectric conversion unit that converts light into electric charges and that is a block arranged alongside the first block in the column direction, and a fifth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the fourth photoelectric conversion unit in the column direction; a first semiconductor chip including a second block having a sixth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the fourth photoelectric conversion unit in the row direction; a third block that is arranged alongside the first block in the row direction and that has a seventh photoelectric conversion unit that converts light into electric charges, an eighth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the seventh photoelectric conversion unit in the column direction; and a ninth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the seventh photoelectric conversion unit in the row direction; and a semiconductor device integrated with the first semiconductor chip. a first circuit disposed so as to overlap the first block in a stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked; a first signal processing unit that performs signal processing on a first signal based on the charges converted in the first photoelectric conversion unit and a second signal based on the charges converted in the second photoelectric conversion unit; and a second signal processing unit that performs signal processing on a third signal based on the charges converted in the third photoelectric conversion unit, the first circuit being disposed so as to overlap the first block in a stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked; and a third signal processing unit that performs signal processing on a fourth signal based on the charges converted in the fourth photoelectric conversion unit and a fifth signal based on the charges converted in the fifth photoelectric conversion unit. and a fourth signal processing unit that performs signal processing on a sixth signal based on the charges converted in the sixth photoelectric conversion unit, and a second circuit that is arranged to overlap the second block in the stacking direction; a fifth signal processing unit that performs signal processing on a seventh signal based on the charges converted in the seventh photoelectric conversion unit and an eighth signal based on the charges converted in the eighth photoelectric conversion unit; and a sixth signal processing unit that performs signal processing on a ninth signal based on the charges converted in the ninth photoelectric conversion unit, and a third circuit that is arranged to overlap the third block in the stacking direction.

[0005] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a cross-sectional view of a back-illuminated imaging element according to an embodiment of the present invention. [Figure 2] 2A and 2B are diagrams illustrating a pixel array and unit blocks of an imaging chip. [Figure 3] FIG. 2 is a circuit diagram corresponding to a pixel. [Figure 4] 1 shows an outline of a unit block, its peripheral circuits, and their connections. [Figure 5] The diagram shows an outline of the connections of peripheral circuits, etc. [Figure 6] 1 is a block diagram showing a configuration of an imaging apparatus according to an embodiment of the present invention. [Figure 7] FIG. 2 is a block diagram showing a specific configuration of a drive unit. [Figure 8] 1 shows a timing chart of operations such as pixel charge accumulation and transfer. [Figure 9] 10 shows a timing chart of an operation for reading out a pixel signal from a pixel. [Figure 10] 10 is a timing chart showing the readout timing of a plurality of pixels included in the imaging unit. [Figure 11] 10 shows another example of the connection relationship of peripheral circuits and the like. DETAILED DESCRIPTION OF THE INVENTION

[0007] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The image sensor 100 includes an image sensor chip 113 that outputs pixel signals corresponding to incident light, a signal processing chip 111 that processes the pixel signals, and a memory chip 112 that stores the pixel signals. The image sensor chip 113, signal processing chip 111, and memory chip 112 are stacked and electrically connected to each other by conductive bumps 109 made of Cu or the like.

[0009] As shown in the figure, incident light is mainly incident in the positive direction of the Z axis, as indicated by the white arrow. In this embodiment, the surface of the imaging chip 113 on which the incident light is incident is referred to as the back surface. As shown by the coordinate axes, the right direction of the paper, perpendicular to the Z axis, is the positive X axis, and the front direction of the paper, perpendicular to the Z axis and the X axis, is the positive Y axis. In the following figures, the coordinate axes are displayed so that the orientation of each figure can be understood, based on the coordinate axes in Figure 1.

[0010] An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer is arranged on the back side of the wiring layer 108. The PD layer 106 has a plurality of PDs (photodiodes) 104 arranged two-dimensionally and transistors 105 provided corresponding to the PDs 104.

[0011] A color filter 102 is provided on the incident light side of the PD layer 106 via a passivation film 103. There are multiple types of color filters 102 that transmit different wavelength ranges, and each has a specific arrangement corresponding to each PD 104. The arrangement of the color filters 102 will be described later. A set of a color filter 102, a PD 104, and a transistor 105 forms one pixel.

[0012] A microlens 101 is provided corresponding to each pixel on the incident light side of the color filter 102. The microlens 101 condenses the incident light toward the corresponding PD 104.

[0013] The wiring layer 108 has wiring 107 that transmits pixel signals from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multi-layered, and may be provided with passive elements and active elements.

[0014] A plurality of bumps 109 are arranged on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with a plurality of bumps 109 provided on the opposing surface of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed together, whereby the aligned bumps 109 are bonded together and electrically connected.

[0015] Similarly, a plurality of bumps 109 are arranged on the opposing surfaces of the signal processing chip 111 and the memory chip 112. These bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressed together, whereby the aligned bumps 109 are bonded together and electrically connected.

[0016] The bonding between the bumps 109 is not limited to Cu bump bonding by solid-phase diffusion, but may also employ micro-bump bonding by solder melting. For example, it is sufficient to provide one bump 109 for each output wiring, as described below. Therefore, the size of the bumps 109 may be larger than the pitch of the PDs 104. Furthermore, in a peripheral region other than the pixel region where the pixels are arranged, bumps larger than the bumps 109 corresponding to the pixel region may also be provided.

[0017] The signal processing chip 111 has through-silicon vias (TSVs) 110 that connect circuits provided on the front and back surfaces of the chip to each other. The TSVs 110 are preferably provided in the peripheral region. The TSVs 110 may also be provided in the peripheral region of the imaging chip 113 and the memory chip 112.

[0018] FIG. 2 is a diagram illustrating the pixel array of the imaging chip 113 and the unit blocks 131. In particular, the imaging chip 113 is shown as viewed from the back side. The imaging chip 113 has an imaging section in which more than 20 million pixels are arranged in a matrix. In the example of FIG. 2, adjacent 4 pixels x 4 pixels, or 16 pixels, form one unit block 131. The grid lines in the diagram show the concept of adjacent pixels being grouped to form the unit block 131.

[0019] As shown in the partially enlarged view of the imaging section, the unit block 131 contains four so-called Bayer arrays, arranged vertically and horizontally, each consisting of four pixels: green pixels Gb and Gr, a blue pixel B, and a red pixel R. The green pixels Gb and Gr have green filters as their color filters 102 and receive light in the green wavelength band of incident light. Similarly, the blue pixel B has a blue filter as its color filter 102 and receives light in the blue wavelength band, and the red pixel R has a red filter as its color filter 102 and receives light in the red wavelength band.

[0020] 2, for the sake of simplicity, an example has been described in which the unit block 131 is made up of 16 pixels, 4 pixels by 4 pixels. Hereinafter, an example will be described in which the unit block 131 has pixels arranged in L rows and P columns, totaling (L×P). There are no particular restrictions on the number of rows and columns, but when the total number of pixels in the imaging unit is about 20 million, it may have, for example, 64 rows and 32 columns. Also, an example will be described in which the imaging unit is formed by arranging a total of (m×n) unit blocks 131 in m rows and n columns.

[0021] 3 is a circuit diagram corresponding to pixel 150. In Fig. 3, a rectangle surrounded by a dotted line typically represents a circuit corresponding to one pixel 150. Note that at least some of the transistors described below correspond to transistor 105 in Fig. 1.

[0022] The PD 104 is connected to a transfer transistor 154, and the gate of the transfer transistor 154 is connected to a wiring Tx_i_j to which a transfer pulse is supplied. Note that the subscript i is a serial number in the entire imaging unit that identifies the unit block 131. The subscript j is a serial number in the unit block 131 that identifies the row number within the unit block 131.

[0023] The drain of the transfer transistor 154 is connected to the source of the reset transistor 152. This forms a so-called FD (floating diffusion) 156 between the drain of the transfer transistor 154 and the source of the reset transistor 152. The drain of the reset transistor 152 is connected to a wiring Vdd to which a power supply voltage is supplied, and the gate thereof is connected to a wiring Rst_i_j to which a reset pulse is supplied.

[0024] One end of the FD 156 is further connected to the source of a pass transistor 158. The gate of the pass transistor 158 is connected to a wiring Wrt_i_j to which a pass pulse is supplied, and the drain is connected to one end of a storage capacitor 160. The pass transistor 158 and the storage capacitor 160 form a so-called memory circuit.

[0025] The one end of the storage capacitor 160 is further connected to the gate of the amplification transistor 162. The drain of the amplification transistor 162 is connected to a wiring Vdd to which a power supply voltage is supplied. The source of the amplification transistor 162 is connected to the drain of the corresponding selection transistor 164. The gate of the selection transistor 164 is connected to a wiring Sel_i_j to which a selection pulse is supplied.

[0026] The source of the selection transistor 164 is connected to a column transmission line 170. A load current source 166 supplies a current to the column transmission line 170. That is, the column transmission line 170 for the selection transistor 164 is formed by a source follower.

[0027] Fig. 4 shows an outline of a unit block 131, its peripheral circuit 133, and their connections. In the unit block 131 of Fig. 4, a total of (P x L) pixels 150 are arranged in L rows and P columns.

[0028] The wiring Rst_i_l (where l is an integer from 1 to L) is connected to the row control unit 200, and is also connected in common to P pixels 150 in the l-th row in the unit block 131. Similarly, the wiring Tx_i_l, wiring Wrt_i_l, and wiring Sel_i_l are also connected to the row control unit 200, and are also connected in common to P pixels 150 in the l-th row in the unit block 131.

[0029] The row control unit 200 may also be called a row selection unit, a vertical scanning circuit, etc. The row control unit 200 is provided for each unit block 131. The row control unit 200 may be provided on the signal processing chip 111 side.

[0030] A column transmission path 170 is provided for each pixel 150 in the same column. These column transmission paths 170_p (where p is an integer from 1 to P) are commonly connected to L pixels 150 in the p-th column in the unit block 131. As a result, the column transmission path 170 is shared by the pixels 150 in the same column in the unit block 131, and transmits signals from the pixels 150 included in that column.

[0031] These column transmission paths 170_p are connected from the imaging chip 113 side to the peripheral circuits 133 provided on the signal processing chip 111 side via bumps 109. The peripheral circuits 133 are provided for each unit block 131, and are arranged so as to overlap the unit blocks 131 in the imaging chip 113 when viewed from the stacking direction.

[0032] The peripheral circuit 133 has a CDS circuit 202 and an A / D conversion circuit 204 connected in series for each column transmission line 170_p. In the example shown in Fig. 4, P pairs of a CDS circuit 202 and an A / D conversion circuit 204 are provided for each unit block 131.

[0033] The peripheral circuit 133 further includes a shift register 206 arranged on the output side of the P A / D conversion circuits 204. In the example of Fig. 4, one shift register 206 is arranged for each unit block 131. The output of the shift register 206 is connected to a shift register 210 via a column bus line 172.

[0034] 5 shows an outline of the connection relationship of the peripheral circuits 133 etc. The unit blocks 131 are arranged in m rows and n columns, and correspondingly, the peripheral circuits 133 are also arranged in m rows and n columns.

[0035] A column bus line 172 is provided for each peripheral circuit 133 in the same column. This column bus line 172_u (where u is an integer from 1 to n) is commonly connected to m peripheral circuits 133 in the u-th column. As a result, the column bus line 172 is shared by the unit blocks 131 in the same column, and transmits signals from the unit blocks 131 included in that column.

[0036] Since the column bus line 172 is shared by the peripheral circuits 133 in the same column, the output of each peripheral circuit 133 is configured to be controlled by an output selection circuit (not shown). For example, the output of 172 in FIG. 4 is enabled or disabled. When disabled, the output is controlled by setting it to high impedance, etc.

[0037] A shift register 210 is arranged on the output side of the n column bus lines 172. In the example of Fig. 5, one shift register 210 is arranged for the entire image sensor 100. The shift register 210 holds signals transmitted from the n column bus lines 172 and outputs them sequentially. The shift registers 206 and 210 may also be called horizontal scanning circuits, multiplexers, etc.

[0038] 6 is a block diagram showing the configuration of an image capturing apparatus according to this embodiment. The image capturing apparatus 500 includes a photographing lens 520 as an image capturing optical system, which guides a subject light beam incident along an optical axis OA to the image capturing element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the image capturing apparatus 500. The image capturing apparatus 500 mainly includes the image capturing element 100, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, and a display unit 506.

[0039] The photographing lens 520 is composed of a group of multiple optical lenses, and focuses a subject light beam from a scene near its focal plane. Note that in Fig. 6, it is represented by a single virtual lens placed near the pupil. The driver 502 controls the charge accumulation of the image sensor 100, readout of pixel signals, and so on, in accordance with instructions from the system controller 501.

[0040] The image sensor 100 passes the pixel signals to an image processing unit 511 in the system control unit 501. The image processing unit 511 performs various image processes using the work memory 504 as a workspace to generate image data. For example, when generating image data in JPEG file format, compression processing is performed after white balance processing, gamma processing, etc. are performed. The generated image data is recorded in a recording unit 505 and converted into a display signal, which is displayed on a display unit 506 for a preset time.

[0041] The photometry unit 503 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor with approximately one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each region of the scene. The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. Note that the pixels used for the AE sensor may be provided within the image sensor 100, in which case there is no need to provide a photometry unit 503 separate from the image sensor 100.

[0042] 7 is a block diagram showing a specific configuration of the driving unit 502. The driving unit 502 includes a sensor control unit 441, a block control unit 442, a synchronization control unit 443, a signal control unit 444, a pixel memory 414, and an arithmetic circuit 415 as distributed control functions, as well as a driving control unit 420 that controls these respective control units. The driving unit 502 further includes an I / F circuit 418 between the driving control unit 420 and a system control unit 501 of the imaging device 500 main body.

[0043] The drive control unit 420 converts instructions from the system control unit 501 into control signals that can be executed by each control unit, and passes them on to each control unit, with reference to the timing memory 430. The timing memory 430 is formed by a flash RAM or the like.

[0044] The sensor control unit 441 is responsible for controlling the transmission of control pulses related to charge accumulation and charge readout of each pixel, which are sent to the imaging chip 113. Specifically, the sensor control unit 441 controls the start and end of charge accumulation of the target pixel by sending a reset pulse, a transfer pulse, and a pass pulse to the row control unit 200 of each unit block 131, and outputs a pixel signal to the column transmission path 170 by sending a selection pulse to the readout pixel.

[0045] The block control unit 442 executes transmission of specific pulses that identify the unit blocks 131 to be controlled and are transmitted to the imaging chip 113. The transfer pulses and the like that each pixel receives via the wiring Tx_i_j and the like are the logical product of the pulses transmitted by the sensor control unit 441 and the specific pulses transmitted by the block control unit 442. In this way, each region can be controlled as a block independent of each other. Note that when using pulses synchronized among multiple unit blocks 131 and when performing an operation spanning multiple unit blocks 131, the block control unit 442 simultaneously transmits specific pulses that identify each of these multiple unit blocks.

[0046] The synchronization control unit 443 sends a synchronization signal to the imaging chip 113. Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, thinning control, and the like can be realized, which control only specific pixels belonging to the same unit block 131. In addition, the signal control unit 444 is responsible for timing control of the CDS circuit 202, the A / D conversion circuit 204, and the shift registers 206 and 210.

[0047] The calculation circuit 415 calculates an AE evaluation value and the like based on the pixel values ​​stored in the pixel memory 414. The calculation circuit 415 outputs the calculation results to the drive control unit 420.

[0048] The pixel memory 414 has a memory space capable of storing pixel values ​​from the pixels 150 of the imaging unit, and stores each pixel value that has been read from each pixel and digitized. The pixel memory 414 is provided with a data transfer interface that transmits pixel signals in accordance with a transfer request. The data transfer interface is connected to a data transfer line that connects to the image processing unit 511. The data transfer line is formed, for example, by a data bus among bus lines. In this case, a transfer request from the system control unit 501 to the drive control unit 420 is executed by address specification using the address bus.

[0049] The transmission of pixel signals via the data transfer interface is not limited to the addressing method, and various other methods can be used. For example, a double data rate method can be used, which uses both the rising and falling edges of the clock signal used to synchronize each circuit when transferring data. A burst transfer method can also be used, which transfers data all at once by omitting some steps such as addressing, thereby increasing speed. It is also possible to use a combination of a bus method using lines connecting the control unit, memory unit, and input / output unit in parallel, and a serial method that transfers data one bit at a time in series.

[0050] With this configuration, the image processing unit 511 can receive only the necessary pixel values, and therefore can complete image processing at high speed, especially when forming a low-resolution image. The drive unit 502, the row control unit 200 in Fig. 4, the peripheral circuit 133, and the shift register 210 in Fig. 5 function as a readout unit that sequentially reads out pixel signals of the pixels 150 included in the imaging unit across multiple unit blocks 131.

[0051] 8 shows a timing chart of operations such as charge accumulation and transfer in the pixel 150. Hereinafter, the charge accumulation and transfer operations in the pixel 150 of FIG. 3 will be described with reference to FIG.

[0052] As an initial state, at time t0, the driving unit 502 turns on the reset transistor 152, the transfer transistor 154, and the pass transistor 158 by setting the voltages of the wirings Rst_i_j, Tx_i_j, and Wrt_i_j to high via the row control unit 200. This resets the PD 104, the FD 156, and the storage capacitor 160.

[0053] At time t1 when an input to start imaging is made, such as by pressing the release button, the drive unit 502 sets the wiring Tx_i_j low to turn off the transfer transistor 154. As a result, light incident on the PD 104 is photoelectrically converted and begins to be stored as electric charge.

[0054] At time t2, just before the set end time t3 of the charge accumulation, the driving unit 502 sets the voltage of the lines Rst_i_j and Wrt_i_j to low to turn off the reset transistor 152 and the pass transistor 158, and then sends a transfer pulse that sets the line Tx_i_j to high from the end time t3 to time t4. As a result, the charge photoelectrically converted by the PD 104 is accumulated in the FD 156.

[0055] After time t4, the driver 502 sends a transfer pulse that sets the line Wrt_i_j high from time t5 to time t6. This transfers the charge accumulated in the FD 156 to the storage capacitor 160, where it is isolated from subsequent charge accumulation in the PD 104 and held there. Thereafter, at time t7, the line Rst_i_j is set high, thereby completing the charge accumulation and transfer operation.

[0056] The above has described the operation of one pixel 150 in Fig. 3. However, as shown in Fig. 4, within a unit block 131, the wirings Rst_i_j, etc. are commonly connected to P pixels 150 in the same row. Therefore, the operation in Fig. 8 above is simultaneously executed at least for the pixels 150 in the same row within the unit block 131.

[0057] Furthermore, during global shuttering, the operation of FIG. 8 is executed simultaneously for the pixels 150 in L rows in the unit block 131 with m rows and n columns. That is, for the wirings Rst_i_j and the like where the subscript i ranges from 1 to m×n and the subscript j ranges from 1 to L, the wirings are simultaneously switched between high and low according to FIG. 8. This makes it possible to photoelectrically convert the image light incident on each pixel 150 at the same time and hold the charge. Unless otherwise specified, the following description will be given assuming that the global shutter is executed.

[0058] 9 shows a timing chart of the operation of reading out pixel signals from the pixels 150. Hereinafter, the operation of reading out pixel signals from the pixels 150 to the column transmission path 170 will be described with reference to FIG.

[0059] At time t8, which is later than time t7, the driver 502 turns on the selection transistor 164 by setting the line Sel_i_j high. As a result, a voltage serving as a pixel signal corresponding to the voltage generated by the charge accumulated in the storage capacitor 160 is output to the column transmission path 170. Furthermore, the driver 502 sends a pass pulse that sets the line Wrt_i_j high while keeping the line Sel_i_j high. As a result, a voltage serving as a reset signal at the node between the storage capacitor 160 and the amplification transistor 162 is output to the column transmission path 170. Thereafter, at time t9, the driver 502 sets the line Sel_i_j low, thereby completing readout of the pixel 150.

[0060] The CDS circuit 202 removes noise based on the pixel signal and the reset signal. The A / D conversion circuit 204 converts the pixel signal from which noise has been removed by the CDS circuit 202 into a digital signal and outputs it.

[0061] Fig. 10 is a timing chart showing the readout timing of the multiple pixels 150 included in the imaging unit. As explained in Fig. 9, the pass pulse for the line Wrt_i_j is sent with the line Sel_i_j set to high, so for the purpose of simplifying the explanation, only the timing chart for the line Sel_i_j is shown in Fig. 9.

[0062] In reading out the entire imaging unit, first, the pixels 150 in the first row in the entire imaging unit are selected. That is, the pixels 150 in the first row in the unit block 131 in the first row are selected. In the example of FIG. 5, the subscript i of the unit block 131 in the first row corresponds to 1 to n. Therefore, the driving unit 502 sends a selection pulse that simultaneously sets the wirings Sel_i_1 (where i is 1 to n) high to the row control unit 200 of the corresponding unit block 131.

[0063] As described above, the wiring Sel_i_1 is commonly connected to the pixels 150 in the first row within the unit block 131. Furthermore, a selection pulse is sent to the unit block 131 in the first row. Therefore, pixel signals of the pixels 150 in the first row are read out to the respective column transmission paths 170 across multiple unit blocks 131.

[0064] Each column transmission path 170 transmits a pixel signal from the pixel 150 selected by the row control unit 200 to the CDS circuit 202 of the corresponding column in the unit block 131. Noise is removed from the pixel signal by the CDS circuit 202, the pixel signal is converted into a digital signal by the A / D conversion circuit 204, and the digital signal is input to the shift register 206. By the readout operation, the shift register 206 receives P digital signals of the first row in the unit block 131 via each column transmission path 170 and temporarily holds them.

[0065] The shift register 206 sequentially outputs P digital signals to the shift register 210 via the column bus line 172. In this case, it is preferable that the unit blocks 131 in the first row are synchronously transmitted with each other. Through this readout operation, the shift register 210 receives the pixels 150 in the first row of the entire imaging unit, i.e., P×n digital signals.

[0066] The shift register 210 sequentially outputs P×n digital signals to the pixel memory 414, and the pixel memory 414 stores the digital signals as pixel values. In this case, it is preferable that the shift register 210 outputs the digital signals in the arrangement order of the pixels 150 in the entire imaging unit. In the example shown in Figures 4 and 5, P digital signals of the pixels 150 in the first row in the first unit block 131 (i=1) are output from left to right, then P digital signals of the pixels 150 in the first row in the second unit block 131 (i=2) are output from left to right, and so on.

[0067] This completes the readout of the pixels 150 in the first row of the entire imaging unit. Next, the pixels 150 in the second row of the entire imaging unit are selected. That is, the pixels 150 in the second row of the unit block 131 in the first row are selected. The driving unit 502 sends a selection pulse that simultaneously sets the wirings Sel_i_2 (where i is 1 to n) high to the row control unit 200 of the corresponding unit block 131. As a result, pixel signals of the pixels 150 in the second row are read out in the same way as the pixels 150 in the first row, and are output to the pixel memory 414 as pixel values.

[0068] Thereafter, the above operation is repeated from the third row to the Lth row, which is the last row in the unit block 131. This completes the readout of the pixels 150 included in the unit block 131 in the first row.

[0069] Next, the pixel 150 in the (L+1)th row in the entire imaging unit is selected. That is, the pixel 150 in the first row in the unit block 131 in the second row is selected. The drive unit 502 sends a selection pulse that simultaneously sets the wirings Sel_i_1 (where i is from (n+1) to 2n) to high to the row control unit 200 of the corresponding unit block 131. As a result, similar to the case of the unit block 131 in the first row, the pixel signals of the pixels 150 in the first row of the unit block 131 in the second row are read out and output as pixel values ​​to the pixel memory 414. Similarly, the (L+2)th row to the 2Lth row in the entire imaging unit, that is, the second row to the Lth row of the unit block 131 in the second row, are sequentially read out. This completes the readout of the pixels 150 included in the unit block 131 in the second row.

[0070] Thereafter, pixels are sequentially read out from the (2L+1)th row to the L×mth row in the entire imaging unit, that is, from the first row of the third unit block 131 to the Lth row of the mth unit block 131. This completes the readout of (L×P)×(n×m) pixels 150 included in the entire imaging unit, that is, the unit blocks 131 with m rows and n columns.

[0071] In the above embodiment, the pixel signals are converted into digital signals by the peripheral circuit 133 before being input to the shift register 210, which sequentially outputs pixels to the pixel memory 414. This makes it possible to prevent noise from being superimposed on the signals while they are held in the shift register 210. Furthermore, since the pixel signals are converted into digital signals before being input to the shift register 206 of the peripheral circuit 133, it is possible to prevent noise from being superimposed on the signals while they are held in the shift register 206.

[0072] Furthermore, by dividing the imaging unit into a plurality of unit blocks 131 and arranging the peripheral circuits 133 corresponding to the unit blocks 131 on the signal processing chip 111 side, A / D conversion can be performed before input to the shift registers 206, 210 without reducing the area of ​​the PD 104. Furthermore, even if the unit blocks 131 are arranged in a matrix and the pixels 150 in the unit blocks 131 are also arranged in a matrix, pixel signals can be output according to the matrix arrangement of the pixels 150 of the entire imaging unit. This eliminates the need for additional circuits, processing, etc. in the pixel memory 414, image processing unit 511, etc., due to the imaging unit being divided into unit blocks 131.

[0073] Fig. 11 shows another example of the connection relationship of the peripheral circuit 133 etc. In Fig. 11, the same components as in Fig. 5 are given the same reference numerals and the description thereof will be omitted.

[0074] The output sides of the n column bus lines 172 are connected to a matrix switch 220. The output sides of the matrix switch 220 are connected to the shift registers 206_1 to 206_k.

[0075] The matrix switch 220 inputs the digital signals transmitted to the column bus lines 172 to one of the plurality of shift registers 206 for each unit block 131 included in the corresponding column. For example, the digital signals from the column bus lines 172_1 and 172_2 are input to the shift register 206_1, and the digital signals from the column bus lines 172_3 and 172_4 are input to the shift register 206_2.

[0076] Furthermore, the matrix switch 220 may dynamically change the combination of the column bus lines 172 and the shift registers 206_1, etc. For example, when reading out from some of the unit blocks 131 in the imaging unit in moving image shooting, live view (also called through image display), crop shooting, etc., the combination of the column bus lines 172 of the unit blocks 131 to be read out and the shift registers 206_1, etc. may be set. For example, when reading out n / 2 unit blocks 131, these unit blocks 131 may be allocated as evenly as possible to the shift registers 206_1 to 206_k. This makes it possible to transmit pixel signals at a preset maximum transmission frequency whether pixel signals are output from unit blocks 131 in m rows and n columns or from a smaller number of unit blocks 131.

[0077] Although an example in which a global shutter is used has been described in the above embodiment, it is also possible not to use a global shutter. In this case, charge accumulation and transfer may be performed simultaneously within a unit block 131, and may be performed in a time-varying manner between multiple unit blocks 131. Alternatively, charge accumulation and transfer may be performed in a time-varying manner between pixels 150 within a unit block 131. Whether or not to use a global shutter may be selected by the user or may be automatically set based on the shooting conditions.

[0078] 3 uses a memory circuit, the memory circuit may not be used, in which case a mechanical shutter, for example, may be used as the global shutter.

[0079] 4 has a CDS circuit 202 and an A / D conversion circuit 204 for each column. The number of pairs of CDS circuits 202 and A / D conversion circuits 204 may be greater or less than this. For example, a pair of CDS circuit 202 and A / D conversion circuit 204 may be provided for one pixel 150. In this case, the pair of CDS circuit 202 and A / D conversion circuit 204 may be provided on the signal processing chip 111 side, and output lines for each pixel 150 may be connected via bumps 109, and a column transmission path for transmitting the output of the A / D conversion circuit 204 for each column may be provided on the signal processing chip 111 side.

[0080] 4 uses a shift register 206 to sequentially input P digital signals for one row to a shift register 210. Alternatively, P systems of column bus lines 172 may be provided for each column, and the peripheral circuit 133 may simultaneously input P digital data to the shift register 210 via the column bus lines 172. Alternatively, the number of column bus lines 172 provided for each column may be the same as the number of bits, and digital signals may be simultaneously transmitted in accordance with the number of bits, or fewer than the number of bits may be provided for each column, and digital signals may be sequentially transmitted in accordance with the number of bits.

[0081] 10, a selection pulse is sent sequentially to each row of the unit blocks 131. Alternatively, a selection pulse may be sent simultaneously to unit blocks 131 in m rows and n columns. That is, a transfer pulse may be sent simultaneously to wirings Sel_i_j where i ranges from 1 to m×n. In this case, the driving unit 502 controls the timing for each shift register 206 of the unit blocks 131 in the same column in accordance with the order of the columns so that after P digital signals are sent from the shift register 206 corresponding to one unit block 131, P digital signals are sent from the shift register 206 corresponding to the next unit block 131.

[0082] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0083] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0084] 100 imaging element, 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging chip, 131 unit block, 133 peripheral circuit, 150 pixel, 152 reset transistor, 154 transfer transistor, 156 FD, 158 pass transistor, 160 storage capacitor, 162 amplification transistor, 164 selection transistor, 166 load current source, 170 column transmission line, 172 column bus line, 200 row control unit, 202 CDS circuit, 204 A / D conversion circuit, 206 shift register, 210 shift register, 220 matrix switch, 414 pixel memory, 415 Arithmetic circuit, 418 I / F circuit, 420 drive control unit, 430 timing memory, 441 sensor control unit, 442 block control unit, 443 synchronization control unit, 444 signal control unit, 500 imaging device, 520 photographic lens, 501 system control unit, 502 drive unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 511 image processing unit, 512 arithmetic unit

Claims

1. a first block including a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first photoelectric conversion unit in the column direction, and a third photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first photoelectric conversion unit in the row direction; a fourth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the first block in the column direction; a fifth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the fourth photoelectric conversion unit in the column direction; a second block having a sixth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the fourth photoelectric conversion unit in the row direction; a third block that is arranged alongside the first block in the row direction and has a seventh photoelectric conversion unit that converts light into electric charges, an eighth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the seventh photoelectric conversion unit in the column direction; and a ninth photoelectric conversion unit that converts light into electric charges and that is arranged alongside the seventh photoelectric conversion unit in the row direction; a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having a first circuit unit including a first signal processing unit that performs signal processing on a first signal based on the charges converted in the first photoelectric conversion unit and a second signal based on the charges converted in the second photoelectric conversion unit, and a second signal processing unit that performs signal processing on a third signal based on the charges converted in the third photoelectric conversion unit; a second circuit unit including a third signal processing unit that performs signal processing on a fourth signal based on the charges converted in the fourth photoelectric conversion unit and a fifth signal based on the charges converted in the fifth photoelectric conversion unit, and a fourth signal processing unit that performs signal processing on a sixth signal based on the charges converted in the sixth photoelectric conversion unit; a third circuit unit including a fifth signal processing unit that performs signal processing on a seventh signal based on the charges converted in the seventh photoelectric conversion unit and an eighth signal based on the charges converted in the eighth photoelectric conversion unit, and a sixth signal processing unit that performs signal processing on a ninth signal based on the charges converted in the ninth photoelectric conversion unit; Equipped with the first circuit unit is disposed at a position overlapping the first block in a stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked, the second circuit portion is disposed at a position overlapping the second block in the stacking direction, The third circuit portion is disposed at a position overlapping with the third block in the stacking direction.

2. 2. The imaging device according to claim 1, the first semiconductor chip has: a semiconductor layer in which the first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, the fourth photoelectric conversion unit, the fifth photoelectric conversion unit, the sixth photoelectric conversion unit, the seventh photoelectric conversion unit, the eighth photoelectric conversion unit, and the ninth photoelectric conversion unit are arranged; and a wiring layer in which a first signal line through which the first signal and the second signal are output, a second signal line through which the third signal is output, a third signal line through which the fourth signal and the fifth signal are output, a fourth signal line through which the sixth signal is output, a fifth signal line through which the seventh signal and the eighth signal are output, and a sixth signal line through which the ninth signal is output are arranged; the wiring layer is disposed between the semiconductor layer and the second semiconductor chip in the stacking direction. Image sensor.

3. 3. The imaging device according to claim 1, the first signal processing unit includes a first conversion unit that converts the first signal and the second signal into digital signals; the second signal processing unit has a second conversion unit that converts the third signal into a digital signal, the third signal processing unit includes a third conversion unit that converts the fourth signal and the fifth signal into digital signals, the fourth signal processing unit has a fourth conversion unit that converts the sixth signal into a digital signal, the fifth signal processing unit includes a fifth conversion unit that converts the seventh signal and the eighth signal into digital signals, The sixth signal processing unit has a sixth conversion unit that converts the ninth signal into a digital signal. Image sensor.

4. 4. The imaging device according to claim 3, the second conversion unit is arranged alongside the first conversion unit in the row direction, the fourth conversion unit is arranged alongside the third conversion unit in the row direction, the sixth conversion unit is arranged alongside the fifth conversion unit in the row direction; Image sensor.

5. 5. The imaging device according to claim 3, the first circuit unit has a first transmission unit that transmits a first digital signal obtained by converting the first signal into a digital signal in the first conversion unit, a second digital signal obtained by converting the second signal into a digital signal in the first conversion unit, and a third digital signal obtained by converting the third signal into a digital signal in the second conversion unit, the second circuit unit has a second transmission unit that transmits a fourth digital signal obtained by converting the fourth signal into a digital signal in the third conversion unit, a fifth digital signal obtained by converting the fifth signal into a digital signal in the third conversion unit, and a sixth digital signal obtained by converting the sixth signal into a digital signal in the fourth conversion unit, the third circuit unit has a third transmission unit that transmits a seventh digital signal converted from the seventh signal to a digital signal by the fifth conversion unit, an eighth digital signal converted from the eighth signal to a digital signal by the fifth conversion unit, and a ninth digital signal converted from the ninth signal to a digital signal by the sixth conversion unit. Image sensor.

6. 6. The imaging device according to claim 5, the first transmission unit transmits the first digital signal, the second digital signal, and the third digital signal using a shift register; the second transmission unit transmits the fourth digital signal, the fifth digital signal, and the sixth digital signal using a shift register; the third transmission unit transmits the seventh digital signal, the eighth digital signal, and the ninth digital signal using a shift register; Image sensor.

7. 7. The imaging device according to claim 1, the first signal processing unit includes a first noise removal unit for removing noise included in the first signal and noise included in the second signal, and a second noise removal unit for removing noise included in the third signal; the second signal processing unit includes a third noise removal unit for removing noise included in the fourth signal and noise included in the fifth signal, and a fourth noise removal unit for removing noise included in the sixth signal; the third signal processing unit includes a fifth noise removal unit for removing noise included in the seventh signal and noise included in the eighth signal, and a sixth noise removal unit for removing noise included in the ninth signal. Image sensor.

8. 8. The imaging device according to claim 7, the second noise removal unit is arranged alongside the first noise removal unit in the row direction, the fourth noise removal unit is arranged alongside the third noise removal unit in the row direction, the sixth noise removal unit is arranged alongside the fifth noise removal unit in the row direction; Image sensor.

9. The imaging element according to claim 2, a first joint portion that electrically joins the first signal line and the second semiconductor chip; a second joint portion that electrically joins the second signal line and the second semiconductor chip; a third joint portion that electrically joins the third signal line and the second semiconductor chip; a fourth joint portion that electrically joins the fourth signal line and the second semiconductor chip; a fifth joint portion that electrically joins the fifth signal line and the second semiconductor chip; a sixth joint portion that electrically joins the sixth signal line and the second semiconductor chip; An imaging element comprising:

10. 10. The imaging device according to claim 9, the first joint portion has first metal members arranged to face each other in the stacking direction, the second joint portion has second metal members arranged to face each other in the stacking direction, The third joint portion includes third metal members arranged to face each other in the stacking direction.

11. The imaging device according to claim 10, the first metal member is made of copper, the second metal member is made of copper, The third metal member is made of copper. Image sensor.

12. The imaging device according to any one of claims 9 to 11, the first signal processing unit performs signal processing on the first signal output via the first joint unit and the second signal output via the first joint unit; the second signal processing unit performs signal processing on the third signal output via the second joint unit; the third signal processing unit performs signal processing on the fourth signal output via the third joint unit and the fifth signal output via the third joint unit; the fourth signal processing unit performs signal processing on the sixth signal output via the fourth joint unit, the fifth signal processing unit performs signal processing on the seventh signal output via the fifth joint unit and the eighth signal output via the fifth joint unit; the sixth signal processing unit performs signal processing on the ninth signal output via the sixth joint unit. Image sensor.

13. The imaging device according to claim 12, the first signal processing unit has a first conversion unit that converts the first signal output via the first joint unit and the second signal output via the first joint unit into digital signals, the second signal processing unit has a second conversion unit that converts the third signal output via the second connection unit into a digital signal, the third signal processing unit has a third conversion unit that converts the fourth signal output via the third joint unit and the fifth signal output via the third joint unit into digital signals, the fourth signal processing unit has a fourth conversion unit that converts the sixth signal output via the fourth connection unit into a digital signal, the fifth signal processing unit has a fifth conversion unit that converts the seventh signal output via the fifth joint unit and the eighth signal output via the fifth joint unit into digital signals, the sixth signal processing unit has a sixth conversion unit that converts the ninth signal output via the sixth connection unit into a digital signal; Image sensor.

14. The imaging device according to claim 13, the second conversion unit is arranged alongside the first conversion unit in the row direction, the fourth conversion unit is arranged alongside the third conversion unit in the row direction, the sixth conversion unit is arranged alongside the fifth conversion unit in the row direction; Image sensor.

15. 15. The imaging device according to claim 13, the first circuit unit has a first transmission unit that transmits a first digital signal obtained by converting the first signal into a digital signal in the first conversion unit, a second digital signal obtained by converting the second signal into a digital signal in the first conversion unit, and a third digital signal obtained by converting the third signal into a digital signal in the second conversion unit, the second circuit unit has a second transmission unit that transmits a fourth digital signal obtained by converting the fourth signal into a digital signal in the third conversion unit, a fifth digital signal obtained by converting the fifth signal into a digital signal in the third conversion unit, and a sixth digital signal obtained by converting the sixth signal into a digital signal in the fourth conversion unit, the third circuit unit has a third transmission unit that transmits a seventh digital signal converted from the seventh signal to a digital signal by the fifth conversion unit, an eighth digital signal converted from the eighth signal to a digital signal by the fifth conversion unit, and a ninth digital signal converted from the ninth signal to a digital signal by the sixth conversion unit. Image sensor.

16. 16. The imaging device according to claim 15, the first transmission unit transmits the first digital signal, the second digital signal, and the third digital signal using a shift register; the second transmission unit transmits the fourth digital signal, the fifth digital signal, and the sixth digital signal using a shift register; the third transmission unit transmits the seventh digital signal, the eighth digital signal, and the ninth digital signal using a shift register; Image sensor.

17. The imaging device according to any one of claims 12 to 16, the first signal processing unit has a first noise removal unit for removing noise included in the first signal output via the first joint unit and noise included in the second signal output via the first joint unit, and a second noise removal unit for removing noise included in the third signal output via the second joint unit, the second signal processing unit includes a third noise removal unit for removing noise included in the fourth signal output via the third joint unit and noise included in the fifth signal output via the third joint unit, and a fourth noise removal unit for removing noise included in the sixth signal output via the fourth joint unit, The third signal processing unit has a fifth noise removal unit for removing noise included in the seventh signal output through the fifth joint unit and noise included in the eighth signal output through the fifth joint unit, and a sixth noise removal unit for removing noise included in the ninth signal output through the sixth joint unit. Image sensor.

18. 18. The imaging device according to claim 17, the second noise removal unit is arranged alongside the first noise removal unit in the row direction, the fourth noise removal unit is arranged alongside the third noise removal unit in the row direction, the sixth noise removal unit is arranged alongside the fifth noise removal unit in the row direction; Image sensor.

19. 19. The imaging device according to claim 1, a first control unit that controls accumulation of the electric charges converted by the first photoelectric conversion unit, accumulation of the electric charges converted by the second photoelectric conversion unit, and accumulation of the electric charges converted by the third photoelectric conversion unit; a second control unit that controls accumulation of the electric charges converted by the fourth photoelectric conversion unit, accumulation of the electric charges converted by the fifth photoelectric conversion unit, and accumulation of the electric charges converted by the sixth photoelectric conversion unit; a third control unit that controls accumulation of the electric charges converted by the seventh photoelectric conversion unit, accumulation of the electric charges converted by the eighth photoelectric conversion unit, and accumulation of the electric charges converted by the ninth photoelectric conversion unit; An imaging element comprising:

20. 20. The imaging device according to claim 19, the first control unit, the second control unit, and the third control unit are disposed on the second semiconductor chip; Image sensor.

21. 19. The imaging device according to claim 1, the first block includes a first transfer unit that transfers the charges converted by the first photoelectric conversion unit, a second transfer unit that transfers the charges converted by the second photoelectric conversion unit, and a third transfer unit that transfers the charges converted by the third photoelectric conversion unit; the second block includes a fourth transfer unit that transfers the charges converted by the fourth photoelectric conversion unit, a fifth transfer unit that transfers the charges converted by the fifth photoelectric conversion unit, and a sixth transfer unit that transfers the charges converted by the sixth photoelectric conversion unit; the third block includes a seventh transfer unit that transfers the charges converted by the seventh photoelectric conversion unit, an eighth transfer unit that transfers the charges converted by the eighth photoelectric conversion unit, and a ninth transfer unit that transfers the charges converted by the ninth photoelectric conversion unit; Image sensor.

22. 22. The imaging device according to claim 21, a first control unit that controls a timing at which the first transfer unit transfers electric charges from the first photoelectric conversion unit, a timing at which the second transfer unit transfers electric charges from the second photoelectric conversion unit, and a timing at which the third transfer unit transfers electric charges from the third photoelectric conversion unit; a second control unit that controls the timing at which the fourth transfer unit transfers the electric charges from the fourth photoelectric conversion unit, the timing at which the fifth transfer unit transfers the electric charges from the fifth photoelectric conversion unit, and the timing at which the sixth transfer unit transfers the electric charges from the sixth photoelectric conversion unit; a third control unit that controls the timing at which the seventh transfer unit transfers the charges from the seventh photoelectric conversion unit, the timing at which the eighth transfer unit transfers the charges from the eighth photoelectric conversion unit, and the timing at which the ninth transfer unit transfers the charges from the ninth photoelectric conversion unit; An imaging element comprising:

23. 23. The imaging device according to claim 22, the first control unit, the second control unit, and the third control unit are disposed on the second semiconductor chip; Image sensor.

24. The imaging device according to claim 21, the first block includes a first charge holding unit to which charges from the first photoelectric conversion unit are transferred by the first transfer unit, a second charge holding unit to which charges from the second photoelectric conversion unit are transferred by the second transfer unit, a third charge holding unit to which charges from the third photoelectric conversion unit are transferred by the third transfer unit, a tenth transfer unit that transfers the charges held in the first charge holding unit, an eleventh transfer unit that transfers the charges held in the second charge holding unit, and a twelfth transfer unit that transfers the charges held in the third charge holding unit; the second block includes a fourth charge holding unit to which charges from the fourth photoelectric conversion unit are transferred by the fourth transfer unit, a fifth charge holding unit to which charges from the fifth photoelectric conversion unit are transferred by the fifth transfer unit, a sixth charge holding unit to which charges from the sixth photoelectric conversion unit are transferred by the sixth transfer unit, a thirteenth transfer unit that transfers the charges held in the fourth charge holding unit, a fourteenth transfer unit that transfers the charges held in the fifth charge holding unit, and a fifteenth transfer unit that transfers the charges held in the sixth charge holding unit; the third block includes a seventh charge holding unit to which charges from the seventh photoelectric conversion unit are transferred by the seventh transfer unit, an eighth charge holding unit to which charges from the eighth photoelectric conversion unit are transferred by the eighth transfer unit, a ninth charge holding unit to which charges from the ninth photoelectric conversion unit are transferred by the ninth transfer unit, a sixteenth transfer unit that transfers the charges held in the seventh charge holding unit, a seventeenth transfer unit that transfers the charges held in the eighth charge holding unit, and an eighteenth transfer unit that transfers the charges held in the ninth charge holding unit; Image sensor.

25. The imaging device according to claim 24, the first block includes a tenth charge retention unit to which charges from the first charge retention unit are transferred by the tenth transfer unit, an eleventh charge retention unit to which charges from the second charge retention unit are transferred by the eleventh transfer unit, and a twelfth charge retention unit to which charges from the third charge retention unit are transferred by the twelfth transfer unit; the second block includes a thirteenth charge retention unit to which charges from the fourth charge retention unit are transferred by the thirteenth transfer unit, a fourteenth charge retention unit to which charges from the fifth charge retention unit are transferred by the fourteenth transfer unit, and a fifteenth charge retention unit to which charges from the sixth charge retention unit are transferred by the fifteenth transfer unit; the third block includes a 16th charge retention unit to which charges from the 7th charge retention unit are transferred by the 16th transfer unit, a 17th charge retention unit to which charges from the 8th charge retention unit are transferred by the 17th transfer unit, and an 18th charge retention unit to which charges from the 9th charge retention unit are transferred by the 18th transfer unit; Image sensor.

26. The imaging device according to claim 25, the first block includes a first transistor including a gate electrically connected to the tenth charge holding unit, a second transistor including a gate electrically connected to the eleventh charge holding unit, and a third transistor including a gate electrically connected to the twelfth charge holding unit; the second block includes a fourth transistor including a gate electrically connected to the thirteenth charge holding unit, a fifth transistor including a gate electrically connected to the fourteenth charge holding unit, and a sixth transistor including a gate electrically connected to the fifteenth charge holding unit; the third block includes a seventh transistor including a gate electrically connected to the sixteenth charge holding portion, an eighth transistor including a gate electrically connected to the seventeenth charge holding portion, and a ninth transistor including a gate electrically connected to the eighteenth charge holding portion; Image sensor.

27. ​​The imaging element according to any one of claims 24 to 26, a first control unit that controls a timing at which the tenth transfer unit transfers the charges from the first charge holding unit, a timing at which the eleventh transfer unit transfers the charges from the second charge holding unit, and a timing at which the twelfth transfer unit transfers the charges from the third charge holding unit; a second control unit that controls a timing at which the thirteenth transfer unit transfers the charges from the fourth charge holding unit, a timing at which the fourteenth transfer unit transfers the charges from the fifth charge holding unit, and a timing at which the fifteenth transfer unit transfers the charges from the sixth charge holding unit; a third control unit that controls the timing at which the charges are transferred from the seventh charge holding unit by the sixteenth transfer unit, the timing at which the charges are transferred from the eighth charge holding unit by the seventeenth transfer unit, and the timing at which the charges are transferred from the ninth charge holding unit by the eighteenth transfer unit; An imaging element comprising:

28. The imaging device according to claim 27, the first control unit controls a timing at which the first transfer unit transfers electric charges from the first photoelectric conversion unit, a timing at which the second transfer unit transfers electric charges from the second photoelectric conversion unit, and a timing at which the third transfer unit transfers electric charges from the third photoelectric conversion unit; the second control unit controls a timing at which the fourth transfer unit transfers the electric charges from the fourth photoelectric conversion unit, a timing at which the fifth transfer unit transfers the electric charges from the fifth photoelectric conversion unit, and a timing at which the sixth transfer unit transfers the electric charges from the sixth photoelectric conversion unit; the third control unit controls a timing at which the seventh transfer unit transfers the electric charges from the seventh photoelectric conversion unit, a timing at which the eighth transfer unit transfers the electric charges from the eighth photoelectric conversion unit, and a timing at which the ninth transfer unit transfers the electric charges from the ninth photoelectric conversion unit. Image sensor.

29. The imaging element according to claim 27 or claim 28, the first control unit, the second control unit, and the third control unit are disposed on the second semiconductor chip; Image sensor.

30. 30. The imaging device according to claim 1, the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the column direction, the fifth photoelectric conversion unit is disposed adjacent to the fourth photoelectric conversion unit in the column direction, the eighth photoelectric conversion unit is disposed adjacent to the seventh photoelectric conversion unit in the column direction; Image sensor.

31. 31. The imaging device according to claim 1, the third photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the row direction, the sixth photoelectric conversion unit is disposed adjacent to the fourth photoelectric conversion unit in the row direction, the ninth photoelectric conversion unit is disposed adjacent to the seventh photoelectric conversion unit in the row direction. Image sensor.

32. The imaging device according to claim 1, wherein: the fourth photoelectric conversion unit is arranged alongside the first photoelectric conversion unit in the column direction; Image sensor.

33. The imaging device according to claim 1, wherein: the seventh photoelectric conversion unit is arranged alongside the first photoelectric conversion unit in the row direction; Image sensor.

34. The imaging device according to claim 1, wherein: the eighth photoelectric conversion unit is arranged alongside the second photoelectric conversion unit in the row direction; Image sensor.

35. 35. The imaging device according to claim 1, the second block is disposed adjacent to the first block in the column direction. Image sensor.

36. 36. The imaging device according to claim 1, the third block is disposed adjacent to the first block in the row direction. Image sensor.

37. 37. The imaging device according to claim 1, the first block includes a tenth photoelectric conversion unit that converts light into electric charges and is arranged alongside the third photoelectric conversion unit in the column direction; the second block includes an eleventh photoelectric conversion unit that converts light into electric charges and is arranged alongside the sixth photoelectric conversion unit in the column direction; the third block includes a twelfth photoelectric conversion unit that converts light into an electric charge and is arranged alongside the ninth photoelectric conversion unit in the column direction; the second signal processing unit performs signal processing on a tenth signal based on the charges converted by the tenth photoelectric conversion unit; the fourth signal processing unit performs signal processing on an eleventh signal based on the charge converted by the eleventh photoelectric conversion unit; the sixth signal processing unit performs signal processing on a twelfth signal based on the charge converted by the twelfth photoelectric conversion unit. Image sensor.

38. 38. The imaging device according to claim 37, the tenth photoelectric conversion unit is disposed adjacent to the third photoelectric conversion unit in the column direction; the eleventh photoelectric conversion unit is disposed adjacent to the sixth photoelectric conversion unit in the column direction, the twelfth photoelectric conversion unit is disposed adjacent to the ninth photoelectric conversion unit in the column direction; Image sensor.

39. 39. The imaging device according to claim 38, the tenth photoelectric conversion unit is disposed adjacent to the second photoelectric conversion unit in the row direction, the eleventh photoelectric conversion unit is disposed adjacent to the fifth photoelectric conversion unit in the row direction, the twelfth photoelectric conversion unit is disposed adjacent to the eighth photoelectric conversion unit in the row direction; Image sensor.

40. The imaging device according to claim 1, the second semiconductor chip has a through electrode for electrically connecting to the first semiconductor chip; Image sensor.

41. 41. The imaging device according to claim 1, An imaging element comprising a third semiconductor chip stacked on the first semiconductor chip.

42. The imaging device according to claim 41, the second semiconductor chip is disposed between the first semiconductor chip and the third semiconductor chip in the stacking direction; Image sensor.

43. The imaging device according to claim 42, the second semiconductor chip has a through electrode for electrically connecting to at least one of the first semiconductor chip and the third semiconductor chip; Image sensor.

44. An imaging device comprising the imaging element according to any one of claims 1 to 42.

45. 45. The imaging device of claim 44, The imaging element receives light from a photographing lens having a plurality of optical lenses. Imaging device.

46. 46. ​​The imaging device according to claim 44 or claim 45, an imaging device comprising an image processing unit electrically connected to the imaging element and generating image data;

Images