semiconductor switching devices

Abstract

To provide a semiconductor device cell having a layout that enables improved semiconductor device performance.SOLUTION: A semiconductor device cell (150) includes a JFET region (29) adjacent to a channel region (28), the JFET region defining a periphery of the semiconductor device cell (150). The JFET region (29) includes a JFET segment (29c) having a first end (29a) disposed proximately to a first corner (69a) of the semiconductor device cell (150) and an opposite second end (29b) proximate to a second corner (69b) of the semiconductor device cell (150). The JFET segment (29c) has a first width (W1) between the first end (29a) and the second end (29b), which is greater than a second width (W2) of the JFET region (29) of the first end (29a) and the second end (29b).SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor power devices, such as silicon carbide power devices, and more particularly to semiconductor device cells having layouts that enable improved semiconductor device performance. [Background technology]

[0002] Semiconductor devices, such as silicon carbide (SiC) power devices, are widely used in conventional electrical systems to switch or convert power for consumption by loads. Many electrical systems utilize a variety of semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and other suitable transistors). For example, MOSFETs can be fabricated as individual transistor packages for high-power applications or as chips with millions of transistors. Thousands of these transistor "cells" can be combined into a single device to handle relatively large currents and voltages.

[0003] Many conventional MOSFETs use a vertical structure with the source and drain terminals on opposite sides of the chip. The vertical geometry eliminates gate congestion and provides a larger channel width. Generally, when a semiconductor device is conducting current, the device's on-state resistance represents its conduction losses, which affect the device's efficiency and its cost. That is, conventional semiconductor device cells contain several internal components that can create resistance to the current flowing through the device. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a schematic diagram of a typical planar MOSFET device. [Figure 2]FIG. 1 is a schematic diagram illustrating the resistance for various regions of a typical MOSFET device. [Figure 3] 3 is a chart depicting the relative resistance contributions of regions of the MOSFET device structure of FIG. 2; [Figure 4] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a striped cell layout. [Figure 5] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a striped cell layout. [Figure 6] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a cellular layout. [Figure 7] 1 is a graph depicting normalized electric field strength in a portion of a SiC layer and a portion of a dielectric layer disposed over the SiC layer, the portion of the SiC layer being disposed between the corners of a well region of a conventional square device cell that is reverse biased. [Figure 8] FIG. 1 is a top view of a single semiconductor device cell in accordance with various aspects described herein. [Figure 9] FIG. 1 is a top view of a system comprising a cellular array of semiconductor device cells in accordance with various aspects described herein. DETAILED DESCRIPTION OF THE INVENTION

[0005] Aspects of the present disclosure may be implemented in any environment, device, or method for cooling a heat-generating module, regardless of the function performed by the heat-generating module.

[0006] As used herein, the term "set" or a "set" of elements may be any number of elements, including only one. When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. In addition, it should be understood that references to "one aspect" or "aspects" of the present disclosure are not intended to be interpreted as excluding the existence of additional aspects that also incorporate the referenced features.

[0007] It will be understood that feature shapes, positions, and alignments disclosed herein are shown and described as being relatively ideal (e.g., square, rectangular, and hexagonal cells and shielding regions with perfectly straight and aligned features) for simplicity. However, as will be understood by those skilled in the art, process variations and technical constraints may result in cellular designs with less than ideal shapes, or even irregular features may be consistent with the present disclosure. Thus, the term "approximately," as used herein to describe feature shapes, positions, or alignments, is meant to encompass ideal or target shapes, positions, and alignments, as well as imperfectly implemented shapes, positions, and alignments that result from variations in semiconductor manufacturing processes, as will be understood by those skilled in the art.

[0008] Additionally, semiconductor device cells are described herein as being disposed or fabricated "at," "in," "on," or "along" the surface of a semiconductor layer. This is intended to include semiconductor device cells having portions disposed within the bulk of the semiconductor layer, portions disposed proximate to the surface of the semiconductor layer, portions disposed flush with the surface of the semiconductor layer, and / or portions disposed above or on top of the surface of the semiconductor layer.

[0009] It will be apparent to those skilled in the art that while terms such as "voltage," "current," and "power" may be used herein, these terms may be interrelated when describing aspects of electrical circuits or circuit operation.

[0010] All directional references (e.g., radial, axial, top, bottom, upward, downward, left, right, lateral, front, rear, top, bottom, upward, downward, vertical, horizontal, clockwise, counterclockwise) are used for identification purposes to aid the reader's understanding of this disclosure and do not specifically impose limitations on their location, orientation, or use. References to connections (e.g., attached, coupled, connected, and coupled) should be interpreted broadly and, unless otherwise indicated, can include intermediate members between collections of elements and can include relative movement between the elements. As such, references to connections do not necessarily infer that two elements are directly connected and in a fixed relationship relative to each other. In a non-limiting example, connections or disconnections can be selectively configured to make, enable, disable, etc., electrical connections between respective elements. The exemplary drawings are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the figures attached hereto may be varied.

[0011] As used herein, a controllable switching element or "switch" is an electrical device that is controllable to toggle between a first mode of operation in which the switch is in a very low resistance or "on" state or otherwise a conducting mode in which current is intended to flow from the switch input to the switch output, and a second mode of operation in which the switch is in a very high resistance or "off" state or otherwise a non-conducting mode in which current is intended to prevent flow between the switch input and the switch output. In a non-limiting example, connections or disconnections, such as enabled or disabled connections, by a controllable switching element can be selectively configured to make, enable, disable, etc., electrical connections between the respective elements.

[0012] Additionally, while various embodiments may be discussed below in the context of SiC MOSFET devices for ease of description and understanding, it should be understood that the present approach is applicable to other types of MOSFETs, such as, but not limited to, SiC DMOSFETs, UMOSFETs, and VMOSFETs. It is contemplated that various material systems (e.g., silicon (Si), germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C), or any other suitable large bandgap semiconductor) may be used. It is further contemplated that other types of device structures utilizing n-channel or p-channel designs (e.g., UMOSFETs, VMOSFETs, insulated gate bipolar transistors (IGBTs), insulated base MOS controlled thyristors (IBMCTs), or any other suitable FET and / or MOS devices) may be used in various non-limiting embodiments.

[0013] One of the most common solid-state semiconductor switching devices used in modern power electronics is the MOSFET device. While an ideal switch conducts current with zero electrical resistance when in its low-resistance "on" or conducting state, a MOSFET will always exhibit finite electrical resistance. Therefore, it is generally desirable to reduce the total resistance (e.g., on-state resistance) to the lowest possible value. It is also desirable to minimize the on-state resistance of a MOSFET without reducing the device's off-state resistance, switching speed, or both.

[0014] A conventional MOSFET typically consists of a periodic arrangement of unit cells. Each unit cell may have a respective electrical resistance, and the on-state resistance of the MOSFET can be defined by the sum of the respective cell resistances in a parallel electrical circuit. In addition, each unit cell resistance can be defined by the set of respective resistances of the structural components of the cells coupled in series. The on-state resistance of a particular MOSFET can therefore be defined at least in part based on the relative geometric configuration of the various functional components within each cell.

[0015] When a MOSFET is in a conducting or on-state, electrons flow through each individual cell from the "source metal" on the top surface of the SiC semiconductor body, through various structures defined within the SiC semiconductor body, and into the "drain metal" on the back surface of the body. Each respective MOSFET unit cell surface can include four mutually exclusive, non-overlapping regions referred to herein as the source contact region, the n+ / p-well region, the channel / accumulation (channel) region, and the junction field effect transistor (JFET) region. The four regions can be electrically coupled in series and can occupy substantially the entire area of ​​the respective cell.

[0016] The resistive contributions of the source contact and channel region to the on-state electrical resistance of a MOSFET are inversely proportional to their respective areas. The resistive contribution of the n+ / p-well region to the on-state electrical resistance of a MOSFET is approximately directly proportional to its area. Because the resistive contribution of the channel region is relatively larger than that of the n+ / p-well region or the source contact region, the on-state electrical resistance of a MOSFET can be reduced by maximizing the relative area of ​​the channel region in the unit cell to the n+ / p-well region or the source contact region. Therefore, conventional techniques typically employ MOSFET structures that maximize the relative ratio of the channel region area by arranging the cell geometry to minimize the relative ratio of the n+ / p-well region area or the source contact region area or both to the channel region, JFET region, or both.

[0017] However, in SiC MOSFETs, current manufacturing techniques can limit such optimization. For example, conventional techniques have focused on reducing the on-state resistance of MOSFETs by using periodic cells created by surrounding a minimum-sized source contact region with a minimum-sized n+ region relative to the channel region. However, the minimum manufacturable source contact region dimensions (using conventional manufacturing techniques) may be larger than the calculated or determined optimal area. In addition, enlarging the channel region of adjacent cells can result in degradation of the off-state breakdown voltage at the corners of the cells.

[0018] Thus, as described in more detail herein, in non-limiting embodiments, cells can be arranged to increase the relative ratio of JFET area between adjacently aligned cells while maintaining the relative geometry of the channel region to the JFET region at the corners of the cells. In this manner, embodiments described herein can arrange a larger net relative ratio of JFET region area to source contact area or n+ region size or both compared to conventional techniques, thereby achieving improved (i.e., lower) on-state resistance for each cell compared to conventional devices. Furthermore, by maintaining the geometry of the channel region to the JFET region at the corners of the cells while enlarging the JFET region between the corners, the degradation of off-state breakdown voltage at the corners of the cells of some prior art solutions can be avoided.

[0019] As described in more detail herein, unwanted increases in on-state resistance resulting from increased areas of the n+ / p-well regions (e.g., in alternating bands) can be negated or overcome within predefined dimensional ranges due to the reduction in on-state resistance achieved by the corresponding increase in area of ​​the JFET regions, thereby resulting in a net reduction in the on-state resistance of each cell compared to conventional designs.

[0020] 1 illustrates an active cell of a conventional planar n-channel field effect transistor, such as a DMOSFET, hereinafter MOSFET device 10. It can be understood that certain commonly understood design elements (e.g., top metallization, passivation, edge termination, etc.) may be omitted to more clearly illustrate and describe certain components of MOSFET device 10, as well as other devices discussed hereinafter.

[0021] The illustrated conventional MOSFET device 10 of Figure 1 includes a semiconductor layer 2 (e.g., an epitaxial SiC semiconductor layer) having a first side 4 and a second side 6. The semiconductor layer 2 includes a drift region 16 having a first conductivity type (e.g., an n-type drift region 16), a well region 18 having a second conductivity type (e.g., a p-well region 18) adjacent to the drift region 16 and disposed proximate to the first side 4. The semiconductor layer 2 also includes a source region 20 having the first conductivity type (e.g., an n-type source region 20) adjacent to the well region 18 and proximate to the first side 4.

[0022] A source contact 22 is disposed on top of first face 4 partially covering source region 20 and well region 18 .

[0023] A dielectric layer 24 (also called a gate insulating layer or gate dielectric layer) is disposed on a portion of the first surface 4 of the semiconductor layer 2, and a gate electrode 26 is disposed on the dielectric layer 24.

[0024] The second surface 6 of the semiconductor layer 2 is a substrate layer 14 (eg, a SiC substrate layer), and a drain contact 12 is disposed along the substrate layer 14 at the bottom of the MOSFET device 10 .

[0025] During on-state operation, a suitable gate voltage (e.g., above the threshold voltage (VTH) of MOSFET device 10) can cause an inversion layer to form in channel region 28 due to carrier accumulation and an extended conduction path in junction field effect transistor (JFET) region 29, allowing current to flow from drain contact 12 (i.e., drain electrode) to source contact 22 (i.e., source electrode). It should be understood that in the MOSFET devices discussed herein, channel region 28 can be generally defined as the upper portion of well region 18 disposed beneath gate electrode 26 and dielectric layer 24.

[0026] Figure 2 is a schematic cross-sectional view of the conventional MOSFET device 10 of Figure 1. The source contact 22 of the MOSFET device 10 illustrated in Figure 2 typically provides an ohmic contact to the source electrode and is disposed over both portions of the source region 20 and portions of the well region 18. The source contact 22 is typically a metallic interface comprising one or more metal layers located between these semiconductor portions of the MOSFET device 10 and the metal source electrode.

[0027] For ease of understanding, the portion of source region 20 (e.g., n+ source region 20) of MOSFET device 10 that is disposed below source contact 22 may be more specifically referred to herein as a source contact region 42 of MOSFET device 10. Similarly, the portion of well region 18 (e.g., p-well region 18) of MOSFET device 10, which may be p+ doped to a higher level than the remainder of well region 18, may be more specifically referred to herein as a body region 44 (e.g., p+ body region 44) of MOSFET device 10. For ease of understanding, the portion of body region 44 that is disposed below source contact 22 (e.g., covered by or directly electrically connected to source contact 22) may be more specifically referred to herein as a body contact region 44 (e.g., p+ body contact region 44) of MOSFET device 10.

[0028] For consistency, portions of source contact 22 may be designated herein based on the portion of the semiconductor device disposed below source contact 22. For example, the portion of source contact 22 disposed above body contact region 44 may be referred to herein as the body contact portion of source contact 22. Similarly, the portion of source contact 22 disposed above source contact region 42 of MOSFET device 10 may be referred to herein as the source contact portion of source contact 22.

[0029] As illustrated schematically in FIG. 2, various regions of MOSFET device 10 can each have an associated resistance, with the total resistance of MOSFET device 10 (e.g., on-state resistance, Rds(on)) being expressed as the sum of each of these resistances. For example, as illustrated in FIG. 2, the on-state resistance Rds(on) of MOSFET device 10 can be approximated as the sum of source region resistance 30 (e.g., Rs, the resistance of source region 20 and source contact 22), inversion channel resistance 32 (e.g., Rch, the resistance of channel region 28 illustrated in FIG. 2), accumulation layer resistance 34 (e.g., Racc, the resistance of the accumulation layer between dielectric layer 24 and the portion of drift region 16 disposed between well regions 18), JFET region resistance 36 (e.g., RJFET, the resistance of the non-depleted neck region between well regions 18), drift region resistance 38 (e.g., Rdrift, the resistance for drift region 16), and substrate layer resistance 48 (e.g., Rsub, the resistance for substrate layer 14). It should be noted that the resistances illustrated in FIG. 2 are not intended to be exhaustive, and other resistances (e.g., drain contact resistance, diffusion resistance, etc.) may potentially be present within the MOSFET device 10.

[0030] 2 may dominate the conduction losses of MOSFET device 10, and addressing these factors can have a significant impact on the on-state resistance Rds(on). For example, in devices where drift resistance 38, substrate layer resistance 48, and contact resistance are negligible, such as low voltage devices or devices that suffer from low inversion layer mobility (e.g., SiC devices), channel resistance 32 may account for a significant portion of the device's conduction losses.

[0031] By way of further example, in medium and high voltage devices, the JFET region resistance 36 can account for a significant portion of the total conduction losses. In some cases, the MOSFET channel and JFET can comprise approximately 55% of the on-state resistance of a typical semiconductor device.

[0032] 3, a chart is shown depicting an example of the relative resistance contributions of various regions of the MOSFET device structure of FIG. 2. The relative resistance for each region is plotted as a function of distance (e.g., path length) of the respective region. It can be seen that the inversion channel resistance 32 of the channel region 28 may be the largest contributor to the on-state resistance Rds(on) of the MOSFET device 10, while the source region resistance 30 (e.g., the resistance of the source region 20 and the resistance of the source contact 22) and the substrate layer resistance 48 (e.g., the resistance of the substrate layer 14) contribute the least resistance to the on-state resistance Rds(on) of the MOSFET device 10.

[0033] 4 illustrates a top view of a conventional semiconductor layer 2 including a MOSFET device structure 41 having a conventional striped cell layout (i.e., a non-cellular layout). The illustrated striped layout of FIG. 4 includes a channel region 28, a source region 20, a source contact region 42, a body contact region 44, and a JFET region 29. It can be appreciated that the set of source contact regions 42 and the set of body contact regions 44 can be formed as continuous stripes along the surface of the semiconductor for the illustrated striped layout of FIG.

[0034] In terms of dimensions, a conventional MOSFET device structure 41 can be described as having a channel region 28 with a particular channel length 43, a distance 45 from the channel region 28 to the source region 20, a width 47 of the source contact region 42 and the body contact region 44, and a width 49 of the JFET region 29. While the conventional striped cell layout illustrated in FIG. 4 exhibits good reliability (e.g., long-term high-temperature performance), the relatively large channel resistance 32 and JFET resistance 36 of the MOSFET device structure 41 result in a relatively large on-state resistance Rds(on) that degrades the electrical performance of the device.

[0035] Another example of a conventional device layout is illustrated in Figure 5, which is a top or plan view of a striped ladder device layout 40 (i.e., a non-cellular layout) with segmented source / body contacts. The illustrated striped ladder device layout 40 includes a channel region 28, a source region 20, a set of segmented source / body contacts 46 (including body contact region 44 and source contact region 42), and a JFET region 29. Figure 5 further illustrates dimensions of the striped ladder device layout 40, including the channel region 28 having a channel length 43, the channel-to-source region 20 distance 45, the width 47 of the source contact region 42 and the body contact region 44, the width 49 of the JFET region 29, the segment length 51 of the source contact region 42, the segment length 52 of the body contact region 44, the subset of device areas 53, and the width 55 of the JFET region 54 within the subset of device areas 53 for the illustrated striped ladder device layout 40.

[0036] For further comparison, another example of a conventional device layout is illustrated in Figure 6. It can be appreciated that the layouts illustrated herein utilize a small number of device cells that represent a subset of the large number of device cells of a semiconductor device on the surface of semiconductor layer 2. It can be further appreciated that in Figures 4-6 and the top view of the device cells presented below, certain features of the device cells (e.g., gate electrode 26, dielectric layer 24, source contact 22) can be omitted to provide a clear view of the surface of semiconductor layer 2. In particular, Figure 6 illustrates a set of device cells 50 in an aligned layout, i.e., where the device cells 50 are not staggered or offset from one another.

[0037] In general, the illustrated conventional cell design and layout illustrated in Figure 6 may enable reduced values ​​of Rd(on) by reducing both the channel resistance 32 and the JFET resistance relative to a conventional striped cell layout such as that illustrated in Figure 5. For example, device cell 50 of Figure 6 achieves approximately 20% less Rd(on) than striped MOSFET device structure 41 of Figure 5, assuming similar manufacturing process limited dimensions.

[0038] 6, the illustrated conventional device cells 50 include a body contact region 44 disposed in a central region 65 of each cell, which may be part of a well region 18, as illustrated in FIG. 1B. The body contact region 44 is surrounded by source regions 20. More specifically, the body contact region 44 of each cell 50 may be surrounded by a source contact region 42 of the source region 20, which may have the same doping as the remainder of the source region 20. As illustrated in FIG. 1, the source region 20 of each cell 50 is surrounded by a channel region 28, which is also part of the well region 18. The channel region 28 is in turn surrounded by a JFET region 29.

[0039] It is recognized that while the device layout illustrated in FIG. 6 may enable a lower on-state resistance Rds(on) relative to a striped cell layout such as that illustrated in FIG. 5, such a design may have a significantly higher electric field in the portion of the JFET region 29 between the corners of the well regions 18 of adjacent device cells 50 under blocking conditions. In a SiC MOS device, the electric field in the dielectric layer 24 (e.g., silicon dioxide (SiO2)) disposed over the JFET region 29 (illustrated in FIGS. 1 and 2) may be approximately 10 times greater than that in a silicon device when the device cell 50 is operated under reverse bias. While SiC is generally tolerant to higher electric fields, the dielectric layer 24 may experience breakdown over long periods of operation, creating reliability issues for the device cell 50.

[0040] In particular, in a SiC MOSFET under reverse bias, the electric field present in the widest portion of the JFET region 29 between adjacent corners 28a of the channel regions 28 of adjacent device cells 50 at corner 69 where the adjacent device cells 50 meet (distance 60 along diagonal arrow 66 is illustrated in FIG. 6 ) is significantly higher than in other portions of the JFET region 29. Therefore, it is desirable to reduce the size of the JFET region 29 between the corners 28a of the channel regions 28 of adjacent device cells 50.

[0041] Figure 7 is a graph 70 plotting the strength of the electric field (in arbitrary units (au)) for a portion of a conventional SiC device cell 50 under reverse bias, the portion being disposed linearly along the diagonal arrow 66 illustrated in Figure 6. Graph 70 of Figure 7 includes a first curve 72 illustrating the electric field in semiconductor layer 2 and a second curve 74 illustrating the electric field in dielectric layer 24 disposed over semiconductor layer 2 (illustrated in Figure 1).

[0042] As illustrated in FIG. 7 , the electric field is small at the center of the conventional SiC device cell 50 (i.e., at x=0 μm), and as one moves diagonally through the corners of the conventional device cell 50, the electric field increases to a peak field strength in the middle of the JFET region 29. The peak or maximum electric field between the corners of the cell (i.e., distance 60 along diagonal arrow 66 in FIG. 6 ) is approximately 20% greater than the peak or maximum electric field between parallel portions of the device cell 50 (i.e., width 49 along arrow 64 in FIG. 3 ). As a result, as shown in FIG. 7 , the peak electric field in the dielectric layer 24 is greater between the corners of the well regions 18 of adjacent device cells 50 (e.g., between the corners of the channel regions 28 of adjacent device cells 50 at corner 69 where the adjacent device cells 50 meet), which may create long-term reliability issues for such unshielded device cells 50.

[0043] With the above in mind, present embodiments are directed to semiconductor device designs and layouts that enable improved semiconductor device performance. In particular, embodiments as disclosed herein are configured to reduce the electric field in the JFET region 29 (as well as in the dielectric layer 24 illustrated in FIG. 1 ) where the corners 69 of adjacent device cells 50 meet, without significantly increasing the on-state resistance Rds(on) of the semiconductor device cells 50.

[0044] Accordingly, embodiments of the present disclosure are arranged to increase the width of the portions of JFET region 29 relative to the portions of JFET region 29 at the corners 69 of the cells, such that the distance between the channel regions 28 at the corners 69 of adjacent device cells 50 is less than the distance between parallel portions of the channel regions 28 of adjacent device cells 50. Thus, embodiments can ensure that no portion of JFET region 29 is wider than the width of JFET region 29 between parallel portions of the channel regions 28 of adjacent device cells 50.

[0045] FIG. 8 depicts a top or plan view illustrating a non-limiting example embodiment of a single semiconductor device cell 150, according to a non-limiting embodiment. As described in more detail herein, the semiconductor device cell 150 can be configured to enable a reduction in the on-state resistance Rds(on) of the MOSFET device 10 compared to conventional techniques. While the illustrated example of FIG. 8 depicts the semiconductor device cell 150 having a square geometry, it should be understood that other embodiments are not so limited. In other non-limiting embodiments, the device cell 150 can have any other desired geometry or shape, including, but not limited to, elongated rectangle, hexagon, polygon, rounded, curved, variable width, elongated or distorted, and various combinations thereof.

[0046] The semiconductor device cell 150 can be disposed on a first surface 4 of a semiconductor layer 2 (e.g., a silicon carbide (SiC) semiconductor layer). The semiconductor device cell 150 can include a drift region 16 having a first conductivity type (as shown in FIG. 1 ). The semiconductor device cell 150 can have a cell perimeter 155 or boundary and a central region 65. In a non-limiting embodiment, the cell perimeter 155 can define a set of cell corners 69. For example, the set of cell corners 69 can include a first cell corner 69 a and a second cell corner 69 b.

[0047] Semiconductor device cell 150 may further include a body contact region 44, a source contact region 42, a source region 20, a channel region 28, a well region 18, and a JFET region 29. It may be understood that semiconductor layer 2, source region 20 including source contact region 42, and JFET region 29 may have a first conductivity type (e.g., n-type), while well region 18 including body contact region 44 and channel region 28 may have a second conductivity type (e.g., p-type).

[0048] As illustrated in FIG. 8 , the body contact region 44 can be disposed in a central region 65, which can be part of the well region 18 as illustrated in FIG. 1 . The body contact region 44 can be surrounded by a source region 20 of a first conductivity type (e.g., n-type or p-type). The periphery of the source region 20 can be surrounded by the well region 18, which can then be surrounded by a channel region 28 of a second conductivity type. It can be appreciated that in some embodiments, the portion of the source region 20 disposed below the source contact 22 can function as part of the source contact region 42 of the semiconductor device cell 150. More specifically, the body contact region 44 of the semiconductor device cell 150 can be surrounded by the source contact region 42 of the source region 20, and the doping of the source contact region 42 can be the same as the rest of the source region 20. The channel region 28 can then be surrounded by the JFET region 29.

[0049] The JFET region 29 can be disposed around the cell perimeter 155 of the semiconductor device cell 150. The JFET region 29 can be adjacent to the channel region 28 at the cell perimeter 155. The JFET region 29 can include a pair of corners disposed at and defining the cell corners 69. For example, the JFET region 29 can include a first corner region 29a and a second corner region 29b. Thus, the JFET region 29 can define the cell perimeter 155, the cell corners 69, or both. At least a portion of the JFET region 29 can define a longitudinal axis L1 along a length or side of the perimeter 155. The JFET region 29 along the length or side of the perimeter 155 includes a first corner region 29a and an opposing second corner region 29b separated by a JFET middle region 29c.

[0050] In non-limiting embodiments, the channel region 28 can define one or more corners 28 a, 28 b. The corners 28 a, 28 b can be right angles. As shown, in some embodiments, each of the corners 28 a, 28 b can be adjacent to a corresponding JFET corner region 29 a, 29 b. In non-limiting embodiments, a first corner 28 a of each of the channel regions 28 can be adjacent to a first corner region 29 a of the JFET region, and a second corner 28 b of the channel region 28 can be adjacent to a second corner region 29 b of the JFET region.

[0051] The JFET intermediate region 29c can define a first width W1. The first width W1 may extend across the JFET intermediate region 29c perpendicular to the longitudinal axis L1. In an embodiment, the first width W1 may extend from an end of the JFET intermediate region 29c that abuts the perimeter 128 of the channel region 28 to the cell perimeter 155.

[0052] At least one of the first corner region 29 a and the second corner region 29 b may define a second width W2. The second width W2 may extend perpendicular to the longitudinal axis L1 and across the JFET region 29. In an embodiment, the second width W2 may extend from an end of one of the first corner region 29 a or the second corner region 29 b of the JFET region 29 that abuts the perimeter 128 of the channel region 28 to the cell perimeter 155.

[0053] In a non-limiting embodiment, the first width W1 is greater than the second width W2. In a non-limiting embodiment, the first width W1 can be approximately 0.7 microns, and the second width W2 can be approximately 0.25 microns. In other embodiments, the first width W1 can be in the range of 0.3 to 1.2 microns, and the second width W2 can be in the range of 0.07 to 0.4 microns. In still other embodiments, the first width W1 can be at least 20% greater than the second width W2.

[0054] Other aspects are not so limited, and the dimensions of the first width W1 or the second width W2, or both, can be varied as desired for various applications without departing from the scope of the disclosure herein. As illustrated in Figure 9, regardless of the dimensions of the first width W1 and the second width W2, or their relative dimensions to each other, or both, they are positioned or defined for the specific purpose of reducing the contribution of the on-state resistance of the JFET region 29, while maintaining tolerance for breakdown voltage between the corners of adjacent semiconductor device cells 150.

[0055] FIG. 9 depicts a top or plan view illustrating a system 170 (e.g., cellular semiconductor devices 160, such as MOSFETs) comprising a cellular array of square semiconductor device cells 150, according to a non-limiting embodiment. The non-limiting embodiment of FIG. 9 is similar to the embodiment depicted in FIG. 8, with one difference that FIG. 9 comprises a set of semiconductor device cells 150 arranged in an aligned cellular-type layout. As used herein, two semiconductor device cells 150 may be referred to as adjacent or neighboring cells when any portion of the boundary of the two cells abuts or touches (e.g., along a portion of the cell perimeter 155 of the semiconductor device cells 150, or at a corner 69, or both). Thus, it can be understood that each square semiconductor device cell 150 in FIG. 9 may have eight adjacent or neighboring semiconductor device cells 150.

[0056] As illustrated in FIG. 9 , the set of semiconductor device cells 150 can include a first neighbor cell 151, a second neighbor cell 152, a third neighbor cell 153, and a fourth neighbor cell 155, as well as the second neighbor cell 152. While the illustrated example of FIG. 9 depicts a set of semiconductor device cells 150 having a rectangular or square geometry, it should be understood that other aspects are not so limited. In other non-limiting aspects, the semiconductor device cells 150 can have any other desired geometry or shape, including, but not limited to, elongated rectangles, hexagons, rounded, curved, variable widths, elongated or distorted shapes, and various combinations thereof. As described in more detail herein, the semiconductor device cells 150 can be configured to enable a reduced on-state resistance Rds(on) of the semiconductor device 160. Each semiconductor device cell 150 can be disposed on a first surface 4 of a semiconductor layer 2 (e.g., a silicon carbide (SiC) semiconductor layer).

[0057] As shown, the JFET region 29 can be disposed around the cell perimeter 155 of each respective semiconductor device cell 150. A first corner region 29a and a second corner region 29b of the JFET region 29 can be defined at the cell perimeter 155 and can define a corner 69 for each semiconductor device cell 150. At least a portion of the JFET region 29 around the cell perimeter 155 of at least one of the adjacent semiconductor device cells 150 (e.g., the first adjacent cell 151) can define a longitudinal axis L1 and have the first corner region 29a and an opposing second corner region 29b separated by a JFET middle region 29c. In a non-limiting embodiment, the first corner 28a of each of the channel regions 28 of the first adjacent cell can be adjacent to the first corner region 29a of the JFET, and the second corner 28b of the channel region 28 can be adjacent to the second corner region 29b of the JFET.

[0058] When arranged in an aligned cellular array, the JFET regions 29 of two adjacent semiconductor device cells 150, e.g., first adjacent cell 151 and second adjacent cell 152, may abut along a portion of the cell perimeters 155 of the first adjacent cell 151 and second adjacent cell 152. In this manner, the abutting JFET regions 29 of the first adjacent cell 151 and the second adjacent cell 152 may define a shared JFET region 29d.

[0059] The abutting JFET regions 29 (i.e., the shared JFET region 29d) can define a third width W3. The third width W3 may extend perpendicular to the longitudinal axis L1 across the abutting JFET intermediate regions 29c of the first neighboring cell 151 and the second neighboring cell 152. In a non-limiting embodiment, the third width W3 may extend from a peripheral edge of the JFET intermediate region 29c abutting the channel region 28 of the first neighboring cell 151, across the abutting JFET regions 29 of the first neighboring cell 151 and the second neighboring cell 152, to the periphery 128 of the channel region 28 of the second neighboring cell 152. In general, the third width W3 can be defined as the shortest distance across the JFET region 29 of the first adjacent cell 151 and the JFET region 29 of the second adjacent cell 152 between a region (e.g., channel region 28) having an opposite doping type (e.g., p-type) compared to that of the JFET region 29 (e.g., n-type).

[0060] The abutting JFET regions 29 can define a fourth width W4. The fourth width W4 may extend perpendicular to the longitudinal axis L1 and across the JFET regions 29 of the first neighboring cell 151 and the second neighboring cell 152, proximate at least one of the first corner region 29 a and the second corner region 29 b of the first neighboring cell 151 and the second neighboring cell 152. In a non-limiting embodiment, the fourth width W4 may extend from an end of the periphery of the channel region 28 of a particular first neighboring cell 151 (e.g., at the respective first corner 28 a or second corner 28 b), across the JFET regions, to the periphery of the channel region 28 of the second neighboring cell 152 (e.g., to the corresponding first corner 28 a or second corner 28 b). In an embodiment, the fourth width W4 may extend from one end of the first corner region 29a or the second corner region 29b of the JFET region 29 abutting the periphery of the channel region 28 of the first adjacent cell 151, across the JFET regions 29 of the first adjacent cell 151 and the second adjacent cell 152, to the periphery of the channel region 28 of the second adjacent cell 152. In general, the fourth width W4 can be defined as the shortest distance across the JFET region 29 of the first adjacent cell 151 and the JFET region 29 of the second adjacent cell 152 from a corner 28a, 28b of the channel region 28 of the first adjacent cell 151 having an opposite doping type (e.g., p-type) compared to that of the JFET region 29 (e.g., n-type) to a corner 28a, 28b of the channel region 28 of the second adjacent cell 152 having an opposite doping type (e.g., p-type) compared to that of the JFET region 29 (e.g., n-type).

[0061] In a non-limiting embodiment, the third width W3 may be equal to the sum of the first width W1 of the first neighboring cell and the first width W1 of the second neighboring cell 152. Similarly, in a non-limiting embodiment, the fourth width W4 may be equal to the sum of the second width W2 of the first neighboring cell and the second width W2 of the second neighboring cell 152. In a non-limiting embodiment, the fourth width W4 defined by the first neighboring cell 151 and the second neighboring cell 152 may be greater than the third width W3 defined by the first neighboring cell 151 and the second neighboring cell 152.

[0062] In a non-limiting embodiment, the third width W3 can be approximately 1.3 microns, and the fourth width W4 can be approximately 0.45 microns. In other embodiments, the third width W3 can be within a range of 0.5 to 2.2 microns, and the fourth width W4 can be within a range of 0.2 to 0.9 microns. In yet other embodiments, the third width W3 can be at least 20% wider than the fourth width W4.

[0063] Other aspects are not so limited, and the dimensions of the third width W3 or the fourth width W4, or both, can be varied as desired for various applications without departing from the scope of the disclosure herein. Regardless of the dimensions of the third width W3 and the fourth width W4, or their relative dimensions to each other, or both, they are positioned or defined for the specific purpose of reducing the on-state resistance contribution of each JFET region 29 of a set of semiconductor device cells 150, while maintaining tolerance for breakdown voltage between corners of adjacent semiconductor device cells 150.

[0064] It can be appreciated that aspects of the present disclosure can achieve a reduction in the on-state resistance of semiconductor device cells 150 beyond conventional techniques by increasing the width of the JFET region 29 at the cell periphery 155, away from the first corner region 29a and the second corner region 29b, without changing (e.g., decreasing or increasing) the dimensions of the channel region corners 28a, 28b proximate the respective corners 69 of the cell, thereby avoiding or reducing the increase in the electric field at the respective corners 69 of the cell, thereby resulting in improved long-term reliability for these semiconductor device cells 150.

[0065] Thus, the semiconductor device cell 150 of the present disclosure reduces conduction losses in the device (e.g., minimizes on-state resistance Rds(on)) by achieving an increase in the width of portions of the JFET region without reducing the distance between the channel regions 28 at the corners 69 of adjacent semiconductor device cells 150.

[0066] Unless otherwise stated, different features and structures of various embodiments can be used in combination with each other as desired. The fact that one embodiment may not be shown in all embodiments is not meant to be interpreted as being unable to do so, but is done for the sake of brevity. Thus, various features of different embodiments can be mixed and matched as desired to form new embodiments, regardless of whether the new embodiments are explicitly described. Any combination or permutation of features described herein is covered by the present disclosure.

[0067] This description uses examples to disclose aspects of the disclosure, including the best mode, and also to enable any person skilled in the art to practice aspects of the disclosure, including making and using any devices or systems and practicing any incorporated methods. The scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that differ from the literal language of the claims, or if they include equivalent structural elements that differ only insignificantly from the literal language of the claims.

[0068] The features disclosed in the above description, in the following claims, and / or in the accompanying drawings can, both individually and in any combination thereof, be relevant to realise embodiments in various forms thereof.

[0069] Various features, aspects, and advantages of the present disclosure may be embodied in any permutation of the aspects of the present disclosure, including, but not limited to, the following technical solutions as defined in the enumerated aspects.

[0070] A semiconductor device cell (150) including a semiconductor layer (2) including a drift region (16) having a first conductivity type, a well region (18) having a second conductivity type disposed adjacent to the drift region (16), a source region (20) having the first conductivity type disposed adjacent to and surrounded by the well region (18), a channel region (28) having the second conductivity type disposed adjacent to and around the well region (18), and a JFET region (29) abutting the periphery of the channel region (128) and defining a semiconductor cell periphery (155), the JFET region (29) being defined by a JFET intermediate region (29c). and a JFET region having at least a first corner (69a) and a second corner (69b) separated by a first corner (69a), wherein a first width W1 of the JFET intermediate region (29c) extending from an end of the JFET intermediate region (29c) abutting the periphery of the channel region (128) to the semiconductor cell periphery (155) is greater than a second width W2 of the JFET region (29c) extending from an end of at least one of the first corner (69a) and the second corner (69b) abutting the periphery of the channel region (128) to the semiconductor cell periphery (155).

[0071] 10. The system (160) of any preceding paragraph, wherein the first corner region (269a) and the second corner region (269b) each form a right angle.

[0072] The system (160) of any preceding paragraph, wherein the channel region (28) defines a third corner region (28a) adjacent to the first corner region (29a).

[0073] The system (160) of any preceding paragraph, wherein the channel region (28) defines a fourth corner region (28b) adjacent the second corner region (29b).

[0074] The system (160) of any preceding paragraph, wherein the JFET region (29) extends from the channel region (28) to the semiconductor cell periphery (155).

[0075] 10. The system (160) of any preceding paragraph, wherein the first width (W1) is in the range of 6 microns and 18 microns.

[0076] 10. The system (160) of any preceding paragraph, wherein the second width (W2) is in the range of 0.07 microns and 1.4 microns.

[0077] 10. The system (160) of any preceding claim, wherein the first width (W1) is at least 20% wider than the second width (W2).

[0078] 10. The system (160) of any preceding claim, wherein the semiconductor device cell (150) is a MOSFET device (10).

[0079] The semiconductor device further comprises a set of semiconductor device cells (151, 152, 153, 154) at least partially disposed in a semiconductor device layer (2) having a first conductivity type, each device cell comprising: a semiconductor layer (2) including a drift region (16) having the first conductivity type; a well region (18) having a second conductivity type disposed adjacent to the drift region (16); a source region (20) having the first conductivity type disposed adjacent to and surrounded by the well region (18); a channel region (28) having the second conductivity type disposed adjacent to and around the well region (18); and a semiconductor cell periphery (15) abutting the periphery of the channel region (28). 5), the JFET region having at least a first corner (69a) and a second corner (69b) separated by a JFET intermediate region (29c), wherein a first width W1 of the JFET intermediate region (29c) extending from an end of the JFET intermediate region (29c) abutting the periphery of the channel region (128) to the semiconductor cell periphery (155) is greater than a second width W2 of the JFET region (29) extending from an end of at least one of the first corner (69a) and the second corner (69b) abutting the periphery of the channel region (128) to the semiconductor cell periphery (155).

[0080] 10. The system (160) of any preceding paragraph, wherein each semiconductor device cell (150) comprises a respective semiconductor cell periphery (155) that is aligned with a respective semiconductor cell periphery (155) of an adjacent semiconductor device cell (150).

[0081] 10. The system (160) of any preceding paragraph, wherein the JFET intermediate regions (29c) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152) abut along portions of the semiconductor cell peripheries (155) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152) to define a shared JFET region (29d) between the first semiconductor device cell (151) and the second semiconductor device cell (152).

[0082] 10. The system (160) of any preceding paragraph, wherein the channel regions (28) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152) are separated by the JFET regions (29) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152).

[0083] 10. The system (160) of any preceding paragraph, wherein the third width (W3) of the shared JFET region is greater than a fourth width (W4) between the channel regions (28) of the first semiconductor device cell (151) and the second semiconductor device cell (152) in at least one of the first corner region (29a) and the second corner region (29b), respectively.

[0084] 10. The system (160) of any preceding paragraph, wherein the third width W3 is equal to the sum of the first width (W1) of the first semiconductor device 151 and the first width (W1) of the second semiconductor device 152, respectively.

[0085] 10. The system (160) of any preceding paragraph, wherein the fourth width (W4) is equal to the sum of the second width (W2) of the first semiconductor device cell (151) and the second width (W2) of the second semiconductor device cell (152), respectively.

[0086] 10. The system (160) of any preceding paragraph, wherein the first axial width (W1) is in the range of 12 microns and 36 microns.

[0087] 10. The system (160) of any preceding paragraph, wherein the second axial width (W2) is in the range of 0.14 microns and 2.8 microns.

[0088] 10. The system (160) of any preceding claim, wherein the first width (W1) is at least 20% wider than the second width (W2).

[0089] The system (160) of any preceding paragraph, wherein the semiconductor device cells (150) collectively define a MOSFET device (10).

[0090] a semiconductor layer (2) including a drift region (16) of a first conductivity type; a well region (18) of a second conductivity type disposed adjacent to the drift region (16); a source region (20) of the first conductivity type disposed adjacent to and surrounded by the well region (18); a channel region (28) of the second conductivity type disposed adjacently around the well region (18); and a JFET region (29) abutting the periphery of the channel region (128) and defining a semiconductor cell periphery (155), the JFET region having at least a first corner (69a) and a second corner (69b), a semiconductor device cell (150) in which the region (29c) has a first end (29a) disposed proximate the first corner (69a) and an opposite second end (29b) proximate the second corner (69b), and a first width W1 of the JFET intermediate region (29c) extending from an end of the JFET intermediate region (29c) abutting the periphery of the channel region (128) to the semiconductor cell periphery (155) is greater than a second width W2 of the JFET region (29c) extending from an end of at least one of the first corner (69a) and the second corner (69b) abutting the periphery of the channel region (128) to the semiconductor cell periphery (155).

[0091] The semiconductor device cell (150) of the preceding paragraph, wherein the first corner region (29a) and the second corner region (29b) each form a right angle.

[0092] The semiconductor device cell (150) of any preceding paragraph, wherein the channel region (28) defines a third corner region (28a) adjacent to the first corner region (29a).

[0093] The semiconductor device cell (150) of any preceding paragraph, wherein the channel region (28) defines a fourth corner region (28b) adjacent to the second corner region (29b).

[0094] 10. The semiconductor device cell (150) of any preceding claim, wherein the JFET region (29) extends from the channel region (28) to the semiconductor cell periphery (155).

[0095] 10. The semiconductor device cell (150) of any preceding paragraph, wherein the first width (W1) is in the range of 6 microns and 18 microns.

[0096] 10. The semiconductor device cell (150) of any preceding paragraph, wherein the second width (W2) is in the range of 0.07 microns and 1.4 microns.

[0097] 10. The semiconductor device cell (150) of any preceding paragraph, wherein the first width (W1) is at least 20% greater than the second width (W2).

[0098] 10. The semiconductor device cell (150) of any preceding claim, wherein the semiconductor device cell (150) is a MOSFET device (10).

[0099] A system (160) comprising a set of semiconductor device cells (150) at least partially disposed in a semiconductor layer (2) having a first conductivity type, each device cell (150) comprising: a semiconductor layer (2) including a drift region (16) having the first conductivity type; a well region (18) having a second conductivity type disposed adjacent to the drift region; a source region (20) having the first conductivity type disposed adjacent to and surrounded by the well region (18); a channel region (28) having the second conductivity type disposed adjacently around the well region (18); and a semiconductor cell periphery (155) abutting the channel region (28) and a periphery (128) of the channel region (28), defining at least and a JFET region (29) each having a first corner (69a) and a second corner (69b), wherein a JFET intermediate region (29c) has a first end (29a) disposed proximate the first corner (69a) and an opposite second end (29b) proximate the second corner (69b), and a first width (W1) of the JFET intermediate region (29c) extending from an end of the JFET intermediate region (29c) abutting the periphery of the channel region (128) to a semiconductor cell periphery (155) is greater than a second width (W2) of the JFET region (29) extending from an end of at least one of the first corner (29a) and the second corner (29b) abutting the periphery of the channel region (128) to the semiconductor cell periphery (155).

[0100] 10. The system (160) of any preceding paragraph, wherein each semiconductor device cell (150) comprises a respective semiconductor cell periphery (155) that is aligned with a respective semiconductor cell periphery (155) of an adjacent semiconductor device cell (150).

[0101] 10. The system (160) of any preceding paragraph, wherein the JFET intermediate regions (29c) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152) abut along portions of the semiconductor cell peripheries (155) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152) to define a shared JFET region (29d) between the first semiconductor device cell (151) and the second semiconductor device cell (152).

[0102] 10. The system (160) of any preceding paragraph, wherein the channel regions (28) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152) are separated by the JFET regions (29) of each of the first semiconductor device cell (151) and the second semiconductor device cell (152).

[0103] 10. The system (160) of any preceding paragraph, wherein the third width (W3) of the shared JFET region (29d) is greater than a fourth width (W4) between the channel regions (28) of the first semiconductor device cell (151) and the second semiconductor device cell (152) in at least one of the first corner region (29a) and the second corner region (29b).

[0104] 10. The system (160) of any preceding paragraph, wherein the third width W3 is equal to the sum of the first width (W1) of the first semiconductor device 151 and the first width (W1) of the second semiconductor device cell 152, respectively.

[0105] 10. The system (160) of any preceding paragraph, wherein the fourth width (W4) is equal to the sum of the second width (W2) of the first semiconductor device cell (151) and the second width (W2) of the second semiconductor device cell (152), respectively.

[0106] 10. The system (160) of any preceding paragraph, wherein the first width (W1) is in the range of 12 microns and 36 microns.

[0107] 10. The system (160) of any preceding paragraph, wherein the second width (W2) is in the range of 0.14 microns and 2.8 microns.

[0108] 10. The system (160) of any preceding claim, wherein the first width (W1) is at least 20% wider than the second width (W2).

[0109] 10. The system (160) of any preceding claim, wherein the semiconductor device cell (150) defines a MOSFET device (10). [Explanation of symbols]

[0110] 2. Semiconductor layer 4. First Side 6 Second Side 10 MOSFET devices 12 Drain Contact 14 substrate layers 16 Drift Region 18 well area 20 Source Region 22 Source Contact 24 dielectric layer 26 gate electrode 28 Channel Region 28a Third corner area, corner 28b Fourth corner area, corner 29 JFET area 29a First corner region, first end, first corner 29b Second corner region, second end, second corner 29c JFET intermediate region, JFET segment 29d Shared JFET area 30 Source region resistance 32 Channel resistance, inversion channel resistance 34 Accumulation layer resistance 36 JFET area resistance, JFET resistance 38 Drift region resistance, drift resistance 40 Stripe Ladder Device Layout 41 Stripe MOSFET device structure 42 Source contact area 43 Channel Length 44 Main body contact area, main body area 45 distance 46 Source / body contact 47 width 48 Substrate layer resistor 49 width 50 device cells 51 segment length 52 segment length 53 Device Area 54 JFET area 55 width 60 distance 64 Arrow 65 Central area 66 Diagonal Arrow 69 angle 69a First corner area, first corner 69b Second corner area, second corner 70 graphs 72 First Curve 74 Second Curve 128 Channel region, periphery 150 semiconductor device cells 151 first semiconductor device cell, first adjacent cell 152 second semiconductor device cell, second adjacent cell 153 semiconductor device cell, third adjacent cell 154 Semiconductor Device Cells 155 Fourth adjacent cell, semiconductor cell periphery 160 Systems, Cellular Semiconductor Devices 170 Systems L1 Longitudinal axis W1 First width W2 Second width W3 Third width W4 Fourth width

Claims

1. a semiconductor device cell (150) including a semiconductor layer (2) including a drift region (16) having a first conductivity type; a well region (18) having a second conductivity type disposed adjacent to the drift region (16); a source region (20) of the first conductivity type disposed adjacent to and surrounded by the well region (18); a channel region (28) having the second conductivity type disposed adjacent to and around the well region (18); a JFET region (29) abutting the periphery of the channel region (28) and defining a semiconductor cell periphery (155), the JFET region (29) having at least one first corner region (29a) and a second corner region (29b) separated by a JFET middle region (29c); A system (160) comprising: a first width (W1) of the JFET intermediate region (29c) extending from an end of the JFET intermediate region (29c) abutting the periphery of the channel region (28) to the semiconductor cell periphery (155) is larger than a second width (W2) of the JFET region (29) extending from an end of at least one of the first corner region (29a) and the second corner region (29b) abutting the periphery of the channel region (28) to the semiconductor cell periphery (155); A system (160) wherein the boundary between the well region (18) and the channel region (28) is square or rectangular in plan view.

2. The system (160) of claim 1, wherein the first corner region (29a) and the second corner region (29b) each form a right angle.

3. The system (160) of claim 1 or 2, wherein the channel region (28) defines a third corner region (28a) adjacent the first corner region (29a).

4. The system (160) of claim 3, wherein the channel region (28) defines a fourth corner region (28b) adjacent the second corner region (29b).

5. The system (160) of claim 1 or 2, wherein the JFET region (29) extends from the channel region (28) to the semiconductor cell periphery (155).

6. 3. The system (160) of claim 1 or 2, wherein the first width (W1) is in the range of 6 microns and 18 microns.

7. The system (160) of claim 1 or 2, wherein the second width (W2) is in the range of 0.07 microns and 1.4 microns.

8. The system (160) of claim 1 or 2, wherein the first width (W1) is at least 20% wider than the second width (W2).

9. The system (160) of claim 1 or 2, wherein the semiconductor device cell (150) is a MOSFET device (10).

10. The semiconductor device further comprises a set of semiconductor device cells (151, 152, 153, 154) at least partially disposed in the semiconductor layer (2) having the first conductivity type, each device cell having: a semiconductor layer (2) including a drift region (16) having a first conductivity type; a well region (18) having a second conductivity type disposed adjacent to the drift region (16); a source region (20) of the first conductivity type disposed adjacent to and surrounded by the well region (18); a channel region (28) having the second conductivity type disposed adjacent to and around the well region (18); a JFET region (29) abutting the periphery of the channel region (28) and defining a semiconductor cell periphery (155), the JFET region having at least a first corner region (29a) and a second corner region (29b) separated by a JFET middle region (29c); Equipped with 3. The system of claim 1, wherein a first width (W1) of the JFET intermediate region (29c) extending from an end of the JFET intermediate region (29c) abutting the periphery of the channel region (28) to the semiconductor cell periphery (155) is greater than a second width (W2) of the JFET region (29) extending from an end of at least one of the first corner region (29a) and the second corner region (29b) abutting the periphery of the channel region (28) to the semiconductor cell periphery (155).

11. The system (160) of claim 10, wherein each semiconductor device cell (150) comprises a respective semiconductor cell periphery (155) that is aligned with a respective semiconductor cell periphery (155) of an adjacent semiconductor device cell (150).

12. 11. The system (160) of claim 10, wherein the JFET intermediate regions (29c) of each of the first and second semiconductor device cells (151) and (152) abut along portions of the respective semiconductor cell peripheries (155) of the first and second semiconductor device cells (151) and (152) to define a shared JFET region (29d) between the first and second semiconductor device cells (151) and (152).

13. 13. The system (160) of claim 12, wherein the respective channel regions (28) of the first semiconductor device cell (151) and the second semiconductor device cell (152) are separated by the respective JFET regions (29) of the first semiconductor device cell (151) and the second semiconductor device cell (152).

14. 13. The system (160) of claim 12, wherein a third width (W3) of the shared JFET region (29d) is greater than a fourth width (W4) between the respective channel regions (28) of the first semiconductor device cell (151) and the second semiconductor device cell (152) in at least one of the first corner region (29a) and the second corner region (29b).

15. 15. The system (160) of claim 14, wherein the third width (W3) is equal to the sum of the first width (W1) of the first semiconductor device cell (151) and the first width (W1) of the second semiconductor device cell (152).

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