Vertical conduction silicon carbide MOSFET device with improved gate bias structure and its fabrication method

Abstract

To provide a vertical-conduction silicon carbide MOSFET device having an improved gate bias application structure and a manufacturing method thereof.SOLUTION: In a vertical-conduction MOSFET device 50, a die 52 is formed within a body 55 of silicon carbide having a first surface 55A and a second surface and a peripheral zone. An insulated gate region 70 extends on the first surface and includes a gate conductive region 72. An annular connection region comprising a conductive material is formed within a surface edge structure extending on the first surface 55A in the peripheral zone. The gate conductive region 72 and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a vertical conduction silicon carbide MOSFET device with an improved gate bias structure and a method for fabricating the same. [Background technology]

[0002] As is known, semiconductor materials with wide bandgaps, e.g., higher than 1.1 eV, low on-resistances, high thermal conductivities, high operating frequencies, and high saturation velocities of charge carriers, make it possible to obtain electronic devices, e.g., diodes and transistors, with better performance than those formed on silicon substrates. This applies in particular to power applications in devices operating at voltages between 600 V and 1,300 V under certain operating conditions, e.g., high temperatures.

[0003] In particular, MOSFET electronic devices are formed starting from a wafer of silicon carbide of one of the polytypes, e.g., 3C-SiC, 4H-SiC, 6H-SiC, etc., that provide the advantages described above. In particular, the following description refers to the 4H-SiC polytype, but the description therein applies without limitation to the other polytypes.

[0004] For example, Figure 1 illustrates a cross-sectional view of a known vertical conduction MOSFET device 1 in a Cartesian coordinate system having a first axis X, a second axis Y, and a third axis Z. MOSFET device 1 is formed from a plurality of elementary cells, only two of which are shown here, identical in structure, adjacently arranged within the same die 2, and connected in parallel. Accordingly, they share a source terminal S, a drain terminal D, and a gate terminal G. Die 2 has a silicon carbide substrate 5 having a first surface 5A and a second surface 5B. Substrate 5 contains a drain region 7, a plurality of body regions 10, and a plurality of source regions 15.

[0005] The drain region 7 is here N-type and extends between the first surface 5A and the second surface 5B of the substrate 5. A drain contact region 9 of a conductive material such as metal or silicide makes direct electrical contact with the drain region 7, extends on the second surface 5B of the substrate 5, and forms the drain terminal D of the MOSFET device 1. The body regions 10 are P-type and extend within the substrate 5 at a distance from the first surface 5A. A surface portion 24 of the drain region 7 is provided between two adjacent body regions 10. The body regions 10 further extend along a second axis Y and here have the shape of a strip in plan view.

[0006] The source regions 15 each extend from the first surface 5A of the substrate 5 into a respective body region 10 and are N-type. Each source region 15 has a width along a first axis Z that is smaller than the width of the respective body region 10 and a depth along a third axis Z that is smaller than the depth of the respective body region 10. Each source region 15, together with an adjacent surface portion 24, laterally defines a channel portion 25 of the respective body region 10.

[0007] The MOSFET device 1 further includes a plurality of insulated gate regions 20, each formed by a gate insulating layer 21 in contact with the first surface 5A of the substrate 5, a gate conductive region 22, typically made of polycrystalline silicon, immediately above the gate insulating layer 21, and an insulating layer 23 that, together with the gate insulating layer 21, surrounds and encapsulates the gate conductive region 22. The gate insulating layer 21 of each insulated gate region 20 extends over a respective surface portion 24 of the drain region 7, over two channel regions 25 adjacent to the respective surface portion 24, and partially over two source regions 15 adjacent to the respective channel regions 25. The gate conductive regions 22 here have the shape of strips extending parallel to the second axis Y (see also FIG. 2), are electrically connected in parallel with each other, and are connected to the gate terminal G of the MOSFET device 1, as will be described below.

[0008] The MOSFET device 1 further includes a plurality of body contact regions 30. The body contact regions 50 are P + 1 , and each of them contacts a respective body contact region 10 and extends from the first surface 5A of the substrate 5 into a respective source region 15. In the illustrated example, each source region 15 contains more than one body contact region 30. The body contact regions 30 are offset from one another along the first axis X and are positioned at a distance from one another along the second axis Y, so that in the cross-sectional view of FIG. 1 they are visible only in the two source regions 15 on the right and left, but not in the central source region 15. The body contact regions 30 and the source regions 15 are in direct electrical contact with a source metallization region 33, which may be made of, for example, a metal.

[0009] 2, the source metallization region 33 generally occupies most of the first surface 5A of the substrate 5 and is divided into two adjacent portions (labeled 33A and 33B in FIG. 2) spaced a distance apart. These two portions 33A and 33B of the source metallization region 22 also form pads for external connection of the MOSFET device 1 and form the source terminal S of the MOSFET device 1.

[0010] 2, two auxiliary source pads 34 and one gate pad 35 also extend over the first surface 5A of the substrate 5. The auxiliary source pads 34, the gate pad 35, and the source metallization region 33 are formed in the same layer and therefore have the same large thickness to provide the desired current capability for the source terminal S.

[0011] Gate pad 35 is connected to gate conductive region 22 (represented by a dotted line in FIG. 2) through a metal connection and a resistive network. Specifically, the metal connection is formed in the same metal layer as pads 33, 34, and 35 and includes gate metal ring 38A and gate metal strips or "fingers" 38B.

[0012] In the embodiment shown in FIG. 2, gate pad 35 is located near one side of die 2 at its midpoint, gate metal fingers 38B extend from gate pad 35 to the opposite side of die 2, and gate metal ring 38A extends around the periphery of die 2 as an extension of gate pad 35 and in electrical contact with die 2.

[0013] In particular, in the plan view of FIG. 2, the die 2 has a rectangular shape having a first side 2A, a second side 2B opposite the first side 2A, a third side 2C, and a fourth side 2D opposite the third side 2C, the third and fourth sides 2C, 2D extending parallel to a first axis X, and the first and second sides 2A, 2B extending parallel to a second axis Y.

[0014] In this geometry, the gate pad 35 is located near the first side 2A, the gate metal fingers 38B extend parallel to the first axis X from the gate pad 35 to the portion of the gate metal ring 38A adjacent the second side 2B, and the gate conductive region 22 extends parallel to the second axis Y.

[0015] The resistive network includes first and second contact portions 36A, 38B connected to gate conductive region 22 and metal contact portions 38B, 38A, as shown in Figures 3 and 4 and described below, where gate insulating layer 21 is not shown for simplicity. In particular, Figure 3 shows a peripheral edge portion (labeled 37) of die 2 adjacent, for example, fourth side 2D.

[0016] An insulating oxide ring 40A, for example made of silicon oxide, extends over the first surface 5A of the substrate 5 and is covered by a passivation layer 42 connected to the insulating layer 23.

[0017] A demarcation region 41, having an annular shape and having a conductivity type opposite that of the substrate 5 (here P type), extends into the substrate 5 generally below the inner edge of the insulating oxide ring 40A. The demarcation region 41 surrounds an active area 44 in the substrate 5 (the limits of which are represented diagrammatically by dotted lines A) and contains the conductive regions of the MOSFET device 1, including the source region 25 and the body region 10 (not visible in FIG. 3). An implanted region 43 (here N) forming a channel stopper is also included. + 2A and 2B, extending from the boundary region 41 to the sides 5A-5D of the die 2 and underneath the insulating oxide annular portion 40A near the outer edge of the insulating oxide annular portion 40A at a distance D from the boundary region 41.

[0018] A polysilicon first connection portion 36A extends along and over the inner edge of the insulating oxide ring portion 40A. The first connection portion 36A is now in direct electrical contact with the gate conductive region 22, which is provided in the same layer, without interruption. Figure 3 also shows a gate metal ring 38A, which extends above the insulating oxide ring portion 40A, crossing the passivation layer 42 and now in direct electrical contact with the first connection portion 36A.

[0019] 4 shows the connection between gate metal finger 38B and gate conductive region 22. Specifically, insulating oxide finger portion 40B, which is formed from the same layer as insulating oxide ring portion 40A, extends over body 5 parallel to first direction X until it contacts the sides of insulating oxide ring portion 40A adjacent first and second sides 2A, 2B of die 2. Insulating oxide finger portion 40B and insulating oxide ring portion 40A form end insulating region 40.

[0020] The second connection portion 36B extends over the insulating oxide finger portion 40B and has an elongated shape in the first direction X. However, the second connection portion 36B has a width (parallel to the second direction Y) that is greater than the width of the insulating oxide finger portion 40B, and therefore also extends over the side of the insulating oxide finger portion 40B, where it is directly connected to the gate conductive region 22.

[0021] The insulating layer 23 covers the second connection portion 36B and has an opening 46 that extends parallel to the first direction X over substantially the entire length of the second connection portion 36B. The gate metal finger 38B extends through the opening 46 and is now in direct electrical contact with the second connection portion 36B.

[0022] The insulating oxide finger portion 40B extends over a P-type insulating finger region 45 formed in the body 5 and extending parallel to the first direction X between two opposite sides of the demarcation region 41 with which it is in direct contact. The insulating oxide finger portion 40B overlies an inactive area 47 (also referred to as a central end area) that separates the two active areas 44.

[0023] In the known device 1, the gate metal fingers 38B and gate metal ring 38A have the purpose of reducing the voltage drop between the gate pad 35 and the gate conductive region 22 due to the inherent resistance of the resistive network formed by the contacts 36A, 36B. However, the presence of the metal contacts 38A, 36B is a disadvantage in some applications.

[0024] In effect, the gate metal fingers 38B split the source metallization into at least two portions 33A, 33B (or more, due to dimensions, in devices with several gate metal fingers 38B). This limits the use of the MOSFET device 1 in power modules that have sintered or soldered clips on the die 2 or require specific costly and / or cumbersome solutions to contact the source metallization region 33.

[0025] Furthermore, the presence of gate metal ring 38A at peripheral edge portion 37 of die 2 is important during reliability evaluation of MOSFET device 1. In particular, innovative reliability tests verifying switching behavior in high humidity environments have shown that gate metal ring 38A is a weak point of the device.

[0026] Metal contact portions 38A, 38B present a significant nuisance both due to their size and the minimum safety space that must be provided between portions 33A, 33B of source metallization region 33 and gate pad 35. For example, in the illustrated configuration, gate metal ring 38A is designed to maintain distance D in FIG. 3 between channel stop region 43 and demarcation region 41. Furthermore, as shown in FIG. 4, distance D' between active areas 44 (the area extending from central end region 47 and gate metal fingers 38B) cannot be used for conduction of MOSFET device 1 and represents wasted area. Summary of the Invention [Problem to be solved by the invention]

[0027] SUMMARY OF THE INVENTION It is an object of the present invention to overcome the drawbacks of the prior art. [Means for solving the problem]

[0028] According to the present invention, there is provided a vertical conduction MOSFET device and method for fabricating the same, as defined in the claims.

[0029] For a better understanding of the invention, some embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0030] [Figure 1] 3 is a cross-sectional view of a portion of the known MOSFET device taken along section line II in FIG. 2; [Figure 2] 2 is a plan view of the MOSFET device of FIG. 1; [Figure 3] 3 is a cross-sectional view of the MOSFET device of FIG. 1 taken along section line III-III in FIG. 2; [Figure 4] 2Note is a cross-sectional view of the MOSFET device of FIG. 1 taken along section line IV-IV. [Figure 5] 1 is a plan view of a MOSFET device according to one embodiment of the present invention; [Figure 6] 6 is a cross-sectional view of the MOSFET device of FIG. 5 taken along section line VI-VI. [Figure 7] 6 is a cross-sectional view of the MOSFET device of FIG. 5 taken along section line VI-VI according to another embodiment of the present invention. [Figure 8] 8 is a cross-sectional view of the MOSFET device of FIG. 5 taken along section line VIII-VIII. [Figure 9] 9 is a cross-sectional view of the MOSFET device of FIG. 5 taken along section line IX-IX. [Figure 10] FIG. 5 shows a possible layout of the gate conductive region of the MOSFET device. [Figure 11] 6 is another possible layout of the gate conductive region of the MOSFET device of FIG. 5; [Figure 12] 7A and 7B are cross-sectional views (taken at the same cross section as FIG. 6) of a semiconductor wafer at successive steps in the fabrication of the MOSFET device of FIG. 6 according to one embodiment of the present invention. [Figure 13] 7A-7C are cross-sectional views (taken at the same cross section as FIG. 6) of a semiconductor wafer at successive fabrication steps of the MOSFET device of FIG. 6 according to different embodiments of the present invention. [Figure 14] 8A and 8B are cross-sectional views (taken at the same cross section as FIG. 7) of a semiconductor wafer at successive steps in the fabrication of the MOSFET device of FIG. 7 according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0031] MOSFET device 50 is formed in die 52 having a generally parallelepiped shape with four lateral surfaces, or sides, 52A-52D, and a top surface 52E. In particular, in the plan view of Figure 5, die 52 has a first side 52A, a second side 52B opposite first side 52A, a third side 52C, and a fourth side 52D opposite third side 52C, with third and fourth sides 52C, 52D parallel to a first axis X of a Cartesian coordinate system XYZ, and first and second sides 52A, 52B parallel to a second axis Y of the Cartesian coordinate system XYZ.

[0032] MOSFET device 50 comprises a number of adjacent, parallel-connected elementary cells (two cells are shown in FIGS. 6 and 7), which therefore share a source terminal S, a drain terminal D, and a gate terminal G.

[0033] 6 and 7, die 52 includes a silicon carbide substrate 55 having a first surface 55 A and a second surface 55 B. Substrate 55 contains a drain region 57, a plurality of body regions 60, and a plurality of source regions 65, which are similar to the similarly named regions 7, 10, and 15, respectively, of FIG.

[0034] A drain contact region 59 of a conductive material such as metal and / or silicide extends over the second surface 55B of the substrate 55 in direct electrical contact with the drain region 57 and forms the drain terminal D of the MOSFET device 50.

[0035] A surface portion 64 of the drain region 57 is defined between two adjacent body regions 60. Each source region 65, together with the adjacent surface portion 64, laterally defines a channel portion 75 of the respective body region 60.

[0036] MOSFET device 50 further includes a plurality of insulated gate regions 70. Each insulated gate region 70 is formed by a gate insulating region 71 in contact with first surface 55A of substrate 55, a gate conductive region 72 directly above gate insulating region 71, and an upper insulating layer 73 surrounding and encapsulating gate insulating region 71 and gate conductive region 72.

[0037] Each gate conductive region 72 is formed here by a gate semiconductor portion 76, typically made of polycrystalline silicon, and a gate metal portion 77 immediately above and in direct electrical contact with the gate semiconductor portion 76. The gate metal portion 77 is typically a metal suicide, such as a suicide of tungsten, titanium, nickel, cobalt, or platinum.

[0038] In the embodiment of FIG. 6, the gate metal portion 77 has the same width (in the direction of the first axis X) as the gate semiconductor portion 76, while in the embodiment of FIG. 7, the gate metal region (labeled 77′) has a smaller width than the gate semiconductor portion 76.

[0039] The gate insulating region 71 of each insulated gate region 70 extends over a respective surface portion 64 of the drain region 57, over two channel regions 75 adjacent to each surface portion 64, and partially over two source regions 65 adjacent to each channel region 75.

[0040] The gate conductive regions 72 are electrically connected in parallel with one another and to the gate terminal G of the MOSFET device 50 as will be described below.

[0041] MOSFET device 50 further includes a plurality of body contact regions 80 (hereinafter also referred to as P-well regions 80), which are similar to body contact regions 30 of FIG.

[0042] The P-well region 80 and the source region 65 are in direct electrical contact with a source metallization region 83, which may be, for example, a metal and / or metal silicide.

[0043] As can be seen from FIG. 5, source metallization region 83 is now formed by a single portion occupying most of top surface 52E of die 50 and also forming a pad for external connection of MOSFET device 50.

[0044] Furthermore, two auxiliary source pads 84 and one gate pad 85 extend on the first surface 55A of the substrate 55. The auxiliary source pad 84, the gate pad 85, and the single source metallization region 83 are formed in the same layer and therefore have the same high thickness, for example, between 1 μm and 10 μm, to provide the desired current capability of the source terminal S. It is noted that, if desired, the source metallization region 83 can be formed by several separate portions rather than a single portion. In any case, the distance between them is not critical in the MOSFET device 50, and there are neither gate metal fingers (38B in FIG. 1 ) nor gate metal rings (38A in FIG. 1 ).

[0045] Gate pad 85 (here located near first side 52A of die 52 at an intermediate location) is connected to gate conductive region 72 (represented by a dotted line in FIG. 5 ) through annular connection region 86, which extends near the periphery of die 52 and has a widened portion forming a contact area 86A located below gate pad 85. Annular connection region 86 is monolithic with gate conductive region 72, formed by the same layer and obtained by the same processing steps that form gate conductive region 72, as will be described in more detail below.

[0046] Annular connection region 86 can also be seen in cross section in Figure 8, where, for simplicity, gate insulation region 71 is not shown. In particular, Figure 8 shows a peripheral edge portion (labeled 87) of die 52 adjacent second side 52B, for example. Edge insulation region 90, here oxide, extends over first surface 55A of substrate 55.

[0047] Edge insulation region 90 here includes oxide layer 96 and an overlying passivation layer 92. Near third and fourth sides 52C, 52D of die 52, passivation layer 92 continues with upper insulation layer 73 of insulated gate region 70, which, in the cross section of FIG. 8, is interrupted by a plurality of openings into which source metallization 83 extends.

[0048] A demarcation region 91 of a conductivity type opposite that of the substrate 55, here P-type, and having an annular shape, extends within the substrate 55 beneath the edge insulating region 90 near but at a distance from the inner edge of the edge insulating region 90. The demarcation region 91 surrounds an active area 94 (the limits of which are shown schematically by dotted line B) in the substrate 55 that contains the conductive region of the MOSFET device 50, including the body region 60 and the source region 65. + A channel stopper region 93, which is annular in shape, extends under the edge insulating region 90 near the sides 52A-52D of the die 52 at a distance D1 from the demarcation region 91 to balance the potential in the edge areas.

[0049] The annular connection region 86 extends in an annular manner only along the inner edge of the edge insulating region 90 and does not have a portion extending between the active areas. As previously mentioned, the annular connection region 86 is formed monolithically with the gate conductive region 72 as a two-layer stack. In particular, the annular connection region 86 includes a semiconductor connection portion 88 and a metal connection portion 89 that is directly overlying and in direct electrical contact with the semiconductor connection portion 88.

[0050] Furthermore, the material of the semiconductor connection region 88 is the same as that of the gate semiconductor portion 76 (typically polycrystalline silicon), and the material of the metal connection portion 89 is the same as that of the gate metal portion 77 (typically a metal silicide, e.g., a silicide of tungsten, titanium, nickel, cobalt, or platinum). The stack of layers forming the gate semiconductor portion 76 and the annular connection region 86 forms a gate bias layer 95.

[0051] As can be seen from Figure 8, annular connection region 86 extends only a minimal distance over edge insulating region 90 and has a very small width, for example, between 10 μm and 50 μm. Furthermore, demarcation region 91 also has a small width (in the first direction in the cross section of Figure 8), for example, between 20 μm and 50 μm. In this manner, the width of peripheral edge portion 87 is reduced, and therefore, for the same dimensions of die 2-52, the dimensions of active area 94 can be increased.

[0052] Furthermore, as can be seen from FIG. 9 (which is similar to and comparable to FIG. 4 , which depicts known MOSFET device 1), in the central region of MOSFET device 50, no non-active edge area extends due to the absence of gate metallization. As a result, in MOSFET device 50, passivation layer 92 / 73 completely covers metal connection portion 89 of annular connection region 86 at the top, and there are no openings or conductive areas through passivation layer 92 / 73, nor are there any surface metal portions that would provide direct electrical contact between the top surface of annular connection region 86 and gate metallization 85. Biasing of annular connection region 86 actually occurs only in that portion adjacent to contact area 86A. Therefore, MOSFET device 50 has a large active area 94, thereby effectively utilizing the area of ​​die 52.

[0053] Figures 10 and 11 show two possible layouts of the gate bias layer 95. In particular, Figure 10 shows a layout of the gate bias layer 95 corresponding to that shown in Figure 5, with the contact areas 86A located on the periphery.

[0054] As will be understood, the annular connection region 86 has first and second branches 86B, 86C that extend adjacent to and along two opposite sides of the body 52 (and, in the embodiment shown in FIG. 10, along the third and fourth sides 52C, 52D of the die 52), and the gate conductive region 72 extends continuously between the first and second branches 86B, 86C of the annular connection region 86.

[0055] 11 shows a different layout of the gate bias layer, here designated by the reference numeral 95'. Again, the gate conductive region 72 extends continuously between the first and second branches 86B, 86C of the annular connection region 86. The centrally located gate conductive region 72 has a widened central portion that is common to several different gate conductive regions 72 and forms a contact area 86A' over which the gate pad 85 extends. In this case, biasing of the annular connection region 86 occurs solely through the gate conductive region 72 connecting the annular connection region 86 to the contact area 86A'.

[0056] Generally, in the case of the MOSFET device 50, the location of the gate pad 85, and therefore the locations of the contact areas 86A, 86A', can be chosen with great flexibility according to the application and possible customer wishes.

[0057] MOSFET devices 52 of Figures 5, 6, 8-11 can be fabricated by depositing / forming a silicide layer before or after defining gate semiconductor portion 76 of gate conductive region 72. For example, Figure 12A shows a silicon carbide (e.g., 3C-SiC, 4H-SiC, 6H-SiC type) wafer 100 intended to form die 52 of Figure 6 after dicing. In particular, in Figure 12A, source regions 65, body regions 60, and P-well regions 80 have already been formed in substrate 55, as well as various edge regions (including boundary definition region 91 and channel stop region 93 of Figure 8) that are not shown here.

[0058] A gate insulating layer 101, a gate conductive layer 102, and a silicide layer 103 have already been deposited, in that order, on the first surface 55A of the substrate 55. The gate insulating layer 101 is, for example, silicon oxide and is intended to form the gate insulating region 71. The gate conductive layer 102 is typically polycrystalline silicon and is designed to form the gate semiconductor portion 76 and the semiconductor contact portion 88 of the gate conductive region 72. The silicide layer 103 is, for example, tungsten silicide (WSi2) and is intended to form the gate metal portion 77 and the metal contact portion 89 (FIGS. 6 and 8).

[0059] After a stabilization annealing treatment, for example at a temperature between 700° C. and 1000° C., the silicide layer 103, the gate conductive layer 102, and the gate insulating layer 101 are defined in a known manner by a photolithography process using the same etching mask (FIG. 12B), thereby forming the gate conductive region 72 (FIGS. 6 and 12B), the annular connection region (FIG. 8), and the gate insulating region 7. Furthermore, the gate metal portion 77 and the gate semiconductor portion 76 are self-aligned with each other, as are the metal connection portion 89 and the semiconductor connection portion 88.

[0060] The steps of forming the upper insulating layer 73, the passivation layer 92, and the metallizations 83-85 then follow, with no openings provided during the formation of the passivation layer 92 for direct contact to the annular connection region 86.

[0061] 13A-13C illustrate steps in different embodiments of a method for fabricating MOSFET device 50 of FIGS. 5, 6, and 8-11. In particular, FIG. 13A illustrates a portion of wafer 100. At the step of FIG. 13A, source region 65, body region 60, P-well region 80, and various edge regions have already been formed in substrate 55.

[0062] Furthermore, a gate insulating layer 101 has already been deposited on the first surface 55A of the substrate 55, and the gate semiconductor portion 76 and semiconductor contact portion 88 of the gate conductive region 72 have already been formed, for example, by depositing and photolithographically defining a polycrystalline silicon layer. A sacrificial layer 105, for example made of silicon oxide, has been deposited on the gate semiconductor portion 76 and on the gate insulating layer 101 where exposed.

[0063] Next (FIG. 13B), the sacrificial layer 105 is etched to form spacers 106 (spacer etching). For this, the etching is unmasked, dry and directional (plasma etching). Due to the anisotropy of the etching, horizontal parts of the sacrificial layer 105 are removed and spacers 106 are formed on the vertical walls of the gate semiconductor portion 76. In this step, parts of the gate insulating layer 101 not covered by the gate semiconductor portion 76 and by the spacers 106 on the source regions 65 are removed to form the gate insulating regions 71. Similar spacers (not shown) are formed on the lateral surfaces of the semiconductor contact portions 88 (FIG. 8).

[0064] Then (FIG. 13C), a metal layer (e.g., titanium or nickel) is deposited by sputtering and reacts with the polycrystalline silicon (in a manner not shown) of the gate semiconductor portion 76 and of the semiconductor connection portion 88 (FIG. 8). For this purpose, a first annealing is carried out at a low temperature between 600° C. and 1000° C. Then, the unreacted metal material (e.g., on the spacers 106) is removed, and a first annealing is carried out at a higher temperature, for example, between 800° C. and 1100° C. Thus, the gate metal portion 77 of the gate conductive region 72 and the metal connection portion 89 of the annular connection region 86 (FIG. 8) are formed.

[0065] As a result, again, gate metal portions 77 are self-aligned with their respective gate semiconductor portions 76, and metal contact portions 89 are self-aligned with semiconductor contact portions 88.

[0066] During this step, a thin silicide layer may form over exposed portions of substrate 55, particularly over source regions 65 and P-well regions 80, which may be removed by appropriate etching or left in place depending on the particular process. The process proceeds with the usual steps of forming top insulating layer 73, passivation layer 92, and metallization 83-85.

[0067] Figures 14A-14B illustrate steps in one embodiment of a process for fabricating MOSFET device 50 of Figures 5, 7, and 8-11. In particular, Figure 14A illustrates wafer 100' after performing the fabrication steps previously described with reference to Figure 13A.

[0068] In particular, in wafer 100', source regions 65, body regions 60, P-well regions 80, and various edge regions have already been formed in substrate 55. A gate insulating layer 101 has already been deposited on a first surface 55A of substrate 55. Gate semiconductor portions 76 and semiconductor contact portions 88 (not visible in FIG. 14A) of gate conductive regions 72 have already been formed, for example, by depositing and photolithographically defining a polysilicon layer. A sacrificial layer 115, for example, made of silicon oxide, has been deposited on gate semiconductor portions 76 and on gate insulating layer 101 where exposed.

[0069] Next (FIG. 14B), a gate contact mask (not shown) is formed on the sacrificial layer 115, and the sacrificial layer 115 is selectively removed on the gate semiconductor portion 76 and the semiconductor connection portion 88 (not visible in FIG. 14B), thus forming masking portions 115′ that cover the side and longitudinal ends of the gate semiconductor portion 76 and the semiconductor connection portion 88 and the gate insulating layer 101 in exposed areas.

[0070] A metal layer (e.g., titanium, cobalt, or platinum) is then deposited by sputtering and reacted with the polycrystalline silicon of the gate semiconductor portion 76 and (in a manner not shown) the semiconductor connection portion 88 (FIG. 8). To this end, a first annealing is performed at a low temperature, for example, between 600°C and 1000°C. The unreacted metal material (on the masking portion 115') is then removed, and a second annealing is performed at a higher temperature, for example, between 800°C and 1100°C. Thus, the gate metal portion 77 of the gate conductive region 72 and the metal connection portion 89 of the annular connection region 86 are formed (FIG. 8).

[0071] The remaining unreacted portions of the sacrificial layer 105 are then removed and further steps are performed to form the upper insulating layer 73, the passivation layer 92 and the metallizations 83-85, respectively.

[0072] The MOSFET device 50 so formed has various advantages. In particular, it has a simplified structure and an increased active area due to the reduced size of the peripheral edge area and the elimination of the inner edge area. The MOSFET device 50 has an improved gate resistance R g MOSFET device 50 has excellent ruggedness and can be used in high current and / or high voltage applications. For example, it can operate at voltages up to 10 kV or currents up to 500 A.

[0073] MOSFET device 50 has improved reliability because its structure is simplified and the polysilicon of gate semiconductor portion 76 does not require special doping. Therefore, there is no precipitation of dopants (typically phosphorus) from gate conductive region 72 into gate insulating region 71. Thus, gate insulating region 71, which is typically made of oxide, provides high reliability.

[0074] In MOSFET devices using silicon carbide substrates, because all junctions, implant regions, and enriched contact regions are activated before forming the respective layers and regions on the surface of substrate 55, the fabrication process has a low thermal budget after forming silicide portions 77, 89, and as a result, these portions have excellent thermal stability.

[0075] Furthermore, the external contact structure (clip) that contacts the source metallization 83 during assembly and packaging of the MOSFET device 50 can be simplified, reducing costs and improving current conduction reliability.

[0076] Finally, it will be appreciated that various variations and modifications can be made to the MOSFET device and method of fabrication described and illustrated herein without departing from the spirit and scope of the invention as defined in the appended claims. For example, in the process embodiment of Figures 12A-12B, the silicide layer 103 can be obtained by reacting a metal layer deposited on the gate conductive layer 102.

Claims

1. In a vertical conduction MOSFET device (50), a silicon carbide body (55) having first and second surfaces (52A, 52B) and a peripheral zone (87); a first current-conducting region (57) of a first conductivity type extending from the second surface (55B) into the body (55) and having a surface portion (64) facing the first surface (55A); a body region (60) of a second conductivity type extending from the first surface (55A) into the body; the body (55) containing a second current-conducting region (65) of the first conductivity type extending from the first surface (55A) of the body to an interior of the body region (60), the second current-conducting region (65) together with the surface portion (64) defining a channel portion (75) within the body region (60); an insulated gate region (70) extending over the first surface (55A) of the body (55) and overlying the channel portion (75), the insulated gate region (70) having a gate conductive region (72); a surface edge structure (90) extending on the first face (55A) of the body (55) in the peripheral zone (87) of the body, the surface edge structure (90) having an annular connecting region (86) made of an electrically conductive material; the gate conductive region (72) and the annular connection region (86) are formed by a gate bias layer (95) including a silicon layer and a metal silicide layer on the silicon layer; the gate conductive region (72) has a gate semiconductor portion (76) formed by the silicon layer and a gate metal portion (77) formed by the metal silicide layer; the annular connection region (86) has a semiconductor connection portion (88) formed by the silicon layer and a metal connection portion (89) formed by the metal silicide layer; A vertical conduction MOSFET device, wherein the surface edge structure (90) has a passivation layer (92) completely covering the metal connection portion (89) of the annular connection region (86).

2. 2. The vertical conduction MOSFET device of claim 1, wherein said silicon layer is a polycrystalline layer.

3. 3. A vertical conduction MOSFET device according to claim 1 or 2, wherein said metal silicide layer is selected from silicides of tungsten, titanium, nickel, cobalt, or platinum.

4. 4. The vertical conduction MOSFET device of claim 1, wherein the gate semiconductor portion (76) has a first width, the gate metal portion (77) has a second width, the semiconductor connection portion (88) has a third width, and the metal connection portion (89) has a fourth width, the first width being equal to the second width and the third width being equal to the fourth width.

5. 4. The vertical conduction MOSFET device of claim 1, wherein the gate semiconductor portion (76) has a first width, the gate metal portion (77) has a second width, the semiconductor connection portion (88) has a third width, and the metal connection portion (89) has a fourth width, the first width being greater than the second width and the third width being greater than the fourth width.

6. The first surface (55A) of the body (55) has an area and a central portion; Furthermore, a conductive contact metal region (83) extending over the first surface (55A) of the body (55) in direct electrical contact with the second current conducting region (65), the conductive contact metal region (83) covering most of the area of ​​the first surface (55A) and having a single contact portion extending uninterrupted across the central portion of the first surface (55A); A vertical conduction MOSFET device according to any one of claims 1 to 5.

7. 7. The vertical conduction MOSFET device of claim 1, wherein the body (55) has two opposite lateral surfaces (52C, 52D), the annular connection region (86) has first and second branches extending near the opposite lateral surfaces (52C, 52D) of the body (55), and the gate conductive region (72) extends continuously between the first and second branches (86A, 86B) of the annular connection region (86).

8. 8. A method for fabricating a vertical conduction MOSFET device according to any one of claims 1 to 7, comprising the steps of: a silicon carbide body (55) having first and second faces (55A, 55B) and a peripheral zone (87), the body (55) containing a first current-conducting region (57) of a first conductivity type extending into the body from the second face and having a surface portion (64) facing the first face, forming a body region (60) of a second conductivity type extending into the body from the second face; forming a second current conducting region (65) of the first conductivity type in the body region extending from the first surface of the body, the second current conducting region (65) together with the surface portion defining a channel portion (75) within the body region; forming an insulated gate region (70) on the first surface of the body at a location above the channel portion, the insulated gate region (70) including a gate conductive region (72); and forming a surface edge structure (90) on the peripheral zone of the body, the surface edge structure (90) extending on the first surface of the body, the surface edge structure (90) including an annular connection region (86) made of a conductive material; and forming the gate conductive region (72) and the annular connection region (86) includes forming a gate bias layer (95) including a silicon layer and a metal silicide layer overlying the silicon layer.

9. forming a gate bias layer (95); depositing a silicon layer on the first surface (55A) of the body (55); forming a metal silicide layer (103) on the silicon layer; and photolithographically defining the silicon layer and the metal silicide layer to form the gate conductive region (72) and the annular connection region (86); 9. The method of claim 8, comprising:

10. forming a gate bias layer (95); depositing the silicon layer on the first surface of the body; photolithographically defining the silicon layer to form a gate semiconductor portion (76) and a semiconductor contact portion (88), each having a lateral surface; forming spacers (106) on said lateral surfaces; depositing a metal layer in direct contact with the gate semiconductor portion (76) and with the semiconductor contact portion (88); and reacting the metal layer to obtain a gate metal portion (77) in contact with the gate semiconductor portion (76) and a metal contact portion in contact with the semiconductor contact portion (88); 9. The method of claim 8, comprising:

11. forming a gate bias layer (95); depositing the silicon layer on the first surface of the body; photolithographically defining the silicon layer to form a gate semiconductor portion (76) and a semiconductor contact portion (88), each having lateral surfaces and longitudinal ends; forming a masking portion (115') covering the lateral surfaces and the longitudinal ends of the gate semiconductor portion (76) and the semiconductor connection portion (88); depositing a metal reaction layer in direct contact with the semiconductor contact portion (88) and with the gate semiconductor portion (76) at the locations exposed by the masking portion (115'); and reacting the metal reaction layer to obtain a gate metal portion (77) in contact with the gate semiconductor portion (76) and a metal contact portion in contact with the semiconductor contact portion (88); 9. The method of claim 8, comprising:

12. 12. The method of claim 11, wherein reacting the metallic reaction layer comprises performing annealing, and further comprising removing unreacted portions of the metallic reaction layer.

13. 13. The method of claim 11 or 12, wherein the silicon layer is polycrystalline silicon and the metal reaction layer is selected from tungsten, titanium, nickel, cobalt, and platinum.

14. the annular connection region (86) includes a semiconductor connection portion (88) formed by the silicon layer and a metal connection portion (89) formed by the metal silicide layer; The method of claim 8 or 9, further comprising depositing a passivation layer (92) completely covering the metal connection portion (89) of the annular connection region (86).

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