Back-contact solar cells, photovoltaic modules

Abstract

To provide a back-contact solar cell and a photovoltaic module that can improve the efficiency of the cell and at the same time improve the passivation performance.SOLUTION: A semiconductor substrate 1 has a front surface and a back surface arranged opposite to each other, the back surface of the semiconductor substrate 1 has an N-type conductive region 2 and a P-type conductive region 3, the N-type conductive region 2 has a plurality of first texture structures 21, the P-type conductive region 3 has a plurality of second texture structures 31, there is a height difference between the first texture structures 21 and the second texture structures 31, the height of the first texture structures 21 is lower than the height of the second texture structures 31, and the one-dimensional dimension of the bottom surface of the first texture structures 21 is larger than the one-dimensional dimension of the bottom surface of the second texture structures 31.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present application relates to the technical field of photovoltaic production, and in particular to back-contact solar cells and photovoltaic modules. [Background technology]

[0002] Back contact solar cells, also known as interdigitated back contact (IBC) solar cells, are a type of back contact solar cell. The greatest feature of IBC solar cells is that the electrodes in the light-emitting region and the base region are both on the back side of the cell, which reduces light shading and gives IBC cells higher short-circuit current and photoelectric conversion efficiency than solar cell sides that are shielded on the light-receiving surface.

[0003] IBCs have no front-side shielding, eliminating losses due to shielding of electrode grid lines and maximizing the utilization of incident photons. Accordingly, to prevent short circuits, p+ and n+ regions must be formed on the backside of the cell in a comb-like, interdigitated pattern, with gap regions formed between the p+ and n+ regions to separate them. Currently, the complex backside structure of IBC cells adversely affects the deposition and formation of film layers on the backside and above, negatively impacting the passivation performance of the cell.

[0004] How to improve the efficiency of IBC cells while simultaneously improving their passivation performance has become a technical challenge to be solved. Summary of the Invention [Problem to be solved by the invention]

[0005] The present application provides a back-contact solar cell, photovoltaic module that can improve the efficiency of the cell while also improving passivation performance, thereby improving the overall performance of the cell. [Means for solving the problem]

[0006] In a first aspect, an embodiment of the present application provides a back-contact solar cell, comprising: a semiconductor substrate having a front surface and a back surface disposed opposite to each other; the back surface of the semiconductor substrate having an N-type conductivity region and a P-type conductivity region, the N-type conductivity region having a plurality of first texture structures and the P-type conductivity region having a plurality of second texture structures, wherein there is a height difference between the first texture structures and the second texture structures, the height of the first texture structures is smaller than the height of the second texture structures, and a one-dimensional dimension of a bottom surface of the first texture structures is larger than a one-dimensional dimension of a bottom surface of the second texture structures; a first passivation layer located on the front surface of the semiconductor substrate; a second passivation layer located on the back surface of the semiconductor substrate; a first electrode penetrating the second passivation layer and forming an ohmic contact with the P-type conductivity region; and a second electrode penetrating the second passivation layer and forming an ohmic contact with the N-type conductivity region.

[0007] In a second aspect, the present embodiments provide a photovoltaic module comprising a cover plate, an encapsulating material layer, and a solar cell string, the solar cell string including a plurality of back contact solar cells according to the first aspect. [Effects of the Invention]

[0008] The technical solution provided in this application can achieve the following technical effects:

[0009] In the present application, texture structures with different dimensions are designed for the N-type conductive region and the P-type conductive region, wherein the N-type conductive region is doped with an N-type element and the P-type conductive region is doped with a P-type element, the N-type conductive region has a plurality of first texture structures, and the P-type conductive region has a plurality of second texture structures, there is a height difference between the first texture structures and the second texture structures, the height of the first texture structures is lower than the height of the second texture structures, and the one-dimensional dimension of the bottom surface of the first texture structures is larger than the one-dimensional dimension of the bottom surface of the second texture structures, and the height of the first texture structure in the N-type conductive region is lower and the one-dimensional dimension of the bottom surface of the first texture structure is larger, thereby reducing the recombination of minority carriers in the N-type conductive region, improving the passivation quality of the N-type conductive region, and further improving the interfacial recombination on the back surface of the cell, and the first texture structures can improve the contact properties between the slurry on the back surface of the cell and the semiconductor substrate, while simultaneously reducing parasitic absorption of sunlight in the N-type conductive region. The second textured structure in the P-type conductive region has a large height, and the bottom surface of the second textured structure has a small linear dimension, which allows more sunlight to be scattered and captured in the P-type conductive region, reducing light loss and improving the light absorption efficiency of the backside of the cell.The back-contact solar cell of the present invention can improve the efficiency of the cell while also improving passivation performance, thereby improving the overall performance of the cell.

[0010] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing the structure of a back contact solar cell provided in the present example. [Figure 2] FIG. 2 is an enlarged view of the structure of a portion A in FIG. [Figure 3] FIG. 3 is an enlarged view of the structure of part B in FIG. [Figure 4]FIG. 4 is a diagram showing the structure of an N-type conductive region having a first texture structure provided in an embodiment of the present invention. [Figure 5] FIG. 5 is a diagram showing the structure of a P-type conductive region having a second texture structure provided in an embodiment of the present invention. [Figure 6] FIG. 6 is a diagram showing the microstructure of the first texture structure provided in the present example. [Figure 7] FIG. 7 is a microscopic view of the second texture structure provided in the present example. [Figure 8] FIG. 8 shows a manufacturing flow chart for a back contact solar cell provided in the present example. [Figure 9] FIG. 9 is a diagram illustrating a photovoltaic module provided in another embodiment of the present application. [Explanation of symbols]

[0012] 1: Semiconductor substrate 2:N-type conductive region 21: First texture structure 3: P type conductive region 31: Second texture structure 4: Separation area 5: First passivation layer 6: Second passivation layer 7: 1st electrode 8:Second electrode 1000: Photovoltaic modules 100: Back contact solar cell 200: First cover plate 300: First sealing adhesive film layer 400: Second sealing adhesive film layer 500: Second cover plate

[0013] The drawings herein are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application, and together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0014] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described in more detail below in combination with drawings and examples. It should be understood that the specific examples described herein are only for the purpose of illustrating the present application and are not intended to limit the present application.

[0015] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance, unless otherwise expressly specified or limited. Unless otherwise specified or explained, the term "plurality" means two or more than two. The terms "connected," "fixed," etc. should be understood broadly. For example, "connected" may be a fixed connection, a detachable connection, an integral connection, or an electrical connection. Furthermore, it may be a direct connection or an indirect connection via an intermediate member. The specific meanings of the above terms in this specification can be understood by those skilled in the art depending on the specific circumstances.

[0016] It should be understood that in the description of this specification, terms indicating directions such as "above" and "below" described in the embodiments of the present application are described in terms of angles shown in the drawings and should not be understood to limit the embodiments of the present application. Furthermore, when a component is referred to as being connected "above" or "below" another component, it should be understood that the component may not only be directly connected "above" or "below" the other component, but may also be indirectly connected "above" or "below" the other component via an intermediate component.

[0017] In the related art, the backside process of an IBC battery involves phosphorus and boron diffusion to form p+ and n+ regions arranged in a comb-like pattern. Specifically, boron diffusion is first performed on the backside of a silicon substrate to form an n+-doped layer. A local laser is then used to remove a portion of the n+-doped layer. Phosphorus diffusion is then performed in the removed n+-doped layer to form a p+-doped layer. Subsequently, etching and pickling are performed to form a gap region between the n+ and p+-doped layers. The gap region is typically groove-shaped and serves to prevent recombination at the contact area between the n+ and p+-doped layers. The backside of an IBC battery typically requires polishing or texturing to form a textured structure. This textured structure effectively reduces the surface reflectance of the silicon substrate, increases light absorption, and improves the photoelectric conversion efficiency of the battery. The presence of a textured structure can also affect the passivation performance of the battery. Currently, the textured structure on the back surface of an IBC battery limits the improvement of the battery's passivation performance and light absorption, so there is a need to improve IBC batteries.

[0018] In view of this, the present invention provides a back contact solar cell, a semiconductor substrate 1 having a front surface and a back surface opposite to each other, the back surface of the semiconductor substrate 1 having an N-type conductive region 2 and a P-type conductive region 3, the N-type conductive region 2 having a plurality of first texture structures 21, the P-type conductive region 3 having a plurality of second texture structures 31, there being a height difference between the first texture structures 21 and the second texture structures 31, the height of the first texture structures 21 being lower than the height of the second texture structures 31, and a one-dimensional dimension of a bottom surface of the first texture structures 21 being larger than a one-dimensional dimension of a bottom surface of the second texture structures 31; a first passivation layer 5 located on the front side of the semiconductor substrate 1; a second passivation layer 6 located on the back surface of the semiconductor substrate 1; a first electrode 7 that penetrates the second passivation layer 6 and forms an ohmic contact with the P-type conductive region 3; and a second electrode 8 that penetrates the second passivation layer 6 and forms an ohmic contact with the N-type conductive region 2.

[0019] In the above invention, the present application designs texture structures with different dimensions for the N-type conductive region 2 and the P-type conductive region 3, wherein the N-type conductive region 2 is doped with an N-type element, the P-type conductive region 3 is doped with a P-type element, the N-type conductive region 2 has a plurality of first texture structures 21, the P-type conductive region 3 has a plurality of second texture structures 31, there is a height difference between the first texture structures 21 and the second texture structures 31, the height of the first texture structures 21 is lower than the height of the second texture structures 31, and the one-dimensional dimension of the bottom surface of the first texture structures 21 is The height of the first texture structure 21 in the N-type conductive region 2 is smaller than the one-dimensional dimension of the bottom surface of the second texture structure 31. The height of the first texture structure 21 in the N-type conductive region 2 is smaller, and the one-dimensional dimension of the bottom surface of the first texture structure 21 is larger. This reduces minority carrier recombination in the N-type conductive region 2, improves the passivation quality of the N-type conductive region 2, and further improves interface recombination on the back surface of the cell. The first texture structure also improves the contact characteristics between the slurry on the back surface of the cell and the semiconductor substrate 1, while simultaneously reducing parasitic absorption of sunlight in the N-type conductive region 2. The height of the second texture structure 31 in the P-type conductive region 3 is larger, and the one-dimensional dimension of the bottom surface of the second texture structure 31 is smaller. This allows more sunlight to be scattered and captured in the P-type conductive region 3, reducing light loss and improving the light absorption efficiency on the back surface of the cell. In addition, by designing texture structures with different dimensions in the N-type conductive region 2 and the P-type conductive region 3 of the present invention, the electrode contact resistance between the first electrode 7 and the second electrode 8 on the back surface can be reduced, further improving the passivation performance of the battery and improving the overall performance of the battery. In the present invention, by designing the dimensions of the texture structures in different regions on the back surface of the battery, it is possible to simultaneously improve the conversion efficiency and passivation performance of the battery to a certain extent, thereby improving the overall performance of the battery.

[0020] In the present application, the height of the first texture structure 21 means the distance from the top of the first texture structure 21 to the bottom of the first texture structure 21 along the thickness direction of the semiconductor substrate 1, and as can be understood, the top and bottom of the first texture structure 21 are arranged opposite each other, and the bottom of the first texture structure 21 is in contact with the N-type conductive region 2. Correspondingly, the height of the second texture structure 31 means the distance from the top of the second texture structure 31 to the bottom of the second texture structure 31 along the thickness direction of the semiconductor substrate 1. Preferably, the first texture structure and the second texture structure are recessed structures recessed toward the substrate. In the solar cell of the present application, there is a height difference between the first texture structure 21 and the second texture structure 31, and when the semiconductor substrate 1 having the N-type conductive region 2 and the P-type conductive region 3 in the solar cell is cut and placed under a measuring device (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.) and observed, the measurement device can observe the cross-sectional angle along the thickness direction of the semiconductor substrate 1. The overall height of the first texture structure 21 in the N-type conductive region 2 and the overall height of the second texture structure 31 in the P-type conductive region 3 are different, and there is a clear height difference between the first texture structure 21 and the second texture structure 31.

[0021] In the present application, the one-dimensional dimension of the bottom surface of the first texture structure 21 refers to the length, width, diagonal length, circular diameter, etc. of the bottom surface of the first texture structure 21, and is not limited thereto. The one-dimensional dimension of the bottom surface of the first texture structure 21 can be determined by directly measuring the surface of the film layer using a measuring device (such as an optical microscope, atomic force microscope, scanning electron microscope, or transmission electron microscope). Correspondingly, the one-dimensional dimension of the bottom surface of the second texture structure 31 refers to the length, width, diagonal length, circular diameter, etc. of the bottom surface of the second texture structure 31, and the one-dimensional dimension of the bottom surface of the second texture structure 31 can be measured using the above-mentioned measuring device.

[0022] In this application, the P-type conductive region 3 refers to a region formed of heavily doped P-type semiconductor material, and the N-type conductive region 2 refers to a region formed of heavily doped N-type semiconductor material. The P-type conductive region 3 and the N-type conductive region 2 are distributed in a comb-like pattern on the back surface of the semiconductor substrate 1 and primarily serve to separate and collect carriers. Here, the P-type conductive region 3 is used to collect holes, and the N-type conductive region 2 is used to collect electrons. They transport the collected carriers to the back electrode of the semiconductor substrate 1, respectively, forming a path with the external load. For this reason, the P-type conductive region 3 and the N-type conductive region 2 cannot be in direct contact. If they were in contact, the collected carriers would come into direct contact on the back surface of the semiconductor substrate 1, forming a short circuit and preventing efficient carrier collection. For this reason, a "groove-shaped" separation region 4 is typically formed between the P-type conductive region 3 and the N-type conductive region 2.

[0023] The semiconductor substrate 1 generally has a front surface and a back surface, the front surface of the semiconductor substrate 1 being the light-receiving surface, ie, the surface that is irradiated with sunlight, and the back surface of the semiconductor substrate 1 being the surface opposite to the front surface.

[0024] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer) or may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) may be, for example, one of a polycrystalline silicon substrate, a single-crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate. The embodiments of the present application are not limited to a specific type of semiconductor substrate 1. When the semiconductor substrate 1 is an N-type substrate, the doped element may be a Group V element such as phosphorus (P), arsenic (As), or tellurium (Te). The N-type semiconductor substrate 1 and the P-type conductive region 3 form a PN junction, and the N-type semiconductor substrate 1 and the N-type conductive region 2 form an N-N+ high-low junction. When the semiconductor substrate 1 is a P-type substrate, the doped element may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type semiconductor substrate 1 and the N-type conductive region 2 form a PN junction, and the P-type semiconductor substrate 1 and the P-type conductive region 3 form a P-P+ high-low junction.

[0025] In this application, the term "textured structure" refers to a micro-nano-sized structure that can scatter or reflect light to enhance light absorption. The textured structure of this application can be formed on the semiconductor substrate 1 by a process such as chemical etching, laser etching, mechanical etching, or plasma etching.

[0026] In some embodiments, the shape of the first texture structure 21 includes a non-pyramidal shape. Compared to a pyramidal shape, during the manufacturing process of a solar cell, the non-pyramidal texture structure is advantageous for the formation of subsequent film layers on the semiconductor substrate 1, resulting in higher passivation quality. The non-pyramidal texture structure has better contact characteristics with the slurry, allowing the screen-printed metal slurry to be better filled when forming electrodes, resulting in better electrode contact, higher open-circuit voltage and backing factor, and higher cell conversion efficiency. Correspondingly, the shape of the second texture structure 31 includes a non-pyramidal shape.

[0027] In some embodiments, the shape of the bottom surface of the first texture structure 21 includes at least one of a diamond, a square, a trapezoid, a similar diamond, a similar square, and a similar trapezoid. The shape of the bottom surface of the second texture structure 31 includes at least one of a diamond, a square, a trapezoid, a similar diamond, a similar square, and a similar trapezoid. The "height" and "one-dimensional dimension" of the above multiple texture structures are usually obtained in the following manner. 1) Select 3 to 5 samples with a diameter of approximately 1 to 2 cm from the center and periphery of the battery cell. 2) Place each sample under the measuring device and select 3 to 5 fields of view from the center and periphery of the sample. 3) Statistical analysis of the height and one-dimensional dimensions of 5 to 20 texture structures in each field of view. 4) The average values ​​of the height and one-dimensional dimension of the texture structure of the selected samples are calculated, and the obtained average values ​​are used as the "height" and "one-dimensional dimension" of the above-mentioned multiple texture structures.

[0028] In some embodiments, the first texture structure 21 has a bottom surface with a one-dimensional dimension of 40 nm or less, and may specifically be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 33 nm, 38 nm, or 40 nm, etc. Preferably, the bottom surface of the first texture structure 21 has a one-dimensional dimension of 30 nm or less. More preferably, the bottom surface of the first texture structure 21 has a one-dimensional dimension of 25 nm or less.

[0029] In some embodiments, the first dimension of the bottom surface of the second texture structure 31 is 30 nm or less, and may be specifically 3 nm, 8 nm, 10 nm, 15 nm, 22 nm, 25 nm, 28 nm, 30 nm, etc. Preferably, the first dimension of the bottom surface of the second texture structure 31 is 20 nm or less. More preferably, the first dimension of the bottom surface of the second texture structure 31 is 10 nm or less.

[0030] The bottom surface of the first texture structure 21 has a larger linear dimension than the second texture structure 31, which allows more sunlight to be scattered and captured in the P-type conductive region 3, reducing light loss and improving the light absorption ability of the second texture structure 31 for sunlight on the backside. At the same time, the P-type conductive region 3 also has a high light absorption effect for long-wavelength light on the front side of the cell, improving the cell's conversion efficiency. The bottom surface of the second texture structure 31 has a smaller linear dimension than the first texture structure 21, and the P-type conductive region 3 has a larger number of second texture structures 31, a smaller height of the second texture structures 31, and a smaller linear dimension of the bottom of the second texture structure 31. This reduces the binding of minority carriers in the N-type conductive region 2, improves the passivation quality of the N-type conductive region 2, and further improves the interfacial bonding on the back side of the cell. Furthermore, the smaller dimension of the second texture structure 31 improves the contact characteristics between the slurry on the back side of the cell and the semiconductor substrate 1.

[0031] In some embodiments, the height difference between the first texture structure 21 and the second texture structure 31 is 0.5 μm to 5 μm, specifically 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm. Within this limited range, the first texture structure 21 and the second texture structure 31 are spaced apart from one another on the back surface of the semiconductor substrate 1. The low height of the second texture structure 31 provides excellent passivation for the P-type conductive region 3 and allows for good contact with the electrode slurry, which is beneficial for improving the open-circuit voltage and backing factor, and achieving superior conversion efficiency. Furthermore, the height difference between the first texture structure 21 and the second texture structure 31 is beneficial for aligning the first electrode 7 and the second electrode 8 on the back surface of the battery.

[0032] In some embodiments, the height of the first texture structure 21 is 0 μm to 8 μm, specifically 0 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm, etc. Preferably, the height of the first texture structure 21 is 0 to 6 μm. More preferably, the height of the first texture structure 21 is 0 to 3 μm.

[0033] In some embodiments, the height of the second texture structure 31 is 1 μm to 10 μm, and specifically may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc. Preferably, the height of the second texture structure 31 is 1 μm to 8 μm. More preferably, the height of the second texture structure 31 is 1 μm to 5 μm.

[0034] The first texture structure 21 is higher than the second texture structure 31, which effectively improves the passivation effect on the back surface of the battery and alleviates the problem of the difference in the interfacial passivation effect between the semiconductor substrate 1 on the back surface of the battery and the second passivation layer 6.

[0035] In some embodiments, FIG. 4 illustrates first texture structures 21 in the N-type conductive region 2. Referring to FIG. 4, in at least a portion of the N-type conductive region 2, two adjacent first texture structures 21 have a height difference H1 of 1 μm or less, specifically 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, or 1 μm. Within the above-mentioned limited range, when sunlight is irradiated into a portion of the N-type conductive region 2, the height difference H1 between two adjacent first texture structures 21 can increase the number of reflections of light on the back surface, thereby improving the optical internal reflection effect of the back surface of the cell. If the height difference H1 between two adjacent first texture structures 21 exceeds 1 μm, the overall thickness of the cell increases, which is detrimental to the deposition of subsequent film layers. Preferably, the height difference H1 is 500 nm or less. As can be understood, any two adjacent first texture structures 21 may have a height difference H1, or some two adjacent first texture structures 21 may have a height difference H1, within the N-type conductive region 2. Referring to Figures 2 and 4, the first texture structures 21 are not arranged at the same height on the surface of the N-type conductive region 2, but are arranged at intervals in height.

[0036] In some embodiments, the N-type conductivity region 2 includes a first N-type conductivity region and a second N-type conductivity region located on one side of the first N-type conductivity region, the second N-type conductivity region being located between the first N-type conductivity region and the P-type conductivity region 3, and the height of the first texture structure 21 located in the first N-type conductivity region is greater than the height of the first texture structure 21 located in the second N-type conductivity region.

[0037] The N-type conductivity region 2 and the P-type conductivity region 3 are alternately arranged on the back surface of the semiconductor substrate 1, with the first N-type conductivity region located in the central region of the N-type conductivity region 2 and the second N-type conductivity region located in the peripheral region of the N-type conductivity region 2. It can be understood that the N-type conductivity region 2 includes a central region and a peripheral region, with the peripheral region surrounding the central region. In the present application, the dimensions of the first textured structure 21 at different locations within the N-type conductivity region 2 are designed so that the first N-type conductivity region, the second N-type conductivity region, and the P-type conductivity region 3 are arranged sequentially, and the textured structures within the first N-type conductivity region, the second N-type conductivity region, and the P-type conductivity region 3 are arranged in a gradient. This allows the back surface of the solar cell to have a higher internal reflection effect and excellent passivation performance during the solar cell manufacturing process, and also improves contact between the semiconductor substrate 1 and the slurry, resulting in a higher open circuit voltage and backing factor, and thus a higher cell conversion efficiency.

[0038] In some embodiments, FIG. 5 illustrates a second texture structure 31 in a P-type conductive region 3. Referring to FIG. 5, in at least a portion of the P-type conductive region 3, two adjacent second texture structures 31 have a height difference H2 of 1 μm or less, specifically 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, or 1 μm. Within the above-mentioned limited range, when sunlight is irradiated into a portion of the P-type conductive region 3, the height difference between two adjacent second texture structures 31 can increase the number of reflections of light on the back surface, thereby improving the optical internal reflection effect of the back surface of the cell. If the height difference H2 between two adjacent second texture structures 31 exceeds 1 μm, the overall thickness of the cell increases, which is detrimental to the deposition of subsequent film layers. Preferably, in at least a portion of the P-type conductive region 3, two adjacent second texture structures 31 have a height difference H2 of 500 nm or less. As can be understood, any two adjacent second texture structures 31 may have a height difference H2 within the P-type conductive region 3, or some two adjacent second texture structures 31 may have a height difference H2. Fig. 3 is a diagram showing an enlarged structure of the portion of Fig. 1B, and with reference to Figs. 3 and 5, the second texture structures 31 are not arranged at the same height on the surface of the P-type conductive region 3, but are arranged at intervals in height.

[0039] In some embodiments, the P-type conductivity region 3 includes a first P-type conductivity region and a second P-type conductivity region located on one side of the first P-type conductivity region, the second P-type conductivity region being located between the first P-type conductivity region and the N-type conductivity region 2, and the height of the second texture structure 31 located in the first P-type conductivity region is lower than the height of the second texture structure 31 located in the second P-type conductivity region.

[0040] The N-type conductive region 2 and the P-type conductive region 3 are alternately disposed on the back surface of the semiconductor substrate 1, with the first P-type conductive region located in the central region of the P-type conductive region 3 and the second P-type conductive region located in the peripheral region of the P-type conductive region 3. It can be understood that the P-type conductive region 3 includes a central region and a peripheral region, with the peripheral region surrounding the central region. In the present application, by designing the dimensions of the second texture structure 31 at different locations within the P-type conductive region 3, the first P-type conductive region, the second P-type conductive region, and the N-type conductive region 2 are disposed sequentially, and the texture structures within the first P-type conductive region, the second P-type conductive region, and the N-type conductive region 2 are disposed in a gradient. This allows the back surface of the solar cell to have a higher internal reflection effect and excellent passivation performance during the solar cell manufacturing process, and also improves the contact between the semiconductor substrate 1 and the slurry, resulting in a higher open circuit voltage and backing factor, and thus a higher cell conversion efficiency.

[0041] In some embodiments, Figure 6 is a diagram showing the microstructure of the first texture structure 21 in the N-type conductive region 2. With continued reference to Figures 4 and 6, in the N-type conductive region 2, the first texture structure 21 includes a first sub-structure 21a and a second sub-structure 21b arranged adjacently, the first sub-structure 21a and the second sub-structure 21b partially overlapping each other, and there is a gap between the first sub-structure 21a and the second sub-structure 21b.

[0042] Within the N-type conductive region 2, there are first substructures 21a and second substructures 21b that overlap each other, and there are also first substructures 21a and second substructures 21b that do not overlap each other, and the overlapping first substructures 21a and second substructures 21b can reduce the roughness of the back surface of the semiconductor substrate 1. The non-overlapping first substructures 21a and second substructures 21b can increase the roughness of the back surface of the semiconductor substrate 1. Furthermore, whether the first substructures 21a and second substructures 21b overlap each other also affects the internal reflection of sunlight into the N-type conductive region 2 on the back surface of the semiconductor substrate 1. In the present application, by determining whether the first substructure 21a and the second substructure 21b overlap, the roughness of the N-type conductive region 2 on the rear surface of the semiconductor substrate 1 can be controlled within a desired range, which improves the passivation effect of the rear surface of the semiconductor substrate 1 and at the same time benefits the contact of the electrode slurry with the N-type conductive region 2, improving the open circuit voltage and backing factor, and adjusting the light absorption effect of the N-type conductive region 2 on the rear surface of the semiconductor substrate 1, thereby balancing the performance of the battery in all aspects and achieving excellent overall performance.

[0043] In some embodiments, the first substructure 21a has a first sidewall facing the second substructure 21b, and the second substructure 21b has a second sidewall facing the first substructure 21a. The first and second sidewalls form a first angle, illustratively the angle α shown in FIG. 2. For partially overlapping first and second substructures 21a and 21b, the magnitude of the first angle can indicate the size of the overlapping area between the first and second substructures 21a and 21b. In some cases, a larger value of the first angle indicates a smaller surface roughness on which the first and second substructures 21a and 21b are located. A smaller value of the first angle indicates a larger surface roughness on which the first and second substructures 21a and 21b are located. For non-overlapping first and second substructures 21a and 21b, the magnitude of the first angle does not necessarily affect the size of the gap between the first and second substructures 21a and 21b. In the present application, the magnitude of the first angle is controlled to control the magnitude of the roughness of the N-type conductive region 2 on the backside of the semiconductor substrate 1. As can be seen, for the first substructure 21a and the second substructure 21b that are partially overlapping, the first angle is the angle between the first sidewall and the second sidewall. For the first substructure 21a and the second substructure 21b that have a gap, the first angle is the angle of intersection between the extension of the first sidewall and the extension of the second sidewall.

[0044] In some embodiments, the first angle is 40° to 60°, and may be, specifically, 40°, 43°, 47°, 50°, 53°, 55°, 58°, or 60°. Within this limited range, the roughness of the N-type conductive region 2 on the rear surface of the semiconductor substrate 1 can be optimized, and at the same time, the N-type conductive region 2 on the rear surface of the semiconductor substrate 1 can have an appropriate light absorption ability and excellent passivation performance, which is advantageous for improving the overall performance of the battery. If the first angle is less than 40°, the overlapping area between the first substructure 21a and the second substructure 21b will be too large, which is unfavorable for enhancing the internal reflection of the N-type conductive region 2 on the backside of the semiconductor substrate 1. If the first angle is more than 60°, the overlapping area between the first substructure 21a and the second substructure 21b will be too small, which is unfavorable for the deposition of subsequent film layers, resulting in poor passivation of the battery, poor contact characteristics of the slurry, and reduced open-circuit voltage and backing factor of the battery, resulting in reduced battery quality and yield. Preferably, the first angle is between 50° and 54°.

[0045] In some embodiments, Figure 7 is a microscopic view of the first texture structure 21 in the P-type conductive region 3. With continued reference to Figures 5 and 7, within the P-type conductive region 3, the second texture structure 31 includes a third sub-structure 31a and a fourth sub-structure 31b arranged adjacently, the third sub-structure 31a and the fourth sub-structure 31b partially overlapping each other, and there are gaps between some of the third sub-structures 31a and the fourth sub-structures 31b.

[0046] Within the P-type conductive region 3, there are third substructures 31a and fourth substructures 31b that overlap each other, and there are also third substructures 31a and fourth substructures 41b that do not overlap each other, and the overlapping third substructures 31a and fourth substructures 41b can reduce the roughness of the back surface of the semiconductor substrate 1. The non-overlapping third substructures 31a and fourth substructures 31b can increase the roughness of the back surface of the semiconductor substrate 1. Furthermore, whether the third substructures 31a and fourth substructures 31b overlap each other also affects the internal reflection of sunlight into the P-type conductive region 3 on the back surface of the semiconductor substrate 1. In the present application, by setting whether or not the third substructure 31a and the fourth substructure 31b overlap, the roughness of the P-type conductive region 3 on the back surface of the semiconductor substrate 1 can be controlled within a desired range, improving the passivation effect of the back surface of the semiconductor substrate 1 while also favoring contact of the electrode slurry with the P-type conductive region 3. This allows the light absorption effect of the P-type conductive region 3 on the back surface of the semiconductor substrate 1 to be adjusted, improving the open circuit voltage and backing factor, and achieving excellent battery conversion efficiency. As can be seen, because the height of the second texture structure 31 is lower than that of the first texture structure 21, whether or not the third substructure 31a and the fourth substructure 31b overlap has little effect on the light absorption of the back surface of the semiconductor substrate 1.

[0047] In some embodiments, the third substructure 31a has a third sidewall facing the fourth substructure 31b, and the fourth substructure 31b has a fourth sidewall facing the third substructure 31a, with the third and fourth sidewalls forming a second angle, illustratively the angle β shown in FIG. 3 . For partially overlapping third and fourth substructures 31a and 31b, the magnitude of the second angle can be used to indicate the size of the overlapping area between the third and fourth substructures 31a and 31b. In some embodiments, a larger value of the second angle indicates a smaller roughness of the surface on which the third and fourth substructures 31a and 31b are located. A smaller value of the second angle indicates a larger roughness of the surface on which the third and fourth substructures 31a and 31b are located. For the third substructure 31a and fourth substructure 31b that do not overlap, the magnitude of the second angle does not necessarily affect the size of the gap between the third substructure 31a and the fourth substructure 31b. In the present application, the magnitude of the second angle is controlled to control the degree of roughness of the P-type conductive region 3 on the back surface of the semiconductor substrate 1. As can be understood, for the third substructure 31a and the fourth substructure 31b that partially overlap, the second angle is the angle between the third sidewall and the fourth sidewall. For the third substructure 31a and the fourth substructure 31b that have a gap, the second angle is the angle between the extension of the third sidewall and the extension of the fourth sidewall.

[0048] In some embodiments, the second angle is 45° to 70°, and may be, for example, 45°, 48°, 50°, 55°, 58°, 62°, 65°, or 70°. Within this limited range, the roughness of the P-type conductive region 3 on the rear surface of the semiconductor substrate 1 can be optimized, and the P-type conductive region 3 on the rear surface of the semiconductor substrate 1 can have suitable light absorption ability and excellent passivation performance, which is beneficial for improving the overall performance of the battery. If the second angle is less than 45°, the overlapping area between the third substructure 31a and the fourth substructure 31b will be too large, which is unfavorable for enhancing the internal reflection of the P-type conductive region 3 on the backside of the semiconductor substrate 1. If the second angle is more than 60°, the overlapping area between the third substructure 31a and the fourth substructure 31b will be too small, which is unfavorable for the deposition of subsequent film layers, resulting in poor passivation of the battery, poor contact characteristics of the slurry, and reduced open circuit voltage and backing factor of the battery, thereby reducing battery quality and yield. Preferably, the second angle is between 55° and 65°.

[0049] In some embodiments, the value of the first angle is smaller than the value of the second angle. As can be seen, the height of the first texture structure 21 in the N-type conductivity region 2 is smaller than the height of the second texture structure 31 in the P-type conductivity region 3, the one-dimensional dimension of the bottom of the first texture structure 21 is larger than the one-dimensional dimension of the bottom of the second texture structure 31, and for the first texture structure 21 and the second texture structure 31, when the value of the first angle is equal to the value of the second angle, the volume of the overlapping portion between the first substructure 21 a and the second substructure 21 b is smaller than the volume of the overlapping portion between the third substructure 31 a and the fourth substructure 31 b, which results in an excessively large difference in passivation performance and internal reflection ability between the P-type conductivity region 3 and the N-type conductivity region 2. Therefore, in the present application, the value of the first angle is controlled to be smaller than the value of the second angle, which is advantageous for achieving balance over the entire back surface of the semiconductor substrate 1 and further improving the overall performance of the battery.

[0050] In some embodiments, the distance between two adjacent N-type conductive regions 2 or two adjacent P-type conductive regions 3 is 0.5 mm to 1.3 mm, and may be specifically 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.1 mm, 1.2 mm, or 1.3 mm, etc.

[0051] In some embodiments, the distribution ratio of the N-type conductive region 2 on the back surface of the semiconductor substrate 1 is 50% to 85%, and may be specifically 50%, 55%, 60%, 65%, 70%, 75%, 80%, or 85%, etc.

[0052] In some embodiments, the distribution ratio of the P-type conductive region 3 on the back surface of the semiconductor substrate 1 is 15% to 50%, and specifically may be 15%, 20%, 25%, 30%, 35%, 40%, 45%, or 50%, etc.

[0053] In the present application, by limiting the spacing between two adjacent N-type conductive regions 2 or two adjacent P-type conductive regions 3 in the semiconductor substrate 1 and limiting the distribution ratio of the N-type conductive regions 2 and the P-type conductive regions 3 on the back surface of the semiconductor substrate 1, a PN junction with excellent conductivity can be formed in the semiconductor substrate 1 during the manufacture of a solar cell, thereby improving the photoelectric performance of the manufactured solar cell.

[0054] In some embodiments, the semiconductor substrate 1 of the present application is fabricated by first depositing a corresponding film layer on the backside structure with a large pyramid base feature using an alkaline polishing machine to form an N-type conductive region 2, then laser cleaving to define a P-type conductive region, and again using an alkaline polishing machine to remove the laser damage and form a small pyramid-based planar feature.

[0055] The present application further provides a method for manufacturing the above-mentioned back contact solar cell, and FIG. 8 shows a manufacturing flow chart of the back contact solar cell provided by the present application example. As shown in FIG. 8, the manufacturing method of the back contact solar cell includes the following steps: providing a semiconductor substrate 1 including a front surface and a back surface disposed opposite to each other; forming an N-type conductive region 2 and a P-type conductive region 3 on a rear surface of a semiconductor substrate 1, the N-type conductive region 2 having a plurality of first texture structures 21, the P-type conductive region 3 having a plurality of second texture structures 31, there being a height difference between the first texture structures 21 and the second texture structures 31, the height of the first texture structures 21 being lower than the height of the second texture structures 31, and the one-dimensional dimension of the bottom surface of the first texture structures 21 being larger than the one-dimensional dimension of the bottom surface of the second texture structures 31; forming a first passivation layer 5 on the front side of the semiconductor substrate 1; forming a second passivation layer 6 on the back surface of the semiconductor substrate 1; forming a first electrode 7 and a second electrode 8 on the surface of the second passivation layer 6.

[0056] The manufacturing method of the back contact solar cell 100 of the present application will be described below clearly and completely in conjunction with the drawings in the embodiments of the present invention. The described embodiments are only some of the embodiments of the present invention, but not all of the embodiments.

[0057] In step S100, a semiconductor substrate 1 is provided, which includes a front surface and a back surface disposed opposite to each other.

[0058] In some embodiments, the front surface of the semiconductor substrate 1 corresponds to the front surface of the cell, which is the surface facing the sun (i.e., the light-receiving surface), and the back surface of the semiconductor substrate 1 corresponds to the back surface of the cell, which is the surface facing away from the sun (i.e., the backlight surface).

[0059] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) is, for example, one of a polycrystalline silicon substrate, a single-crystal silicon substrate, a microcrystalline silicon substrate, and a silicon carbide substrate, and the embodiments of the present application are not limited to a specific type of the semiconductor substrate 1.

[0060] In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, and specifically may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, or 240 μm, etc., and is not limited here.

[0061] In step S200, an N-type conductive region 2 and a P-type conductive region 3 are formed on the rear surface of a semiconductor substrate 1.

[0062] In S201, the rear surface of the semiconductor substrate 1 is subjected to acid cleaning and a first polishing process using a first alkaline solution, thereby forming a first texture structure 21 on the rear surface of the semiconductor substrate 1.

[0063] In S202, a P-type conductive region 3 is determined and formed by laser cleavage, and the region where the first texture structure 21 is formed is made into an N-type conductive region 2. Then, a second polishing process is performed on the P-type conductive region 3 on the back surface of the semiconductor substrate 1 using a second alkaline solution, thereby forming a second texture structure 31 in the P-type conductive region 3, and creating a height difference between the first texture structure 21 and the second texture structure 31, where the height of the first texture structure 21 is lower than the height of the second texture structure 31, and the one-dimensional dimension of the bottom surface of the first texture structure 21 is larger than the one-dimensional dimension of the bottom surface of the second texture structure 31.

[0064] In S201 and S202, the time of the first polishing process and the time of the second polishing process can be controlled to be different, and / or the concentrations of the first alkaline solution and the second alkaline solution can be controlled to be different, thereby making the dimensions and shapes of the first texture structure 21 and the second texture structure 31 different.

[0065] In some embodiments, the first alkaline solution and / or the second alkaline solution is a sodium hydroxide solution.

[0066] In step S300, a first passivation layer 5 is formed on the front surface of the semiconductor substrate 1.

[0067] In the present application, by forming a first passivation layer 5 on the front surface of the semiconductor substrate 1, the first passivation layer 5 can utilize the passivation effect to reduce the concentration of minority carriers on the surface of the semiconductor substrate 1, suppress carrier recombination on the cell surface, and reduce the surface recombination rate, while also reducing the series resistance and improving the electron transport capacity.

[0068] In some embodiments, the first passivation layer 5 may include, but is not limited to, a single oxide layer or a multi-layer structure, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. Of course, other types of passivation layers may also be used, and the present invention does not limit the specific material of the first passivation layer 5. The first passivation layer 5 can provide good passivation and reflection reduction effects for the semiconductor substrate 1, which is beneficial to improving the conversion efficiency of the battery.

[0069] In some embodiments, the thickness of the first passivation layer 5 ranges from 10 nm to 100 nm, specifically 10 nm, 20 nm, 30 nm, 42 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, etc., and of course may be other values ​​within the above range and is not limited here.

[0070] In some embodiments, the manufacturing method of the present application further comprises forming a reflection-reducing layer on the surface of the first passivation layer 5 to reduce light reflection on the front surface of the cell.

[0071] In some embodiments, the reflection-reducing layer may be, for example, a silicon oxynitride layer or an aluminum oxide / silicon nitride stack, without limitation herein. Taking the silicon oxynitride layer as an example, the presence of the silicon oxynitride layer can effectively reduce light reflection and increase light transmittance, and the reflectance can be adjusted to achieve the desired reflection-reducing effect by controlling the film thickness. Furthermore, the raw material NH4 for the silicon oxynitride layer decomposes into H atoms during the reaction, and the H atoms penetrate into the semiconductor substrate 1 at high temperatures and bond with dangling bonds on the surface, thereby fulfilling a passivation function.

[0072] In some embodiments, the thickness of the first passivation layer 5 ranges from 40 nm to 100 nm, and may be specifically 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, etc., or of course other values ​​within the above range, and is not limited here.

[0073] In some embodiments, the first passivation layer 5 and / or the reflection reduction layer can be deposited using plasma enhanced chemical vapor deposition, although other methods, such as organic chemical vapor deposition, may also be used. The present examples do not limit the specific embodiment of the first passivation layer 5.

[0074] In step S400, a second passivation layer 6 is formed on the back surface of the semiconductor substrate 1.

[0075] In some embodiments, the second passivation layer 67 may include one or more of a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide / silicon nitride stack structure. Of course, other types of passivation layers may be used for the second passivation layer 67, and the present application does not limit the specific material of the second passivation layer 67. For example, in other embodiments, the second passivation layer 6 may be a stack of silicon dioxide and silicon nitride. The second passivation layer 6 described above can provide a good passivation effect for the silicon substrate, contributing to improving the conversion efficiency of the battery.

[0076] In some embodiments, the second passivation layer 6 can be deposited using plasma enhanced chemical vapor deposition, although other methods may of course be used, such as organic chemical vapor deposition.

[0077] In some embodiments, the thickness of the second passivation layer 6 is in the range of 10 nm to 100 nm, and may be, specifically, 10 nm, 20 nm, 30 nm, 42 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, or may be other values ​​within the above range, and is not limited here.

[0078] In step S500, a first electrode 7 and a second electrode 8 are formed on the surface of the second passivation layer 6. This results in a back contact solar cell, the structure of which is shown in FIG.

[0079] Specifically, in this step, a metallization process is performed on the surface of the second passivation layer 6 to obtain a first electrode 7 and a second electrode 8, which correspond to the P-type conductive region 32 and the N-type conductive region 2, respectively. The first electrode 7 and the second electrode 8 are manufactured using a screen printing method and then sintered, so that the first electrode 7 penetrates the second passivation layer 6 to form an ohmic contact with the N-type conductive region 2, and the second electrode 8 penetrates the second passivation layer 6 to form an ohmic contact with the P-type conductive region 3, or the first electrode 7 penetrates the second passivation layer 6 to form an ohmic contact with the P-type conductive region 3, and the second electrode 8 penetrates the second passivation layer 6 to form an ohmic contact with the N-type conductive region 2. Of course, the first electrode 7 and the second electrode 8 can also be formed on the back surface of the battery using at least one of a metal evaporation method and a plating method.

[0080] Note that the present embodiment does not limit the specific materials of the first electrode 7 and the second electrode 8. For example, when the first electrode 7 forms an ohmic contact with the P-type conductive region 3 and the second electrode 8 forms an ohmic contact with the N-type conductive region 2, the first electrode 7 is a silver electrode or a silver / aluminum electrode, and the second electrode 8 is a silver electrode. For example, a silver paste is printed on the underside of the second passivation layer 67 corresponding to the N-type conductive region 24, and a silver paste or a silver / aluminum paste doped with a small amount of aluminum is printed on the underside of the second passivation layer 6 corresponding to the P-type conductive region 3, followed by sintering. The second passivation layer 6 is burned through by the pastes, and the formed silver electrode or silver / aluminum electrode is in ohmic contact with the P-type conductive region 3, and the formed silver electrode is in ohmic contact with the N-type conductive region 24.

[0081] In the present application, unless otherwise specified, the operation steps may be performed in order or out of order. In the present application, the order of the steps for manufacturing a solar cell is not limited and can be adjusted according to the actual production process.

[0082] In an embodiment of the present application, a photovoltaic module 1000 is provided that includes a cell string formed by electrically connecting back-contact solar cells as described above.

[0083] Specifically, referring to FIG. 9, a photovoltaic module 1000 includes a first cover plate 200 , a first sealing adhesive film layer 300 , a solar cell string, a second sealing adhesive film layer 400 and a second cover plate 500 .

[0084] In some embodiments, a solar cell string includes multiple back contact solar cells 100 as described above connected via conduction bands as described above, and the connection method between the back contact solar cells 100 may be by partial stacking or stitching.

[0085] In some embodiments, the first cover plate 200, the second cover plate 500 may be a transparent or opaque cover plate, for example, a glass cover plate, a plastic cover plate.

[0086] Both sides of the first sealing adhesive film layer 300 are in contact with and bonded to the first cover plate 200 and the battery string, respectively, and both sides of the second sealing adhesive film layer 400 are in contact with and bonded to the second cover plate 500 and the battery string, respectively. Here, the first sealing adhesive film layer 300 and the second sealing adhesive film layer 400 may each be a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0087] In order to prevent the photovoltaic module 1000 from shifting during stacking, the photovoltaic module 1000 can be sealed by surrounding the entire side, i.e., by using sealing tape to completely cover and seal the side of the photovoltaic module 1000.

[0088] The photovoltaic module 1000 further includes an edge sealing member fixed and sealed to a portion of the edge of the photovoltaic module 1000. The edge sealing member may be fixed and sealed to an edge near a corner of the photovoltaic module 1000. This edge sealing member may be a high-temperature resistant tape. This high-temperature resistant tape has excellent high-temperature resistance and does not decompose or fall off during the lamination process, ensuring reliable sealing of the photovoltaic module 1000. Here, both ends of the high-temperature resistant tape are fixed to the second cover plate 500 and the first cover plate 200, respectively. Both ends of the high-temperature resistant tape may be adhered to the second cover plate 500 and the first cover plate 200, respectively, and the center of the high-temperature resistant tape can provide positional restriction to the side edges of the photovoltaic module 1000, preventing the photovoltaic module 1000 from shifting during lamination.

[0089] The above is only a preferred embodiment of the present application, and does not limit the present application, and various modifications and variations are possible for those skilled in the art. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. a semiconductor substrate having a front surface and a back surface opposite to each other, the back surface of the semiconductor substrate having an N-type conductive region and a P-type conductive region, the N-type conductive region having a plurality of first texture structures, the P-type conductive region having a plurality of second texture structures, there being a height difference between the first texture structures and the second texture structures, the height of the first texture structures being lower than the height of the second texture structures, and a one-dimensional dimension of a bottom surface of the first texture structures being larger than a one-dimensional dimension of a bottom surface of the second texture structures; a first passivation layer located on the front side of the semiconductor substrate; a second passivation layer located on the back surface of the semiconductor substrate; a first electrode that penetrates the second passivation layer and forms an ohmic contact with the P-type conductivity region; a second electrode that penetrates the second passivation layer and forms an ohmic contact with the N-type conductivity region; A back contact solar cell characterized in that:

2. a one-dimensional dimension of a bottom surface of the first texture structure is 40 nm or less; 10. The back contact solar cell of claim 1.

3. The one-dimensional dimension of the bottom surface of the second texture structure is 30 nm or less.

10. The back contact solar cell of claim 1.

4. in at least a portion of the N-type conductive region, two adjacent first texture structures have a height difference, and the height difference is 1 μm or less.

10. The back contact solar cell of claim 1.

5. the N-type conductive region includes a first N-type conductive region and a second N-type conductive region located on one side of the first N-type conductive region, the second N-type conductive region is located between the first N-type conductive region and the P-type conductive region, and a height of a first texture structure located in the first N-type conductive region is greater than a height of a first texture structure located in the second N-type conductive region; 10. The back contact solar cell of claim 1.

6. in at least a portion of the P-type conductive region, two adjacent second texture structures have a height difference, and the height difference between two adjacent second texture structures is 1 μm or less.

10. The back contact solar cell of claim 1.

7. the P-type conductive region includes a first P-type conductive region and a second P-type conductive region located on one side of the first P-type conductive region, the second P-type conductive region is located between the first P-type conductive region and the N-type conductive region, and a height of a second texture structure located in the first P-type conductive region is lower than a height of a second texture structure located in the second P-type conductive region; 10. The back contact solar cell of claim 1.

8. In the N-type conductivity region, the first texture structure includes a first sub-structure and a second sub-structure that are adjacently disposed, some of the first sub-structures and the second sub-structures partially overlap each other, and another part of the first sub-structures and the second sub-structures have gaps therebetween; the first substructure has a first sidewall facing the second substructure, the second substructure has a second sidewall facing the first substructure, and the first sidewall and the second sidewall form a first angle; 10. The back contact solar cell of claim 1.

9. In the P-type conductivity region, the second texture structure includes a third sub-structure and a fourth sub-structure that are adjacently disposed, some of the third sub-structures and the fourth sub-structures partially overlap each other, and there is a gap between another part of the third sub-structures and the fourth sub-structures; the third substructure has a third sidewall facing the fourth substructure, the fourth substructure has a fourth sidewall facing the third substructure, and the third sidewall and the fourth sidewall form a second angle; The back contact solar cell of claim 8 .

10. the value of the first angle is equal to or less than the value of the second angle, and / or the first angle is between 40° and 60°, and / or the second angle is between 45° and 70°; 10. The back contact solar cell of claim 9.

11. a distance between two adjacent N-type conductive regions or two adjacent P-type conductive regions is 0.5 mm to 1.3 mm, a distribution ratio of the N-type conductive regions on the rear surface of the semiconductor substrate is 50% to 85%, and a distribution ratio of the P-type conductive regions on the rear surface of the semiconductor substrate is 15% to 50%; 10. The back contact solar cell of claim 1.

12. The shape of the first texture structure and / or the shape of the second texture structure comprises a non-pyramid shape.

10. The back contact solar cell of claim 1.

13. The shape of the bottom surface of the first texture structure and / or the second texture structure includes at least one of a diamond, a square, a trapezoid, a similar diamond, a similar square, and a similar trapezoid.

10. The back contact solar cell of claim 1.

14. a cover plate, an encapsulating material layer, and a solar cell string, the solar cell string including a plurality of back contact solar cells according to any one of claims 1 to 13; A photovoltaic module characterized by:

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