ReRAM module with intermediate electrodes

Abstract

The resistive RAM module comprises a source electrode and an intermediate electrode formed on the source electrode. The intermediate electrode has a closed curve profile. The resistive RAM module further comprises a memristor element deposited on the intermediate electrode. The resistive RAM module further comprises a sink electrode in contact with the memristor element. The intermediate electrode is electrically between the source electrode and the memristor element, and the memristor element is electrically between the intermediate electrode and the sink electrode.

Description

[Technical Field]

[0001] The present invention relates generally to random access memories, and more particularly to resistive RAM modules. [Background technology]

[0002] Random access memory (referred to herein as "RAM") is a class of memory used in computer storage systems. RAM is available in several forms, many of which are useful for fast access to information both inside and outside of the processor cache. As such, several types of RAM are installed on system boards such as motherboards. These types of RAM can store information in different ways depending on the form of RAM. Some types, for example, store bits of information (e.g., "1" or "0") by changing the state of a transistor-capacitor pair within a RAM cell.

[0003] Some types of RAM store bits of information by changing the state of electrical resistance across the RAM cell. These resistive RAM (ReRAM) modules contain a memristor element located between two electrodes. By introducing a voltage to the memristor element, a pattern of conductive defects can be generated in the memristor element. This pattern, often called a conductive filament, can be controlled to switch the memristor element between a high-resistance state and a low-resistance state. Summary of the Invention

[0004] Some embodiments of the present disclosure may be exemplified as a resistive RAM module comprising a source electrode and an intermediate electrode. The intermediate electrode is formed on the source electrode. The resistive RAM module further comprises a memristor element disposed on the intermediate electrode such that the intermediate electrode is electrically between the source electrode and the memristor element. The resistive RAM module further comprises a sink electrode in contact with the memristor element such that the memristor element is electrically between the intermediate electrode and the sink electrode. The intermediate electrode has a closed curve profile having at least one point.

[0005] Some embodiments of the present disclosure may be further exemplified as a method of forming a resistive RAM module. The method includes attaching a set of seed pillars to a surface of a layer of the resistive RAM module. The seed pillars are attached perpendicular to the surface. The layer includes a source electrode embedded in an interlayer dielectric. The method further includes depositing nitride on sidewalls of the seed pillars such that the nitride buildup creates a set of nitride boundaries surrounding the seed pillars. Each nitride boundary in the set partially overlaps at least two other nitride boundaries such that a gap is formed at the center of the nitride boundary. The method further includes depositing intermediate electrodes on top of the source electrodes and in the gaps. The method further includes removing the seed pillars. The method further includes depositing memristor elements on the intermediate electrodes and depositing sink electrodes on the memristor elements.

[0006] Some embodiments of the present disclosure may be further exemplified as a computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a computer to cause the computer to perform the method for forming a resistive RAM module. [Brief explanation of the drawings]

[0007] [Figure 1] (A) is a schematic cross-sectional side view of a resistive RAM module having an intermediate electrode with a concave closed curve profile, (B) is a schematic top view of the resistive RAM module, and (C) is a schematic enlarged top view of a conductive filament formed in a memristor element between the intermediate electrode and the sink electrode in the resistive RAM module. [Figure 2A] 1A-1C are side views of source electrodes on a substrate in a first stage of forming a resistive RAM (ReRAM) module having an intermediate electrode with a concave closed curve profile, according to some embodiments of the present disclosure. [Figure 2B] 1A-1C are top views of source electrodes in a first stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2C] FIG. 10 is a side view of a patterned oxide layer on a source electrode in a second stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2D] FIG. 10 is a top view of a patterned oxide layer on a source electrode in a second stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2E] FIG. 10 is a side view of a set of hard mask elements added to an oxide layer in a third stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2F] FIG. 10 is a top view of a set of hard mask elements in a third stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2G] FIG. 10 is a side view of a set of patterned seed pillars in a fourth stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2H] FIG. 10 is a top view of a set of patterned seed pillars in a fourth stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2I]FIG. 10 is a side view of the buildup of nitride interfaces on the sidewalls of seed pillars in a fifth stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2J] FIG. 10 is a top view of a nitride interface in a fifth stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2K] FIG. 10 is a side view of the nitride interface after removal of excess nitride in a sixth stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2L] FIG. 10 is a top view of a source electrode in the gap between nitride boundaries in a sixth stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2M] FIG. 10 is a side view of an intermediate electrode having a concave closed curve profile in a seventh stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2N] FIG. 10 is a top view of an intermediate electrode having a concave closed curve profile in a seventh stage of forming a ReRAM module according to some embodiments of the present disclosure. [Figure 2O] FIG. 10 is a side view of the intermediate electrode after removal of the nitride interface and seed pillars in an eighth stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2P] FIG. 10 is a top view of the intermediate electrode after removal of the nitride boundary and seed pillars in an eighth stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2Q] FIG. 10 is a side view of a ReRAM module after addition of an insulating layer around the base of the intermediate electrode in a ninth stage of forming the ReRAM module according to some embodiments of the present disclosure. [Figure 2R] FIG. 10 is a top view of a ReRAM module after addition of an insulating layer around the base of the intermediate electrode in a ninth stage of forming the ReRAM module according to some embodiments of the present disclosure. [Figure 2S]FIG. 10 is a side view of a memristor element added to an intermediate electrode in a tenth stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2T] FIG. 10 is a top view of a memristor element added to an intermediate electrode in a tenth stage of forming a ReRAM module, according to some embodiments of the present disclosure. [Figure 2U] FIG. 11 is a cross-sectional side view of a ReRAM module after addition of a sink electrode to a memristor element in an eleventh stage of forming the ReRAM module according to some embodiments of the present disclosure. [Figure 2V] FIG. 11 is a top view of a ReRAM module after addition of a sink electrode in an eleventh stage of forming the ReRAM module according to some embodiments of the present disclosure. [Figure 2W] FIG. 12 is a cross-sectional side view of a ReRAM module after addition of nitride caps to the intermediate electrodes and memristor elements in a twelfth stage of forming the ReRAM module according to some embodiments of the present disclosure. [Figure 2X] 1A is a top view of a ReRAM module after addition of a nitride cap and removal of excess sink electrode material according to some embodiments of the present disclosure. FIG. [Figure 3] 1A-1C illustrate an exemplary method for forming a resistive RAM (ReRAM) module having an intermediate electrode with a concave closed curve profile, according to some embodiments of the present disclosure. [Figure 4] 1A-1C illustrate an exemplary set of nitride rings that may be used, according to some embodiments of the present disclosure, to form an intermediate electrode having a concave closed curve profile with three points. [Figure 5] 1A-1C illustrate an exemplary set of nitride rings that may be used, according to some embodiments of the present disclosure, to form an intermediate electrode having a concave closed curve profile with six points. [Figure 6] FIG. 1 illustrates representative major components of an exemplary computer system that may be used in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Random access memory (referred to herein as "RAM") is a form of computer storage capable of storing information for rapid retrieval by another computer component, such as a processor. RAM is found, for example, in the cache memory of many processors and is used as the main memory in many computer systems. The structure of RAM and the process by which RAM stores information differ based on the form of RAM used. For example, RAM used in processor caches may have a six-transistor memory cell form, while RAM used in system memory may have a transistor-capacitor cell form. In typical RAM forms, the cell can store one bit of information, and the state of the cell (e.g., charged or uncharged) can be used to set the bit on or off (also referred to as setting the bit to "true" or "false," "1" or "0," etc.).

[0009] In resistive random access memory (referred to herein as "ReRAM"), for example, memory cells take the form of a dielectric solid-state material, sometimes referred to as a "memristor" or "memristor element." For example, a ReRAM module may take the form of an oxide layer disposed between two electrodes in a memory stack (sometimes referred to as "source" and "sink" electrodes, "bottom" and "top" electrodes, or "wordline" and "bitline" electrodes). Normally non-conductive, allowing oxide defects to form in this oxide layer changes the material's resistance, making it conductive. These oxide defects, sometimes referred to as "oxygen vacancies," represent locations of oxide bonds where oxygen has been removed (typically transferred to other parts of the oxide layer). When these defects form in a continuous path (sometimes referred to as a "filament" or "conductive filament") between two ends of the memristor, the electrical resistance between those two ends can drop significantly. Furthermore, when an electric field of a certain voltage is subsequently applied to the memristor, oxygen previously removed from an oxide bond location (i.e., an oxygen vacancy location in the filament) can migrate back to the previous oxide bond location. When this happens, the "filament" is distorted, again significantly increasing the electrical resistance between the two ends of the memristor. This process is reversible; therefore, by applying an electric field of a specific voltage to the memristor, the memristor can be switched between a high-resistance state and a low-resistance state.

[0010] Thus, in ReRAM, an electrical charge can be applied to a memory module to switch the electrical resistance of the memory module between a first resistance value (sometimes referred to as "high resistance") and a second resistance value (sometimes referred to as "low resistance"). The state of the module can be used to store information. For example, by setting each state to 1 or 0 (e.g., a high resistance state is set to "1" and a low resistance state is set to "0"), the state of the memristor can be used to store one information bit.

[0011] Unlike some other types of RAM, ReRAM is considered nonvolatile, meaning that it will not lose stored information in the absence of power. In other words, ReRAM's state (high or low resistance) is stable when power to a computer system is removed. For this reason, ReRAM has potential advantages in long-term storage, such as replacing (or supplementing) hard disk drives and solid-state drives. When successfully applied to long-term storage, ReRAM can significantly improve the storage performance of computer systems due to ReRAM's low read latency and high write speed compared to other long-term storage solutions.

[0012] However, difficulties in forming ReRAM can make its use in storage systems difficult, if not entirely impossible. For example, as mentioned above, for ReRAM to form, a sufficient voltage must be applied across the ReRAM module to form a continuous path of oxide defects (i.e., a conductive filament). This "sufficient voltage" is sometimes referred to as the formation voltage.

[0013] However, while the application of the formation voltage is controllable, the exact location of the oxide defects that form as a result of the formation voltage can be very difficult to control. The random formation of filaments can cause variations in the resistance of ReRAM devices. In very large binary memory structures (e.g., memory chips with relatively large amounts of free space between each memory cell on the bit lines, word lines, or both), this may not pose a problem because the difference between the on and off states is sufficiently separated to be distinguishable using sensing circuitry.

[0014] In these high-capacity memory structures, memristor elements are often large and isolated from other switching elements. Therefore, even in ReRAM modules where the probability of filament formation is relatively equal across the entire area of ​​the memristor element, the likelihood of a filament forming at the very edge of the memristor is low. However, as memory structures become smaller, ReRAM modules and memristor elements become smaller, and the distance between the center of the memristor element and the very edge of the memristor element also becomes shorter. Therefore, the likelihood of a filament forming at the very edge of the memristor increases. As a result, the difference in resistance between the on and off states in these smaller-capacity ReRAM structures can be significant. In some instances, ReRAM filaments can be formed with resistances between a "fully on" state and a "fully off" state. These partially formed states need to be controllably programmed in artificial intelligence applications, such as those used by ReRAM arrays that comprise neural networks. ReRAM devices without controllable filament formation may require additional circuitry to induce, sense, or correct differences in the resistance of partial states.

[0015] For example, a filament formed near the edge of a memristor element may have a higher than normal leakage risk compared to other elements of the memory structure. Specifically, if a conductive filament is formed very close to the edge of a memristor, a portion of the filament may be close enough to the conductive material outside the memristor to form a conductive path to that conductive material. This may result in a substantial short circuit between one end of the conductive filament and the conductive material, preventing the memristor from switching from a high-resistance state to a low-resistance state. In other words, a ReRAM device may be difficult to control at normal switching voltages, or may even become completely non-functional. As ReRAM devices become smaller, the likelihood of filaments forming near the edge of a memristor element increases. Therefore, there is an increasing need to control the filament formation location with greater precision.

[0016] Finally, the formation process of the conductive filaments in a typical ReRAM memory structure can require a high formation voltage. Unfortunately, the formation voltage for a typical ReRAM module is often significantly higher than the voltage required to switch the resistance state of the ReRAM after the conductive filaments are formed. For example, a typical ReRAM module may be designed to operate at a voltage similar to other memory systems (e.g., 1.2 volts). However, conductive filament formation in such a ReRAM module may require a voltage (i.e., the formation voltage) greater than 4 volts to be applied to the ReRAM module. Furthermore, applying this formation voltage typically requires applying it via the same paths (e.g., via bit lines and word lines) as the voltages that switch between states when the ReRAM is used in a system. In other words, the formation voltage must be applied by the final circuit design of the ReRAM module and associated connections to the system, depending on the application.

[0017] Unfortunately, applying a formation voltage (e.g., 4V) through circuitry designed to handle only memory switching voltages (e.g., 1.2V) can cause damage to the circuitry. For example, in a typical complementary metal-oxide semiconductor (sometimes referred to as "CMOS") system, applying a voltage significantly higher than the voltage for which the circuitry is designed can cause shorts to form across the conduction channel between the gate and the conduction channel, and between the source and the drain. In cutting-edge systems with very small components, high voltages can also damage contacts and wiring.

[0018] To address some of the above issues, some embodiments of the present disclosure control the formation location of a conductive filament in a memristor element by forming an intermediate electrode electrically between a source electrode and a sink electrode. A memristor element can be formed electrically between the intermediate electrode and the sink electrode. As used herein, the term "electrically between" does not necessarily refer to the physical location of the elements, but rather to the location of a set of elements with respect to the current flowing between them. For example, if a current flowing from a source electrode to a sink electrode typically passes through the intermediate electrode before passing from the source electrode to the sink electrode, the intermediate electrode is considered to be electrically between the source electrode and the sink electrode. Thus, applying a voltage across the source electrode and the sink electrode can cause the same voltage to exist across the intermediate electrode and the sink electrode, which are separated by the memristor element. If this voltage is of sufficient magnitude, oxygen vacancies begin to form in the memristor element, leading to the formation of a conduction channel.

[0019] The intermediate electrode may exhibit a closed curve cross-sectional profile having one or more points. Points on a closed curve cross-sectional profile (sometimes referred to herein as a "closed curve profile" or simply a "profile") typically occur at locations where two different curves meet (e.g., similar to the corners of a square or triangle, the points of a star, the points of a teardrop, or the bottom end of a "heart"). At these points, the memristor may be more exposed to the electric field induced by the voltage than elsewhere. As a result, oxygen vacancies may be more likely to form at those points, increasing the likelihood that conductive filaments will also form there. In this way, the location of conductive filament formation can be controlled. This may prevent the filaments from leaking to other structures outside the memristor device.

[0020] The curves that make up the closed curve profile of the intermediate electrode may be convex, concave, or linear. Thus, in some embodiments, the closed curve profile may be a concave closed curve profile, in which one or more of the curves that make up the profile are concave. In such a profile, when two concave curves meet at a point, the cross-sectional profile (and therefore the electrode material) at that point may be particularly narrow. This may result in significant exposure to the electric field at that point, and therefore, conductive filaments may be highly likely to form there as well.

[0021] Furthermore, because exposure to the electric field can be increased at narrow points in the intermediate electrode, the conductive filaments can form near those points at lower formation voltages. As mentioned above, the formation voltages of typical memristor elements are often higher than the voltages at which the memory structure is designed to operate. For this reason, reducing the voltage applied to the memory structure during formation of the conductive filaments can avoid damaging other components of the memory structure that are not designed to withstand those higher voltages.

[0022] 1A is a schematic cross-sectional side view of a resistive RAM module 100 having an intermediate electrode 102 with a concave closed curve profile (shown in the diagram of FIG. 1B). The intermediate electrode 102 is electrically connected to a source electrode 104 and a sink electrode 106. The source electrode 104 is patterned on a substrate layer 108 with an interlayer dielectric 110. The intermediate electrode 102 is patterned on the source electrode 104 and is embedded in an insulating layer 112. The source electrode 104, intermediate electrode 102, and sink electrode 106 may be made of, for example, titanium, titanium nitride, tungsten, or other conductive materials.

[0023] The memristor element 114 is electrically between the intermediate electrode 102 and the sink electrode 106. The memristor element 114 may be a metal oxide film with insulating properties, such as hafnium oxide. When sufficient voltage is present across the intermediate electrode 102 and the sink electrode 106, oxide defects may begin to form in the memristor element 114, giving rise to conductive filaments.

[0024] 1(B) is a schematic top view of the resistive RAM module 100. As shown in FIG. 1(B), the concave closed curve profile of the intermediate electrode 102 results in four narrow points (e.g., point 116) similar to a four-point star. As will be described later, this profile can be used to control the formation of a conductive filament to one of four locations in the memristor element 114. As can also be seen in FIG. 1(B), the closed curve profile of the intermediate electrode 102 is shared by the memristor elements 114 patterned on the intermediate electrode 102.

[0025] Finally, the sink electrode 106 is patterned on the memristor element 114, causing the shape of the sink electrode 106 to form a negative pattern of the concave closed curve profile shared by the intermediate electrode 102 and the memristor element 114. This results in the sink electrode 106 curving around the narrow points of the intermediate electrode 102, increasing the current through the memristor element 114 in those regions when a voltage is applied across the intermediate electrode 102 and the sink electrode 106. This increased current may lead to more oxide defects during voltage application, thereby increasing the likelihood of conductive filament formation at the four narrow points.

[0026] For example, the effect of the formation voltage may be significantly greater at point 116 than at region 118. In other words, the current flowing through memristor element 114 during application of the formation voltage may be higher at point 116 than at region 118. As a result, oxide defects may be more likely to form across the memristor element at point 116 than across the memristor element in region 118. Furthermore, in some embodiments, the increased current at point 116 may actually enable the formation of a conductive filament at point 116 at a lower formation voltage than would normally be required for a typical memristor element topology. In some instances, this lower formation voltage results in insufficient current passing through the memristor element in region 118 to cause oxide defects. With oxide defect formation in region 118 consequently infeasible, the location of the conductive filament becomes even more controllable.

[0027] FIG. 1(C) illustrates an exemplary result of applying a formation voltage across the intermediate electrode 102 and the sink electrode 106 at point 116. Specifically, FIG. 1(C) is a schematic, enlarged top view of a conductive filament 120 formed across the memristor element 114 between the intermediate electrode 102 and the sink electrode 106. The conductive filament 120 is a collection of oxide defects (shown as small open circles) collected at the same location as the memristor element 114. As a result, a small conductive path is formed between the intermediate electrode 102 and the sink electrode 106. As voltage continues to be applied, current continues to flow through the conductive filament 120, causing more oxide defects to form on the filament 120 and grow, decreasing the resistance across the memristor element 114 at the filament 120. Once the filament reaches a target size and resistance, the application of the formation voltage can be stopped. In this regard, applying a switching voltage across the intermediate electrode 102 and the sink electrode 106 may cause the conductive filament 120 to switch between a low resistance state (e.g., as shown in FIG. 1(C)) and a high resistance state, with oxide defects being replaced by oxide bonds.

[0028] It is noteworthy that while the profiles in FIGS. 1(A)-(C) are characterized by closed curves with only concave curves, some embodiments of the present disclosure may feature intermediate electrodes with one or more curves of different shapes. For example, in some embodiments, the intermediate electrode may feature a polygonal profile (e.g., a square, triangle, or rectangle) in which all curves are straight line segments. Some embodiments of the present disclosure may feature profiles in which the curves are convex. Some embodiments of the present disclosure may also feature profiles with a mixture of two or all of convex, concave, and straight "curves" (i.e., straight line segments). In these profiles, the point where two curves meet may increase exposure to the electric field and thus focus the formation of conductive filaments. However, a narrower point (such as the point where two concave curves meet) may be more effective at significantly increasing that exposure and therefore focusing the formation of conductive filaments.

[0029] Therefore, for the reasons explained in Figures 1(A)-(C), patterning electrodes with concave closed curve profiles in a ReRAM module can significantly increase control over the location of conductive filaments formed in the module. Furthermore, the increased current at the narrow point of such electrodes during formation voltage application allows for the use of lower formation voltages, reducing the risk of damage to other structures in the memory module.

[0030] However, patterning electrodes with concave closed-loop profiles, such as the four-point example shown in Figures 1(A)-(C), can be challenging using typical process flows. Therefore, some embodiments of the present disclosure present process flows for forming memory cells with electrodes having concave closed-loop profiles.

[0031] 2A-2X illustrate a process flow in which, for example, a four-point electrode (such as the intermediate electrode 102) may be formed in a ReRAM module. FIG. 2A is a side view of a first stage of forming a ReRAM module 200 in which a source electrode 202 is formed on a semiconductor substrate 204 along with an interlayer dielectric 206. Similarly, FIG. 2B is a top view of the first stage of forming the ReRAM module 200. The orientation of the source electrode 202 is visible in FIG. 2B, as is the interlayer dielectric 206. Furthermore, the position at which the ReRAM module 200 is shown in FIG. 2A is also defined by a line of sight 208. In some embodiments, the source electrode 202 may be part of a larger "bit line" or "word line" electrode. Suitable electrode materials for the source electrode 202 include, but are not limited to, metals such as titanium (Ti) and / or tungsten (W). In another embodiment, the source electrode 202 can include a metal nitride (e.g., titanium nitride, tantalum nitride, titanium aluminum nitride, or tungsten nitride), or a metal semiconductor compound (e.g., a metal silicide), or a combination comprising at least one of the foregoing. The metal silicide can include nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, erbium silicide, or a combination comprising at least one of the foregoing.

[0032] 2C and 2D are side and top views of a second stage in forming the ReRAM module 200. In this stage, an oxide layer 210 is deposited on top of the source electrode 202 and the interlayer dielectric 206, thereby temporarily covering the source electrode 202 and the interlayer dielectric 206. For clarity, FIG. 2D shows the location of the source electrode 202 below the oxide layer 210 with a dotted line.

[0033] 2E and 2F illustrate side and top views of a third stage of forming the ReRAM module 200. In this stage, circular hard mask deposition layers 212, 214, 216, and 218 are deposited on the oxide layer 210. In some embodiments, the hard mask deposition layers 212-218 can be nitride hard masks. While the hard mask deposition layers 212-218 are shown as circular in FIGS. 2E and 2F, other shapes may be used in some embodiments. As shown, the hard mask deposition layers 212-218 surround a central location on the source electrode 202. As illustrated in FIGS. 2G-2L, the shape of these hard mask deposition layers can affect the shape of the seed pillars and the nitride buildup on those seed pillars.

[0034] 2G and 2H are side and top views of the fourth stage of forming the ReRAM module 200. In this stage, most of the oxide layer 210 is removed, but the oxide material underneath the hard mask deposition layers 212-218 remains. This oxide material forms four seed pillars that correspond in number, location, and shape to the four hard mask deposition layers. As shown, the four seed pillars are cylindrical with radii that match the radii of the hard mask deposition layers 212-218. Only two (seed pillars 220 and 222) are visible in FIG. 2G. All four seed pillars are covered by the hard mask deposition layers 212-218 in FIG. 2H.

[0035] 2I and 2J are side and top views of a fifth stage in forming the ReRAM module 200. In this stage, a bottom nitride layer 224 is applied to the top surfaces of the interlayer dielectric 206 and the source electrode 202. Furthermore, nitride buildup on the sidewalls of the four seed pillars (including the hard mask deposition layers 212-218) forms four nitride boundaries 226, 228, 230, and 232. Because the four seed pillars forming the nitride boundaries 226-232 have circular cross-sectional profiles, the nitride boundaries 226-232 have the form of nitride rings, as shown. However, by adjusting the shape of the seed pillars, nitride boundaries of other shapes can be produced. For example, if the seed pillars have a square cross-sectional profile, the nitride boundary of the seed pillar can have an octagonal shape. If the seed pillars have a closed curve profile with convex sides, the nitride boundary on the seed pillar can have a similar profile.

[0036] The nitride interfaces 226-232 have radii large enough to partially overlap each other. As a result, the nitride interfaces 226-232 substantially form a single structure with a gap 234 between them. As shown in FIG. 2J, the gap 234 has a concave closed curve profile with four points when viewed from above. Note that it may be possible to change the shape of the gap 234 by varying the shape of the profile of one or more of the four seed pillars, and therefore the nitride interfaces 226-232. For example, if all four seed pillars have the same rectangular shape but the position of the rectangular shapes is maintained, all of the nitride interfaces 226-232 may have an octagonal profile. The gap between the nitride interfaces 226-232 may be formed by one hypotenuse of each octagon, thereby causing the gap 234 to have a rectangular profile.

[0037] 2K and 2L show side and top views of a sixth stage in forming the ReRAM module 200. In this stage, the lower nitride layer 224 is removed. This can be done, for example, by a top-down reactive ion etching process. As a result, excess nitride from the top of the nitride interfaces 226-232 is also removed, exposing some of the hard mask deposition layers 212-218. Note that removing the lower nitride layer 224 also exposes the portion of the source electrode 202 below the gap 234. As a result, the portion of the source electrode 202 visible below the gap 234 has a four-point concave closed curve profile that matches the profile of the gap 234.

[0038] 2M and 2N are side and top views of a seventh stage in forming the ReRAM module 200. At this stage, an intermediate electrode 236 is inserted into the gap 234 between the nitride boundaries 226-232. The material from which the intermediate electrode 236 can be formed can be the same as the material from which the source electrode 202 can be formed (e.g., a metal such as Ti or W, a metal nitride such as titanium nitride and tantalum nitride, or a metal-semiconductor compound such as a metal silicide).

[0039] In some embodiments, the intermediate electrode 236 may include a stack of a thin conductive layer and a thick metal layer. The conductive layer stack may include a stack structure of a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), an aluminum-containing alloy (e.g., TiAl, TiAlC, TaAl, TaAlC), titanium, tantalum, or a combination of at least one of the above. Specifically, the intermediate electrode 236 may include a stack structure of titanium nitride and TiAlC. The metal layer may include titanium, tantalum, tungsten, molybdenum, platinum, hafnium, copper, aluminum, gold, nickel, indium, or a combination including at least one of the above, specifically tungsten. The electrode material for the intermediate electrode 236 may be deposited using processes such as CVD, ALD, PVD, sputtering, evaporation, and electrochemical plating.

[0040] Intermediate electrode 236 is illustrated in FIG. 2M as a dotted line 238 because, when viewed from the perspective of FIG. 2M, intermediate electrode 236 is located behind nitride interfaces 226 and 228. In other words, intermediate electrode 236 is not directly visible from FIG. 2M. However, the top of intermediate electrode 236 is visible in FIG. 2N. As a result of being formed within gap 234, intermediate electrode 236 not only forms directly on top of electrode 202, but also has a four-point concave closed curve profile that matches the profile of gap 234. Note that intermediate electrode 236 is illustrated as being slightly shorter than nitride interfaces 226-232. While this is not strictly required, in some embodiments, intermediate electrode 236 may be as tall as nitride interfaces 226-232 or as tall as hard mask deposition layers 212-218. However, the portion of the intermediate electrode 236 that forms outside of the gap 234 may need to be removed in an etching process to prevent future shorting between the intermediate electrode 236 and the sink electrode.

[0041] 2O and 2P are side and top views of an eighth stage in forming the ReRAM module 200. In this stage, the nitride interfaces 226-232, the hard mask deposition layers 212-218, and the seed pillars 220, 222, as well as the two unnumbered seed pillars, are all etched away from the source electrode 202 and the interlayer dielectric 206. This exposes the intermediate electrode 236, as shown in FIG.

[0042] 2Q and 2R are side and top views of a ninth stage of forming the ReRAM module 200. In this stage, an insulating layer 240 (e.g., an oxide layer) is formed on the source electrode 202 and on the lower portion of the intermediate electrode 236. In some embodiments, the insulating layer 240 is a high-k dielectric. In some embodiments, the insulating layer 240 is a transition metal oxide. An example of a material that may be suitable for the ReRAM dielectric is NiO. X , Ta y O X , TiO X , HfO X , Tay O X , WO X , ZrO X , Al y O X , SrTiO X , or a combination comprising at least one of the foregoing. Conformal deposition processes include, but are not limited to, CVD, ALD, and PVD. According to an exemplary embodiment, the insulating layer 204 may have a thickness of 1 to 15 nanometers, specifically 3 to 9 nanometers, and more specifically 4 to 7 nanometers. This insulating layer 240 may serve to insulate the source electrode 202 from other conductive portions of the ReRAM module 200. In other words, current flowing through the source electrode 202 can only flow to other portions of the ReRAM module 200 via the intermediate electrode 236. For clarity, the portions of the intermediate electrode 236 and the source electrode 202 covered by the insulating layer 240 are shown here with dotted lines.

[0043] 2S and 2T are side and top views of a tenth stage of forming the ReRAM module 200. At this stage, the memristor element 242 is deposited on the insulating layer 240 and the intermediate electrode 236. Thus, the intermediate electrode 236 is completely covered by the memristor element 242 both when viewed from above in FIG. 2T and when viewed from the side in FIG. 2S (the origin is indicated by line of sight 208). Because the memristor element 242 is attached to the intermediate electrode 236, the memristor element 242 shares the four-point concave closed curve profile of the intermediate electrode 236, as shown in FIGS. 2S and 2T.

[0044] The memristor element 242 may be a metal oxide with insulating properties, such as hafnium oxide or tungsten trioxide. However, other resistive switching materials may also be used. For example, instead of a metal oxide, another metal chalcogen, such as a metal sulfide, may be used. These metal chalcogens typically form a switching material with a nominal thickness of 5 nm. However, in some embodiments, the memristor element 242 may be formed from a thinner switching material, such as hexagonal boron nitride (h-BN), molybdenum disulfide (MoS2), or tungsten disulfide (WS2).

[0045] As before, for clarity, the portions of the intermediate electrode 236 and source electrode 202 that are covered by the insulating layer 240 or the memristor element 242 are shown here with dotted lines.

[0046] 2U and 2V are side and top views of an eleventh stage of forming the ReRAM module 200. Note that the perspective from which the side view in FIG. 2U is depicted is different from that of the previous figures. As indicated by line of sight 244 in FIG. 2V, FIG. 2U is a cross-sectional side view of the ReRAM module 200. Thus, the intermediate electrode 236 is completely covered by the memristor element 242, but is visible in FIG. 2U. In the eleventh stage of forming the ReRAM module 200, a sink electrode 246 is deposited on the memristor element 242. Suitable electrode materials for the sink electrode 246 include, but are not limited to, metals such as titanium (Ti), titanium nitride (TiN), or tungsten (W), or combinations thereof. In another embodiment, the sink electrode 246 may include a metal nitride (e.g., titanium nitride, tantalum nitride, titanium aluminum nitride, or tungsten nitride), or a metal-semiconductor compound (e.g., a metal silicide), or a combination comprising at least one of the foregoing. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, erbium silicide, or a combination comprising at least one of the foregoing. The sink electrode 246 may be part of the final bit line electrode for some memory cells in the ReRAM module 200. This deposition positions the memristor element 242 electrically between the intermediate electrode 236 and the sink electrode 246, allowing for potential conductive filament formation through the memristor element 242.

[0047] 2W and 2X are side and top views of a twelfth stage of forming the ReRAM module 200. In this stage, the intermediate electrode 236 and the memristor element 242 are recessed within the sink electrode 246. Furthermore, an insulating nitride cap 248 is formed in the resulting recess on top of the intermediate electrode 236 and the memristor element 242. This can help prevent short circuits from forming between the intermediate electrode 236 and the sink electrode 246 on top of the intermediate electrode 236. These short circuits can occur, for example, if the memristor element 242 does not cover the top of the intermediate electrode 236 and if the memristor element 242 is particularly thin near its top. The insulating nitride cap 248 may not be necessary for the ReRAM module 200 to function properly, but it can prevent potential failures.

[0048] In a twelfth stage of forming the ReRAM module 200, a portion of the sink electrode 246 is etched away to form a line perpendicular to the source electrode 202. This allows the sink electrode 246 to serve as a bit line for the ReRAM module 200 in combination with the source electrode 202 serving as a word line for the ReRAM module 200. As shown, an insulating layer 250 (e.g., a dielectric layer) is formed on the ReRAM module 200 from which the portion of the sink electrode 246 has been removed.

[0049] After the twelfth step of forming the ReRAM module 200, a formation voltage can be applied between the source electrode 202 and the sink electrode 246. This application of the formation voltage can form a conductive filament at one of the four narrow points of the memristor element 242. Thus, the concave closed-loop profile of the intermediate electrode 236 and the memristor element 242 can be used to control the position of the conductive filament and prevent potential filament failure. A description and illustration of such conductive filament formation is provided by FIG. 1(C).

[0050] 2A-2X, some embodiments of the present disclosure may be embodied in a process for forming a ReRAM module. Accordingly, for purposes of understanding, FIG. 3 illustrates an exemplary method 300 for forming a resistive RAM (ReRAM) module having an intermediate electrode with a concave closed curve profile, according to some embodiments of the present disclosure.

[0051] Method 300 begins at block 302, where seed pillars are attached to the module. In some embodiments, the seed pillars may be attached to the source electrode or to the insulating layer in which the source electrode is embedded. These seed pillars may be attached, for example, by applying a layer of oxide to the source electrode and insulating layer, applying a hard mask deposition layer on top of the oxide layer, and etching away any oxide not below the hard mask deposition layer. As described in connection with Figures 2E-2H, this may result in the seed pillars having the form of pillars below the hard mask deposition layer that share the same cross-sectional profile as the hard mask deposition layer. Thus, the hard mask deposition layer may be positioned such that a portion of the source electrode is directly centered between the hard mask deposition layers, resulting in the seed pillars surrounding that portion of the source electrode. In some embodiments, one or more of the hard mask deposition layers may have a circular profile, such that the corresponding seed pillars share a circular profile (i.e., form seed pillar cylinders).

[0052] The method 300 then proceeds to block 304, where nitride buildup is applied to the sidewalls of the seed pillars. This results in the formation of nitride boundaries around overlapping seed pillars, forming gaps between the nitride boundaries. In some embodiments, one or more nitride boundaries may be formed on seed pillars having a circular profile, where the nitride boundaries have the form of nitride rings. Exemplary nitride rings are illustrated in FIGS. 2I-2M and 4 and 5.

[0053] The method 300 then proceeds to block 306, where the source electrode is exposed at the bottom of the gap between the seed pillar and the nitride buildup. Exposing the source electrode may include etching away a top layer of nitride buildup formed on top of the source electrode (and other portions of the ReRAM module). Exposing the source electrode after nitride application is shown in Figures 2K and 2L.

[0054] The method 300 then proceeds to block 308, where an intermediate electrode is applied on top of the source electrode so as to fill most or all of the gaps between the nitride buildups. This intermediate electrode may be composed of, for example, titanium, titanium nitride, tungsten, or other conductive material that is resistant to etching.

[0055] This can result in an intermediate electrode having a top-down cross-sectional profile similar or identical to the top-down cross-sectional profile of the gap between the nitride deposits. For example, the intermediate electrode can have a concave closed curve profile with several narrow points. Such profiles are illustrated in Figures 1(A)-(C), 2N-2R, 4, and 5.

[0056] The method 300 then proceeds to block 310, where the accumulated nitride and seed pillars (including the hard mask deposition layer) are removed from the ReRAM module. This may be performed, for example, by a reactive ion etching process that does not remove the intermediate electrodes.

[0057] Once the nitride and seed pillars are removed, method 300 proceeds to block 312, where a memristor element is attached to the intermediate electrode. This memristor element may be composed of hafnium oxide or other metal oxides with insulating properties. As a result of these insulating properties, when a conductive filament forms through the memristor, current may not travel through the memristor element. Furthermore, this memristor element should have a concave closed curve profile similar to the profile of the intermediate electrode, and therefore should also have at least one narrow point near the narrow point on the intermediate electrode. This may significantly increase the likelihood that a conductive filament will form at the narrow point.

[0058] In some embodiments, block 312 may further include applying an insulating layer to the ReRAM module before applying the memristor element. This may prevent potential short circuits between the source electrode (on which the intermediate electrode is formed) and the memristor element. In other words, the insulating layer may prevent any current from the source electrode from flowing to the memristor element except through the intermediate electrode.

[0059] Once the memristor element is attached to the intermediate electrode in block 312, method 300 proceeds to block 314, where a sink electrode is attached to the memristor element. This places the memristor element electrically between the intermediate electrode and the sink electrode. Because current from the source electrode should flow through the intermediate electrode to the memristor element, this also results in a voltage being applied across the source and sink electrodes, causing a current to flow through the memristor element. When this current is sufficiently large (i.e., when the voltage across the source and sink electrodes is sufficiently large), a conductive filament may then be formed across the memristor element.

[0060] In some embodiments, block 314 may include placing the memristor element and the intermediate electrode in a recessed position. This may cause the sink electrode to be slightly higher than both the memristor element and the intermediate electrode (with respect to the bottom of the ReRAM module). This may also allow for nitride deposition on the top of the memristor element and the intermediate electrode. The nitride cap may prevent an unintentional short between the top of the intermediate electrode and the top of the sink electrode. In other words, any current between the intermediate electrode and the sink electrode may be forced to flow through the conductive filament in the memristor element.

[0061] In the embodiments disclosed in Figures 1(A)-(C) and 2A-2X, an intermediate electrode having a four-point concave closed curve profile is shown. However, some embodiments of the present disclosure may utilize intermediate electrodes having concave closed curve profiles with other numbers of narrow points. As discussed above, increasing the current at the narrow points where the intermediate electrode, memristor element, and sink electrode interface with one another may increase the likelihood of forming conductive filaments at those narrow points. However, the number of narrow points is not required for the present invention.

[0062] For example, FIG. 4 illustrates an exemplary set of nitride rings 402-406 that may be used to form an intermediate electrode having a three-point concave closed curve profile, according to some embodiments of the present disclosure. In FIG. 4, a set of seed pillars 408, 410, and 412 surrounds a section of a source electrode 414. The nitride rings 402-406 are attached to the sidewalls of their seed pillars 408-412 so that they overlap, forming a gap 416 at the center between the seed pillars 408-412 and the nitride rings 402-406. Because three seed pillars are used herein, the gap 416 has a three-point concave closed curve profile. When an intermediate electrode is deposited within the gap 416, it may then be formed using three narrow points.

[0063] 5 is a top view of an exemplary set of nitride rings 502-512 that may be used to form an intermediate electrode having a six-point concave closed curve profile, according to some embodiments of the present disclosure. The overlap of the nitride rings 502-512 creates a gap 514 above the source electrode 516. By filling the gap with an intermediate electrode, an electrode having a six-point concave closed curve profile can be formed.

[0064] It should be noted that FIGS. 2A-2X, 4, and 5 illustrate that embodiments of the present disclosure may include nitride interfaces of different thicknesses and overlapping amounts. Furthermore, the location of the seed pillars in each of FIGS. 2A-2X, 4, and 5 is different, indicating that embodiments of the present disclosure may include different locations of the seed pillars and nitride interfaces. These characteristics may be altered to create gaps between nitride interfaces of different shapes and sizes, which may be used in other embodiments to create intermediate electrodes of different shapes and sizes. Furthermore, as discussed above, by altering the shape of the hard mask deposition layer used to create the seed pillars, the shape of the seed pillars on which the nitride interfaces accumulate may be customized. This, in turn, affects the nitride accumulation on the seed pillars and the shape of those nitride interfaces. This may be used to customize the shape of the intermediate electrodes formed in the gaps between those nitride interfaces.

[0065] FIG. 6 illustrates representative major components of an exemplary computer system 601 that may be used in accordance with embodiments of the present disclosure. The specific components illustrated are presented for illustrative purposes only and are not necessarily variations of such. Computer system 601 may include a processor 610, memory 620, an input / output interface (also referred to herein as I / O or I / O interface) 630, and a main bus 640. Main bus 640 may provide a communication path for other components of computer system 601. In some embodiments, main bus 640 may connect to other components, such as a dedicated digital signal processor (not shown).

[0066] The processor 610 of the computer system 601 may include one or more CPUs 612. The processor 610 may further include one or more memory buffers or caches (not shown) that provide temporary storage of instructions and data for the CPU 612. The CPU 612 may execute instructions with input provided from and result output to the cache or memory 620. The CPU 612 may include one or more circuits configured to perform one or more methods according to embodiments of the present disclosure. In some embodiments, the computer system 601 may include multiple processors 610, as is typical in larger systems. However, in other embodiments, the computer system 601 may include a single processor with a single CPU 612.

[0067] The memory 620 of the computer system 601 may include a memory controller 622 and one or more memory modules (not shown) for temporary or permanent storage of data. In some embodiments, the memory 620 may include random-access semiconductor memory, storage devices, or storage media (either volatile or non-volatile) for storing data and programs. The memory controller 622 may communicate with the processor 610 and facilitate the storage and retrieval of information in the memory modules. The memory controller 622 may communicate with the I / O interface 630 and facilitate the storage and retrieval of inputs or outputs in the memory modules. In some embodiments, the memory modules may be dual-in-line memory modules.

[0068] I / O interface 630 may include an I / O bus 650, a terminal interface 652, a storage interface 654, an I / O device interface 656, and a network interface 658. I / O interface 630 may connect main bus 640 to I / O bus 650. I / O interface 630 may route instructions and data from processor 610 and memory 620 to various interfaces of I / O bus 650. I / O interface 630 may further route instructions and data from the various interfaces of I / O bus 650 to processor 610 and memory 620. The various interfaces may include terminal interface 652, storage interface 654, I / O device interface 656, and network interface 658. In some embodiments, the various interfaces may include a subset of the interfaces described above (e.g., an embedded computer system in an industrial application may not include terminal interface 652 and storage interface 654).

[0069] Logical modules throughout computer system 601, including but not limited to memory 620, processor 610, and I / O interface 630, may communicate faults and changes to one or more components to a hypervisor or operating system (not shown). The hypervisor or operating system may allocate the various resources available in computer system 601 and track the location of data and processes within memory 620 assigned to the various CPUs 612. In embodiments that combine or reconfigure elements, aspects of the functionality of the logical modules may be combined or redistributed. These variations will be apparent to those skilled in the art.

[0070] The present invention may be a system, method, or computer program product, or combination thereof, at any possible level of technical detail, including a computer-readable storage medium having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0071] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical encryption devices such as punch cards or grooved ridge structures with instructions recorded on them, and any suitable combination of the above. As used herein, a computer-readable storage medium should not be construed as being itself a primary signal, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through a fiber optic cable), or an electrical signal transmitted by an electrical wire.

[0072] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or any combination thereof. This network may comprise copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or any combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0073] Computer-readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer, and partially on a remote computer, or entirely on a remote computer or server. In the latter situation, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer readable program instructions to personalize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the present invention.

[0074] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0075] The computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to manufacture a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in the blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may further be stored on a computer-readable storage medium that causes a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium having the instructions stored thereon comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in the blocks of the flowcharts and / or block diagrams.

[0076] The computer-readable program instructions may further be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be executed on the computer, other programmable apparatus, or other device to create a computer-implemented process, such that the instructions, when executed on the computer, other programmable apparatus, or other device, perform the functions / acts specified in the flowchart and / or block diagram blocks.

[0077] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specialized logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may actually be implemented as a single step, executed simultaneously, nearly simultaneously, partially, or entirely overlapping in time, or the blocks may even be executed in reverse order, depending on the functionality involved. It will also be recognized that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by dedicated hardware-based systems that perform specialized functions or operations or execute a combination of dedicated hardware and computer instructions.

[0078] The description of various embodiments of the present invention has been provided for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been chosen to best explain the principles of the embodiments, practical applications or technical improvements of existing technologies, or to enable others of ordinary skill in the art to which the disclosure pertains to understand the embodiments disclosed herein.

Claims

1. A source electrode; an intermediate electrode formed perpendicular to an upper surface of the source electrode; a memristor element, wherein the intermediate electrode is a deposition layer deposited on a side surface of the intermediate electrode such that the intermediate electrode is electrically between the source electrode and the memristor element; a sink electrode in contact with the memristor element such that the memristor element is electrically between the intermediate electrode and the sink electrode; Equipped with the intermediate electrode has a closed curve profile with at least one point; Resistive RAM module.

2. 2. The resistive RAM module according to claim 1, wherein the closed curve profile is a concave closed curve profile.

3. The resistive RAM module of claim 2 , wherein the memristor elements share the concave closed curve profile.

4. 4. The resistive RAM module of claim 3, wherein said sink electrode forms a negative pattern of said concave closed curve profile.

5. The resistive RAM module of claim 2 , wherein the concave closed curve profile has four points.

6. The resistive RAM module of claim 1 , further comprising a nitride cap formed on the intermediate electrode and the memristor element.

7. 1. A method of forming a ReRAM module, the method comprising: applying a set of seed pillars to a surface of a layer of the ReRAM module, the seed pillars being perpendicular to the surface, the layer comprising a source electrode embedded in an interlayer dielectric; depositing nitride on the sidewalls of the seed pillar such that a nitride buildup results in a set of nitride boundaries surrounding the seed pillar, each nitride boundary in the set partially overlapping at least two other nitride boundaries such that a gap is formed in the center of the nitride boundary; depositing an intermediate electrode on top of the source electrode and in the gap; removing the nitride and the seed pillar; depositing a memristor element on the intermediate electrode; depositing a sink electrode on the memristor element; A method comprising:

8. disposing the memristor element and the intermediate electrode in a recessed position within the sink electrode to form a recess; depositing a nitride cap on top of the memristor element and the intermediate electrode within the recess; The method of claim 7 further comprising:

9. The method of claim 7 , wherein depositing the intermediate electrode comprises filling the gap with the intermediate electrode.

10. The method of claim 7 , wherein the intermediate electrode has a concave closed curve profile.

11. The method of claim 10 , wherein the memristor elements share the concave closed curve profile.

12. The method of claim 11 , wherein the sink electrode forms a negative pattern of the concave closed curve profile.

13. The method of claim 10 , wherein the concave closed curve profile has three points.

14. 14. The method of claim 13, further comprising applying a formation voltage between the source electrode and the sink electrode, the formation voltage causing a conductive filament to form at one of the narrow points.

15. 1. A computer program product comprising a computer-readable storage medium having program instructions embodied by the computer-readable storage medium, the program instructions causing the computer to: applying a set of seed pillars to a surface of a layer of a ReRAM module, the seed pillars being perpendicular to the surface, the layer comprising a source electrode embedded in an interlayer dielectric; depositing nitride on the sidewalls of the seed pillar such that a nitride buildup results in a set of nitride boundaries surrounding the seed pillar, each nitride boundary in the set partially overlapping at least two other nitride boundaries such that a gap is formed in the center of the nitride boundary; depositing an intermediate electrode on top of the source electrode and in the gap; removing the nitride and the seed pillar; depositing a memristor element on the intermediate electrode; depositing a sink electrode on the memristor element; a computer program product executable by said computer to cause said computer to perform

16. 16. The computer program product of claim 15, wherein the intermediate electrode has a concave closed curve profile.

17. 16. The computer program product of claim 15, wherein the memristor elements share a concave closed curve profile.

18. 17. The computer program product of claim 16, wherein the sink electrode forms a negative pattern of the concave closed curve profile.

19. 17. The computer program product of claim 16, wherein the concave closed curve profile has six points.

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