SiC semiconductor device

Abstract

This SiC semiconductor device includes: an SiC chip having a main surface; and an n-type drift region which is formed on the outer layer of the main surface and which has an impurity concentration that has been adjusted using at least two types of pentavalent elements.

Description

[Technical Field]

[0001] This application corresponds to Patent Application No. 2021-014602 filed with the Japan Patent Office on February 1, 2021, the entire disclosure of which is incorporated herein by reference. The present invention relates to a SiC semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a SiC-SBD including a SiC substrate and a SiC epitaxial layer formed on the SiC substrate. Patent Document 2 discloses a semiconductor device including a SiC substrate and n-type drift regions and p-type pillar regions formed alternately on the SiC substrate in a direction perpendicular to the thickness direction of the SiC substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2008 / 0237608 [Patent Document 2] US Patent Application Publication No. 2019 / 0148485 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a SiC semiconductor device capable of improving electrical characteristics. [Means for solving the problem]

[0005] One embodiment provides a SiC semiconductor device including a SiC chip having a main surface, and an n-type drift region formed in a surface layer portion of the main surface and having an impurity concentration adjusted by at least two kinds of pentavalent elements.

[0006] One embodiment provides a SiC semiconductor device including a SiC chip having a main surface, and a p-type drift region formed in a surface layer portion of the main surface and having an impurity concentration adjusted by a trivalent element other than boron.

[0007] One embodiment provides a SiC semiconductor device including: a SiC chip having a main surface; an n-type drift region formed in a surface layer portion of the main surface and having an impurity concentration adjusted by at least two pentavalent elements; and a p-type impurity region formed in the drift region so as to form a p-n junction with the drift region.

[0008] One embodiment provides a SiC semiconductor device including: a SiC chip having a main surface; an n-type drift region formed in a surface layer portion of the main surface; and a p-type impurity region formed in the drift region so as to form a p-n junction with the drift region, the p-type impurity region having an impurity concentration adjusted by a trivalent element other than boron.

[0009] One embodiment provides a SiC semiconductor device including: a SiC chip having a main surface; a p-type drift region formed in a surface layer portion of the main surface and having an impurity concentration adjusted by a trivalent element other than boron; and an n-type impurity region formed in the drift region so as to form a p-n junction with the drift region and having an impurity concentration adjusted by a pentavalent element other than phosphorus and nitrogen.

[0010] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing the SiC semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. [Figure 3] FIG. 3 is a graph showing the impurity concentration in the SiC chip shown in FIG. [Figure 4A] FIG. 4A is a cross-sectional view showing a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 4B] FIG. 4B is a cross-sectional view showing a step subsequent to FIG. 4A. [Figure 4C] FIG. 4C is a cross-sectional view showing a step subsequent to FIG. 4B. [Figure 4D] FIG. 4D is a cross-sectional view showing a step subsequent to FIG. 4C. [Figure 5] FIG. 5 is a cross-sectional view for specifically explaining the step of FIG. 4D. [Figure 6] FIG. 6 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a graph showing the impurity concentration in the SiC chip shown in FIG. [Figure 8A] FIG. 8A is a cross-sectional view showing a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 8B] FIG. 8B is a cross-sectional view showing a step subsequent to FIG. 8A. [Figure 9] FIG. 9 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a graph showing the impurity concentration in the SiC chip shown in FIG. [Figure 11] FIG. 11 corresponds to FIG. 9 and is a cross-sectional view showing the SiC semiconductor device according to the fourth embodiment. [Figure 12] FIG. 12 is a graph showing the impurity concentration in the SiC chip shown in FIG. [Figure 13] FIG. 13 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the fifth embodiment. [Figure 14] FIG. 14 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the sixth embodiment. [Figure 15] FIG. 15 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the seventh embodiment. [Figure 16] FIG. 16 corresponds to FIG. 2 and is a cross-sectional view showing the SiC semiconductor device according to the eighth embodiment. [Figure 17] FIG. 17 is a plan view showing the SiC semiconductor device according to the ninth embodiment. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. [Figure 19A] FIG. 19A is a cross-sectional view showing a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 19B] FIG. 19B is a cross-sectional view showing a step subsequent to that shown in FIG. 19A. [Figure 20] FIG. 20 corresponds to FIG. 18 and is a cross-sectional view showing the SiC semiconductor device according to the tenth embodiment. [Figure 21A] FIG. 21A is a cross-sectional view showing a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 21B] FIG. 21B is a cross-sectional view showing a step subsequent to that shown in FIG. 21A. [Figure 22] FIG. 22 corresponds to FIG. 18 and is a cross-sectional view showing the SiC semiconductor device according to the eleventh embodiment. [Figure 23] FIG. 23 corresponds to FIG. 18 and is a cross-sectional view showing the SiC semiconductor device according to the twelfth embodiment. [Figure 24] FIG. 24 is a plan view showing a structure in which the functional device according to the first embodiment is applied to the SiC semiconductor device according to the first embodiment. [Figure 25] FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. [Figure 26] FIG. 26 is a plan view of the SiC chip shown in FIG. [Figure 27] FIG. 27 is a plan view showing a structure in which the functional device according to the second embodiment is applied to the SiC semiconductor device according to the tenth embodiment. [Figure 28] FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in FIG. [Figure 29] FIG. 29 is a plan view of the SiC chip shown in FIG. [Figure 30] FIG. 30 is a plan view showing a structure in which a functional device according to a third embodiment is applied to the SiC semiconductor device according to the first embodiment. [Figure 31] FIG. 31 is a cross-sectional view taken along line XXXI-XXXI shown in FIG. [Figure 32] FIG. 32 is an enlarged view of region XXXII shown in FIG. [Figure 33] 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in FIG. [Figure 34] FIG. 34 is an enlarged view of region XXXIV shown in FIG. [Figure 35] FIG. 35 is a plan view showing a structure in which the functional device according to the fourth embodiment is applied to the SiC semiconductor device according to the tenth embodiment. [Figure 36] FIG. 36 is an enlarged view of area XXXVI shown in FIG. [Figure 37] FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in FIG. [Figure 38] FIG. 38 is a cross-sectional view showing a structure in which the functional device according to the fifth embodiment is applied to the SiC semiconductor device according to the tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] The attached drawings are not strictly illustrative but are schematic diagrams and are not necessarily to scale. In the attached drawings, in order to clarify the structure of each semiconductor region, the conductivity type (n-type or p-type) of each semiconductor region is indicated in parentheses along with the elements (element symbols) that make up that conductivity type. The terms "substantially equal" and "substantially constant" in this specification include cases where the numerical value of the measurement object (measurement point) is completely identical to the numerical value of the comparison object (comparison point), as well as cases where the numerical value of the measurement object (measurement point) is within a range of 0.9 to 1.1 times the numerical value of the comparison object (comparison point).

[0013] Fig. 1 is a plan view showing a SiC semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a graph showing the impurity concentration in the SiC chip 2 shown in Fig. 2. In Fig. 3, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0014] 1 and 2, the SiC semiconductor device 1A includes a SiC chip 2 formed in a rectangular parallelepiped shape. The SiC chip 2 may also be referred to as a "chip" or a "semiconductor chip." In this embodiment, the SiC chip 2 is made of a hexagonal SiC (silicon carbide) single crystal. The hexagonal SiC single crystal has a plurality of polytypes including a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, a 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the SiC chip 2 is made of a 4H-SiC single crystal, but other polytypes are not excluded.

[0015] The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from their normal direction Z (hereinafter simply referred to as "plan view"). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed from the plan.

[0016] The first main surface 3 and the second main surface 4 each face the c-plane ((0001) plane) of the SiC single crystal. Preferably, the first main surface 3 is formed by the silicon surface of the SiC single crystal, and the second main surface 4 is formed by the carbon surface of the SiC single crystal. The first main surface 3 and the second main surface 4 have an off-angle θ inclined at a predetermined angle in a predetermined off-direction D relative to the c-plane. The off-direction D is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle θ may be greater than 0° and not greater than 10°. The off-angle θ is preferably not greater than 5°. It is particularly preferable that the off-angle θ be 2° or greater and 4.5° or less.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. In other words, the first direction X is the off-direction D.

[0018] The SiC semiconductor device 1A includes an n-type base region 6 formed in a region on the second main surface 4 side (surface layer portion of the second main surface 4) in the SiC chip 2. The base region 6 is formed in a layer extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The base region 6 has an impurity concentration adjusted by a first impurity (=n-type impurity) made of a pentavalent element. The first impurity is preferably composed of one type of pentavalent element. The first impurity may be any one of the pentavalent elements phosphorus (P), nitrogen (N), arsenic (As), and antimony (Sb). The first impurity is preferably a pentavalent element other than phosphorus. In this embodiment, the first impurity is nitrogen.

[0019] 3, the base region 6 has a first concentration C1 that is substantially constant in the thickness direction. The first concentration C1 is 1×10 18 cm -3 More than 1×10 21 cm -3 The base region 6 may have a thickness of 5 μm or more and 300 μm or less. The thickness of the base region 6 is preferably 50 μm or more and 250 μm or less. In this embodiment, the base region 6 is formed on a SiC substrate.

[0020] The SiC semiconductor device 1A includes an n-type buffer region 7 formed in a region on the first main surface 3 side with respect to the base region 6 within the SiC chip 2. The buffer region 7 is formed in the middle of the SiC chip 2 in the thickness direction, spaced apart from the first main surface 3 toward the second main surface 4. The buffer region 7 is formed in a layer extending along the first main surface 3 and is exposed from the first to fourth side surfaces 5A to 5D. The buffer region 7 contains a pentavalent element and has an impurity concentration that decreases (specifically, gradually decreases) toward the first main surface 3. The buffer region 7 preferably contains any one of the pentavalent elements phosphorus, nitrogen, arsenic, and antimony. The buffer region 7 preferably contains a pentavalent element other than phosphorus.

[0021] Referring to FIG. 3, in this form, the buffer region 7 has an impurity concentration adjusted by the first impurity (= nitrogen), and has a concentration gradient (concentration distribution) that decreases (specifically, gradually decreases) from the first concentration C1 to a second concentration C2 (C2 < C1) less than the first concentration C1 from the base region 6 toward the first main surface 3. The second concentration C2 may be 1×10 14 cm -3 or more and 1×10 16 cm -3 or less. The buffer region 7 may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the buffer region 7 is preferably 1 μm or more and 3 μm or less. In this form, the buffer region 7 is formed in a SiC epitaxial layer.

[0022] The SiC semiconductor device 1A includes an n-type drift region 8 formed in the surface layer portion of the first main surface 3. The drift region 8 is formed in a region between the first main surface 3 and the buffer region 7 within the SiC chip 2. The drift region 8 is formed in a layer extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The drift region 8 is concentration-adjusted by at least two kinds of pentavalent elements.

[0023] That is, the drift region 8 includes a region in which at least two pentavalent elements are mixed in the region between the first main surface 3 and the buffer region 7. The drift region 8 preferably contains a pentavalent element other than phosphorus and has an impurity concentration adjusted by the pentavalent element other than phosphorus. The drift region 8 particularly preferably contains nitrogen as a pentavalent element and a pentavalent element other than nitrogen. The drift region 8 preferably contains at least one of arsenic and antimony as a pentavalent element other than phosphorus and nitrogen.

[0024] Referring to FIG. 3, the drift region 8 has an impurity concentration that increases toward the first main surface 3. Specifically, the drift region 8 has a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the second concentration C2 to a third concentration C3 (C2 < C3) exceeding the second concentration C2 from the buffer region 7 toward the first main surface 3. The third concentration C3 is the peak concentration of the drift region 8.

[0025] The third concentration C3 only needs to be located in the vicinity (surface layer portion) of the first main surface 3 and does not necessarily have to coincide with the first main surface 3. The third concentration C3 is equal to or less than the first concentration C1 (C2 < C3 ≦ C1). The third concentration C3 is preferably 10 times or more the second concentration C2. The third concentration C3 is preferably less than the first concentration C1 (C3 < C1). The third concentration C3 is 1×10 15 cm -3 or more and may be 1×10 17 cm -3 or less.

[0026] The drift region 8 has a base concentration CA and an additional concentration CB. The additional concentration CB complements the base concentration CA. The impurity concentration of the drift region 8 consists of the sum of the base concentration CA and the additional concentration CB. The base concentration CA is due to the first impurity that is a pentavalent element. The first impurity is a pentavalent element other than phosphorus (in this form, nitrogen). The additional concentration CB is due to the second impurity that is a pentavalent element other than the first impurity. The second impurity is a pentavalent element other than phosphorus and nitrogen. The second impurity is, in this form, at least one of arsenic and antimony.

[0027] The drift region 8 has a base concentration CA (first impurity) and an additional concentration CB (second impurity) in regions on the side of the first main surface 3 and the side of the second main surface 4 (buffer region 7 side) with respect to the intermediate portion MID between the first main surface 3 and the buffer region 7. In this form, the drift region 8 has the base concentration CA (first impurity) and the additional concentration CB (second impurity) throughout the entire thickness direction.

[0028] The base concentration CA has a substantially constant concentration distribution in the thickness direction. In this form, the base concentration CA is approximately equal to the second concentration C2 which is the lower limit value of the concentration of the buffer region 7 (CA≒C2). Of course, the base concentration CA may have a concentration gradient (concentration distribution) that increases from the buffer region 7 toward the first main surface 3. The additional concentration CB has a concentration distribution that increases (specifically, gradually increases) toward the first main surface 3. The additional concentration CB exceeds the base concentration CA (CA<CB). The additional concentration CB is preferably 10 times or more the base concentration CA. The additional concentration CB is preferably less than the first concentration C1 (CA<CB<C1).

[0029] The drift region 8 preferably has a thickness exceeding the thickness of the buffer region 7. The drift region 8 may have a thickness of 1 μm or more and 25 μm or less. The drift region 8 may have a thickness belonging to any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less. The drift region 8 particularly preferably has a thickness of 1 μm or more and 10 μm or less. In this form, the drift region 8 is formed in the SiC epitaxial layer.

[0030] The SiC semiconductor device 1A includes a functional device 9 formed on the first main surface 3 side by utilizing the drift region 8. In FIGS. 1 and 2, the functional device 9 is simply shown by a two-dot chain line. The functional device 9 has at least a part of the drift region 8 as a carrier mobility region (=current path). The functional device 9 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the SiC chip 2.

[0031] The functional device 9 may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a semiconductor passive device. The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET). The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode (SBD), and a fast recovery diode (FRD). The semiconductor passive device may include at least one of a resistor and a capacitor.

[0032] The functional device 9 may include a circuit network (e.g., an integrated circuit such as an LSI) in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a semiconductor passive device are combined. The functional device 9 typically includes at least one of a SiC-MISFET and a SiC-SBD.

[0033] As described above, the SiC semiconductor device 1A includes the SiC chip 2 and the drift region 8. The SiC chip 2 has a first main surface 3. The drift region 8 is formed in a surface layer portion of the first main surface 3 and has an impurity concentration adjusted by at least two pentavalent elements. The at least two pentavalent elements are mixed in a predetermined thickness range of the surface layer portion of the first main surface 3. With this structure, the impurity concentration due to one pentavalent element can be complemented by the impurity concentration due to the other pentavalent element. This allows the drift region 8 to have an impurity concentration with reduced variation from the target concentration. Therefore, a SiC semiconductor device 1A with improved electrical characteristics can be provided.

[0034] Drift region 8 preferably has an impurity concentration adjusted to increase toward first main surface 3. According to this structure, drift region 8 can be appropriately formed with at least two kinds of pentavalent elements, having a concentration gradient (concentration distribution) that increases toward first main surface 3.

[0035] Drift region 8 preferably has an impurity concentration adjusted by a pentavalent element other than phosphorus. Drift region 8 preferably contains nitrogen as a pentavalent element and a pentavalent element other than nitrogen. Drift region 8 preferably has a base concentration CA due to a first impurity that is a pentavalent element and an additional concentration CB due to a second impurity that is a pentavalent element other than the first impurity.

[0036] The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably nitrogen. The second impurity is preferably a pentavalent element other than phosphorus. The second impurity is preferably at least one of arsenic and antimony. The base concentration CA preferably has a substantially constant concentration distribution in the thickness direction. The additional concentration CB preferably has a concentration distribution that increases toward the first main surface 3.

[0037] Drift region 8 may have a thickness of 1 μm or more and 25 μm or less. With this structure, the impurity concentration of drift region 8 can be appropriately adjusted by at least two pentavalent elements. The thickness of drift region 8 is preferably 1 μm or more and 10 μm or less.

[0038] The SiC chip 2 is preferably made of a hexagonal SiC single crystal. The first main surface 3 preferably faces the c-plane of the SiC single crystal. The first main surface 3 preferably has an off-angle θ of 10° or less with respect to the c-plane. The off-angle θ preferably has an off-direction D aligned with the a-axis direction of the SiC single crystal. The drift region 8 is preferably formed in a SiC epitaxial layer. The SiC semiconductor device 1A preferably includes a functional device 9 formed on the first main surface 3 using at least a portion of the drift region 8. This structure can improve the electrical characteristics of the functional device 9.

[0039] Figures 4A to 4D are cross-sectional views showing a method for manufacturing the SiC semiconductor device 1A shown in Figure 1. Figure 5 is a cross-sectional view for specifically explaining the step of Figure 4D.

[0040] Referring to FIG. 4A, an n-type SiC wafer 10 is prepared. The SiC wafer 10 is a disc-shaped single crystal plate. The SiC wafer 10 has an impurity concentration adjusted by a first impurity. The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably composed of one type of pentavalent element. The first impurity is preferably one of nitrogen, arsenic, and antimony. In this embodiment, the first impurity is nitrogen. The SiC wafer 10 has a first concentration C1 that is approximately constant in the thickness direction. The SiC wafer 10 forms the foundation of the base region 6.

[0041] The SiC wafer 10 has a first wafer main surface 11 on one side and a second wafer main surface 12 on the other side. The first wafer main surface 11 and the second wafer main surface 12 face the c-plane of the SiC single crystal. The c-plane includes the silicon face ((0001) face) and the carbon face ((000-1) face) of the SiC single crystal. It is preferable that the first wafer main surface 11 faces the silicon face and the second wafer main surface 12 faces the carbon face. The first wafer main surface 11 and the second wafer main surface 12 each face the c-plane of the SiC single crystal. It is preferable that the first wafer main surface 11 is formed by the silicon face of the SiC single crystal and the second wafer main surface 12 is formed by the carbon face of the SiC single crystal.

[0042] The first wafer main surface 11 and the second wafer main surface 12 have an off angle θ inclined at a predetermined angle in a predetermined off direction D with respect to the c-plane. The off direction D is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle θ may be greater than 0° and not greater than 10°. The off angle θ is preferably not greater than 5°. The off angle θ is particularly preferably not less than 2° and not greater than 4.5°. The SiC wafer 10 may have a thickness of not less than 50 μm and not greater than 500 μm. The thickness of the SiC wafer 10 is adjusted by grinding the second wafer main surface 12.

[0043] Referring to FIG. 4B, an n-type first SiC epitaxial layer 13 is formed on the first wafer main surface 11 by epitaxial growth. The first SiC epitaxial layer 13 is formed in a manner that inherits the off-direction D and off-angle θ from the SiC wafer 10. The first SiC epitaxial layer 13 is formed by epitaxially growing SiC on the first wafer main surface 11 while introducing a pentavalent element (first impurity in this form). The impurity concentration of the first SiC epitaxial layer 13 is adjusted so that it decreases (specifically, gradually decreases) from a first concentration C1 to a second concentration C2 starting from the SiC wafer 10. The first SiC epitaxial layer 13 forms the basis of the buffer region 7.

[0044] 4C, an n-type second SiC epitaxial layer 14 is formed on the first SiC epitaxial layer 13 by epitaxial growth. The second SiC epitaxial layer 14 is formed in a manner that inherits the off-direction D and off-angle θ from the first SiC epitaxial layer 13. The second SiC epitaxial layer 14 is formed by epitaxially growing SiC on the first SiC epitaxial layer 13 while introducing a pentavalent element (first impurity in this form). The impurity concentration of the second SiC epitaxial layer 14 is adjusted to be approximately constant in the crystal growth direction.

[0045] In this embodiment, the impurity concentration of the second SiC epitaxial layer 14 is adjusted to maintain a substantially constant second concentration C2 from the first SiC epitaxial layer 13 toward the crystal growth direction. Of course, the impurity concentration of the second SiC epitaxial layer 14 may also be adjusted to increase (specifically, gradually increase) from the first SiC epitaxial layer 13 toward the crystal growth direction. The second SiC epitaxial layer 14 forms the base of the drift region 8. In other words, the second SiC epitaxial layer 14 is formed to have a lower concentration than the target concentration of the drift region 8.

[0046] 4D, a pentavalent element is implanted into second SiC epitaxial layer 14 by ion implantation to form n-type drift region 8 having a target concentration. In this step, the pentavalent element is implanted throughout second SiC epitaxial layer 14 so that the impurity concentration increases (specifically, gradually increases) in the crystal growth direction. This forms n-type drift region 8 having a concentration gradient (target concentration) that increases from second concentration C2 to third concentration C3 in the crystal growth direction.

[0047] Referring to FIG. 5, the ion implantation method in this embodiment is a channeling implantation method. In the channeling implantation method, a pentavalent element is implanted into the second SiC epitaxial layer 14 along the direction of the sparse atomic arrangement of the SiC single crystal (=crystal axis direction). Specifically, the crystal axis of the SiC single crystal is the c-axis ( <0001> This method reduces the probability that the pentavalent element will collide with constituent atoms of the SiC single crystal, allowing the pentavalent element to be implanted deep into the second SiC epitaxial layer 14. In this process, the pentavalent element is implanted into the region on the main surface (crystal growth surface) side of the second SiC epitaxial layer 14 and the region on the SiC wafer 10 side, relative to the intermediate portion of the second SiC epitaxial layer 14.

[0048] In this step, a second impurity consisting of a pentavalent element different from the first impurity (=nitrogen) contained in the second SiC epitaxial layer 14 is implanted. In this embodiment, the second impurity is at least one of arsenic and antimony. This forms a drift region 8 having a base concentration CA (=second concentration C2) due to the first impurity and an additional concentration CB due to the second impurity. The base concentration CA has a substantially constant concentration distribution in the thickness direction. The additional concentration CB has a concentration distribution that increases toward the first main surface 3.

[0049] The implantation depth of the second impurity into the second SiC epitaxial layer 14 is precisely adjusted by adjusting the implantation energy, implantation temperature, and implantation angle of the second impurity. The implantation energy of the second impurity may be adjusted in the range of 10 keV to 1000 keV (preferably 100 keV or higher). The implantation temperature of the second impurity may be adjusted in the range of 300°C to 1000°C.

[0050] The implantation angle of the second impurity is set within a range of ±5° with the crystal axis (=c-axis) of the SiC single crystal as the reference (=0°). The implantation angle of the second impurity is preferably set within a range of ±2°. In this embodiment, the second SiC epitaxial layer 14 (SiC wafer 10) has an off angle θ tilted to a predetermined off direction D. Therefore, the implantation angle of the second impurity with respect to the second SiC epitaxial layer 14 or the tilt angle of the second SiC epitaxial layer 14 with respect to the implantation direction of the second impurity is adjusted according to the off direction D and the off angle θ.

[0051] Of course, the second impurity may be pentavalent phosphorus or nitrogen. However, phosphorus or nitrogen have the property of being difficult to implant into deep regions of second SiC epitaxial layer 14 by channeling implantation. Therefore, the second impurity is preferably at least one of arsenic and antimony.

[0052] After the second impurity is implanted, annealing is performed to electrically activate the second impurity and simultaneously repair lattice defects and the like that have occurred in second SiC epitaxial layer 14. The annealing temperature for second SiC epitaxial layer 14 may be 500°C or higher and 2000°C or lower. This forms drift region 8. Thereafter, functional device 9 is formed using a part of drift region 8 on the main surface (crystal growth surface) side of second SiC epitaxial layer 14. Through the processes including those described above, SiC semiconductor device 1A is manufactured.

[0053] It is also conceivable to form the second SiC epitaxial layer 14 having the target concentration of the drift region 8 by epitaxial growth from the beginning. However, this method makes it difficult to accurately control the amount of pentavalent element introduced, resulting in the formation of a drift region 8 having a relatively large concentration variation relative to the target concentration. This problem becomes more pronounced as the second SiC epitaxial layer 14 becomes thicker. Furthermore, this problem becomes more pronounced as the impurity concentration of the second SiC epitaxial layer 14 becomes higher.

[0054] In contrast, the manufacturing method of the SiC semiconductor device 1A includes a first step of preparing an n-type second SiC epitaxial layer 14 and a second step of forming an n-type drift region 8. In the first step, a low-concentration n-type second SiC epitaxial layer 14 is prepared. Specifically, the impurity concentration of the second SiC epitaxial layer 14 is lower than the target concentration of the drift region 8. In the second step, a pentavalent element (n-type impurity) is implanted into the second SiC epitaxial layer 14 by ion implantation, thereby forming an n-type drift region 8 having the target concentration.

[0055] According to this manufacturing method, the impurity concentration of the second SiC epitaxial layer 14 is compensated for by the increased impurity concentration due to the ion implantation method. Compared to epitaxial growth methods that involve the introduction of impurities, the ion implantation method allows for more appropriate adjustment of the amount of introduced impurities. This reduces the concentration variation in the drift region 8 relative to the target concentration. Therefore, it is possible to manufacture and provide a SiC semiconductor device 1A with improved electrical characteristics.

[0056] In the manufacturing method of the SiC semiconductor device 1A, a second SiC epitaxial layer 14 having an impurity concentration adjusted by a first impurity may be prepared. In this case, the drift region 8 may be formed by implanting a second impurity different from the first impurity into the second SiC epitaxial layer 14. The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably nitrogen. The second impurity is preferably a pentavalent element other than phosphorus. The second impurity is preferably at least one of arsenic and antimony.

[0057] The ion implantation method is preferably a channeling implantation method in which the second impurity is implanted along the crystal axis of the second SiC epitaxial layer 14. The second impurity is preferably implanted into the second SiC epitaxial layer 14 at an implantation angle of ±5° or less with respect to the crystal axis of the SiC single crystal. The crystal axis of the SiC single crystal is preferably the c-axis. The second SiC epitaxial layer 14 preferably has an off-angle θ of 10° or less with respect to the c-plane of the SiC single crystal. The off-angle θ preferably has an off-direction D along the a-axis direction of the SiC single crystal.

[0058] Fig. 6 corresponds to Fig. 2 and is a cross-sectional view showing a SiC semiconductor device 1B according to the second embodiment. Fig. 7 is a graph showing the impurity concentration in the SiC chip 2 shown in Fig. 6. In Fig. 7, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth. Hereinafter, structures corresponding to those described in the first embodiment are given the same reference numerals, and their description will be omitted.

[0059] 6 and 7, similar to SiC semiconductor device 1A, SiC semiconductor device 1B includes SiC chip 2, n-type base region 6, n-type buffer region 7, n-type drift region 8, and functional device 9. In this embodiment, drift region 8 includes first region 8a and second region 8b formed in this order from the bottom toward first main surface 3.

[0060] The first region 8a is a region having an impurity concentration adjusted by one type of pentavalent element, and is formed in a surface layer portion of the first main surface 3, spaced apart from the first main surface 3. Specifically, the first region 8a is formed in a layer shape extending along the first main surface 3 on the buffer region 7, and is exposed from the first to fourth side surfaces 5A to 5D. The first region 8a is formed in a region on the second main surface 4 side (the buffer region 7 side) with respect to the intermediate portion MID. The first region 8a is preferably formed at an interval from the intermediate portion MID toward the second main surface 4.

[0061] The first region 8a contains a first impurity and has a base concentration CA due to the first impurity. The first impurity is the same as in the first embodiment. That is, the first impurity may be any one of phosphorus, nitrogen, arsenic, and antimony. The first impurity is preferably a pentavalent element other than phosphorus. In this embodiment, the first impurity is nitrogen. The base concentration CA is approximately equal to the lower limit of the concentration (=second concentration C2) of the buffer region 7 (CA≒C2). The first region 8a has an approximately constant concentration distribution in the thickness direction. Of course, the first region 8a may have a concentration gradient (concentration distribution) that increases from the buffer region 7 (second concentration C2) toward the first main surface 3.

[0062] The second region 8b is a region having an impurity concentration adjusted by at least two kinds of pentavalent elements. The second region 8b is formed in a layer shape extending along the first main surface 3 in a region between the first main surface 3 and the first region 8a, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The second region 8b is formed in a region on the first main surface 3 side with respect to the intermediate portion MID. It is preferable that the second region 8b is also formed in a region on the second main surface 4 side, across the intermediate portion MID.

[0063] The second region 8b has a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the base concentration CA (≈second concentration C2) in the first region 8a to a third concentration C3. In this embodiment, the second region 8b has a base concentration CA due to the first impurity and an additional concentration CB due to a second impurity consisting of a pentavalent element other than the first impurity. The second impurity is the same as in the first embodiment. That is, the second impurity preferably includes at least one of arsenic and antimony.

[0064] The basic concentration CA of the second region 8b has a substantially constant concentration distribution in the thickness direction, as in the first embodiment. Of course, the basic concentration CA of the second region 8b may have a concentration gradient (concentration distribution) that increases toward the first main surface 3. The additional concentration CB of the second region 8b has a concentration gradient (concentration distribution) that increases toward the first main surface 3, as in the first embodiment. The second region 8b has a resistance value that is less than the resistance value of the first region 8a. In other words, the first region 8a is a high-resistance region, and the second region 8b is a low-resistance region.

[0065] As described above, SiC semiconductor device 1B also provides the same effects as those described for SiC semiconductor device 1A.

[0066] Figures 8A and 8B are cross-sectional views showing a method for manufacturing SiC semiconductor device 1B shown in Figure 6. Referring to Figure 8A, first SiC epitaxial layer 13 and second SiC epitaxial layer 14 are formed on SiC wafer 10 through steps similar to those shown in Figures 4A to 4C.

[0067] 8B, similar to the step of FIG. 4D, a pentavalent element (n-type impurity) is implanted into second SiC epitaxial layer 14 up to the middle of its thickness direction by ion implantation (channeling implantation in this embodiment), thereby forming n-type drift region 8 having a target concentration. In this embodiment, drift region 8 includes a first region 8a consisting of a part of second SiC epitaxial layer 14, and a second region 8b in which a pentavalent element is further implanted into second SiC epitaxial layer 14. The impurity concentration of second region 8b is adjusted to increase toward the crystal growth direction of second SiC epitaxial layer 14.

[0068] In this step, a second impurity (at least one of arsenic and antimony) composed of a pentavalent element different from the first impurity (nitrogen) contained in second SiC epitaxial layer 14 is implanted to the middle of the thickness direction of second SiC epitaxial layer 14. As a result, first region 8a having a base concentration CA (second concentration C2) due to the first impurity is formed. Also, second region 8b having a base concentration CA due to the first impurity and an additional concentration CB due to the second impurity is formed.

[0069] As described above, the method for manufacturing SiC semiconductor device 1B also provides the same effects as those described for the method for manufacturing SiC semiconductor device 1A.

[0070] Fig. 9 corresponds to Fig. 2 and is a cross-sectional view showing a SiC semiconductor device 1C according to a third embodiment. Fig. 10 is a graph showing the impurity concentration in the SiC chip 2 shown in Fig. 9. In Fig. 10, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth. Hereinafter, structures corresponding to those described in the first and second embodiments are given the same reference numerals, and their description will be omitted.

[0071] 9 and 10, SiC semiconductor device 1C has a structure in which the “n-type region” in SiC semiconductor device 1A is replaced with a “p-type region.” Specifically, SiC semiconductor device 1C includes p-type base region 16, p-type buffer region 17, and p-type drift region 18 instead of n-type base region 6, n-type buffer region 7, and n-type drift region 8.

[0072] The p-type base region 16 has an impurity concentration adjusted by a first impurity (=p-type impurity) made of a trivalent element. The first impurity is preferably composed of one type of trivalent element. The first impurity may be any one of boron (B), aluminum (Al), gallium (Ga), and indium (In). The first impurity is preferably a trivalent element other than boron. In this embodiment, the first impurity is aluminum.

[0073] The base region 16 has a substantially constant first concentration C1 in the thickness direction. The first concentration C1 is 1×10 18 cm -3 or more and may be 1×10 21 cm -3 or less. The base region 16 may have a thickness of 5 μm or more and 300 μm or less. The thickness of the base region 16 is preferably 50 μm or more and 250 μm or less. In this form, the base region 16 is formed on the SiC substrate.

[0074] The p-type buffer region 17 contains a trivalent element and has an impurity concentration adjusted so that the impurity concentration decreases (specifically, gradually decreases) toward the first main surface 3. The buffer region 17 preferably contains any one of boron, aluminum, gallium, and indium. The buffer region 17 preferably contains a trivalent element other than boron. In this form, the buffer region 17 is concentration-adjusted by the first impurity (= aluminum).

[0075] The buffer region 17 has a concentration gradient (concentration distribution) that decreases (specifically, gradually decreases) from the first concentration C1 to a second concentration C2 (C2 < C1) less than the first concentration C1 from the base region 16 toward the first main surface 3. The second concentration C2 is 1×10 14 cm -3 or more and may be 1×10 16 cm -3 or less. The buffer region 17 may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the buffer region 17 is preferably 1 μm or more and 3 μm or less. In this form, the buffer region 17 is formed on the SiC epitaxial layer.

[0076] The p-type drift region 18 contains a trivalent element other than boron and has an impurity concentration adjusted by the trivalent element other than boron. The drift region 18 preferably contains at least one of aluminum, gallium, and indium. The drift region 18 has an impurity concentration adjusted to increase toward the first main surface 3. Specifically, the drift region 18 has a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the second concentration C2 to a third concentration C3 (C2 < C3) exceeding the second concentration C2 toward the first main surface 3 from the buffer region 17.

[0077] The third concentration C3 is the peak concentration of the drift region 18. The third concentration C3 only needs to be located in the vicinity (surface layer portion) of the first main surface 3 and does not necessarily have to coincide with the first main surface 3. The third concentration C3 is not more than the first concentration C1 (C3 ≤ C1). The third concentration C3 is preferably at least 10 times the second concentration C2. The third concentration C3 is preferably less than the first concentration C1 (C2 < C3 < C1). The third concentration C3 is 1×10 15 cm -3 or more and may be 1×10 17 cm -3 or less.

[0078] The drift region 18 has a base concentration CA and an additional concentration CB. The additional concentration CB complements the base concentration CA. The impurity concentration (third concentration C3) of the drift region 18 consists of the sum of the base concentration CA and the additional concentration CB. The base concentration CA is due to a first impurity that is a trivalent element. The additional concentration CB is due to a second impurity that is a trivalent element of the same type as the first impurity or a trivalent element of a different type from the first impurity. The second impurity may be at least one of aluminum, gallium, and indium. In this form, the second impurity is aluminum.

[0079] The drift region 18 has a base concentration CA (first impurity) and an additional concentration CB (second impurity) in the region on the side of the first main surface 3 and the region on the side of the second main surface 4 (buffer region 17 side) with respect to the intermediate portion MID. In this form, the drift region 18 has the base concentration CA (first impurity) and the additional concentration CB (second impurity) throughout the entire thickness direction.

[0080] The base concentration CA has a substantially constant concentration distribution in the thickness direction. In this form, the base concentration CA is approximately equal to the second concentration C2, which is the lower limit value of the concentration in the buffer region 17 (CA≈C2). Of course, the base concentration CA may have a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from the buffer region 17 toward the first main surface 3. The additional concentration CB has a concentration distribution that increases toward the first main surface 3. The additional concentration CB exceeds the base concentration CA (CA < CB). The additional concentration CB is preferably 10 times or more the base concentration CA. The additional concentration CB is preferably less than the first concentration C1 (CA < CB < C1).

[0081] The drift region 18 preferably has a thickness exceeding the thickness of the buffer region 17. The drift region 18 may have a thickness of 1 μm or more and 25 μm or less. The drift region 18 may have a thickness belonging to any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less. The drift region 18 particularly preferably has a thickness of 1 μm or more and 10 μm or less. In this form, the drift region 18 is formed in the SiC epitaxial layer.

[0082] As described above, the SiC semiconductor device 1C also exhibits the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1C is manufactured by replacing a pentavalent element with a predetermined trivalent element in the manufacturing method of the SiC semiconductor device 1A (Figs. 4A to 4D). Therefore, the manufacturing method of the SiC semiconductor device 1C also exhibits the same effects as those described for the manufacturing method of the SiC semiconductor device 1A.

[0083] Fig. 11 corresponds to Fig. 9 and is a cross-sectional view showing a SiC semiconductor device 1D according to the fourth embodiment. Fig. 12 is a graph showing the impurity concentration in the SiC chip 2 shown in Fig. 11. In Fig. 12, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth. Hereinafter, structures corresponding to those described in the first to third embodiments are given the same reference numerals, and their description will be omitted.

[0084] 11 and 12, like the SiC semiconductor device 1C, the SiC semiconductor device 1D includes a SiC chip 2, a p-type base region 16, a p-type buffer region 17, a p-type drift region 18, and a functional device 9. As in the third embodiment, the drift region 18 has an impurity concentration adjusted by a trivalent element other than boron. In this embodiment, the drift region 18 includes a first region 18a and a second region 18b formed in this order from the bottom toward the first main surface 3.

[0085] The first region 18a is a region having an impurity concentration adjusted by one type of trivalent element, and is formed in a surface layer portion of the first main surface 3, spaced apart from the first main surface 3. Specifically, the first region 18a is formed in a layer shape extending along the first main surface 3 on the buffer region 17, and is exposed from the first to fourth side surfaces 5A to 5D. The first region 18a is formed in a region on the second main surface 4 side (the buffer region 17 side) with respect to the intermediate portion MID. The first region 18a is preferably formed at an interval from the intermediate portion MID toward the second main surface 4.

[0086] In this embodiment, the first region 18a contains a first impurity that is a trivalent element and has a base concentration CA due to the first impurity. The first impurity may be any one of aluminum, gallium, and indium. In this embodiment, the first impurity is aluminum. The base concentration CA is approximately equal to a second concentration C2, which is the lower limit of the concentration of the buffer region 17 (CA≒C2). The first region 18a has an approximately constant concentration distribution in the thickness direction. Of course, the first region 18a may have a concentration gradient (concentration distribution) that increases from the buffer region 17 (second concentration C2) toward the first main surface 3.

[0087] The second region 18b is formed in a region between the first main surface 3 and the first region 18a. The second region 18b is formed in a layer shape extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The second region 18b is formed in a region on the first main surface 3 side with respect to the intermediate portion MID. It is preferable that the second region 18b is also formed in a region on the second main surface 4 side, across the intermediate portion MID.

[0088] The second region 18b has an impurity concentration adjusted by a first impurity and a second impurity, which may be the same trivalent element as the first impurity or a different trivalent element from the first impurity. The second impurity may be any one of aluminum, gallium, and indium. In this embodiment, the second impurity is aluminum. The second region 18b has a concentration gradient (concentration distribution) that increases (specifically, gradually increases) from a base concentration CA (= second concentration C2) in the first region 18a to a third concentration C3. In this embodiment, the second region 18b has a base concentration CA due to the first impurity and an additional concentration CB due to the second impurity.

[0089] The base concentration CA of the second region 18b has a substantially constant concentration distribution in the thickness direction, as in the third embodiment. Of course, the base concentration CA of the second region 18b may have a concentration gradient (concentration distribution) that increases toward the first main surface 3. The additional concentration CB has a concentration gradient (concentration distribution) that increases toward the first main surface 3, as in the third embodiment. The second region 18b has a resistance value that is less than the resistance value of the first region 18a. In other words, the first region 18a is a high-resistance region, and the second region 18b is a low-resistance region.

[0090] As described above, the SiC semiconductor device 1D also provides the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1D is manufactured by replacing the pentavalent element with a predetermined trivalent element in the manufacturing method for the SiC semiconductor device 1B according to the second embodiment (FIGS. 8A and 8B). Therefore, the manufacturing method for the SiC semiconductor device 1D also provides the same effects as those described for the manufacturing method for the SiC semiconductor device 1A.

[0091] Fig. 13 is a cross-sectional view showing a SiC semiconductor device 1E according to a fifth embodiment, corresponding to Fig. 2. Hereinafter, structures corresponding to those described in the first to fourth embodiments are given the same reference numerals, and descriptions thereof will be omitted.

[0092] 13, SiC semiconductor device 1E has a structure in which n-type base region 6 according to the first embodiment is replaced with p-type base region 16 according to the third embodiment. In this case, n-type buffer region 17 may have, at the boundary with p-type base region 6, a cancellation region in which the p-type impurity concentration due to a trivalent element in base region 6 is cancelled out by the n-type impurity concentration due to a pentavalent element.

[0093] As described above, the SiC semiconductor device 1E also provides the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1E is manufactured by preparing a p-type SiC wafer 10 having an impurity concentration adjusted with a predetermined trivalent element in the manufacturing method for the SiC semiconductor device 1A (FIGS. 4A to 4D). Therefore, the manufacturing method for the SiC semiconductor device 1E also provides the same effects as those described for the manufacturing method for the SiC semiconductor device 1A according to the first embodiment.

[0094] Fig. 14 is a cross-sectional view showing a SiC semiconductor device 1F according to the sixth embodiment, corresponding to Fig. 6. Hereinafter, structures corresponding to those described in the first to fifth embodiments will be given the same reference numerals, and their description will be omitted.

[0095] 14, the SiC semiconductor device 1F has a structure in which the n-type base region 6 according to the second embodiment is replaced with the p-type base region 16 according to the third embodiment. In this case, the n-type buffer region 17 may have, at the boundary with the p-type base region 6, a cancellation region in which the p-type impurity concentration due to a trivalent element in the base region 6 is cancelled out by the n-type impurity concentration due to a pentavalent element.

[0096] As described above, SiC semiconductor device 1F also provides the same effects as those described for SiC semiconductor device 1A. SiC semiconductor device 1F is manufactured by preparing p-type SiC wafer 10 having an impurity concentration adjusted with a predetermined trivalent element in the manufacturing method for SiC semiconductor device 1A (FIGS. 4A to 4D and 8A to 8B). Therefore, the manufacturing method for SiC semiconductor device 1F also provides the same effects as those described for SiC semiconductor device 1A.

[0097] Fig. 15 is a cross-sectional view showing a SiC semiconductor device 1G according to the seventh embodiment, corresponding to Fig. 2. Hereinafter, structures corresponding to those described in the first to sixth embodiments are given the same reference numerals, and descriptions thereof will be omitted.

[0098] 15, the SiC semiconductor device 1G has a structure in which the p-type base region 16 according to the third embodiment is replaced with the n-type base region 6 according to the first embodiment. In this case, the p-type buffer region 17 may have, at the boundary with the n-type base region 6, a cancellation region in which the n-type impurity concentration due to the pentavalent element in the base region 6 is cancelled out by the p-type impurity concentration due to the trivalent element.

[0099] As described above, the SiC semiconductor device 1G also provides the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1G is manufactured by preparing an n-type SiC wafer 10 having an impurity concentration adjusted by a predetermined pentavalent element in the manufacturing method for the SiC semiconductor device 1C according to the third embodiment. Therefore, the manufacturing method for the SiC semiconductor device 1G also provides the same effects as those described for the manufacturing method for the SiC semiconductor device 1A according to the first embodiment.

[0100] Fig. 16 is a cross-sectional view showing a SiC semiconductor device 1H according to the eighth embodiment, corresponding to Fig. 6. Hereinafter, structures corresponding to those described in the first to seventh embodiments will be given the same reference numerals, and descriptions thereof will be omitted.

[0101] 16, SiC semiconductor device 1H has a structure in which p-type base region 16 according to the fourth embodiment is replaced with n-type base region 6 according to the first embodiment. In this case, p-type buffer region 17 may have, at the boundary with n-type base region 6, a cancellation region in which the n-type impurity concentration due to pentavalent elements in base region 6 is cancelled out by the p-type impurity concentration due to trivalent elements.

[0102] As described above, the SiC semiconductor device 1H also provides the same effects as those described for the SiC semiconductor device 1A. The SiC semiconductor device 1H is manufactured by preparing an n-type SiC wafer 10 having an impurity concentration adjusted by a predetermined pentavalent element in the manufacturing method for the SiC semiconductor device 1D according to the fourth embodiment. Therefore, the manufacturing method for the SiC semiconductor device 1H also provides the same effects as those described for the manufacturing method for the SiC semiconductor device 1A according to the first embodiment.

[0103] Fig. 17 is a plan view showing a SiC semiconductor device 1I according to the ninth embodiment. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 17. Hereinafter, structures corresponding to those described in the first to eighth embodiments will be given the same reference numerals, and their description will be omitted.

[0104] 17 and 18, the SiC semiconductor device 1I includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, and a functional device 9, similar to the SiC semiconductor device 1A according to the first embodiment. The SiC chip 2 has an off-angle θ and an off-direction D, similar to the first embodiment. In this embodiment, the SiC semiconductor device 1I includes a plurality of p-type column regions 19 formed in the drift region 8. The column regions 19 may also be referred to as "impurity regions."

[0105] The column regions 19 are formed using a portion of the SiC chip 2. The column regions 19 are formed in the drift region 8 at intervals inward from the periphery of the SiC chip 2 in a plan view. In this embodiment, the column regions 19 are each formed in a strip shape extending in the first direction X (a-axis direction) in a plan view, and are arranged at intervals in the second direction Y (m-axis direction). In other words, the column regions 19 are formed in stripes extending in the off direction D (=first direction X) in a plan view.

[0106] Of course, the column regions 19 may be arranged at intervals in the first direction X (a-axis direction) in a plan view, and each may be formed in a strip shape extending in the second direction Y (m-axis direction). That is, the column regions 19 may be formed in a stripe shape extending in a direction (=second direction Y) perpendicular to the off-direction D in a plan view. The column regions 19 may also be formed in a lattice shape intersecting the first direction X and the second direction Y in a plan view. The column regions 19 may also be arranged in a dot shape at intervals in the first direction X and the second direction Y.

[0107] The multiple column regions 19 may be arranged at intervals (column pitch) of 0.5 μm or more and 10 μm or less. It is preferable that the multiple column regions 19 are arranged at approximately equal intervals. The multiple column regions 19 may each have a width (column width) of 0.5 μm or more and 10 μm or less. It is preferable that the multiple column regions 19 each have approximately equal widths.

[0108] The plurality of column regions 19 each form a pn junction with the drift region 8. Specifically, the plurality of column regions 19 are formed in a columnar shape extending in the thickness direction of the drift region 8 in a cross-sectional view, and each form a pn junction with the drift region 8 along the thickness direction. It is preferable that the plurality of column regions 19 each extend from the first main surface 3 to cross the intermediate portion MID. The plurality of column regions 19 are each formed at intervals from the bottom of the drift region 8 (i.e., the buffer region 7) toward the first main surface 3. The plurality of column regions 19 face the buffer region 7 across a relatively low-concentration bottom region of the drift region 8.

[0109] The multiple column regions 19 each form a superjunction structure with the drift region 8. That is, the multiple column regions 19 each form a pn junction extending in the thickness direction of the drift region 8 so as to expand the depletion layer in the width direction of the drift region 8. The multiple column regions 19 are preferably arranged at intervals such that the depletion layer expanding from one column region 19 is connected to the depletion layer expanding from the other adjacent column region 19.

[0110] The plurality of column regions 19 are formed in such a manner that the n-type impurity concentration of the drift region 8 is replaced with a p-type impurity concentration by a trivalent element. That is, the plurality of column regions 19 each have, in addition to the pentavalent element that constitutes the drift region 8 (basic concentration CA and additional concentration CB), a trivalent element introduced at a p-type impurity concentration that exceeds the n-type impurity concentration of the drift region 8.

[0111] The plurality of column regions 19 contain a trivalent element other than boron and have an impurity concentration adjusted by the trivalent element other than boron. The plurality of column regions 19 preferably contain at least one of aluminum, gallium, and indium. The plurality of column regions 19 have an impurity concentration adjusted to increase (specifically, gradually increase) toward the first main surface 3.

[0112] The plurality of column regions 19 preferably have a p-type impurity concentration gradient proportional to the concentration gradient of the drift region 8. The plurality of column regions 19 preferably have impurity concentrations adjusted to maintain charge balance with the drift region 8. "Maintaining charge balance" means that the depletion layers extending from the plurality of column regions 19 are connected in the regions between adjacent pairs of column regions 19.

[0113] For example, when the column width is x (0 < x) times the column pitch, the plurality of column regions 19 maintain charge balance when the impurity concentration of the plurality of columns is 1 / x times the impurity concentration of the drift region 8. When the column width is equal to the column pitch, the plurality of column regions 19 preferably have a concentration gradient of p-type impurities that rises from the second concentration C2 to the third concentration C3 corresponding to the drift region 8 having a concentration gradient that rises from the second concentration C2 to the third concentration C3.

[0114] In this form, the functional device 9 is formed using the drift region 8 and the plurality of column regions 19. That is, the SiC semiconductor device 1I includes a super junction type functional device 9.

[0115] As described above, the SiC semiconductor device 1I includes a SiC chip 2, an n-type drift region 8, and a p-type column region 19 (impurity region). The SiC chip 2 has a first main surface 3. The drift region 8 is formed in the surface layer portion of the first main surface 3 and has an impurity concentration adjusted by at least two types of pentavalent elements. The column region 19 is formed in the drift region 8 so as to form a pn junction with the drift region 8. According to this structure, the same effects as those described for the SiC semiconductor device 1A are achieved. Also, according to this structure, a pn junction can be appropriately formed between the drift region 8 and the column region 19. Therefore, a SiC semiconductor device 1I capable of improving electrical characteristics (for example, breakdown voltage due to the column region 19) can be provided.

[0116] From another perspective, the SiC semiconductor device 1I includes a SiC chip 2, an n-type drift region 8, and a p-type column region 19 (impurity region). The SiC chip 2 has a first main surface 3. The drift region 8 is formed in the surface layer portion of the first main surface 3. The column region 19 is formed in the drift region 8 so as to form a pn junction with the drift region 8 and has an impurity concentration adjusted by a trivalent element other than boron.

[0117] Boron has the property of being difficult to introduce into deep regions of the SiC chip 2. Therefore, by adjusting the impurity concentration of the column region 19 with a trivalent element other than boron, it is possible to form the column region 19 having an impurity concentration with reduced variation from the target concentration. This makes it possible to appropriately form a pn junction between the drift region 8 and the column region 19. Therefore, it is possible to provide a SiC semiconductor device 1I that can improve electrical characteristics (for example, the breakdown voltage caused by the column region 19).

[0118] The drift region 8 preferably has a concentration distribution that increases toward the first main surface 3. The column region 19 preferably has a concentration distribution that increases toward the first main surface 3. The drift region 8 preferably contains at least one trivalent element selected from nitrogen, arsenic, and antimony. The column region 19 preferably contains at least one trivalent element selected from aluminum, gallium, and indium.

[0119] The column region 19 preferably extends in the thickness direction within the drift region 8 so as to form a superjunction structure with the drift region 8 at a pn junction. The column region 19 preferably crosses the intermediate portion MID. The column region 19 is preferably formed at a distance from the bottom of the drift region 8 toward the first main surface 3.

[0120] Figures 19A and 19B are cross-sectional views showing a method for manufacturing SiC semiconductor device 1I shown in Figure 17. Referring to Figure 19A, drift region 8 is formed in second SiC epitaxial layer 14 through steps similar to those shown in Figures 4A to 4D.

[0121] 19B, a resist mask RM having a predetermined pattern is formed on second SiC epitaxial layer 14. Resist mask RM exposes regions in drift region 8 where a plurality of column regions 19 are to be formed, and covers the remaining regions. Next, a trivalent element (p-type impurity) is implanted into drift region 8 by ion implantation via resist mask RM, thereby forming a plurality of p-type column regions 19 having a target concentration.

[0122] In this step, a trivalent element is implanted into drift region 8 so that the impurity concentration increases (specifically, gradually increases) in the crystal growth direction. The ion implantation method used in this step is channeling implantation. In channeling implantation, a trivalent element is implanted into a region on the main surface (crystal growth surface) side of second SiC epitaxial layer 14 and a region on the SiC wafer 10 side of an intermediate portion of second SiC epitaxial layer 14.

[0123] The implantation depth of the trivalent element into the drift region 8 is precisely adjusted by adjusting the implantation energy of the trivalent element, the implantation temperature of the second impurity, the implantation angle of the second impurity, etc. The implantation energy of the trivalent element may be adjusted in the range of 10 keV to 1000 keV (preferably 100 keV or higher). The implantation temperature of the trivalent element may be adjusted in the range of 300°C to 1000°C.

[0124] The implantation angle of the trivalent element is set within a range of ±5° with the crystal axis (c-axis) of the SiC single crystal as the reference (=0°). The implantation angle of the trivalent element is preferably set within a range of ±2°. In this embodiment, the second SiC epitaxial layer 14 (SiC wafer 10) has an off-angle θ tilted to a predetermined off-direction D. Therefore, in the channeling implantation method, the implantation angle of the trivalent element with respect to the second SiC epitaxial layer 14 or the tilt angle of the second SiC epitaxial layer 14 with respect to the implantation direction of the trivalent element is adjusted according to the off-direction D and the off-angle θ.

[0125] In this configuration, a plurality of column regions 19 extending in the off-direction D (=first direction X) are formed. With this structure, the implantation angle of the trivalent element is an inclination angle with respect to the off-direction D, so that the vector component of the trivalent element implanted into the second SiC epitaxial layer 14 is aligned with the off-direction D. Therefore, the trivalent element is implanted along a line extending in the off-direction D in a plan view, and is implanted approximately perpendicular to the c-plane of the SiC single crystal in a cross-sectional view perpendicular to the off-direction D.

[0126] The trivalent element used in the channeling implantation method may be at least one of boron, aluminum, gallium, and indium. However, boron has the property of being difficult to implant into deep regions of the second SiC epitaxial layer 14 by the channeling implantation method. Therefore, the trivalent element used in the channeling implantation method is preferably a trivalent element other than boron.

[0127] After the trivalent element is implanted, annealing is performed to electrically activate the trivalent element and simultaneously repair lattice defects and the like that have occurred in the second SiC epitaxial layer 14. The annealing temperature for the second SiC epitaxial layer 14 may be 500°C or higher and 2000°C or lower. The activation of the trivalent element may be performed simultaneously with the activation of the pentavalent element in the drift region 8. This results in the formation of the trivalent element. Thereafter, a functional device 9 utilizing the drift region 8 and a plurality of column regions 19 is formed on the main surface (crystal growth surface) side of the second SiC epitaxial layer 14. Through the processes including those described above, the SiC semiconductor device 1I is manufactured.

[0128] As described above, the manufacturing method of the SiC semiconductor device 1I includes a first step of preparing the second SiC epitaxial layer 14, a second step of forming the n-type drift region 8, and a third step of forming the p-type column region 19. In the first step, a low-concentration n-type second SiC epitaxial layer 14 is prepared. Specifically, the impurity concentration of the second SiC epitaxial layer 14 is lower than the target concentration of the drift region 8. In the second step, a pentavalent element (n-type impurity) is implanted into the second SiC epitaxial layer 14 by ion implantation, thereby forming the n-type drift region 8 having the target concentration. In the third step, a trivalent element (p-type impurity) is implanted into the second SiC epitaxial layer 14 by ion implantation, thereby forming the p-type column region 19 that forms a pn junction with the drift region 8.

[0129] This manufacturing method achieves the same effects as those described for the manufacturing method of the SiC semiconductor device 1A. Furthermore, the manufacturing method of the SiC semiconductor device 1I makes it possible to appropriately form a pn junction between the drift region 8 and the column region 19. Therefore, it is possible to manufacture and provide the SiC semiconductor device 1I that can improve electrical characteristics (for example, the breakdown voltage due to the column region 19).

[0130] From another perspective, the manufacturing method of SiC semiconductor device 1I includes a first step of preparing second SiC epitaxial layer 14 in which n-type drift region 8 is formed, and a second step of forming p-type column region 19. In the second step, a trivalent element (p-type impurity) other than boron is implanted into second SiC epitaxial layer 14 by ion implantation, thereby forming p-type column region 19 that forms a pn junction with drift region 8.

[0131] Boron has the property of being difficult to introduce into a deep region of the second SiC epitaxial layer 14. Therefore, by adjusting the impurity concentration of the column region 19 with a trivalent element other than boron, it is possible to suppress variations in the impurity concentration of the column region 19 relative to the target concentration. This allows a pn junction to be appropriately formed between the drift region 8 and the column region 19. Therefore, it is possible to manufacture and provide a SiC semiconductor device 1I that can improve electrical characteristics (for example, the breakdown voltage due to the column region 19).

[0132] In the manufacturing method of the SiC semiconductor device 1I, a second SiC epitaxial layer 14 having an impurity concentration adjusted by a first impurity may be prepared. In this case, the drift region 8 may be formed by implanting a second impurity different from the first impurity into the second SiC epitaxial layer 14. The first impurity is preferably a pentavalent element other than phosphorus. The first impurity is preferably nitrogen. The second impurity is preferably a pentavalent element other than phosphorus. The second impurity is preferably at least one of arsenic and antimony.

[0133] In the process of forming the column region 19, a channeling implantation method may be performed in which a trivalent element is implanted along the crystal axis of the second SiC epitaxial layer 14. The trivalent element used in the channeling implantation method is preferably a trivalent element other than boron. The trivalent element used in the channeling implantation method may be at least one of aluminum, gallium, and indium.

[0134] The trivalent element is preferably implanted into the second SiC epitaxial layer 14 at an implantation angle of ±5° or less with respect to the crystal axis of the SiC single crystal. The crystal axis of the SiC single crystal is preferably the c-axis. The second SiC epitaxial layer 14 preferably has an off-angle θ of 10° or less with respect to the c-plane of the SiC single crystal. The off-angle θ preferably has an off-direction D aligned with the a-axis direction of the SiC single crystal.

[0135] In the channeling implantation method, it is preferable to form column regions 19 extending along the off-direction D. According to this process, the vector component of the implanted trivalent element is aligned with the off-direction D. As a result, the trivalent element is implanted almost perpendicular to the c-plane of the SiC single crystal on a line extending in the off-direction D, and therefore the column regions 19 can be properly formed.

[0136] Fig. 20 corresponds to Fig. 18 and is a plan view showing a SiC semiconductor device 1J according to the tenth embodiment. Hereinafter, structures corresponding to those described in the first to ninth embodiments are given the same reference numerals, and descriptions thereof will be omitted.

[0137] 20 , like the SiC semiconductor device 1B according to the second embodiment, the SiC semiconductor device 1J includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, and a functional device 9. The drift region 8 includes a first region 8a and a second region 8b. In this embodiment, the SiC semiconductor device 1J includes a plurality of p-type column regions 19 formed in the drift region 8.

[0138] The multiple column regions 19 are formed in a manner similar to the column regions 19 according to the ninth embodiment in plan view. In this embodiment, the multiple column regions 19 are each formed in the second region 8b so as to form a pn junction with the second region 8b of the drift region 8. Specifically, the multiple column regions 19 are formed in a columnar shape extending in the thickness direction of the second region 8b in cross-sectional view, and each form a pn junction with the second region 8b along the thickness direction.

[0139] Preferably, the plurality of column regions 19 each extend across the intermediate portion MID from the first main surface 3. Preferably, the plurality of column regions 19 are formed at intervals from the first region 8a toward the first main surface 3, and each face the buffer region 7 with parts of the first region 8a and the second region 8b sandwiched therebetween. Preferably, the lower ends of the plurality of column regions 19 are located in a region between the intermediate portion MID and the first region 8a.

[0140] The multiple column regions 19 each form a superjunction structure with the second region 8b. That is, the multiple column regions 19 each form a pn junction extending in the thickness direction of the second region 8b so as to expand the depletion layer in the width direction of the second region 8b. The multiple column regions 19 are preferably arranged at intervals such that the depletion layer extending from one column region 19 is connected to the depletion layer extending from the other adjacent column region 19.

[0141] In this embodiment, the plurality of column regions 19 are formed in such a manner that the n-type impurity concentration of the second region 8b is replaced (cancelled) by a p-type impurity concentration with a trivalent element. That is, in addition to the pentavalent element constituting the second region 8b (basic concentration CA and additional concentration CB), the plurality of column regions 19 each contain a trivalent element introduced at a p-type impurity concentration exceeding the n-type impurity concentration of the second region 8b. The plurality of column regions 19 preferably have a p-type impurity concentration gradient proportional to the concentration gradient of the second region 8b. The plurality of column regions 19 preferably have impurity concentrations adjusted to maintain charge balance with the second region 8b.

[0142] In this embodiment, the functional device 9 is formed by utilizing the drift region 8 and a plurality of column regions 19. That is, the SiC semiconductor device 1J includes a functional device 9 of a superjunction type.

[0143] As described above, the SiC semiconductor device 1J also provides the same effects as those described for the SiC semiconductor device 1I according to the ninth embodiment.

[0144] Figures 21A and 21B are cross-sectional views showing a method for manufacturing SiC semiconductor device 1J shown in Figure 20. With reference to Figure 21A, drift region 8 is formed in second SiC epitaxial layer 14 through steps similar to those shown in Figures 4A to 4C and 8A to 8B. Drift region 8 includes a first region 8a and a second region 8b.

[0145] 21B, a resist mask RM having a predetermined pattern is formed on the second SiC epitaxial layer 14. The resist mask RM exposes regions in the drift region 8 where a plurality of column regions 19 are to be formed, and covers the remaining regions. Next, a trivalent element (p-type impurity) is implanted into the drift region 8 by ion implantation (channeling implantation in this embodiment) through the resist mask RM, thereby forming a plurality of p-type column regions 19 having a target concentration.

[0146] In this step, a trivalent element other than boron is implanted into second region 8b up to the middle of the second region 8b in the thickness direction. Specifically, the trivalent element is implanted into second region 8b at a distance from first region 8a toward first main surface 3. In this embodiment, the trivalent element other than boron is at least one of aluminum, gallium, and indium.

[0147] As described above, the method for manufacturing the SiC semiconductor device 1J also provides the same effects as those described for the method for manufacturing the SiC semiconductor device 1I according to the ninth embodiment.

[0148] Fig. 22 is a cross-sectional view showing a SiC semiconductor device 1K according to the eleventh embodiment, corresponding to Fig. 18. Hereinafter, structures corresponding to those described in the first to tenth embodiments are given the same reference numerals, and their description will be omitted.

[0149] 22, like the SiC semiconductor device 1C according to the third embodiment, the SiC semiconductor device 1K includes a SiC chip 2, a p-type base region 16, a p-type buffer region 17, a p-type drift region 18, and a functional device 9. In this embodiment, the SiC semiconductor device 1K includes a plurality of n-type column regions 20 formed in the drift region 18. The column regions 20 may also be referred to as "impurity regions."

[0150] The column regions 20 are formed using a portion of the SiC chip 2. The column regions 20 are formed in a manner similar to the column regions 19 according to the ninth embodiment, except that they contain pentavalent elements instead of trivalent elements. In this embodiment, the column regions 20 are formed such that the p-type impurity concentration of the drift region 18 is replaced with an n-type impurity concentration by the pentavalent elements. That is, in addition to the trivalent elements that constitute the drift region 18 (basic concentration CA and additional concentration CB), the column regions 20 each contain a pentavalent element introduced at an n-type impurity concentration that exceeds the p-type impurity concentration of the drift region 18.

[0151] The plurality of column regions 20 contain a pentavalent element other than phosphorus and nitrogen, and have an impurity concentration adjusted by the pentavalent element other than phosphorus and nitrogen. The plurality of column regions 20 preferably contain at least one of arsenic and antimony. The plurality of column regions 20 have an impurity concentration adjusted to increase (specifically, gradually increase) toward the first main surface 3. The plurality of column regions 20 preferably have an n-type impurity concentration gradient proportional to the concentration gradient of the drift region 18. The plurality of column regions 20 preferably have an impurity concentration adjusted to maintain charge balance with the drift region 18.

[0152] In this embodiment, the functional device 9 is formed by utilizing the drift region 18 and a plurality of column regions 20. That is, the SiC semiconductor device 1K includes a functional device 9 of a superjunction type.

[0153] As described above, the SiC semiconductor device 1K also provides the same effects as those described for the SiC semiconductor device 1I according to the ninth embodiment. The SiC semiconductor device 1K is manufactured by replacing the pentavalent element with a predetermined trivalent element in the manufacturing method for the SiC semiconductor device 1I according to the ninth embodiment (FIGS. 4A to 4D and 19A to 19B). Therefore, the manufacturing method for the SiC semiconductor device 1K also provides the same effects as those described for the manufacturing method for the SiC semiconductor device 1I according to the ninth embodiment.

[0154] Fig. 23 is a plan view showing a SiC semiconductor device 1L according to the twelfth embodiment, corresponding to Fig. 18. Hereinafter, structures corresponding to those described in the first to eleventh embodiments will be given the same reference numerals, and descriptions thereof will be omitted.

[0155] 20 , like the SiC semiconductor device 1D according to the fourth embodiment, the SiC semiconductor device 1L includes a SiC chip 2, a p-type base region 16, a p-type buffer region 17, a p-type drift region 18, and a functional device 9. The drift region 18 includes a first region 18a and a second region 18b. In this embodiment, the SiC semiconductor device 1L includes a plurality of n-type column regions 20 formed in the drift region 18.

[0156] The multiple column regions 20 are formed in the same manner as the column regions 19 according to the tenth embodiment (ninth embodiment) except that they contain a pentavalent element instead of a trivalent element. The multiple column regions 20 are also formed in the same manner as the eleventh embodiment. In this embodiment, the multiple column regions 20 are each formed in the second region 18b so as to form a pn junction with the second region 18b. Specifically, the multiple column regions 20 are formed in a columnar shape extending in the thickness direction of the second region 18b in a cross-sectional view, and each form a pn junction along the thickness direction of the second region 18b.

[0157] Preferably, the plurality of column regions 20 each extend across the intermediate portion MID from the first main surface 3. Preferably, the plurality of column regions 20 are formed at intervals from the first region 18a toward the first main surface 3, and face the buffer region 17 with parts of the first region 18a and the second region 18b sandwiched therebetween. Preferably, the lower ends of the plurality of column regions 20 are located in a region between the intermediate portion MID and the first region 18a.

[0158] In this embodiment, the plurality of column regions 20 are formed in such a manner that the p-type impurity concentration of the second region 18b is replaced (cancelled) by a pentavalent element to an n-type impurity concentration. That is, in addition to the trivalent element that constitutes the second region 18b (basic concentration CA and additional concentration CB), the plurality of column regions 20 each have a pentavalent element introduced at an n-type impurity concentration that exceeds the p-type impurity concentration of the second region 18b.

[0159] The multiple column regions 20 each form a superjunction structure with the second region 18b. That is, the multiple column regions 20 each form a pn junction extending in the thickness direction of the second region 18b so as to expand the depletion layer in the width direction of the second region 18b. The multiple column regions 20 are preferably arranged at intervals such that the depletion layer extending from one column region 20 is connected to the depletion layer extending from the other adjacent column region 20. The multiple column regions 20 preferably have an n-type impurity concentration gradient that is at least proportional to the concentration gradient of the second region 18b. The multiple column regions 20 preferably have an impurity concentration adjusted to maintain charge balance with the second region 18b.

[0160] In this embodiment, the functional device 9 is formed by utilizing the drift region 18 and a plurality of column regions 20. That is, the SiC semiconductor device 1L includes a functional device 9 of a superjunction type.

[0161] As described above, the SiC semiconductor device 1L also provides the same effects as those described for the SiC semiconductor device 1J according to the tenth embodiment. The SiC semiconductor device 1L is manufactured by replacing the pentavalent element with a predetermined trivalent element in the manufacturing method for the SiC semiconductor device 1J according to the tenth embodiment (FIGS. 4A to 4D and 21A to 21B). Therefore, the manufacturing method for the SiC semiconductor device 1L also provides the same effects as those described for the manufacturing method for the SiC semiconductor device 1J according to the tenth embodiment.

[0162] Hereinafter, examples of the functional device 9 that can be applied to the first to twelfth embodiments will be described. In the following, a specific example of the functional device 9 will be described using any one of the SiC semiconductor devices 1A to 1L according to the first to twelfth embodiments.

[0163] Fig. 24 is a plan view showing a structure in which a functional device 9 according to a first embodiment is applied to a SiC semiconductor device 1A according to the first embodiment. Fig. 25 is a cross-sectional view taken along line XXV-XXV shown in Fig. 24. Fig. 26 is a plan view of the SiC chip 2 shown in Fig. 25. Hereinafter, structures corresponding to those described in the first embodiment will be given the same reference numerals, and their description will be omitted.

[0164] 24 to 26, SiC semiconductor device 1A includes SiC chip 2, n-type base region 6, n-type buffer region 7, n-type drift region 8, and functional device 9. In this embodiment, functional device 9 is a SiC-SBD. In this embodiment, base region 6 is formed as a cathode region of the SiC-SBD. SiC semiconductor device 1A also includes p-type guard region 21, insulating film 22, first principal surface electrode 23, and second principal surface electrode 24.

[0165] The guard region 21 is formed in the surface layer portion of the drift region 8 at a distance inward from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). The guard region 21 extends in a band shape along the periphery of the first main surface 3 in a plan view. In this embodiment, the guard region 21 is formed in a ring shape surrounding the inner portion of the first main surface 3 in a plan view. As a result, the guard region 21 is formed as a guard ring region. The guard region 21 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the periphery side of the first main surface 3. The p-type impurities in the guard region 21 may or may not be activated.

[0166] Insulating film 22 covers first main surface 3. Specifically, insulating film 22 covers the periphery of first main surface 3 and the region between guard regions 21 so as to cover the outer edge of guard region 21. Insulating film 22 has openings 25 that expose the inner part of first main surface 3 and the inner edge of guard region 21.

[0167] The first principal surface electrode 23 covers the first principal surface 3. Specifically, the first principal surface electrode 23 extends into the opening 25 from above the insulating film 22 and covers the first principal surface 3 within the opening 25. The first principal surface electrode 23 is electrically connected to the drift region 8 and the guard region 21 within the opening 25. In this embodiment, the first principal surface electrode 23 forms a Schottky junction with the drift region 8. The second principal surface electrode 24 covers the second principal surface 4. Specifically, the second principal surface electrode 24 covers almost the entire area of ​​the second principal surface 4. The second principal surface electrode 24 forms an ohmic contact with the base region 6.

[0168] As described above, this structure can provide a SiC semiconductor device 1A having a SiC-SBD whose electrical characteristics are improved by the drift region 8. Of course, the structure of the functional device 9 (SiC-SBD) according to the first embodiment can also be applied to any one of the first to twelfth embodiments except for the first embodiment.

[0169] Fig. 27 is a plan view showing a structure in which a functional device 9 according to a second embodiment is applied to a SiC semiconductor device 1J according to the tenth embodiment. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in Fig. 27. Fig. 29 is a plan view of the SiC chip 2 shown in Fig. 28. Hereinafter, structures corresponding to those described in the tenth embodiment will be given the same reference numerals, and their description will be omitted.

[0170] 27 to 29, SiC semiconductor device 1J includes SiC chip 2, n-type base region 6, n-type buffer region 7, n-type drift region 8, p-type column region 19, and functional device 9. Drift region 8 includes first region 8a and second region 8b. In this embodiment, functional device 9 is a superjunction SiC-SBD. In this embodiment, base region 6 is formed as a cathode region of the SiC-SBD.

[0171] Similar to the functional device 9 according to the first embodiment (see FIGS. 24 to 26), the SiC semiconductor device 1J includes a p-type guard region 21, an insulating film 22, a first principal surface electrode 23, and a second principal surface electrode 24. Differences from the functional device 9 according to the first embodiment (see FIGS. 24 to 26) will be described below.

[0172] In this embodiment, the guard region 21 is formed shallower than the column regions 19 and is located at a depth closer to the first main surface 3 than the bottoms of the columns. The guard region 21 is preferably formed in a region closer to the first main surface 3 than the intermediate portions of the column regions 19. The guard region 21 may be connected to both longitudinal ends of the column regions 19. In this embodiment, the insulating film 22 has openings 25 in the inner portion of the first main surface 3 that expose the inner edges of the column regions 19 and the guard region 21. The first main surface electrode 23 is electrically connected to the drift region 8, the column regions 19, and the guard region 21 within the openings 25.

[0173] As described above, this structure can provide a SiC semiconductor device 1J having a superjunction SiC-SBD whose electrical characteristics are improved by the drift region 8 and the column region 19. Of course, the structure of the functional device 9 (superjunction SiC-SBD) according to the second embodiment can also be applied to any one of the ninth to twelfth embodiments except for the tenth embodiment.

[0174] FIG. 30 is a plan view showing a structure in which a functional device 9 according to a third embodiment is applied to a SiC semiconductor device 1A according to the first embodiment. FIG. 31 is a cross-sectional view taken along line XXXI-XXXI shown in FIG. 30. FIG. 32 is an enlarged view of region XXXII shown in FIG. 30. FIG. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in FIG. 32. FIG. 34 is an enlarged view of region XXXIV shown in FIG. 31. Hereinafter, structures corresponding to those described in the first embodiment will be given the same reference symbols, and their description will be omitted.

[0175] 30 to 34, SiC semiconductor device 1A includes SiC chip 2, n-type base region 6, n-type buffer region 7, n-type drift region 8, and functional device 9. In this embodiment, functional device 9 is a trench gate SiC-MISFET. In this embodiment, base region 6 is formed as a drain region of the SiC-MISFET.

[0176] The SiC semiconductor device 1A has an active surface 31, an outside surface 32, and first to fourth connecting surfaces 33A to 33D formed on the first main surface 3. The active surface 31, the outside surface 32, and the first to fourth connecting surfaces 33A to 33D define an active mesa 34 on the first main surface 3. The active surface 31 may be referred to as the "first surface," the outside surface 32 may be referred to as the "second surface" or "peripheral surface," and the active mesa 34 may be referred to as the "plateau."

[0177] The active surface 31 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 31 has a flat surface extending in the first direction X and the second direction Y. The active surface 31 has the off-angle θ and off-direction D described above. In this embodiment, the active surface 31 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0178] The outer side surface 32 is located outside the active surface 31 and is recessed from the active surface 31 in the thickness direction (toward the second main surface 4) of the SiC chip 2. Specifically, the outer side surface 32 is recessed to a depth less than the thickness of the drift region 8 so as to expose the drift region 8. The outer side surface 32 is formed in a band shape extending along the active surface 31 in a plan view. In this embodiment, the outer side surface 32 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 31 in a plan view. The outer side surface 32 has a flat surface extending in the first direction X and the second direction Y and is formed approximately parallel to the active surface 31. The outer side surface 32 has an off angle θ and an off direction D, similar to the active surface 31. The outer side surface 32 is in communication with the first to fourth side surfaces 5A to 5D.

[0179] The first to fourth connection surfaces 33A to 33D extend in the normal direction Z and connect the active surface 31 and the outer surface 32. The first connection surface 33A is located on the first side surface 5A side, the second connection surface 33B is located on the second side surface 5B side, the third connection surface 33C is located on the third side surface 5C side, and the fourth connection surface 33D is located on the fourth side surface 5D side. The first connection surface 33A and the second connection surface 33B extend in the first direction X and face the second direction Y. The third connection surface 33C and the fourth connection surface 33D extend in the second direction Y and face the first direction X. The first to fourth connection surfaces 33A to 33D expose the drift region 8.

[0180] The first to fourth connection surfaces 33A to 33D may extend substantially perpendicularly between the active surface 31 and the outer side surface 32 so as to define the square-prism-shaped active plateaus 34. The first to fourth connection surfaces 33A to 33D may be inclined obliquely downward from the active surface 31 toward the outer side surface 32 so as to define the square-prism-shaped active plateaus 34. In this manner, the SiC semiconductor device 1A includes the active plateaus 34 formed in the drift region 8 on the first main surface 3. The active plateaus 34 are formed only in the drift region 8, and are not formed in the base region 6 or the buffer region 7.

[0181] The SiC semiconductor device 1A includes a SiC-MISFET formed on the active surface 31. The structure of the SiC-MISFET will be specifically described below. The SiC semiconductor device 1A includes a p-type body region 35 formed in a surface layer portion of the active surface 31. The body region 35 forms a part of the body diode of the SiC-MISFET. The body region 35 may be formed over the entire surface layer portion of the active surface 31.

[0182] The SiC semiconductor device 1A includes an n-type source region 36 formed in a surface layer portion of the body region 35. The source region 36 forms the source of the SiC-MISFET. The source region 36 may be formed over the entire surface layer portion of the body region 35. The source region 36 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 8. The source region 36 forms a channel CH of the SiC-MISFET together with the drift region 8 within the body region 35.

[0183] The SiC semiconductor device 1A includes a plurality of trench gate structures 37 formed on the active surface 31. The plurality of trench gate structures 37 form gates of the SiC-MISFET and control the inversion (on) and non-inversion (off) of the channel CH. The plurality of trench gate structures 37 are formed to cross the body region 35 and the source region 36 and reach the drift region 8.

[0184] The trench gate structures 37 are formed at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. Each trench gate structure 37 is formed at an interval from the bottom of the drift region 8 toward the active surface 31, and faces the buffer region 7 with part of the drift region 8 in between.

[0185] Each trench gate structure 37 includes a gate trench 38, a gate insulating film 39, and a gate electrode 40. The gate trench 38 is formed in the active surface 31. The gate insulating film 39 is formed in the form of a film on the inner wall of the gate trench 38. The gate electrode 40 is buried in the gate trench 38 with the gate insulating film 39 in between. The gate electrode 40 faces the drift region 8, the body region 35, and the source region 36 with the gate insulating film 39 in between. A gate potential is applied to the gate electrode 40.

[0186] The SiC semiconductor device 1A includes a plurality of trench source structures 41 formed on the active surface 31. The plurality of trench source structures 41 are each formed in a region between two adjacent trench gate structures 37 on the active surface 31. The plurality of trench source structures 41 are each formed in a strip shape extending in the second direction Y in a plan view. The plurality of trench source structures 41 are formed to cross the body region 35 and the source region 36 and reach the drift region 8. The plurality of trench source structures 41 are formed at intervals from the bottom of the drift region 8 toward the active surface 31, and face the buffer region 7 with a part of the drift region 8 in between.

[0187] Each trench source structure 41 has a depth greater than the depth of the trench gate structure 37. The bottom wall of each trench source structure 41 is located closer to the bottom of the drift region 8 than the bottom wall of each trench gate structure 37. In this embodiment, the bottom wall of each trench source structure 41 is located substantially flush with the outer surface 32. Of course, each trench source structure 41 may have a depth substantially equal to the depth of the trench gate structure 37.

[0188] Each trench source structure 41 includes a source trench 42, a source insulating film 43, and a source electrode 44. The source trench 42 is formed in the active surface 31. The source insulating film 43 is formed in the form of a film on the inner wall of the source trench 42. The source electrode 44 is buried in the source trench 42 with the source insulating film 43 sandwiched therebetween. A source potential is applied to the source electrode 44.

[0189] The SiC semiconductor device 1A includes a plurality of p-type contact regions 45 formed in regions along the plurality of trench source structures 41 in the drift region 8. The p-type impurity concentrations of the plurality of contact regions 45 exceed the p-type impurity concentration of the body region 35. The plurality of contact regions 45 cover the corresponding trench source structures 41 in a one-to-many correspondence with a gap in the second direction Y. The plurality of contact regions 45 may cover the corresponding trench source structures 41 in a one-to-one correspondence. Each contact region 45 covers the sidewall and bottom wall of the corresponding trench source structure 41 and is electrically connected to the body region 35.

[0190] The SiC semiconductor device 1A includes a plurality of p-type well regions 46 formed in regions along the plurality of trench source structures 41 in a surface layer portion of the active surface 31. The p-type impurity concentrations of the plurality of well regions 46 are preferably greater than the p-type impurity concentration of the body region 35 and less than the p-type impurity concentration of the contact region 45. The plurality of well regions 46 respectively cover the corresponding trench source structures 41 with the plurality of contact regions 45 interposed therebetween. Each well region 46 may be formed in a strip shape extending along the corresponding trench source structure 41. Each well region 46 covers the sidewalls and bottom wall of the corresponding trench source structure 41 and is electrically connected to the body region 35.

[0191] 34, the SiC semiconductor device 1A includes a p-type outer contact region 48 formed in a surface layer portion of the drift region 8 on the outer surface 32. The outer contact region 48 preferably has a p-type impurity concentration that exceeds the p-type impurity concentration of the body region 35. The outer contact region 48 is formed spaced apart from the periphery of the active surface 31 and the periphery of the outer surface 32 in a plan view. The outer contact region 48 is formed in a band shape extending along the active surface 31 in a plan view. In this embodiment, the outer contact region 48 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 31 in a plan view.

[0192] The outer contact region 48 is formed at a distance from the bottom of the drift region 8 to the outer surface 32. The entire outer contact region 48 is located on the bottom side of the drift region 8 with respect to the bottom walls of the multiple trench gate structures 37. The outer contact region 48 forms a pn junction with the drift region 8. This forms a pn junction diode with the outer contact region 48 as the anode and the drift region 8 as the cathode.

[0193] The SiC semiconductor device 1A includes a p-type outer well region 49 formed in a surface layer portion of the outer side surface 32. The outer well region 49 has a p-type impurity concentration lower than the p-type impurity concentration of the outer contact region 48. The p-type impurity concentration of the outer well region 49 is preferably approximately equal to the p-type impurity concentration of the well region 46. The outer well region 49 is formed in a region between the periphery of the active surface 31 and the outer contact region 48 in a plan view.

[0194] The outer well region 49 is formed in a band shape extending along the active surface 31 in a plan view. In this embodiment, the outer well region 49 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 31 in a plan view. The outer well region 49 is electrically connected to the outer contact region 48. In this embodiment, the outer well region 49 extends from the outer side surface 32 toward the first to fourth connection surfaces 33A to 33D and covers the first to fourth connection surfaces 33A to 33D within the SiC chip 2. The outer well region 49 is electrically connected to the body region 35 in a surface layer portion of the active surface 31.

[0195] The outer well region 49 is formed deeper than the outer contact region 48. The outer well region 49 is formed at a distance from the bottom of the drift region 8 to the outer surface 32. The outer well region 49 is located on the bottom side of the drift region 8 with respect to the bottom walls of the multiple trench gate structures 37. The outer well region 49 forms a pn junction with the drift region 8.

[0196] The SiC semiconductor device 1A includes at least one (preferably two to 20) p-type field region 50 formed in a surface layer portion of the outer surface 32 in a region between the outer contact region 48 and the periphery of the outer surface 32. The multiple field regions 50 relieve the electric field within the SiC chip 2 at the outer surface 32. The number, width, depth, p-type impurity concentration, etc. of the field regions 50 are arbitrary and can take various values ​​depending on the electric field to be relieved. In this embodiment, the SiC semiconductor device 1A includes five field regions 50.

[0197] The multiple field regions 50 are formed at intervals from the outer contact region 48 toward the periphery of the outer side surface 32. The multiple field regions 50 are formed in strip shapes extending along the active surface 31 in a plan view. In this embodiment, the multiple field regions 50 are formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active surface 31 in a plan view. As a result, the multiple field regions 50 are each formed as an FLR (Field Limiting Ring) region.

[0198] The multiple field regions 50 are formed at intervals from the bottom of the drift region 8 to the outer surface 32. The multiple field regions 50 are located on the bottom side of the drift region 8 with respect to the bottom walls of the multiple trench gate structures 37. The multiple field regions 50 are formed deeper than the outer contact regions 48. The innermost field region 50 may be connected to the outer contact region 48. The field regions 50 other than the innermost field region 50 may be formed in an electrically floating state.

[0199] The SiC semiconductor device 1A includes a main surface insulating film 51 that covers the first main surface 3 (the active surface 31, the outer side surface 32, and the first to fourth connecting surfaces 33A to 33D). The main surface insulating film 51 is continuous with the gate insulating film 39 and the source insulating film 43, and exposes the gate electrode 40 and the source electrode 44.

[0200] The SiC semiconductor device 1A includes a sidewall structure 52 formed above the outer side surface 32 so as to cover at least one of the first to fourth connection surfaces 33A to 33D. Specifically, the sidewall structure 52 is formed on the main surface insulating film 51. The sidewall structure 52 may include an inorganic insulator or polysilicon.

[0201] The SiC semiconductor device 1A includes an interlayer insulating film 53 formed on a main surface insulating film 51. The interlayer insulating film 53 covers the active surface 31, the outer side surface 32, and the first to fourth connecting surfaces 33A to 33D. The interlayer insulating film 53 covers the main surface insulating film 51 with a sidewall structure 52 sandwiched therebetween.

[0202] The SiC semiconductor device 1A includes a gate principal surface electrode 54 (first principal surface electrode) formed on the first principal surface 3 (on the interlayer insulating film 53). The gate principal surface electrode 54 transmits an externally input gate potential to the plurality of trench gate structures 37 (gate electrodes 40). In this embodiment, the gate principal surface electrode 54 is disposed on the active surface 31, but is not disposed on the outer side surface 32. The gate principal surface electrode 54 includes a gate pad electrode 55 and a gate wiring electrode 56. In this embodiment, the gate pad electrode 55 is disposed in a region close to the center of the first connection surface 33A on the periphery of the active surface 31.

[0203] The gate wiring electrode 56 is drawn out from the gate principal surface electrode 54 onto the interlayer insulating film 53. The gate wiring electrode 56 is formed in a strip shape extending along the periphery of the active surface 31 so as to intersect (specifically, orthogonally intersect) with the ends of the plurality of trench gate structures 37 in a plan view. The gate wiring electrode 56 penetrates the interlayer insulating film 53 and is electrically connected to the plurality of trench gate structures 37 (gate electrodes 40). The gate wiring electrode 56 transmits the gate potential applied to the gate principal surface electrode 54 to the plurality of trench gate structures 37.

[0204] The SiC semiconductor device 1A includes a source principal surface electrode 57 (second principal surface electrode) formed on the first principal surface 3 (on the interlayer insulating film 53). The source principal surface electrode 57 transmits a source potential input from the outside to the multiple trench source structures 41 (source electrodes 44). In this embodiment, the source principal surface electrode 57 is disposed on the active surface 31 and the outer side surface 32. The source principal surface electrode 57 includes a source pad electrode 58 and a source wiring electrode 59. The source pad electrode 58 is disposed on the active surface 31 at a distance from the gate principal surface electrode 54.

[0205] In this embodiment, the source pad electrode 58 is formed in a polygonal shape having a recess recessed inward into the active surface 31 on a side along the gate principal surface electrode 54 in a plan view so as to be aligned with the gate principal surface electrode 54. The source pad electrode 58 penetrates the interlayer insulating film 53 and is electrically connected to the plurality of trench source structures 41, the source regions 36, and the plurality of well regions 46. The source pad electrode 58 transmits a source potential input from the outside to the plurality of trench source structures 41, the source regions 36, and the plurality of well regions 46.

[0206] The source wiring electrode 59 is drawn out from the source pad electrode 58 onto the interlayer insulating film 53 and is formed in a strip shape extending along the periphery (first to fourth connection surfaces 33A to 33D) of the active surface 31. In this embodiment, the source wiring electrode 59 is formed in a ring shape (specifically, a quadrangular ring) that collectively surrounds the gate main surface electrode 54, the source pad electrode 58, and the gate wiring electrode 56 in plan view.

[0207] The source wiring electrode 59 covers the sidewall structure 52 with the interlayer insulating film 53 sandwiched therebetween, and is drawn out from the active surface 31 side to the outer surface 32 side. The source wiring electrode 59 penetrates the interlayer insulating film 53 on the outer surface 32 side and is electrically connected to the outer contact region 48. It is preferable that the source wiring electrode 59 covers the entire area of ​​the sidewall structure 52 and the entire area of ​​the outer contact region 48 over the entire periphery. The source wiring electrode 59 transmits the source potential applied to the source pad electrode 58 to the multiple outer contact regions 48.

[0208] The SiC semiconductor device 1A includes a drain electrode 60 (third principal surface electrode) formed on the second principal surface 4. The drain electrode 60 covers the entire second principal surface 4 and is continuous with the periphery of the second principal surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 60 forms ohmic contact with the base region 6 (second principal surface 4). The drain electrode 60 transmits a drain potential to the base region 6.

[0209] As described above, this structure can provide a SiC semiconductor device 1A having a trench-gate type SiC-MISFET whose electrical characteristics are improved by the drift region 8. Of course, the structure of the functional device 9 (SiC-MISFET) according to the third embodiment can also be applied to any one of the first to twelfth embodiments except for the first embodiment.

[0210] For example, when the structure of the functional device 9 according to the third embodiment is applied to a drift region 8 having a first region 8a and a second region 8b, the active plateau 34 is formed only in the second region 8b of the drift region 8, and the functional device 9 is formed in the second region 8b. Furthermore, when the structure of the functional device 9 according to the third embodiment is formed in a p-type drift region 18, the structure is such that the "n-type region" is replaced with the "p-type region" and the "p-type region" is replaced with the "n-type region".

[0211] Fig. 35 is a plan view showing a structure in which a functional device 9 according to a fourth embodiment is applied to a SiC semiconductor device 1J according to the tenth embodiment. Fig. 36 is an enlarged view of region XXXVI shown in Fig. 35. Fig. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in Fig. 36. Hereinafter, structures corresponding to those described in the tenth embodiment will be given the same reference numerals, and their description will be omitted.

[0212] 35 to 37, the SiC semiconductor device 1J includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, a p-type column region 19, and a functional device 9. The drift region 8 includes a first region 8a and a second region 8b, as in the tenth embodiment. The column region 19 is formed in the second region 8b, as in the tenth embodiment. FIGS. 35 to 37 show an example in which the column regions 19 are arranged at intervals in a first direction X (a-axis direction) in a plan view and formed in strips extending in a second direction Y (m-axis direction). In this embodiment, the functional device 9 is a trench-gate superjunction SiC MISFET. The structure of the SiC MISFET will be specifically described below.

[0213] The SiC semiconductor device 1J includes a p-type body region 61 formed in a surface layer portion of the first main surface 3. The body region 61 forms a part of the body diode of the SiC-MISFET. Specifically, the body region 61 is formed at a distance from the lower ends of the plurality of column regions 19 toward the first main surface 3 so as to be connected to the plurality of column regions 19. It is preferable that the body region 61 is formed at a distance from the middle portions of the plurality of column regions 19 toward the first main surface 3.

[0214] The SiC semiconductor device 1J includes an n-type source region 62 formed in a surface layer portion of a body region 61. The source region 62 forms the source of the SiC-MISFET. The source region 62 has an n-type impurity concentration that exceeds the n-type impurity concentration of the drift region 8. The source region 62 forms a channel CH of the SiC-MISFET together with the drift region 8 within the body region 61.

[0215] The SiC semiconductor device 1J includes a plurality of trench gate structures 63 formed on the first main surface 3. The plurality of trench gate structures 63 form gates of the SiC-MISFET and control the inversion (on) and non-inversion (off) of the channel CH. The plurality of trench gate structures 63 are formed to cross the body region 61 and the source region 62 and reach the drift region 8.

[0216] Specifically, the plurality of trench gate structures 63 are each formed in a region between two adjacent column regions 19 in plan view. The plurality of trench gate structures 63 are each formed in a strip shape extending in the direction in which the plurality of column regions 19 extend in plan view. In other words, the plurality of trench gate structures 63 are arranged in stripes extending parallel to the plurality of column regions 19. Of course, the plurality of trench gate structures 63 are each formed in a strip shape extending in a direction intersecting (orthogonal to) the plurality of column regions 19 in plan view.

[0217] Each trench gate structure 63 is formed at an interval from the bottom of the drift region 8 toward the first main surface 3, and faces the buffer region 7 across a part of the drift region 8. Specifically, each trench gate structure 63 is formed in the second region 8b at an interval from the first region 8a toward the first main surface 3, and faces the buffer region 7 across a part of the second region 8b and the first region 8a.

[0218] Each trench gate structure 63 includes a gate trench 64, a gate insulating film 65, and a gate electrode 66. The gate trench 64 is formed in the first main surface 3. The gate insulating film 65 is formed in the form of a film on the inner wall of the gate trench 64. The gate electrode 66 is buried in the gate trench 64 with the gate insulating film 65 sandwiched between them. The gate electrode 66 faces the drift region 8 (second region 8b), the body region 61, and the source region 62 with the gate insulating film 65 sandwiched between them. A gate potential is applied to the gate electrode 66.

[0219] The SiC semiconductor device 1J includes a plurality of p-type contact regions 67 formed in a surface layer portion of the body region 61. The p-type impurity concentrations of the plurality of contact regions 67 exceed the p-type impurity concentration of the body region 61. The plurality of contact regions 67 are each formed in a region between two adjacent gate trenches 64 in a planar view. The plurality of contact regions 67 face the plurality of column regions 19 in a one-to-one correspondence in a planar view. The plurality of contact regions 67 are each formed in a strip shape extending in the second direction Y in a planar view. The plurality of contact regions 67 are each formed at an interval in the first direction X from the two adjacent gate trenches 64.

[0220] The SiC semiconductor device 1J includes a main surface insulating film 68 that covers the first main surface 3. The main surface insulating film 68 is continuous with the gate insulating film 65 and exposes the gate electrode 66. The SiC semiconductor device 1J also includes an interlayer insulating film 69 formed on the main surface insulating film 68. The interlayer insulating film 69 covers the first main surface 3 with the main surface insulating film 68 sandwiched therebetween.

[0221] The SiC semiconductor device 1J includes a gate principal surface electrode 70 (first principal surface 3 electrode) formed on the first principal surface 3 (on the interlayer insulating film 69). The gate principal surface electrode 70 transmits a gate potential input from the outside to the multiple trench gate structures 63 (gate electrodes 66). The gate principal surface electrode 70 includes a gate pad electrode 71 and a gate wiring electrode 72. In this embodiment, the gate pad electrode 71 is disposed in a region close to the center of the first side surface 5A on the periphery of the first principal surface 3.

[0222] The gate wiring electrode 72 is drawn out from the gate principal surface electrode 70 onto the interlayer insulating film 69. The gate wiring electrode 72 is formed in a strip shape extending along the periphery of the first principal surface 3 so as to intersect (specifically, orthogonally intersect) with the ends of the plurality of trench gate structures 63 in a plan view. The gate wiring electrode 72 penetrates the interlayer insulating film 69 and is electrically connected to the plurality of trench gate structures 63 (gate electrodes 66). The gate wiring electrode 72 transmits the gate potential applied to the gate principal surface electrode 70 to the plurality of trench gate structures 63.

[0223] The SiC semiconductor device 1J includes a source main surface electrode 73 (second main surface electrode) formed on the first main surface 3 (on the interlayer insulating film 69). The source main surface electrode 73 transmits a source potential input from the outside to the source region 62 and the plurality of contact regions 67. The source main surface electrode 73 includes a source pad electrode 74. The source pad electrode 74 is disposed on the first main surface 3 at a distance from the gate main surface electrode 70.

[0224] In this embodiment, the source pad electrode 74 is formed in a polygonal shape having a recess recessed inward into the first main surface 3 so as to align with the gate main surface electrode 70 on a side along the gate main surface electrode 70 in a plan view. The source pad electrode 74 penetrates the interlayer insulating film 69 and is electrically connected to the source region 62 and the plurality of contact regions 45. The source pad electrode 74 transmits a source potential input from the outside to the source region 62 and the plurality of contact regions 45.

[0225] The SiC semiconductor device 1J includes a drain electrode 75 (third principal surface electrode) formed on the second principal surface 4. The drain electrode 75 covers the entire second principal surface 4 and is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second principal surface 4. The drain electrode 75 forms ohmic contact with the base region 6 (second principal surface 4).

[0226] As described above, this structure can provide a SiC semiconductor device 1J having a trench-gate superjunction SiC-MISFET whose electrical characteristics are improved by the drift region 8 and the plurality of column regions 19. Of course, the structure of the functional device 9 (SiC-MISFET) according to the fourth embodiment can also be applied to any one of the ninth to twelfth embodiments except for the tenth embodiment. For example, when the structure of the functional device 9 according to the fourth embodiment is formed in a p-type drift region 18, the structure is such that the "n-type region" is replaced with a "p-type region" and the "p-type region" is replaced with an "n-type region."

[0227] 38 is a cross-sectional view showing a structure in which a functional device 9 according to the fifth embodiment is applied to a SiC semiconductor device 1J according to the tenth embodiment. Hereinafter, structures corresponding to those described in the tenth embodiment are given the same reference numerals, and their description will be omitted.

[0228] Referring to FIG. 38 , the SiC semiconductor device 1J includes a SiC chip 2, an n-type base region 6, an n-type buffer region 7, an n-type drift region 8, a p-type column region 19, and a functional device 9. The drift region 8 includes a first region 8a and a second region 8b, as in the tenth embodiment. The column region 19 is formed in the second region 8b, as in the tenth embodiment. FIG. 38 illustrates an example in which the column regions 19 are arranged at intervals in a first direction X (a-axis direction) in a planar view and formed in strips extending in a second direction Y (m-axis direction). In this embodiment, the functional device 9 is a planar-gate superjunction SiC MISFET. The structure of the SiC MISFET will be specifically described below.

[0229] The SiC semiconductor device 1J includes a plurality of p-type body regions 81 formed in a surface layer portion of the first main surface 3. The plurality of body regions 81 form part of body diodes of the SiC-MISFET. Specifically, the plurality of body regions 81 are formed at intervals from the lower ends of the plurality of column regions 19 toward the first main surface 3 so as to be connected to the plurality of column regions 19 in a one-to-one correspondence. It is preferable that the body regions 81 are formed at intervals from the middle portions of the plurality of column regions 19 toward the first main surface 3 in the thickness direction. The plurality of body regions 81 may each be formed in a strip shape extending along the plurality of column regions 19 in a plan view.

[0230] The SiC semiconductor device 1J includes a plurality of n-type source regions 82 formed in the surface layer portions of the plurality of body regions 81, respectively. These form the source of the SiC-MISFET. The source regions 82 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 8. The plurality of source regions 82 are each formed in the inner portion of the corresponding body region 81, spaced apart from the periphery of the corresponding body region 81 in plan view. The plurality of source regions 82 may each be formed in a strip shape extending along the plurality of column regions 19 in plan view. The source region 82, together with the drift region 8, forms a channel CH of the SiC-MISFET within the body region 81.

[0231] The SiC semiconductor device 1J includes a plurality of p-type contact regions 83 formed in the surface layer portions of the plurality of body regions 81, respectively. The p-type impurity concentrations of the plurality of contact regions 83 exceed the p-type impurity concentration of the body region 81. The plurality of contact regions 83 are each formed in the surface layer portions of the corresponding body regions 81 so as to penetrate the corresponding source regions 82. The plurality of contact regions 83 may each be formed in a strip shape extending along the plurality of column regions 19 in a plan view. The SiC semiconductor device 1J includes a plurality of planar gate structures 84 formed on the first main surface 3. The plurality of planar gate structures 84 form gates of the SiC-MISFET and control the inversion (on) and non-inversion (off) of the channel CH. The plurality of planar gate structures 84 cover the drift region 8, the body region 81, and the source region 82, respectively.

[0232] Specifically, the plurality of planar gate structures 84 are each formed in a region between two adjacent body regions 81 in a planar view. The plurality of planar gate structures 84 are each formed in a strip shape extending in the direction in which the plurality of column regions 19 extend in a planar view. In other words, the plurality of planar gate structures 84 are arranged in stripes extending parallel to the plurality of column regions 19. Of course, the plurality of planar gate structures 84 are each formed in a strip shape extending in a direction intersecting (orthogonal to) the plurality of column regions 19 in a planar view.

[0233] Each planar gate structure 84 includes a gate insulating film 85 and a gate electrode 86. The gate insulating film 85 covers the channel CH on the first main surface 3. The gate insulating film 85 specifically covers the drift region 8 (second region 8b), the body region 81, and the source region 82. The gate electrode 86 faces the channel CH across the gate insulating film 85. The gate electrode 86 specifically faces the drift region 8 (second region 8b), the body region 81, and the source region 82 across the gate insulating film 85. A gate potential is applied to the gate electrode 86.

[0234] The SiC semiconductor device 1J includes an interlayer insulating film 87 formed on the first main surface 3. The interlayer insulating film 87 covers a plurality of planar gate structures 84. Like the functional device 9 according to the third embodiment, the SiC semiconductor device 1J includes a gate main surface electrode 70 (first main surface electrode), a source main surface electrode 73 (second main surface electrode), and a drain electrode 75. The gate main surface electrode 70 includes a gate pad electrode 71 and a gate wiring electrode 72. The gate wiring electrode 72 penetrates the interlayer insulating film 87 and is electrically connected to a plurality of planar gate structures 84 (gate electrodes 86). The source main surface electrode 73 includes a source pad electrode 74. The source pad electrode 74 penetrates the interlayer insulating film 87 and is electrically connected to a plurality of source regions 82 and a plurality of contact regions 45.

[0235] As described above, this structure can provide a SiC semiconductor device 1J having a planar gate superjunction SiC-MISFET whose electrical characteristics are improved by the drift region 8 and the plurality of column regions 19. Of course, the structure of the functional device 9 (SiC-MISFET) according to the fifth embodiment can also be applied to any one of the ninth to twelfth embodiments except for the tenth embodiment. For example, when the structure of the functional device 9 according to the fifth embodiment is formed in a p-type drift region 18, the structure is such that the "n-type region" is replaced with a "p-type region" and the "p-type region" is replaced with an "n-type region."

[0236] Each of the above-described embodiments can be implemented in further different forms. In each of the above-described embodiments, a structure has been described in which the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. However, each of the above-described embodiments may also employ a structure in which the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. A specific structure in this case can be obtained by interchanging the "a-axis direction" and "m-axis direction" in each of the above-described embodiments.

[0237] In the above-described embodiments, an example in which a SiC chip 2 is used has been described. However, instead of the SiC chip 2, a WBG (Wide Band Gap) semiconductor chip made of a WBG semiconductor other than SiC may be used. A WBG semiconductor is a semiconductor having a band gap that exceeds the band gap of Si (silicon). A specific structure in this case can be obtained by replacing "SiC" with "WBG semiconductor" in the description of the above-described embodiments. The WBG semiconductor chip may be made of a diamond chip made of, for example, a C single crystal (diamond). In other words, the WBG semiconductor chip may be made of a WBG semiconductor single crystal containing C (carbon).

[0238] In the above-described ninth and tenth embodiments, examples have been described in which the drift region 8 has an impurity concentration adjusted by at least two pentavalent elements, and the plurality of column regions 19 have impurity concentrations adjusted by a trivalent element other than boron. However, in the above-described ninth and tenth embodiments, the drift region 8 may have an impurity concentration adjusted by at least two pentavalent elements, and the plurality of column regions 19 may have impurity concentrations adjusted by any trivalent element. Furthermore, in the above-described ninth and tenth embodiments, the drift region 8 may have an impurity concentration adjusted by any pentavalent element, and the plurality of column regions 19 may have impurity concentrations adjusted by a trivalent element other than boron.

[0239] In the above-described eleventh and twelfth embodiments, examples have been described in which the drift region 18 has an impurity concentration adjusted by a trivalent element other than boron, and the plurality of column regions 20 have impurity concentrations adjusted by a pentavalent element other than phosphorus and nitrogen. However, in the above-described eleventh and twelfth embodiments, the drift region 18 may have an impurity concentration adjusted by a trivalent element other than boron, and the plurality of column regions 20 may have impurity concentrations adjusted by any pentavalent element. Also, in the above-described eleventh and twelfth embodiments, the drift region 18 may have an impurity concentration adjusted by any pentavalent element, and the plurality of column regions 20 may have impurity concentrations adjusted by a pentavalent element other than phosphorus and nitrogen.

[0240] Below are examples of features extracted from this specification and drawings. [A1] to [A29], [B1] to [B22], [C1] to [C33], and [D1] to [D24] below provide a semiconductor device capable of improving electrical characteristics. [E1] to [E22] below provide a manufacturing method for a semiconductor device capable of improving electrical characteristics. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments.

[0241] [A1] A semiconductor device (1A-1L) including a WBG (Wide Band Gap) semiconductor chip (2) having a main surface (3), and an n-type drift region (8, 18) formed in a surface layer portion of the main surface (3) and having an impurity concentration adjusted by at least two pentavalent elements.

[0242] [A2] The semiconductor device (1A to 1L) according to A1, wherein the drift region (8, 18) has an impurity concentration adjusted to increase toward the main surface (3).

[0243] [A3] The semiconductor device (1A to 1L) according to A1 or A2, wherein the drift region (8, 18) has an impurity concentration adjusted with a pentavalent element other than phosphorus.

[0244] [A4] The semiconductor device (1A to 1L) according to any one of A1 to A3, wherein the drift region (8, 18) contains nitrogen as a pentavalent element and a pentavalent element other than nitrogen.

[0245] [A5] A semiconductor device (1A to 1L) according to any one of A1 to A4, wherein the drift region (8, 18) has a base concentration (CA) due to a first impurity that is a pentavalent element, and an additional concentration (CB) due to a second impurity that is a pentavalent element other than the first impurity.

[0246] [A6] The semiconductor device (1A to 1L) according to A5, wherein the first impurity is a pentavalent element other than phosphorus, and the second impurity is a pentavalent element other than phosphorus.

[0247] [A7] The semiconductor device (1A to 1L) according to A6, wherein the first impurity is nitrogen, and the second impurity is at least one of arsenic and antimony.

[0248] [A8] The semiconductor device (1A to 1L) according to any one of A5 to A7, wherein the additional concentration (CB) has a concentration distribution that increases toward the main surface (3).

[0249] [A9] The semiconductor device (1A to 1L) according to any one of A5 to A8, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0250] [A10] A semiconductor device (1A to 1L) including a WBG (Wide Band Gap) semiconductor chip (2) having a main surface (3), and a p-type drift region (8, 18) formed in a surface layer portion of the main surface (3) and having an impurity concentration adjusted by a trivalent element other than boron.

[0251] [A11] The semiconductor device (1A to 1L) according to A10, wherein the drift region (8, 18) has an impurity concentration adjusted to increase toward the main surface (3).

[0252] [A12] The semiconductor device (1A to 1L) according to A10 or A11, wherein the drift region (8, 18) contains at least one trivalent element selected from the group consisting of aluminum, gallium, and indium.

[0253] [A13] A semiconductor device (1A to 1L) according to any one of A10 to A12, wherein the drift region (8, 18) has a base concentration (CA) due to a first impurity that is a trivalent element, and an additional concentration (CB) due to a second impurity that is the same as or different from the first impurity and that is a trivalent element.

[0254] [A14] The semiconductor device (1A to 1L) according to A13, wherein the first impurity is aluminum, and the second impurity is at least one of aluminum, gallium, and indium.

[0255] [A15] The semiconductor device (1A to 1L) according to A13 or A14, wherein the additional concentration (CB) has a concentration distribution that increases toward the main surface (3).

[0256] [A16] The semiconductor device (1A to 1L) according to any one of A13 to A15, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0257] [A17] The semiconductor device (1A to 1L) according to any one of A1 to A16, wherein the drift region (8, 18) has a thickness in any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0258] [A18] The semiconductor device (1A to 1L) according to any one of A1 to A17, wherein the WBG semiconductor chip (2) contains C (carbon).

[0259] [A19] The semiconductor device (1A to 1L) according to any one of A1 to A18, wherein the WBG semiconductor chip (2) is made of a SiC chip (2).

[0260] [A20] The semiconductor device (1A to 1L) described in A19, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the main surface (3) faces the c-plane of the SiC single crystal and has an off angle (θ) of 10° or less between it and the c-plane.

[0261] [A21] The semiconductor device (1A to 1L) according to A20, wherein the off angle (θ) has an off direction (D) along the a-axis direction of the SiC single crystal.

[0262] [A22] The semiconductor device (1A to 1L) according to any one of A1 to A21, wherein the drift region (8, 18) is formed in a WBG semiconductor epitaxial layer.

[0263] [A23] The semiconductor device (1A to 1L) according to any one of A1 to A22, further comprising a functional device (9) formed on the main surface (3).

[0264] [A24] The semiconductor device (1A to 1L) according to A23, wherein the functional device (9) includes a diode.

[0265] [A25] The semiconductor device (1A to 1L) according to A24, further comprising an insulating film (22) covering the main surface (3) so as to partially expose the main surface (3), a first main surface electrode (23) electrically connected to the main surface (3), and a second main surface electrode (24) formed on a surface (4) opposite the main surface (3).

[0266] [A26] The semiconductor device (1A to 1L) according to A25, wherein the insulating film (22) exposes the drift region (8, 18), and the first main surface electrode (23) forms a Schottky junction with the drift region (8, 18).

[0267] [A27] The semiconductor device (1A to 1L) according to A23, wherein the functional device (9) further includes a transistor.

[0268] [A28] The semiconductor device (1A to 1L) according to A27, further including a channel (CH) formed in a surface layer portion of the drift region (8, 18), and a gate structure (37, 63, 84) formed on the main surface (3) for controlling the on / off of the channel (CH).

[0269] [A29] The semiconductor device (1A to 1L) according to A28, further including a first main surface electrode (54, 70) arranged on the main surface (3) and electrically connected to the gate structure (37, 63, 84), a second main surface electrode (57, 73) arranged on the main surface (3) and electrically connected to the channel (CH), and a third main surface electrode (60, 75) formed on a surface (4) opposite to the main surface (3).

[0270] [B1] A WBG (Wide Band Gap) semiconductor chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side; a first conductivity type base region (6, 16) formed in a region on the second main surface (4) side in the WBG semiconductor chip (2), containing a first impurity of a first conductivity type and having a first concentration (C1); and a first conductivity type base region (6, 16) formed in a region on the first main surface (3) side in the WBG semiconductor chip (2) with respect to the base region (6, 16), containing the first impurity and having a concentration that decreases from the first concentration (C1) to a second concentration (C2) starting from the base region (6, 16). a first conductivity type buffer region (7, 17) having a concentration distribution, and a first conductivity type drift region (8, 18) formed in a region between the first main surface (3) and the buffer region (7, 17) in the WBG semiconductor chip (2), containing the first impurity and a second impurity of the first conductivity type different from the first impurity, and having a concentration distribution that increases from the second concentration (C2) to a third concentration (C3) starting from the buffer region (7, 17).

[0271] [B2] The semiconductor device (1A to 1L) according to B1, wherein the drift region (8, 18) contains the first impurity and the second impurity in a surface region and a bottom region relative to an intermediate portion (MID) between the first main surface (3) and the buffer region (7, 17).

[0272] [B3] The semiconductor device (1A to 1L) according to B1 or B2, wherein the third concentration (C3) is less than the first concentration (C1).

[0273] [B4] The semiconductor device (1A to 1L) according to any one of B1 to B3, wherein the third concentration (C3) is 10 times or more the second concentration (C2).

[0274] [B5] A semiconductor device (1A to 1L) according to any one of B1 to B4, wherein the drift region (8, 18) includes a base concentration (CA) due to the first impurity and an additional concentration (CB) due to the second impurity.

[0275] [B6] The semiconductor device (1A to 1L) according to B5, wherein the additional concentration (CB) has a concentration distribution that increases toward the first main surface (3).

[0276] [B7] The semiconductor device (1A to 1L) according to B5 or B6, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0277] [B8] The semiconductor device (1A to 1L) according to any one of B1 to B7, wherein the first conductivity type is n-type.

[0278] [B9] The semiconductor device (1A to 1L) according to B8, wherein the first impurity is a pentavalent element other than phosphorus.

[0279] [B10] The semiconductor device (1A to 1L) according to B8 or B9, wherein the first impurity is nitrogen.

[0280] [B11] The semiconductor device (1A to 1L) according to any one of B8 to B10, wherein the second impurity is a pentavalent element other than phosphorus.

[0281] [B12] The semiconductor device (1A to 1L) according to any one of B8 to B11, wherein the second impurity is at least one of arsenic and antimony.

[0282] [B13] A semiconductor device (1A to 1L) according to any one of B1 to B12, wherein the base region (6, 16) has a first thickness, the buffer region (7, 17) has a second thickness less than the first thickness, and the drift region (8, 18) has a third thickness greater than or equal to the second thickness.

[0283] [B14] The semiconductor device (1A to 1L) according to B13, wherein the third thickness is less than the first thickness.

[0284] [B15] The semiconductor device (1A to 1L) according to B13 or B14, wherein the third thickness falls within any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0285] [B16] The semiconductor device (1A to 1L) according to any one of B1 to B15, wherein the WBG semiconductor chip (2) contains C (carbon).

[0286] [B17] The semiconductor device (1A to 1L) according to any one of B1 to B16, wherein the WBG semiconductor chip (2) is made of a SiC chip (2).

[0287] [B18] The semiconductor device (1A to 1L) according to B17, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the first main surface (3) faces the c-plane of the SiC single crystal and has an off angle (θ) of 10° or less between it and the c-plane.

[0288] [B19] The semiconductor device (1A to 1L) according to B18, wherein the off angle (θ) has an off direction (D) along the a-axis direction of the SiC single crystal.

[0289] [B20] A semiconductor device (1A to 1L) according to any one of B1 to B19, wherein the base region (6, 16) is formed in a semiconductor substrate, the buffer region (7, 17) is formed in an epitaxial layer, and the drift region (8, 18) is formed in an epitaxial layer.

[0290] [B21] The semiconductor device (1A to 1L) according to any one of B1 to B20, further comprising a functional device (9) formed on the first main surface (3).

[0291] [B22] The semiconductor device (1A to 1L) according to B21, wherein the functional device (9) includes at least one of a diode and a transistor.

[0292] [C1] A semiconductor device (1A-1L) including: a WBG (Wide Band Gap) semiconductor chip (2) having a main surface (3); an n-type drift region (8, 18) formed in a surface layer portion of the main surface (3) and having an impurity concentration adjusted by at least two pentavalent elements; and a p-type impurity region (19, 20) formed in the drift region (8, 18) so as to form a p-n junction with the drift region (8, 18).

[0293] [C2] A semiconductor device (1A-1L) including a WBG semiconductor chip (2) having a main surface (3), an n-type drift region (8, 18) formed in a surface layer portion of the main surface (3), and a p-type impurity region (19, 20) formed in the drift region (8, 18) so as to form a p-n junction with the drift region (8, 18), the p-type impurity region (19, 20) having an impurity concentration adjusted by a trivalent element other than boron.

[0294] [C3] The semiconductor device (1A to 1L) according to C2, wherein the drift region (8, 18) has an impurity concentration adjusted by at least two kinds of pentavalent elements.

[0295] [C4] A semiconductor device (1A to 1L) according to any one of C1 to C3, wherein the drift region (8, 18) has a concentration distribution that increases toward the main surface (3), and the impurity region (19, 20) has a concentration distribution that increases toward the main surface (3).

[0296] [C5] The semiconductor device (1A to 1L) according to any one of C1 to C4, wherein the drift region (8, 18) contains a pentavalent element other than phosphorus.

[0297] [C6] The semiconductor device (1A to 1L) according to any one of C1 to C5, wherein the impurity regions (19, 20) contain at least one trivalent element selected from aluminum, gallium, and indium.

[0298] [C7] A semiconductor device (1A to 1L) according to any one of C1 to C6, wherein the impurity regions (19, 20) extend in the thickness direction within the drift regions (8, 18) so as to form a super junction structure with the drift regions (8, 18) and the pn junction.

[0299] [C8] The semiconductor device (1A to 1L) according to any one of C1 to C7, wherein the impurity regions (19, 20) cross a middle portion (MID) of the drift region (8, 18) in the thickness direction of the drift region (8, 18).

[0300] [C9] The semiconductor device (1A to 1L) according to any one of C1 to C8, wherein the impurity regions (19, 20) are formed at intervals from the bottom of the drift region (8, 18) toward the main surface (3).

[0301] [C10] A semiconductor device (1A to 1L) according to any one of C1 to C9, wherein the drift region (8, 18) includes a base concentration (CA) due to a first impurity that is a pentavalent element, and an additional concentration (CB) due to a second impurity that is a pentavalent element other than the first impurity.

[0302] [C11] The semiconductor device (1A to 1L) according to C10, wherein the drift region (8, 18) includes a first region (8a, 18a) formed in a surface layer of the main surface (3) at a distance from the main surface (3) and consisting of the basic concentration (CA), and a second region (8b, 18b) formed in a region between the main surface (3) and the first region (8a, 18a) and consisting of the basic concentration (CA) and the additional concentration (CB), and the impurity region (19, 20) is formed in the second region (8b, 18b) so as to form the pn junction with the second region (8b, 18b).

[0303] [C12] The semiconductor device (1A to 1L) according to C11, wherein the impurity regions (19, 20) are formed in the second regions (8b, 18b) at intervals on the main surface (3) side from the first regions (8a, 18a).

[0304] [C13] The semiconductor device (1A to 1L) according to any one of C10 to C12, wherein the additional concentration (CB) has a concentration distribution that increases toward the main surface (3).

[0305] [C14] The semiconductor device (1A to 1L) according to any one of C10 to C13, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0306] [C15] The semiconductor device (1A to 1L) according to any one of C10 to C14, wherein the first impurity is a pentavalent element other than phosphorus.

[0307] [C16] The semiconductor device (1A to 1L) according to any one of C10 to C15, wherein the first impurity is nitrogen, and the second impurity is at least one of arsenic and antimony.

[0308] [C17] A semiconductor device (1A-1L) comprising: a WBG semiconductor chip (2) having a main surface (3); a p-type drift region (8, 18) formed in a surface layer portion of the main surface (3) and having an impurity concentration adjusted by a trivalent element other than boron; and an n-type impurity region (19, 20) formed in the drift region (8, 18) so as to form a p-n junction with the drift region (8, 18), and having an impurity concentration adjusted by a pentavalent element other than phosphorus and nitrogen.

[0309] [C18] The semiconductor device (1A to 1L) according to C17, wherein the drift regions (8, 18) have a concentration distribution that increases toward the main surface (3), and the impurity regions (19, 20) have a concentration distribution that increases toward the main surface (3).

[0310] [C19] The semiconductor device (1A to 1L) according to C17 or C18, wherein the impurity regions (19, 20) extend in the thickness direction within the drift regions (8, 18) so as to form a super junction structure with the drift regions (8, 18) and the pn junction.

[0311] [C20] A semiconductor device (1A to 1L) according to any one of C17 to C19, wherein the drift region (8, 18) contains at least one trivalent element selected from aluminum, gallium, and indium, and the impurity region (19, 20) contains at least one of arsenic and antimony.

[0312] [C21] The semiconductor device (1A to 1L) according to any one of C1 to C20, wherein the drift region (8, 18) has a thickness in any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0313] [C22] The semiconductor device (1A to 1L) according to any one of C1 to C21, wherein the WBG semiconductor chip (2) contains C (carbon).

[0314] [C23] The semiconductor device (1A to 1L) according to any one of C1 to C22, wherein the WBG semiconductor chip (2) is made of a SiC chip (2).

[0315] [C24] The semiconductor device (1A to 1L) described in C23, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the main surface (3) faces the c-plane of the SiC single crystal and has an off angle (θ) of 10° or less between it and the c-plane.

[0316] [C25] The semiconductor device (1A to 1L) described in C24, wherein the off angle (θ) has an off direction (D) along the a-axis direction of the SiC single crystal, and the impurity regions (19, 20) are formed in a band shape extending along the a-axis direction in a planar view.

[0317] [C26] The semiconductor device (1A to 1L) according to any one of C1 to C25, wherein the drift region (8, 18) is formed in an epitaxial layer.

[0318] [C27] The semiconductor device (1A to 1L) according to any one of C1 to C26, further comprising a functional device (9) formed on the main surface (3).

[0319] [C28] The semiconductor device (1A to 1L) according to C27, wherein the functional device (9) includes a diode.

[0320] [C29] The semiconductor device (1A to 1L) according to C28, further comprising an insulating film (22) covering the main surface (3) so as to partially expose the main surface (3), a first main surface electrode (23) electrically connected to the main surface (3), and a second main surface electrode (24) formed on a surface (4) opposite the main surface (3).

[0321] [C30] The semiconductor device (1A to 1L) according to C29, wherein the insulating film (22) exposes the drift region (8, 18), and the first main surface electrode (23) forms a Schottky junction with the drift region (8, 18).

[0322] [C31] The semiconductor device (1A to 1L) according to C27, wherein the functional device (9) further includes a transistor.

[0323] [C32] The semiconductor device (1A to 1L) according to C31, further comprising: a channel (CH) formed in a surface layer portion of the drift region (8, 18); and a gate structure (37, 63, 84) formed on the main surface (3) for controlling the on / off of the channel (CH).

[0324] [C33] A semiconductor device (1A to 1L) according to C32, further comprising: a first principal surface electrode (54, 70) disposed on the principal surface (3) and electrically connected to the gate structure (37, 63, 84); a second principal surface electrode (57, 73) disposed on the principal surface (3) and electrically connected to the channel (CH); and a third principal surface electrode (60, 75) formed on a surface (4) opposite to the principal surface (3).

[0325] [D1] A WBG (Wide Band Gap) semiconductor chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side; a first conductivity type base region (6, 16) formed in a region on the second main surface (4) side in the WBG semiconductor chip (2), containing a first conductivity type first impurity and having a first concentration (C1); a first conductivity type buffer region (7, 17) formed in a region on the first main surface (3) side of the base region (6, 16) in the WBG semiconductor chip (2), containing the first impurity and having a concentration distribution that decreases from the first concentration (C1) to a second concentration (C2) starting from the base region (6, 16); a first conductivity type drift region (8, 18) formed in a region between the first main surface (3) and the buffer region (7, 17) within the first conductivity type drift region (8, 18), containing the first impurity and a second impurity of a first conductivity type different from the first impurity, and having a concentration distribution that increases from the second concentration (C2) to a third concentration (C3) starting from the buffer region (7, 17), and a plurality of second conductivity type column regions (19, 20) formed in the drift region (8, 18) so as to form a super junction structure with the drift region (8, 18).

[0326] [D2] The semiconductor device (1A to 1L) according to D1, wherein the column regions (19, 20) extend in the thickness direction so as to cross the intermediate portions (MIDs) of the drift regions (8, 18).

[0327] [D3] The semiconductor device (1A to 1L) according to D1 or D2, wherein the column regions (19, 20) are formed at intervals from the bottom of the drift region (8, 18) toward the first main surface (3).

[0328] [D4] The semiconductor device (1A to 1L) according to any one of D1 to D3, wherein the column regions (19, 20) have a concentration distribution that increases toward the first main surface (3).

[0329] [D5] A semiconductor device (1A to 1L) according to any one of D1 to D4, wherein the drift region (8, 18) includes a base concentration (CA) due to the first impurity and an additional concentration (CB) due to the second impurity.

[0330] [D6] The semiconductor device (1A to 1L) according to D5, wherein the drift region (8, 18) includes a first region (8a, 18a) formed in a surface layer of the first main surface (3) at a distance from the first main surface (3) and consisting of the basic concentration (CA), and a second region (8b, 18b) formed in a region between the first main surface (3) and the first region (8a, 18a) and consisting of the basic concentration (CA) and the additional concentration (CB), and the column region (19, 20) is formed in the second region (8b, 18b) so as to form the super junction structure with the second region (8b, 18b).

[0331] [D7] The semiconductor device (1A to 1L) according to D6, wherein the column regions (19, 20) are formed in the second regions (8b, 18b) at intervals from the first regions (8a, 18a) toward the first main surface (3).

[0332] [D8] The semiconductor device (1A to 1L) according to any one of D5 to D7, wherein the additional concentration (CB) has a concentration distribution that increases toward the first main surface (3).

[0333] [D9] The semiconductor device (1A to 1L) according to any one of D5 to D8, wherein the base concentration (CA) has a substantially constant concentration distribution in the thickness direction.

[0334] [D10] The semiconductor device (1A to 1L) according to any one of D1 to D9, wherein the first conductivity type is n-type and the second conductivity type is p-type.

[0335] [D11] The semiconductor device (1A to 1L) according to D10, wherein the column regions (19, 20) contain a trivalent element other than boron.

[0336] [D12] The semiconductor device (1A to 1L) according to D10 or D11, wherein the column regions (19, 20) contain at least one trivalent element selected from the group consisting of aluminum, gallium, and indium.

[0337] [D13] The semiconductor device (1A to 1L) according to any one of D10 to D12, wherein the first impurity is a pentavalent element other than phosphorus, and the second impurity is a pentavalent element other than phosphorus.

[0338] [D14] The semiconductor device (1A to 1L) according to any one of D10 to D13, wherein the first impurity is nitrogen, and the second impurity is at least one of arsenic and antimony.

[0339] [D15] A semiconductor device (1A to 1L) described in any one of D1 to D14, wherein the base region (6, 16) has a first thickness, the buffer region (7, 17) has a second thickness less than the first thickness, and the drift region (8, 18) has a third thickness greater than or equal to the second thickness.

[0340] [D16] The semiconductor device (1A to 1L) according to D15, wherein the third thickness is less than the first thickness.

[0341] [D17] The semiconductor device (1A to 1L) according to D15 or D16, wherein the third thickness falls within any one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0342] [D18] The semiconductor device (1A to 1L) according to any one of D1 to D17, wherein the WBG semiconductor chip (2) contains C (carbon).

[0343] [D19] The semiconductor device (1A to 1L) according to any one of D1 to D18, wherein the WBG semiconductor chip (2) is made of a SiC chip (2).

[0344] [D20] The semiconductor device (1A to 1L) described in D19, wherein the SiC chip (2) is made of a hexagonal SiC single crystal, and the first main surface (3) faces the c-plane of the SiC single crystal and has an off angle (θ) of 10° or less between it and the c-plane.

[0345] [D21] A semiconductor device (1A to 1L) according to D20, wherein the off angle (θ) has an off direction (D) along the a-axis direction of the SiC single crystal, and the column regions (19, 20) are formed in a band shape extending along the a-axis direction in a planar view.

[0346] [D22] A semiconductor device (1A to 1L) according to any one of D1 to D21, wherein the base region (6, 16) is formed in a semiconductor substrate, the buffer region (7, 17) is formed in an epitaxial layer, and the drift region (8, 18) is formed in an epitaxial layer.

[0347] [D23] The semiconductor device (1A to 1L) according to any one of D1 to D22, further comprising a functional device (9) formed on the first main surface (3).

[0348] [D24] The semiconductor device (1A to 1L) according to D23, wherein the functional device (9) includes at least one of a diode and a transistor.

[0349] [E1] A method for manufacturing a semiconductor device (1A to 1L), comprising the steps of: preparing an epitaxial layer (14) of a first conductivity type made of a WBG (Wide Band Gap) semiconductor single crystal and adjusted to a low concentration; and forming a drift region (8, 18) of the first conductivity type having a target concentration by injecting impurities of the first conductivity type into the epitaxial layer (14) by an ion implantation method.

[0350] [E2] A method for manufacturing a semiconductor device (1A to 1L) according to E1, wherein the epitaxial layer (14) is prepared with a low concentration adjusted by a first impurity, and the drift region (8, 18) is formed by implanting a second impurity of a first conductivity type different from the first impurity into the epitaxial layer (14).

[0351] [E3] The method for manufacturing the semiconductor device (1A to 1L) according to E2, wherein the ion implantation method is a channeling implantation method in which the second impurity is implanted along the crystal axis (c-axis) of the WBG semiconductor single crystal.

[0352] [E4] A method for manufacturing a semiconductor device (1A to 1L) according to E3, wherein the second impurity is implanted into the epitaxial layer (14) at an angle of ±5° or less with respect to the crystal axis (c-axis) of the WBG semiconductor single crystal.

[0353] [E5] A method for manufacturing a semiconductor device (1A-1L) according to any one of E1 to E4, further comprising, after the step of forming the drift region (8, 18), a step of forming a second conductivity type impurity region (19, 20) that forms a pn junction with the drift region (8, 18) by injecting a second conductivity type impurity into the epitaxial layer (14) by ion implantation.

[0354] [E6] A method for manufacturing a semiconductor device (1A to 1L) according to E5, wherein the ion implantation method is a channeling implantation method in which the second conductivity type impurity is implanted along the crystal axis (c-axis) of the WBG semiconductor single crystal.

[0355] [E7] A method for manufacturing a semiconductor device (1A to 1L) according to E6, wherein the second conductivity type impurity is implanted into the epitaxial layer (14) at an angle of ±5° or less with respect to the crystal axis (c-axis) of the WBG semiconductor single crystal.

[0356] [E8] A method for manufacturing a semiconductor device (1A to 1L), comprising the steps of: preparing an n-type epitaxial layer (14) made of a WBG (Wide Band Gap) semiconductor single crystal and adjusted to a low concentration with nitrogen, which is a pentavalent element; and forming an n-type drift region (8, 18) having a target concentration by implanting a pentavalent element other than nitrogen into the epitaxial layer (14) by ion implantation.

[0357] [E9] The method for manufacturing a semiconductor device (1A to 1L) according to E8, wherein the ion implantation method is a channeling implantation method in which the pentavalent element is implanted along the crystal axis (c-axis) of the WBG semiconductor single crystal.

[0358] [E10] The method for manufacturing the semiconductor device (1A to 1L) according to E8 or E9, wherein the drift region (8, 18) is formed by implanting the pentavalent element other than phosphorus.

[0359] [E11] A method for manufacturing a semiconductor device (1A to 1L) according to any one of E8 to E10, wherein the drift region (8, 18) is formed by implanting at least one of the pentavalent elements arsenic and antimony.

[0360] [E12] A method for manufacturing a semiconductor device (1A-1L) according to any one of E8 to E11, further comprising, after the step of forming the drift region (8, 18), a step of forming p-type column regions (19, 20) that form a p-n junction with the drift region (8, 18) by implanting a trivalent element into the epitaxial layer (14) by ion implantation.

[0361] [E13] The method for manufacturing a semiconductor device (1A to 1L) according to E12, wherein the ion implantation method is a channeling implantation method in which the trivalent element is implanted along the crystal axis (c-axis) of the WBG semiconductor single crystal.

[0362] [E14] A method for manufacturing a semiconductor device (1A-1L), comprising the steps of: preparing an epitaxial layer (14) made of a WBG (Wide Band Gap) semiconductor single crystal and including an n-type drift region (8, 18); and forming p-type impurity regions (19, 20) that form a p-n junction with the drift region (8, 18) by implanting a trivalent element other than boron into the epitaxial layer (14) by ion implantation.

[0363] [E15] The method for manufacturing the semiconductor device (1A to 1L) according to E14, wherein the impurity regions (19, 20) that form a super junction structure with the drift regions (8, 18) are formed.

[0364] [E16] The method for manufacturing the semiconductor device (1A to 1L) according to E14 or E15, wherein a plurality of the impurity regions (19, 20) are formed.

[0365] [E17] A method for manufacturing a semiconductor device (1A to 1L) according to any one of E14 to E16, wherein the ion implantation method is a channeling implantation method in which the trivalent element is implanted along the crystal axis (c-axis) of the WBG semiconductor single crystal.

[0366] [E18] A method for manufacturing a semiconductor device (1A to 1L) according to any one of E14 to E17, wherein the impurity regions (19, 20) are formed by implanting at least one trivalent element selected from aluminum, gallium, and indium.

[0367] [E19] The method for producing a semiconductor device (1A to 1L) according to any one of E1 to E18, wherein the WBG semiconductor single crystal contains C (carbon).

[0368] [E20] The method for producing a semiconductor device (1A to 1L) according to any one of E1 to E19, wherein the WBG semiconductor single crystal is made of a SiC single crystal.

[0369] [E21] The method for manufacturing the semiconductor device (1A to 1L) according to E20, wherein the epitaxial layer (14) has an off angle (θ) of 10° or less with respect to the c-plane of the SiC single crystal.

[0370] [E22] The method for producing a semiconductor device (1A to 1L) according to E21, wherein the off angle (θ) has an off direction (D) along the a-axis direction of the SiC single crystal.

[0371] Although the embodiments have been described in detail, these are merely examples used to clarify the technical content, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0372] 1A SiC semiconductor device 1B SiC semiconductor device 1C SiC semiconductor device 1D SiC semiconductor device 1E SiC semiconductor device 1F SiC semiconductor device 1G SiC semiconductor device 1H SiC semiconductor device 1I SiC semiconductor device 1J SiC semiconductor device 1K SiC semiconductor device 1L SiC semiconductor device 2 SiC chips 3 First main surface 4 Second main surface 6 n-type base region 7 n-type buffer region 8 n-type drift region 8a 1st area 8b 2nd area 9 Functional Devices 14 Second SiC epitaxial layer 16 p-type base region 17 p-type buffer region 18 p-type drift region 18a 1st area 18b Second area 19 Column region (impurity region) 20 Column region (impurity region) 22 insulating film 23 First principal surface electrode 24 Second principal surface electrode 37 Trench gate structure (gate structure) 54 Gate main surface electrode (first main surface electrode) 57 Source main surface electrode (second main surface electrode) 60 Drain electrode (third principal surface electrode) 63 Trench gate structure (gate structure) 70 Gate main surface electrode (first main surface electrode) 73 Source main surface electrode (second main surface electrode) 75 Drain electrode (third principal surface electrode) 84 Planar gate structure (gate structure) C1 1st concentration C2 second concentration C3 3rd concentration CA basal concentration CB addition concentration D Off direction θ Off angle MID Middle part of the drift region

Claims

1. a SiC chip having a main surface; an n-type drift region formed in a surface layer portion of the main surface in a layer shape extending along the main surface, the n-type drift region including at least two types of pentavalent elements in the same layer, and having an impurity concentration adjusted by the two types of pentavalent elements.

2. A SiC chip having a main surface; an n-type drift region formed in a surface layer portion of the main surface and having an impurity concentration adjusted by at least two kinds of pentavalent elements; The drift region has a base concentration due to a first impurity that is a pentavalent element and an additional concentration due to a second impurity that is a pentavalent element other than the first impurity.

3. 3. The SiC semiconductor device according to claim 1, wherein the drift region has an impurity concentration adjusted to increase toward the main surface.

4. 4. The SiC semiconductor device according to claim 1, wherein the drift region has an impurity concentration adjusted by a pentavalent element other than phosphorus.

5. 5. The SiC semiconductor device according to claim 1, wherein the drift region contains nitrogen as a pentavalent element and a pentavalent element other than nitrogen.

6. 2. The SiC semiconductor device according to claim 1, wherein the drift region has a base concentration due to a first impurity that is a pentavalent element and an additional concentration due to a second impurity that is a pentavalent element other than the first impurity.

7. the first impurity is a pentavalent element other than phosphorus, The SiC semiconductor device according to claim 2 , wherein the second impurity is a pentavalent element other than phosphorus.

8. the first impurity is nitrogen; The SiC semiconductor device according to claim 7 , wherein the second impurity is at least one of arsenic and antimony.

9. 9. The SiC semiconductor device according to claim 2, wherein the additional concentration has a concentration distribution that increases toward the main surface.

10. 10. The SiC semiconductor device according to claim 2, wherein the base concentration has a substantially constant concentration distribution in the thickness direction.

11. The semiconductor device described in claim 1, wherein the drift region includes a first region formed in a layer extending along the main surface and containing one type of pentavalent element, and a second region formed in a layer extending along the main surface in a region between the main surface and the first region and containing the at least two types of pentavalent elements in the same layer.

12. a SiC chip having a main surface; a p-type drift region formed in a surface layer portion of the main surface and having an impurity concentration adjusted by a trivalent element other than boron; The drift region has an impurity concentration adjusted to increase toward the main surface.

13. The SiC semiconductor device according to claim 12 , wherein the drift region contains at least one trivalent element selected from the group consisting of aluminum, gallium, and indium.

14. A SiC semiconductor device as described in claim 12 or 13, wherein the drift region has a base concentration due to a first impurity which is a trivalent element, and an additional concentration due to a second impurity which is a trivalent element that is the same as or different from the first impurity.

15. A SiC chip having a main surface; a p-type drift region formed in a surface layer portion of the main surface and having an impurity concentration adjusted by a trivalent element other than boron; The drift region has a base concentration due to a first impurity that is a trivalent element and an additional concentration due to a second impurity that is the same as or different from the first impurity and that is a trivalent element.

16. the first impurity is aluminum; 16. The SiC semiconductor device according to claim 14, wherein the second impurity is at least one of aluminum, gallium, and indium.

17. The SiC semiconductor device according to any one of claims 14 to 16, wherein the additional concentration has a concentration distribution that increases toward the main surface.

18. The SiC semiconductor device according to any one of claims 14 to 17, wherein the base concentration has a substantially constant concentration distribution in the thickness direction.

19. The SiC semiconductor device according to any one of claims 1 to 18, wherein the drift region has a thickness belonging to any one of the ranges of 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, and 20 μm to 25 μm.

20. The SiC chip is made of a hexagonal SiC single crystal, The SiC semiconductor device according to any one of claims 1 to 19, wherein the main surface faces a c-plane of the SiC single crystal and has an off angle of 10° or less between the main surface and the c-plane.

21. The SiC semiconductor device according to claim 20 , wherein the off-angle has an off-direction along an a-axis direction of the SiC single crystal.

22. The SiC semiconductor device according to any one of claims 1 to 21, wherein the drift region is formed in a SiC epitaxial layer.

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