Semiconductor Devices

Abstract

To provide a semiconductor device with stable electric characteristics, or a semiconductor device with normally off electric characteristics.SOLUTION: A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor. The oxide semiconductor contains fluorine in a channel formation region, and the fluorine concentration in the channel formation region is 1×1020 atoms / cm3 or more and 1×1022 atoms / cm3 or less. Fluorine addition is performed by an ion injection method.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. The present invention also relates to a method for manufacturing a transistor and a semiconductor device, for example, a display device. device, light-emitting device, lighting device, power storage device, storage device, imaging device, processor, electronic device Or, the manufacture of display devices, liquid crystal display devices, light-emitting devices, storage devices, imaging devices, and electronic equipment. The present invention also relates to a display device, a liquid crystal display device, a light emitting device, a storage device, an imaging device, an electric device, a display device, a liquid crystal display device, a light emitting device, a storage device, an electric device, a display device, a light emitting device, a storage device, a light emitting ... This relates to a method for driving a child device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of devices, including display devices, light-emitting devices, lighting devices, storage devices, imaging devices, electro-optical devices, and semiconductor devices. Physical circuits and electronic devices may include semiconductor devices. [Background technology]

[0004] The technology of constructing transistors using semiconductors on substrates with insulating surfaces is attracting attention. Such transistors are widely used in semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor that can be used in transistors.

[0005] Silicon used as a semiconductor in transistors is classified into amorphous silicon and polycrystalline silicon depending on the application. For example, it is used in transistors that make up large display devices. In this case, it is preferable to use amorphous silicon, for which film formation technology on large-area substrates has been established. On the other hand, it is applied to transistors that constitute high-performance display devices that are integrated with driving circuits. In this case, if polycrystalline silicon is used, it is possible to fabricate transistors with high field effect mobility. Polycrystalline silicon is preferable because it can be obtained by heat treatment at high temperature or by laser light. A method for forming the film by processing is known.

[0006] In recent years, transistors using oxide semiconductors (typically In-Ga-Zn oxide) have become Development is intensifying.

[0007] Oxide semiconductors have a long history. In 1988, crystalline In-Ga-Zn oxide was first used in semiconductor devices. In 1995, the use of oxides was also disclosed (see Patent Document 1). A transistor using a semiconductor has been invented, and its electrical characteristics have been disclosed (Patent Document See reference 2. ).

[0008] The transistor using an oxide semiconductor includes a transistor using amorphous silicon and a transistor using a multi-layer silicon oxide. It has different characteristics from transistors using crystalline silicon. It is known that a display device using such a transistor has low power consumption. Conductors can be deposited using methods such as sputtering, making it possible to form transistors that make up large display devices. In addition, a transistor using an oxide semiconductor can be used as a high-voltage transistor. Because of its high effective mobility, it is possible to realize a highly functional display device in which a driving circuit is integrally formed. It is possible to use some of the production facilities for amorphous silicon transistors by improving them. This also has the advantage of reducing capital investment.

[0009] For example, in order to mass-produce semiconductor devices such as display devices, transistors using oxide semiconductors are required. The electrical characteristics of the capacitor must be stable.

[0010] In a transistor using an oxide semiconductor, it is very important to control oxygen vacancies in the oxide semiconductor. It is important to minimize oxygen vacancies in order to obtain stable transistor characteristics. It is preferable to do so, and one technique for this purpose is to inject oxygen into an oxide semiconductor (particularly See patent document 3. ). [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 63-239117 [Patent Document 2] Special Publication No. 11-505377 [Patent Document 3] Japanese Patent Application Laid-Open No. 2012-238880 Summary of the Invention [Problem to be solved by the invention]

[0012] An object of the present invention is to provide a transistor having stable electrical characteristics. An object of the present invention is to provide a transistor having marrow-off electrical characteristics. An object of the present invention is to provide a transistor with a small subthreshold swing value. Another object is to provide a transistor with a small short-channel effect. An object of the present invention is to provide a transistor with low leakage current when off. Another object is to provide a transistor with excellent electrical characteristics. Another object of the present invention is to provide a transistor having high frequency characteristics. One of the objectives is to provide a

[0013] Another object of the present invention is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. It is an object of the present invention to provide a device or an electronic device having the module. It is an object of the present invention to provide a novel semiconductor device. Another object of the present invention is to provide a novel electronic device.

[0014] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0015] As mentioned above, it is very important to control oxygen vacancies in oxide semiconductors. In order to obtain transistor characteristics, it is preferable to reduce oxygen vacancies as much as possible. In addition, the compensated oxygen vacancies may be repopulated by oxygen due to damage during the transistor manufacturing process. It is also important to form stable bonds to avoid defects.

[0016] Therefore, one embodiment of the present invention is to add fluorine to a channel formation region of a semiconductor. , compensates for oxygen vacancies in semiconductors and also fills the oxygen vacancies with fluorine, which forms stable bonds. By compensating, a transistor having stable and good electrical characteristics is provided.

[0017] One embodiment of the present invention is a gate electrode, a gate insulator, and an oxide semiconductor. The conductor is a semiconductor device having fluorine in a channel forming region.

[0018] In one embodiment of the present invention, the fluorine concentration in the channel formation region is 1×10 20 atom s / cm 3 More than 1×10 22 atoms / cm 3 The semiconductor device is as follows.

[0019] In one embodiment of the present invention, the oxide semiconductor is This is a semiconductor device in which the fluorine concentration in the region is low.

[0020] In one embodiment of the present invention, the oxide semiconductor contains indium, zinc, and an element M (the element M is aluminum). Semiconductor devices containing one or more selected from the group consisting of aluminum, gallium, yttrium and tin It is a location.

[0021] One embodiment of the present invention is a module including the semiconductor device described above and a printed board. do.

[0022] One embodiment of the present invention is a semiconductor device including the above-described semiconductor device or the above-described module and a speaker. , an operation key, or a battery.

[0023] One embodiment of the present invention is to form an oxide semiconductor over a substrate, and and a drain electrode, and fluorine is added to the oxide semiconductor. and a semiconductor device in which an insulator is formed on the drain electrode and a gate electrode is formed on the insulator. This is the manufacturing method.

[0024] Another embodiment of the present invention is a method for forming an oxide semiconductor over a substrate, adding fluorine to the oxide semiconductor, and a source electrode and a drain electrode in contact with the oxide semiconductor; A semiconductor device in which an insulator is formed on a drain electrode and a gate electrode, and a gate electrode is formed on the insulator. This is how to make the device.

[0025] Another embodiment of the present invention is a method for forming an oxide semiconductor over a substrate, and forming a source electrode in contact with the oxide semiconductor. and forming an insulating oxide semiconductor on the source electrode and the drain electrode. Fluorine is added to the oxide semiconductor through the insulator, and a gate electrode is formed on the insulator. The present invention relates to a method for manufacturing a semiconductor device.

[0026] Another embodiment of the present invention is a method for forming a gate electrode over a substrate, forming an insulator over the gate electrode, forming an oxide semiconductor on a gate electrode via an insulator, adding fluorine to the oxide semiconductor, A method for manufacturing a semiconductor device in which a source electrode and a drain electrode are formed in contact with an oxide semiconductor be.

[0027] Another embodiment of the present invention is a method for forming a gate electrode over a substrate, forming an insulator over the gate electrode, An oxide semiconductor is formed on the gate electrode via an insulator, and a source electrode is formed in contact with the oxide semiconductor. and a method for manufacturing a semiconductor device in which a drain electrode is formed and fluorine is added to an oxide semiconductor. be.

[0028] One embodiment of the present invention is a method for manufacturing a semiconductor device, in which the addition of fluorine is performed by an ion implantation method. It is the law.

[0029] In one embodiment of the present invention, the oxide semiconductor contains indium, zinc, and an element M (the element M is aluminum). Semiconductor devices containing one or more selected from the group consisting of aluminum, gallium, yttrium and tin This is how to make the device. [Effects of the Invention]

[0030] A transistor having stable electrical characteristics can be provided. Alternatively, a transistor having subthreshold electric characteristics can be provided. It is possible to provide a transistor with a small swing value. It is possible to provide a small transistor. Alternatively, it is possible to provide a transistor with a small leakage current when it is not conducting. It is possible to provide a transistor having excellent electrical characteristics. Alternatively, a highly reliable transistor can be provided. Therefore, it is possible to provide a transistor having excellent frequency characteristics.

[0031] Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module having the semiconductor device or the module may be provided. It is possible to provide an electronic device having a module. Or, a new module can be provided. Or, a new electronic Equipment can be provided.

[0032] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0033] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 2] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 3] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 5] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 7] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a band diagram according to one embodiment of the present invention. [Figure 10] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 11] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 12] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 13] Electron diffraction pattern of CAAC-OS. [Figure 14] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 15] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 21] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 22] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 23] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 24] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 25] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 31] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 32]FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 33] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 36] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 37] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 40] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 41] FIG. 10 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 42] FIG. 2 is a diagram for explaining the amount of fluorine added in the depth direction. [Figure 43] FIG. 10 is a graph showing the sheet resistance of samples. [Figure 44] Graph showing the ESR results of the sample. DETAILED DESCRIPTION OF THE INVENTION

[0034] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and details can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used in different The hatch pattern is used in common between drawings. However, there are cases where no particular symbol is attached.

[0035] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0036] In this specification and the like, the terms "film" and "layer" are interchangeable. It is possible to replace it.

[0037] Also, voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative and is expressed in terms of its magnitude relative to a reference potential. Therefore, even if it is described as "ground potential," For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." With respect to the potential, a positive potential and a negative potential are defined.

[0038] The ordinal numbers such as 1st and 2nd are used for convenience and do not represent the order of processes or stacking. Therefore, for example, "the first" should not be replaced with "the second" or "the third" In addition, ordinal numbers described in this specification and the like can be replaced with other numbers as appropriate. and the ordinal numbers used to identify an aspect of the present invention may not match.

[0039] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be written as "insulator." In addition, the boundary between "semiconductor" and "insulator" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "insulator." Similarly, the term "insulator" used herein can be interpreted as "semiconductor." " can sometimes be rephrased as ".

[0040] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "conductor." Similarly, the term "conductor" used in this specification can be used to refer to a "semiconductor." " can sometimes be rephrased as ".

[0041] The impurities in a semiconductor refer to, for example, substances other than the main components that make up the semiconductor. For example, the concentration Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and carrier mobility The semiconductor may become an oxide semiconductor, and the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1 and Group 2. These include elements, group 14 elements, group 15 elements, and transition metals other than the main component, in particular, for example, Hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, oxygen vacancies can be created by the inclusion of impurities such as hydrogen. In addition, when the semiconductor is silicon, there are cases where an impurity that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0042] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source voltage) in the region where the The distance between the source and drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is any one value, maximum value, The minimum or average value.

[0043] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0044] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the ratio of the channel formation region to be formed may be large. The effective channel width of the channel that is actually formed is larger than the apparent channel width shown by the The width will be larger.

[0045] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0046] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area where the source and drain face each other The channel width of the In this specification, it is sometimes referred to as "channel width." In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the embedded channel can be determined by taking a cross-sectional TEM image and analyzing the image. The value can be determined by

[0047] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0048] In this specification, when it is stated that A has a shape that protrudes more than B, it is not limited to a top view. In the cross-sectional view, at least one end of A is located outside at least one end of B. Therefore, it may be stated that A has a shape that protrudes more than B. For example, in the top view, one end of A is outside one end of B. It can be read as having.

[0049] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0050] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0051] In the specification, the term "semiconductor" can be read as "oxide semiconductor." Other semiconductors include group 14 semiconductors such as silicon and germanium, and silicon carbide. Zn, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, cadmium sulfide Compound semiconductors such as silicon and organic semiconductors can be used.

[0052] (Embodiment 1) In this embodiment, an example of a transistor according to one embodiment of the present invention will be described.

[0053] <Transistor 1> 1A and 1B illustrate transistors according to one embodiment of the present invention. 1(B) is a top view of the structure shown in FIG. 1(A) along the dashed line A1-A2 and the dashed line A3- The transistor 100 includes a substrate 400, a conductor 413, and a Insulator 402, semiconductor 406a, semiconductor 406b, semiconductor 406c, and conductor 416a , a conductor 416b, an insulator 412, and a conductor 404.

[0054] The semiconductor 406a, 406b, or 406c in the transistor 100 has fluorine. Fluorine may be contained in all three layers. Either one layer may have it, or either two layers may have it.

[0055] As shown in this embodiment, the semiconductor in the transistor is formed by a plurality of layers. In this case, it is preferable that the semiconductor having the channel formation region contains fluorine. For example, when the semiconductor 406b has a channel formation region, the semiconductor 406b may contain fluorine. It is preferable that:

[0056] The conductor 404 is a first gate electrode (front gate electrode) of the transistor 100. The conductor 413 also functions as a second The conductor 416 also functions as a gate electrode (also referred to as a back gate electrode). a and conductor 416b serve as the source and drain electrodes of transistor 100. The insulator 412 also functions as a gate insulator.

[0057] The transistor 100 according to this embodiment is a top gate transistor having a back gate. For example, a transistor without a back gate may be used. Alternatively, a bottom gate structure may be used. In this case, the conductor 413 is The conductor 404 functions as a gate, and the conductor 404 functions as a back gate. It may be configured without it.

[0058] A manufacturing method of the transistor 100 shown in FIG. 1 will be described with reference to FIGS.

[0059] 2(A), 3(A), 4(A), 5(A) and 6(A) show an embodiment of the present invention. 1A to 1C are top views illustrating a manufacturing method of the transistor 100. A1-A2 and dashed line A3-A4 are marked, and the corresponding cross-sectional view is shown in FIG. 2(B). 3(B), 4(B), 5(B) and 6(B).

[0060] First, a substrate 400 is prepared.

[0061] The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates. There are various substrates, such as zirconia substrates (yttria-stabilized zirconia substrates), and resin substrates. The substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of insulators inside the semiconductor substrate. A semiconductor substrate having a region, such as SOI (Silicon On Insulator) Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, or a substrate with a semiconductor or an insulator provided on a conductive substrate. Alternatively, a substrate having an element mounted on it may be used. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0062] A flexible substrate may be used as the substrate 400. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to a flexible substrate 400. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil made of woven fibers may be used. The substrate 400 may be stretchable. Also, the substrate 400 may be designed to retain its original shape when the bending or pulling is stopped. Alternatively, the substrate 4 may have a property of not returning to its original shape. The thickness of the film 00 is, for example, 5 μm or more and 1000 μm or less, preferably 10 μm or more and 700 μm or less. The thickness of the substrate 400 is preferably 15 μm or more and 500 μm or less. In addition, by thinning the substrate 400, it is possible to reduce the weight of the semiconductor device. Regardless of the material used, some materials may have elasticity and will retain their original shape when the bending or pulling is stopped. Therefore, if the semiconductor device on the substrate 400 is dropped, etc., In other words, a durable semiconductor device can be provided. Cut.

[0063] The substrate 400, which is a flexible substrate, may be made of, for example, metal, alloy, resin, glass, or The substrate 400, which is a flexible substrate, can be made of a material having a linear expansion coefficient of 1000 kJ / cm. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester, poly Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, making it suitable for flexible substrates. 400 is suitable.

[0064] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE) E: Molecular Beam Epitaxy (MBE) or Pulsed Laser Deposition (PL) D: Pulsed Laser Deposition) method, atomic layer deposition (ALD: At This can be done using a omic layer deposition method or the like.

[0065] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method, which uses light. Depending on the source gas, metal CVD (MCVD) and metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0066] The PECVD method can produce high-quality films at relatively low temperatures. Since no plasma is used, this is a film formation method that does not cause damage to the processed object due to plasma. The wiring, electrodes, elements (transistors, capacitors, etc.) included in the semiconductor device are It may charge up by receiving charge from Zuma. At this time, the accumulated charge This may destroy wiring, electrodes, elements, etc. included in the semiconductor device. In the case of the TCVD method, which does not use plasma, such plasma damage does not occur, so The TCVD method can increase the yield of semiconductor devices. Since no damage occurs, it is easy to obtain a film with few defects.

[0067] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Easy to obtain.

[0068] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases, this is preferable.

[0069] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having a composition. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by hand, the time required for film formation is shortened by the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0070] Next, a resist or the like is formed on the conductor, and the conductor 413 is formed by processing using the resist. When simply saying that a resist is formed, it is assumed that an anti-reflection layer is formed under the resist. This also includes cases where

[0071] The resist is removed after the object is processed by etching or other methods. In this case, plasma treatment and / or wet etching is used. Plasma ashing is suitable for this purpose. If the removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% to 1% by volume The remaining resist may be removed by using water or the like.

[0072] The conductor that becomes the conductor 413 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, Phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium Sm, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, Conductors containing one or more of tantalum and tungsten may be used in a single layer or a multilayer. For example, the conductive material may be an alloy or compound, and may be a conductor containing aluminum, copper, and titanium. Conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen may also be used.

[0073] Next, the insulator 402 is formed (see FIGS. 2A and 2B). The film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. It can be done.

[0074] The insulator 402 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 402 may be made of aluminum oxide, aluminum oxide, or aluminum alloy. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0075] The insulator 402 is an insulator having excess oxygen and / or hydrogen traps. preferable.

[0076] Insulators with excess oxygen are analyzed by thermal desorption spectroscopy (TDS) at temperatures above 100°C. 1×10 in the range of film surface temperature below 700℃ or between 100℃ and 500℃ 18 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 or more than 1×10 20 at oms / cm 3 It may release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0077] The method for measuring the amount of released oxygen using TDS analysis is described below.

[0078] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated based on the integral value of the ion intensity of the released gas. Then, by comparison with a standard sample, the total amount of gas released can be calculated.

[0079] For example, the TDS analysis results of a silicon substrate containing a predetermined density of hydrogen as a standard sample, and From the TDS analysis results of the measurement sample, the amount of released oxygen molecules (N O2 ) is expressed as Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the carbon atoms are derived from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but The possibility is low and is not considered here. The abundance ratio of oxygen atoms and oxygen molecules containing oxygen atoms with mass number 18 in nature is The rate is so small that it is not taken into consideration.

[0080] N O2 =N H2 / S H2 ×S O2 ×α

[0081] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. Measurements are made using a silicon substrate containing a fixed amount of hydrogen atoms.

[0082] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0083] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0084] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (ES) R: Electron Spin Resonance (G) shows a g value near 2.01. It may also have symmetrical signals.

[0085] The insulator 402 may also have a function of preventing diffusion of impurities from the substrate 400 or the like. stomach.

[0086] Next, a semiconductor film that will become the semiconductor 406a is formed. Sputtering, CVD, MBE, PLD, ALD, etc. can be done.

[0087] Next, by adding oxygen, the semiconductor that becomes the semiconductor 406a can be made to contain excess oxygen. The addition of oxygen is preferably performed by, for example, ion implantation at an acceleration voltage of 2 kV to 10 kV. The dose is 5×10 14 ions / cm 2 More than 1×10 17 ions / cm 2 below This can be done as follows.

[0088] Next, fluorine may be added to the semiconductor that will become the semiconductor 406a. The addition of oxygen to the semiconductor that will become semiconductor 406a and the addition of fluorine to the semiconductor that will become semiconductor 406b are sequentially performed. You may switch the order.

[0089] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0090] Next, a semiconductor film that will become the semiconductor 406b is formed. Sputtering, CVD, MBE, PLD, ALD, etc. The semiconductor film that becomes the semiconductor 406a and the semiconductor film that becomes the semiconductor 406b can be formed. By performing the film formation and the deposition in succession without exposing to the atmosphere, impurities are prevented from being mixed into the film and the interface. can be reduced.

[0091] Next, heat treatment is preferably performed. By the heat treatment, the semiconductor 406a is formed. The hydrogen concentration in the semiconductor that becomes the conductor and semiconductor 406b may be reduced. In addition, the oxygen vacancies in the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b are reduced. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably The heating may be carried out at a temperature of 450°C or higher and 600°C or lower, more preferably 520°C or higher and 570°C or lower. Heat treatment is carried out in an inert gas atmosphere or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or The heat treatment is carried out in an atmosphere containing 10% or more of fluorine. The heat treatment may be carried out under reduced pressure. After heat treatment in an inert gas atmosphere, an oxidizing gas was introduced for 10 minutes to compensate for the oxygen that was released. The heat treatment may be carried out in an atmosphere containing at least pm, at least 1%, or at least 10% of Zn. Therefore, the crystallinity of the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b can be improved. It can also remove impurities such as hydrogen and water.

[0092] Next, fluorine is added to the semiconductor that will become the semiconductor 406a and the semiconductor that will become the semiconductor 406b. It should be noted that the semiconductor that will become the semiconductor 406a and the semiconductor that will become the semiconductor 406b may be Heat treatment and fluorine doping to the semiconductor that will become semiconductor 406a and the semiconductor that will become semiconductor 406b The addition of and may be performed in reverse order.

[0093] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0094] Next, a resist or the like is formed on the semiconductor that will become the semiconductor 406b, and processing is performed using the resist. Then, the semiconductor 406b and the semiconductor 406a are formed (see FIGS. 3A and 3B). .).

[0095] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0096] Examples of the conductor include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, and aluminum. , titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium , zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and tantalum Conductors containing one or more types of tin may be used in a single layer or in a multilayer structure. The conductor may be a compound, and examples thereof include a conductor containing aluminum, a conductor containing copper and titanium, and a conductor containing copper and titanium. Conductors containing indium, tin and oxygen, conductors containing titanium and nitrogen Conductors containing elements may also be used.

[0097] Next, a resist or the like is formed on the conductor, and the conductor 416a and the conductor 416b are processed using the resist. and a conductor 416b is formed (see FIGS. 4A and 4B).

[0098] Next, fluorine may be added to the semiconductor 406a and the semiconductor 406b. This can be done by using the conductors 416a and 416b as masks. In the semiconductor 406a and the semiconductor 406b, the conductor 416a and the conductor 416b The non-overlapping regions can be selectively doped with fluorine.

[0099] Also, for example, by reducing the thickness of the conductors 416a and 416b, the semiconductor The conductor 406a and the semiconductor 406b overlap with the conductor 416a and the conductor 416b. Fluorine may also be added to the overlapping region. The semiconductor 406a has different fluorine concentrations in the area overlapping with the semiconductor 6b and the area not overlapping with the semiconductor 406a. For example, semiconductor 406a and semiconductor 406b can be formed. In FIG. 4B, the region overlapping with the conductor 416a and the conductor 416b is the conductor 416 The fluorine concentration is lower than that of the region that does not overlap with a and the conductor 416b.

[0100] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0101] Here, for example, the conductor 413 is a gate electrode, the insulator 402 is a gate insulator, and the conductor 416 is a gate insulating film. If a is the source electrode and the conductor 416b is the drain electrode, the process is completed up to FIG. The transistor may have a Tom gate structure.

[0102] Next, the semiconductor 436c is formed. The semiconductor 436c is formed by a method such as sputtering or CVD. The method can be performed using a method such as a method of deposition, an MBE method, a method of deposition using PLD, an ALD method, or the like. Before the formation of the semiconductor 406a, the semiconductor 406b, the conductor 416a, and the conductor 416b, For example, the surface may be etched using plasma containing a rare gas. After that, the semiconductor 436c can be formed without exposure to the atmosphere. As a result, the semiconductor 406a, the semiconductor 406b, the conductor 416a, and the conductor 416b are It is possible to reduce the amount of impurities entering the interface between the semiconductor 436c and the film. Impurities present in the film may be more easily diffused than impurities in the film. By reducing the amount of contaminants, it is possible to provide stable electrical characteristics to the transistor. do.

[0103] Next, fluorine may be added to the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c. It should be noted that the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c are all doped with fluorine. It is not necessary to add fluorine to any one layer, and fluorine may be added to any one or two layers.

[0104] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0105] Next, the insulator 442 is formed. The insulator 442 can be formed by a sputtering method, a CVD method, or the like. This can be done using MBE, PLD, ALD, or the like. The formation of the insulating film 442 and the formation of the insulating film 443 are performed successively without exposure to the atmosphere. Furthermore, the incorporation of impurities into the interface can be reduced.

[0106] The insulator 442 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 442 may be made of aluminum oxide, aluminum alloy, or aluminum alloys. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0107] Next, the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c are connected via the insulator 442. Fluorine may be added. It is not necessary to add fluorine to all of the layers c. Fluorine may also be added to the insulator 442.

[0108] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0109] Next, the conductor 434 is formed. The conductor 434 can be formed by a sputtering method, a CVD method, or the like. This can be done by using the MBE method, PLD method, ALD method, etc. The formation of the conductive material 434 and the formation of the conductive material 435 are carried out successively without exposure to the atmosphere. Furthermore, the incorporation of impurities into the interface can be reduced (see FIGS. 5(A) and 5(B)). ).

[0110] The conductor 434 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Sodium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sodium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and A conductor containing one or more of tungsten and silicon may be used in a single layer or a multilayer. Conductors that may be alloys or compounds include aluminum-containing conductors, copper- and titanium-containing conductors, and the like. conductors containing copper and manganese, conductors containing indium, tin and oxygen, conductors containing titanium and Conductors containing nitrogen may also be used.

[0111] Next, a resist or the like is formed on the conductor 434, and the resist is used to process the conductor 40. 4 is formed. In addition, the resist or the conductor 404 is used to process the insulator 442, In addition, the resist, the conductor 404, or the insulator 412 is used to form a semiconductor. The conductor 436c is processed to form the semiconductor 406c. The capacitor 404 and the capacitor 405 have the same shape when viewed from above, but the capacitor 404 and the capacitor 405 have the same shape when viewed from above. The resistor is not limited to this shape. For example, the semiconductor 406c and the insulator 412 may be The conductor 404 may be processed using a different resist. After that, a conductor that will become the conductor 404 may be formed, or an insulating layer may be formed after the conductor 404 is formed. A resist or the like may be separately formed on the insulator that will become the insulating body 412. 406c may be connected to an adjacent transistor or the like (see FIGS. 6(A) and 6(B)). See B). ).

[0112] Next, an insulating film may be formed. The insulating film may be formed by a sputtering method, a CVD method, an MBE method, or the like. The method can be carried out by using a PLD method, an ALD method, or the like.

[0113] Examples of insulators include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator is preferably aluminum oxide, silicon nitride oxide, Silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, acid Insulators containing neodymium oxide, hafnium oxide or tantalum oxide are used in single or multilayer configurations. Just use it.

[0114] The insulator preferably functions as a barrier layer. The insulator has a function of blocking hydrogen and / or hydrogen. It is preferable that the insulating material 412 has a higher ability to block oxygen and / or hydrogen than the insulating material 412. It's nice.

[0115] Through the above steps, the transistor 100 of one embodiment of the present invention can be manufactured.

[0116] As described above, by adding fluorine to the channel formation region of the semiconductor, The oxygen vacancies can be compensated for by fluorine, which forms stable bonds. To provide a transistor having stable and good electrical characteristics by compensating for the above. can be done.

[0117] As shown in FIG. 6B, the semiconductor 40 6b can be electrically surrounded (the electric field generated by the conductor can electrically The structure of the transistor that surrounds the channel is called the surrounded channel (s-cha). Therefore, the entire semiconductor 406b (top, bottom and side surfaces) In the s-channel structure, the source-drain A large current can be passed between the gates, and the current (on-state current) during conduction can be increased.

[0118] In addition, when the transistor has an s-channel structure, the side surface of the semiconductor 406b is also Therefore, the thicker the semiconductor 406b, the larger the channel formation region. That is, the thicker the semiconductor 406b, the higher the on-state current of the transistor. In addition, the thicker the semiconductor 406b, the greater the proportion of the region where carriers are highly controllable. Therefore, the subthreshold swing value can be reduced. For example, 10 nm or more Preferably 20 nm or more, more preferably 40 nm or more, and even more preferably 100 nm or more However, the productivity of the semiconductor device is low. Therefore, for example, it is set to 300 nm or less, preferably 200 nm or less, and more preferably Preferably, the semiconductor 406b has a region with a thickness of 150 nm or less.

[0119] Because of the high on-current that can be obtained, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, a semiconductor having the transistor can be The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. More preferably, the transistor has a region of 20 nm or less, and the channel width is preferably Preferably, the thickness is 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has.

[0120] Note that the conductor 413 is not necessarily formed (see FIG. 7A). The semiconductor 406c may protrude from the conductor 404 (see FIG. 7B). The insulator 442 and the semiconductor 436c do not necessarily need to be processed (see FIG. 7C). ) In addition, the width of the conductor 413 in the A1-A2 cross section is larger than that of the semiconductor 406b. (See FIG. 8A.) The conductor 413 and the conductor 404 may be connected to each other through an opening. The conductor 404 may be provided (see FIG. 8(B)). Also, the conductor 404 may not be provided (see FIG. 8(C)). )reference.).

[0121] <Semiconductors> As shown in this embodiment, the semiconductor 406a and the semiconductor 406b are disposed above and below the semiconductor 406b. By providing 6c, the electrical characteristics of the transistor can be improved in some cases.

[0122] The semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, if indium is included, the carrier mobility (electron mobility) increases. 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. , yttrium, or tin. Other elements that can be used for element M include ho, Uranium, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, Examples include tantalum, cerium, neodymium, hafnium, and tungsten. In some cases, the element M may be a combination of the above elements. For example, it is an element with a high bond energy with oxygen. Alternatively, the element M may be, for example, an element having an energy level higher than that of an oxide semiconductor. The semiconductor 406b preferably contains zinc. When an oxide semiconductor contains zinc, it may be more likely to crystallize.

[0123] However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. 6b is a zinc-free oxide, such as zinc tin oxide or gallium tin oxide. oxide semiconductors containing lead, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay.

[0124] The semiconductor 406b is made of, for example, an oxide with a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 The energy is preferably from 3 eV to 3.5 eV, more preferably from 3 eV to 3.5 eV.

[0125] For example, the semiconductor 406a and the semiconductor 406c contain oxygen other than the oxygen that constitutes the semiconductor 406b. The semiconductor 406b is an oxide semiconductor composed of one or more elements. The semiconductor 406a and the semiconductor 406 are formed from one or more elements other than oxygen. c is formed, the interface between the semiconductor 406a and the semiconductor 406b, and the semiconductor 406b Defect levels are unlikely to be formed at the interface between the semiconductor 406c and the silicon dioxide.

[0126] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c contain at least indium. When the semiconductor 406a is an In-M-Zn oxide, the sum of In and M is preferably When the atomic percentage is 100, it is preferable that In is less than 50 atomic percent and M is less than 50. atomic %, more preferably In is less than 25 atomic % and M is 75 atomic % When the semiconductor 406b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. %, and M is less than 75 atomic %, and more preferably In is 34 atomic % The semiconductor 406c is In-M-Zn. In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as the semiconductor 406a may be used. In addition, the semiconductor 406c may not necessarily contain indium. The semiconductor 406a and / or the semiconductor 406c may be gallium oxide. The number of atoms of each element contained in the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c is simply It does not have to be an integer ratio.

[0127] The semiconductor 406b is an oxide having a higher electron affinity than the semiconductors 406a and 406c. For example, the semiconductor 406b is made of a material selected from the semiconductors 406a and 406c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. Preferably, an oxide having a larger value than the above-mentioned value is used, and more preferably, an oxide having a larger value than the above-mentioned value by 0.15 eV or more and 0.4 eV or less. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0128] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor 406c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably Preferably, it is 90% or more.

[0129] In this way, a transistor in which semiconductors 406a and 406c are arranged above and below semiconductor 406b is formed. When a gate voltage is applied to the transistor, the semiconductor 406a, the semiconductor 406b, and the semiconductor A channel is formed in the semiconductor 406b having a large electron affinity in the body 406c.

[0130] Here, between the semiconductor 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the semiconductor 406c, The semiconductor 406b may have a mixed region of the semiconductor 406c. Therefore, the power density of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c is low. In the laminate, the energy changes continuously near each interface (also known as continuous junction). (See FIG. 9.) The semiconductor 406a, the semiconductor 406b, and In the semiconductor 406c, the interfaces between the semiconductors may not be clearly distinguishable.

[0131] At this time, the electrons are not in the semiconductor 406a and the semiconductor 406c but in the semiconductor 406b As described above, the electrons move mainly through the interface between the semiconductor 406a and the semiconductor 406b. The defect density at the interface between the semiconductor 406b and the semiconductor 406c is By lowering the concentration, the movement of electrons in the semiconductor 406b is less hindered, The on-state current of the transistor can be increased.

[0132] The on-current of a transistor can be increased by reducing the factors that hinder the movement of electrons. For example, if there are no factors that hinder the movement of electrons, it is assumed that electrons will move efficiently. The movement of electrons is also hindered, for example, when the physical unevenness of the channel formation region is large. will be done.

[0133] In order to increase the on-current of the transistor, for example, the upper or lower surface of the semiconductor 406b (The surface to be formed, in this case the semiconductor 406a) in a range of 1 μm × 1 μm, Root (RMS: Root Mean Square) roughness is less than 1 nm, preferably 0.6 nm or less, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm x 1 μm is less than 1 nm. Preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm The maximum height difference (PV) in the range of 1 μm x 1 μm should be less than 1 μm. ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably The RMS roughness, Ra and PV are measured by SII Nanotech. Measurements were performed using a scanning probe microscope system such as SPA-500 manufactured by Technology Co., Ltd. It is possible.

[0134] In addition, in order to increase the on-current of the transistor, the thickness of the semiconductor 406c is as small as possible. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the semiconductor 406c may be a semiconductor having a channel region. The semiconductor 406b is formed by the element other than oxygen (hydrogen, silicon, etc.) that constitutes the adjacent insulator. Therefore, the semiconductor 406c has a function of blocking some For example, the thickness is 0.3 nm or more, preferably 1 nm or more. More preferably, the semiconductor 406c has a region with a thickness of 2 nm or more. The semiconductor 406c is formed by: It is preferable that the material has oxygen blocking properties.

[0135] In order to increase reliability, the semiconductor 406a is thick and the semiconductor 406c is thin. For example, it is 10 nm or more, preferably 20 nm or more, and more preferably 40 nm or more. More preferably, the semiconductor 406a may have a region with a thickness of 60 nm or more. By increasing the thickness of the semiconductor 406a, the interface between the adjacent insulator and the semiconductor 406a However, the distance to the semiconductor 406b where the channel is formed can be increased. Since the productivity of the device may decrease, for example, it is recommended to set the thickness to 200 nm or less, preferably 120 nm or less. The semiconductor 406a may have a thickness of 80 nm or less, more preferably 80 nm or less. stomach.

[0136] For example, secondary ion mass spectroscopy (SIMS) is performed between the semiconductor 406b and the semiconductor 406a. Secondary Ion Mass Spectrometry (1×1) 0 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, preferably 1 x 1 0 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 More preferably, 1×10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 Silicon concentration below In addition, there is a region between the semiconductor 406b and the semiconductor 406c, which is 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, I prefer Or 1 x 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 Below, further Preferably 1 x 10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 below The silicon concentration is in the region of 0.1.

[0137] In addition, in order to reduce the hydrogen concentration in the semiconductor 406b, the semiconductor 406a and the semiconductor 406 It is preferable to reduce the hydrogen concentration of the semiconductor 406a and the semiconductor 406c. In 1×10 16 atoms / cm 3 Over 2×10 20 atoms / cm 3 below, Preferably 1 x 10 16 atoms / cm 3 5x10 or more 19 atoms / cm 3below, More preferably 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below or less, more preferably 1 × 10 16 atoms / cm 3 5x10 or more 18 atoms / c m 3 The semiconductor 406b has a region where the hydrogen concentration is as follows: Therefore, it is preferable to reduce the nitrogen concentration in the semiconductor 406a and the semiconductor 406c. 06a and semiconductor 406c are measured by SIMS at 1×10 15 atoms / cm 3 Below top 5×10 19 atoms / cm 3 Less than 1 × 10 15 atoms / cm 3 Below top 5×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 or less, more preferably 1 × 10 15 atoms / cm 3 5x10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0138] The three-layer structure described above is an example. For example, a two-layer structure without semiconductor 406a or semiconductor 406c Alternatively, the semiconductor 406a may be formed on or under the semiconductor 406c. The semiconductors 406a, 406b, and 406c are exemplified above and below the semiconductor 406. Alternatively, a four-layer structure may be formed by using one of the semiconductors 406a and 406b. , two or more locations below the semiconductor 406a, above the semiconductor 406c, and below the semiconductor 406c In addition, any of the semiconductors exemplified as semiconductor 406a, semiconductor 406b, and semiconductor 406c Alternatively, it may have an n-layer structure (n is an integer of 5 or more) having one or more of these.

[0139] <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0140] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include conductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors.

[0141] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0142] <caac-os> First, we will explain CAAC-OS. It is also called an oxide semiconductor with aligned nanocrystals. can.

[0143] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0144] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS. It can be said that the decrease in electron mobility caused by this is unlikely to occur.

[0145] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used to obtain a high-resolution TEM image. In particular, it is called a Cs-corrected high-resolution TEM image. This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Denshi Co., Ltd. This can be done.

[0146] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 10(A) is shown in Figure 10(B). From Figure 10(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0147] As shown in Figure 10(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 10(B) and Figure 10(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the pellets are It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The rheotomes can also be called nanocrystals (nc).

[0148] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 10(D)). The inclination between the pellets observed in FIG. 10(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 10(D).

[0149] In addition, Fig. 11(A) shows the Cs of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 11(A). Enlarged Cs-corrected high-resolution TEM images are shown in Fig. 11(B), Fig. 11(C), and Fig. 11(D), respectively. 11(D). From Fig. 11(B), Fig. 11(C) and Fig. 11(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0150] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 12(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0151] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0152] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 12(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in FIG. 12(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0153] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 13(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 13(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals that It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 13(B) is the (010) plane of the InGaZnO4 crystal. The second ring in Figure 13(B) is thought to be due to the (100) plane. This is thought to be due to the (110) plane.

[0154] CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can also be considered an oxide semiconductor with a low impurity concentration. It can also be said that the oxide semiconductor has few oxygen vacancies.

[0155] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in oxide semiconductors can become carrier traps or trap water. By capturing atoms, they can become a carrier generation source.

[0156] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0157] In addition, oxide semiconductors with low defect state density (few oxygen vacancies) can reduce carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. The C-OS transistor has electrical characteristics that make the threshold voltage negative (normal Also, it is rare for the acid to become pure or substantially pure. The oxide semiconductor has fewer carrier traps. The charge takes a long time to be released and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are On the other hand, transistors using CAAC-OS may have unstable electrical characteristics. The resulting transistor has little fluctuation in electrical characteristics and is highly reliable.

[0158] In addition, because the density of defect states in CAAC-OS is low, the capacitance generated by light irradiation can be reduced. Therefore, the CAAC-OS transistor is less likely to be captured by the defect level. The electrical characteristics of the transistors are less affected by irradiation with visible light or ultraviolet light.

[0159] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0160] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region in which no clear crystal part can be identified. The crystal part contained in the crystal is 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often present. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline nc-OS is called a high-resolution In some cases, the grain boundaries cannot be clearly seen in the TEM image. Therefore, in the following, we will refer to the pellets in nc-OS as the origin of the pellets. The crystalline part of S is sometimes called a pellet.

[0161] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD device that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peak is detected. Also, for nc-OS, the probe diameter (e.g., When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of, for example, 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size When nanobeam electron diffraction is performed on nc-OS, spots are observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy area.

[0162] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0163] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower defect state density than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. The defect level density is higher than that of AC-OS.

[0164] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0165] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0166] In amorphous oxide semiconductors, no crystalline parts can be observed in high-resolution TEM images.

[0167] When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and only a halo pattern is observed. It is measured.

[0168] There are various views on amorphous structures. For example, A structure that does not have a crystal structure is called a completely amorphous structure. In addition, although it does not have long-range order, the order of the atoms from the nearest neighbors to the atoms is called a "structure." A structure that has order within the range of atoms or the next nearest neighbor atoms is called an amorphous structure. Therefore, according to the strictest definition, oxides with even a slight degree of order in the atomic arrangement Amorphous oxide semiconductors cannot be called amorphous oxide semiconductors. Therefore, an oxide semiconductor having a crystalline portion cannot be called an amorphous oxide semiconductor. Therefore, for example, the CAAC-OS and the nc-OS can be used as an amorphous oxide semiconductor or It cannot be called a completely amorphous oxide semiconductor.

[0169] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0170] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portions can be identified.

[0171] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0172] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0173] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0174] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0175] Figure 14 shows an example of the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of eOS grows in size according to the cumulative amount of electron irradiation. As shown in Figure 14 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was sized at 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the crystals grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 14, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. You will realize something.

[0176] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0177] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0178] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0179] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0180] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide. The film may be a stacked film containing two or more of a semiconductor and a CAAC-OS.

[0181] (Embodiment 2) In this embodiment mode, a transistor having a shape partially different from that of the transistor shown in Embodiment 1 is used. The method for manufacturing the capacitor will be described below.

[0182] <Transistor 2> Figure 15(A), Figure 16(A), Figure 17(A), Figure 18(A), Figure 19(A), Figure 20(A) 21A and 21B are top views illustrating a method for manufacturing a transistor. The dashed dotted lines F1-F2 and F3-F4 are drawn, and the corresponding cross-sectional views are shown in FIG. 15(B), Fig. 16(B), Fig. 17(B), Fig. 18(B), Fig. 19(B), Fig. 20(B) and shown in FIG. 21(B).

[0183] First, prepare the substrate 500. For the substrate 500, refer to the description of the substrate 400.

[0184] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0185] Next, a resist or the like is formed on the conductor, and the conductor 513 is formed by processing using the resist. Complete.

[0186] Next, an insulator film is formed. The insulator film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0187] Next, an edge is formed from the upper surface of the insulator to the lower surface thereof so as to be parallel to the lower surface of the substrate 500. By performing the etching, the conductor 513 is exposed and the insulator 503 is formed (FIG. 15(A)). 15(B). By forming the insulator 503 in this manner, the conductor The height of the upper surface of 513 and the height of the upper surface of insulator 503 can be made to be approximately the same. Therefore, it is possible to suppress shape defects in subsequent processes.

[0188] Next, an insulator 502 is formed (see FIGS. 16(A) and 16(B)). The film formation of 2 is performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. For the insulator 502, refer to the description of the insulator 402.

[0189] Next, the semiconductor 536a is formed. The semiconductor 536a is formed by a method such as sputtering or CVD. The method can be performed using a method such as a method of deposition, an MBE method, a method of deposition using PLD, an ALD method, or the like. For details, refer to the description of the semiconductor that will become the semiconductor 406a.

[0190] Next, oxygen may be added to the semiconductor 536a so that the semiconductor 536a contains excess oxygen. The addition is performed by, for example, ion implantation at an acceleration voltage of 2 kV to 10 kV, and a dose of Amount 5 x 10 14 ions / cm 2 More than 1×10 17 ions / cm 2 If you do the following: good.

[0191] Next, fluorine may be added to the semiconductor 536a. The order of the addition of fluorine to the semiconductor 536a and the addition of fluorine to the semiconductor 536b may be reversed.

[0192] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0193] Next, the semiconductor 536b is formed. The semiconductor 536b can be formed by a sputtering method, a CVD method, or the like. The method can be performed using a method such as a method of deposition, an MBE method, a method of deposition using PLD, an ALD method, or the like. For details, please refer to the description of the semiconductor that will be the semiconductor 406b. The film and the semiconductor 536b are formed successively without exposure to the atmosphere. This can reduce the amount of impurities entering the interface.

[0194] Next, it is preferable to perform a heat treatment. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. Preferably, the temperature is 450°C or higher and 600°C or lower, more preferably 520°C or higher and 570°C or lower. Heat treatment should be carried out in an inert gas atmosphere or with an oxidizing gas concentration of 10 ppm or more, or 1% or more. The heat treatment is carried out in an atmosphere containing 10% or more of fluorine. The heat treatment may be carried out under reduced pressure. The treatment is carried out by heating in an inert gas atmosphere, followed by the addition of an oxidizing gas to replace the oxygen that has been removed. The heat treatment may be carried out in an atmosphere containing 0 ppm or more, 1% or more, or 10% or more. The crystallinity of the semiconductor 536a and the semiconductor 536b can be increased by the above-described process. It can remove any impurities.

[0195] Next, fluorine may be added to the semiconductor 536a and the semiconductor 536b. Heat treatment of the semiconductor 536a and the semiconductor 536b, and The order of the addition of fluorine and the addition of fluorine may be reversed.

[0196] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0197] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. The conductors can be formed by PLD, ALD, or the like. Please refer to the description of the conductor that will become conductor 416b.

[0198] Next, a resist or the like is formed on the conductor, and the conductor 516a and the conductor 516b are processed using the resist. and a conductor 516b is formed (see FIGS. 17A and 17B).

[0199] Next, fluorine may be added to the semiconductor 536a and the semiconductor 536b. This can be done by using the conductors 516a and 516b as a mask. In the semiconductor 536a and the semiconductor 536b, the conductor 516a and the conductor 516b The non-overlapping regions can be selectively doped with fluorine.

[0200] Also, for example, by reducing the thickness of the conductors 516a and 516b, the semiconductor The conductor 536a and the semiconductor 536b overlap with the conductor 516a and the conductor 516b. Fluorine may also be added to the overlapping region. 6b and a semiconductor 536a having different fluorine concentrations in the overlapping region and the non-overlapping region. For example, semiconductor 536a and semiconductor 536b can be formed. In the region of the conductor 516b, the region overlapping with the conductor 516a and the conductor 516b is the conductor 516 The fluorine concentration is lower than that of the region that does not overlap with a and the conductor 516b.

[0201] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0202] Next, a resist or the like is formed on the semiconductor 536b, and the resist, the conductor 516a, and the conductor The semiconductor 506b and the semiconductor 506a are formed by processing using the conductive material 516b (FIG. 18). See Figure 18(A) and Figure 18(B).

[0203] The conductor 516a, the conductor 516b, the semiconductor 506a, and the semiconductor 506b are formed by After the conductor is formed, the following method may be used.

[0204] First, a resist or the like is formed on the conductor, and then the resist is used to process the conductor 516 and the semiconductor. A conductor 506b and a semiconductor 506a are formed (see FIGS. 21(A) and 21(B)). At this time, the semiconductor 506b and the semiconductor 506a are formed by removing the resist and then 516 may be used for processing.

[0205] Next, a resist or the like is formed on the conductor 516, and the conductor 51 is processed using the resist. 6a and a conductor 516b are formed (see FIGS. 18(A) and 18(B)).

[0206] Next, the semiconductor 536c is formed. The semiconductor 536c can be formed by a sputtering method, a CVD method, or the like. The method can be performed using a method such as a method of deposition, an MBE method, a method of deposition using PLD, an ALD method, or the like. Please refer to the description of the semiconductor 436c.

[0207] Next, the insulator 542 is formed. The insulator 542 can be formed by a sputtering method, a CVD method, or the like. This can be done by using an MBE method, a PLD method, an ALD method, or the like. See the description of the edge 442.

[0208] Next, the semiconductor 506a, the semiconductor 506b, and the semiconductor 536c are connected via the insulator 542. Fluorine may be added. It is not necessary to add fluorine to all of the layers c. Fluorine may also be added to the insulator 542.

[0209] Fluorine is added, for example, by ion implantation at an acceleration voltage of 1 kV to 200 kV. Preferably, the voltage is 5 kV or more and 100 kV or less, and the dose is 5×10 19 ions / cm 3 Below top 5×10 22 ions / cm 3 Less than 1 × 10 20 ions / cm 3 1 x10 22 ions / cm 3 This can be done as follows.

[0210] Next, a conductor 534 is formed (see FIGS. 19(A) and 19(B)). The film formation of 4 is performed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductor 534 can be implemented by the same method as described above for the conductor 434.

[0211] Next, a resist or the like is formed on the conductor 534, and the resist is used to process the conductor 50. 4 is formed. In addition, the resist or the conductor 504 is used to process the insulator 542, In addition, the resist, the conductor 504, or the insulator 542 is used to form a semiconductor. The conductor 536c is processed to form a semiconductor 506c (see FIGS. 20(A) and 20(B)). Here, the semiconductor 506c, the insulator 512, and the conductor 504 are shown as a top view. Sometimes they are processed to have a similar shape, but they are not limited to this shape. For example, the insulator 512 and the conductor 504 may be processed using different resists. After forming the insulating layer 512, a conductive material that will become the conductive material 504 may be formed. After forming the insulating layer 4, a resist or the like may be separately formed on the insulating layer that will become the insulating layer 512. Also, for example, the semiconductor 506c may be connected to an adjacent transistor.

[0212] Next, an insulating film may be formed. The insulating film may be formed by a sputtering method, a CVD method, an MBE method, or the like. The method can be carried out by using a PLD method, an ALD method, or the like.

[0213] Examples of insulators include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator is preferably aluminum oxide, silicon nitride oxide, Silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, acid Insulators containing neodymium oxide, hafnium oxide or tantalum oxide are used in single or multilayer configurations. Just use it.

[0214] The insulator preferably functions as a barrier layer. and / or has a function of blocking hydrogen. Alternatively, the insulator may be, for example, insulator 502 Alternatively, it is preferable that the insulating layer 512 has a higher ability to block oxygen and / or hydrogen than the insulating layer 512. I wish.

[0215] Through the above steps, a transistor according to one embodiment of the present invention can be manufactured.

[0216] As described above, by adding fluorine to the channel formation region of the semiconductor, The oxygen vacancies can be compensated for by fluorine, which forms stable bonds. To provide a transistor having stable and good electrical characteristics by compensating for the above. can be done.

[0217] As shown in FIG. 20B, the transistor has an s-channel structure. The electric field from the conductor 504 and the conductor 513 flows through the conductor 51 on the side of the semiconductor 506b. This structure is unlikely to be obstructed by the conductive material 516a and the conductive material 516b.

[0218] Note that the conductor 513 does not necessarily have to be formed (see FIG. 22A). Alternatively, the semiconductor 506c may protrude from the conductor 504 (see FIG. 22B). ) The insulator 542 and the semiconductor 536c do not need to be processed (see FIG. 22C). In addition, even if the width of the conductor 513 in the F1-F2 cross section is larger than that of the semiconductor 506b, (See FIG. 23A.) In addition, the conductor 513 and the conductor 504 are connected through the opening. The conductor 504 may be provided (see FIG. 23B). See (C). ).

[0219] (Embodiment 3) In this embodiment, a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described. An example of this will be described.

[0220] <CMOSインバータ> The circuit diagram shown in FIG. 24(A) includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected, so-called CMO The figure shows the configuration of an S inverter. An n-channel transistor 2100 is made of an oxide semiconductor. It is preferable to use a transistor having a conductor, thereby forming a CMOS inverter. The power consumption in the circuit can be reduced.

[0221] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 24B is that of the transistor 2100 and the transistor 2200. The figure shows a configuration in which the source and drain of each transistor are connected. It can function as a so-called CMOS analog switch. The transistor 2100 is preferably a transistor including an oxide semiconductor.

[0222] <Semiconductor device structure 1> 25 is a cross-sectional view of the semiconductor device corresponding to FIG. 24(A). The transistor 2200 includes a transistor 2100. The transistor 2100 is disposed above the transistor 2200. 20 is used as an example, but a semiconductor according to one embodiment of the present invention may also be used. The body device is not limited to this. For example, the body device shown in FIG. 6, FIG. 7, FIG. 8, FIG. 22 or FIG. The transistor shown in FIG. 23 may be used as the transistor 2100. Therefore, for the transistor 2100, the above-described transistor description will be used as appropriate. I will take your opinion into consideration.

[0223] A transistor 2200 shown in FIG. 25 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472 a in the semiconductor substrate 450 and a region 472 b in the semiconductor substrate 450. It has a region 472b, an insulator 462, and a conductor 454.

[0224] In transistor 2200, regions 472a and 472b are source and The insulator 462 functions as a drain region. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by applying a potential to the body 454. That is, the potential applied to the conductor 454 causes a conduction line between the region 472a and the region 472b. The non-conduction can be controlled.

[0225] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium, or or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A compound semiconductor substrate made of gallium oxide or the like may be used. A single crystal silicon substrate is used as the substrate 450 .

[0226] The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart n-type conductivity. The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart p-type conductivity. In this case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, even if the semiconductor substrate 450 is an i-type, It's okay.

[0227] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The ON characteristics of the transistor 2200 can be improved.

[0228] Regions 472a and 472b are regions containing impurities that impart p-type conductivity. In this way, transistor 2200 constitutes a p-channel transistor.

[0229] Note that transistor 2200 is separated from adjacent transistors by regions 460 and the like. The region 460 is an insulating region.

[0230] The semiconductor device shown in FIG. 25 includes an insulator 464, an insulator 466, an insulator 468, and a conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and insulator It has an edge 490, an insulator 492, and an insulator 494.

[0231] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the insulator 464. 64. Insulator 468 is disposed on insulator 466. Insulator 468 is disposed on insulator 466. 90 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 490. Also, an insulator 492 is disposed on the transistor 2100. Also, an insulator 4 94 is disposed on the insulator 492 .

[0232] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings have openings that reach the conductor 454. The openings also have conductors 480a, 480b, and 480c, respectively. The conductive material 480b or the conductive material 480c is embedded therein.

[0233] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a portion that is in contact with the conductor 480c, and an opening that reaches the conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0234] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0235] The insulator 490 has an opening that overlaps with the channel formation region of the transistor 2100 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. are.

[0236] The conductor 474a may function as the gate electrode of the transistor 2100. Alternatively, for example, applying a constant potential to the conductor 474a can turn on the transistor 210. The electrical properties, such as the threshold voltage of 0, may be controlled. a and the conductor 404 that functions as the gate electrode of the transistor 2100 are electrically connected to each other. By doing so, the on-current of the transistor 2100 can be increased. In addition, since the punch-through phenomenon can be suppressed, the transistor 210 This makes it possible to stabilize the electrical characteristics in the saturated region of 0.

[0237] The insulator 492 is connected to one of the source and drain electrodes of the transistor 2100. An opening through one conductor 516b to conductor 474b and transistor 2100 An opening reaching the conductor 516a, which is the other of the source electrode or drain electrode of the transistor, An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c are provided. The openings are provided with a conductor 496a and a conductor 496b. , the conductor 496c or the conductor 496d is embedded in each opening. may further be via any of the components such as transistor 2100.

[0238] The insulator 494 also has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b and the conductor The opening reaches the conductor 496d, and the opening reaches the conductor 496c. The conductive material 498a, the conductive material 498b, and the conductive material 498c are embedded in the respective conductive materials. do.

[0239] Insulator 464, insulator 466, insulator 468, insulator 490, insulator 492 and insulator Examples of 494 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. For example, the insulator 401 may be aluminum oxide, magnesium oxide, or the like. Nesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gas oxide Sodium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Neodymium, hafnium oxide or tantalum oxide may be used.

[0240] Insulator 464, insulator 466, insulator 468, insulator 490, insulator 492 or insulator At least one of the components 494 has an insulator that blocks impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 2100. By disposing an insulator having a locking function, the electrical characteristics of the transistor 2100 are improved. It can stabilize gender.

[0241] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in single or multilayer configurations.

[0242] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, Conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, Conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, The conductors 498a, 498b, and 498c may include, for example, boron, nitrogen, and the like. , oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt , nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium A conductor containing one or more of aluminum, silver, indium, tin, tantalum and tungsten is formed in a single layer. For example, it may be an alloy or a compound, and aluminum may be used. Conductors containing copper and titanium, Conductors containing copper and manganese, Indium Alternatively, a conductor containing tin and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

[0243] The semiconductor device shown in FIG. 26 is the same as the transistor 2200 of the semiconductor device shown in FIG. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The transistor 2200 is a Fin type. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 2200. In addition, the contribution of the electric field of the gate electrode can be increased, The off characteristics of the transistor 2200 can be improved.

[0244] 27 is a circuit diagram of the semiconductor device shown in FIG. 25. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 27 shows a case where the semiconductor device 200 is provided on a semiconductor substrate 450 which is an SOI substrate. 1 shows a structure in which region 456 is separated from semiconductor substrate 450 by insulator 452. By using an SOI substrate as the conductor substrate 450, punch-through phenomena and the like can be suppressed. Therefore, the off-state characteristics of the transistor 2200 can be improved. The insulator 452 may be formed by insulating a portion of the semiconductor substrate 450. For example, the insulator 452 can be silicon oxide.

[0245] The semiconductor device shown in FIGS. 25 to 27 includes a p-channel transistor formed on a semiconductor substrate. The area occupied by the element is reduced by fabricating an n-channel transistor above it. That is, the degree of integration of the semiconductor device can be increased. A p-channel transistor and a p-channel transistor were fabricated using the same semiconductor substrate. Compared to the conventional method, the process can be simplified, thereby increasing the productivity of semiconductor devices. In addition, the yield of the semiconductor device can be increased. The transistor is placed in the LDD (Lightly Doped Drain) region, shallow trench In some cases, complex processes such as choke structure and distortion design can be omitted. Compared to manufacturing transistors using semiconductor substrates, productivity and yield can be improved. It may be possible to reduce the

[0246] <Storage device 1> A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0247] The semiconductor device shown in FIG. 28A includes a transistor 3200 using a first semiconductor and a second The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0248] The transistor 3300 preferably has a low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 00. The small off-state current of the capacitor 3300 allows for long-term recording at a specific node of the semiconductor device. It is possible to retain the memory contents, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in low power consumption semiconductors. It becomes a body device.

[0249] In FIG. 28A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0250] The semiconductor device shown in FIG. 28A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. do.

[0251] Writing and holding of data will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the capacitor The voltage is applied to a node FG electrically connected to one of the electrodes of the capacitor 3400. A predetermined charge is applied to the gate of the register 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. The transistor 3300 is set to a potential at which it is in a non-conductive state, thereby making the transistor 3300 in a non-conductive state. As a result, the charge is held at the node FG (retention).

[0252] Since the off-state current of the transistor 3300 is small, the charge of the node FG is retained for a long time. It will be held.

[0253] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the second wiring 3002 takes a potential according to the amount of charge held in the node FG. If 3200 is an n-channel type, a high level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 Apparent threshold voltage V when low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it "conductive." The potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in a write operation, the charge applied to node FG can be determined. When a high level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." Meanwhile, the node FG When a low level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. You can put it out.

[0254] When memory cells are arranged in an array, the information of the desired memory cell is read. In order to prevent the information of other memory cells from being read, A potential at which transistor 3200 is in a "non-conducting state" regardless of the charge applied to FG. , that is, V th_H A lower potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 is in a "conducting state" regardless of the charge applied to the FG. , that is, V th_L A higher potential may be applied to the fifth wiring 3005 .

[0255] <Storage device 2> The semiconductor device shown in FIG. 28B differs from the semiconductor device shown in FIG. 28A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information.

[0256] The reading of data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0257] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), , the potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C×V 1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (= It can be seen that it is higher than (CB×VB0+C×V0) / (CB+C)).

[0258] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0259] In this case, the transistor to which the first semiconductor is applied is used in a drive circuit for driving the memory cell. A transistor to which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the drive circuit.

[0260] The semiconductor device described above uses a transistor including an oxide semiconductor and having low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the data for a long period of time. It is possible to maintain the volume.

[0261] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, injection of electrons into the floating gate Since electrons are not introduced or extracted from the floating gate, there is no risk of insulator degradation. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as a conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which has led to a dramatic improvement in reliability. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0262] <Semiconductor device structure 2> 29 is a cross-sectional view of the semiconductor device corresponding to FIG. 28(A). has a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are arranged above the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100 described above. The transistor 3200 may be the transistor shown in FIG. Please refer to the description of transistor 2200. Note that in FIG. The case where the transistor 3200 is an n-channel transistor has been described. It may also be a transistor of the NAND type.

[0263] A transistor 3200 shown in FIG. 29 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 472 a in the semiconductor substrate 450 and a region 472 b in the semiconductor substrate 450. It has a region 472b, an insulator 462, and a conductor 454.

[0264] The semiconductor device shown in FIG. 29 includes an insulator 464, an insulator 466, an insulator 468, and a conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 496 c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, and conductor It includes an insulator 498d, an insulator 490, an insulator 492, and an insulator 494.

[0265] The insulator 464 is disposed on the transistor 3200. The insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 468 is disposed on insulator 466. 90 is disposed on the insulator 468. Also, the transistor 3300 is disposed on the insulator 490. Also, an insulator 492 is disposed on the transistor 3300. Also, an insulator 4 94 is disposed on the insulator 492 .

[0266] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings have openings that reach the conductor 454. The openings also have conductors 480a, 480b, and 480c, respectively. The conductive material 480b or the conductive material 480c is embedded therein.

[0267] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a portion that is in contact with the conductor 480c, and an opening that reaches the conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0268] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0269] The insulator 490 has an opening overlapping the channel formation region of the transistor 3300 and a conductive The opening reaches the conductor 476a and the opening reaches the conductor 476b. The mouths are embedded with conductors 474a, 474b, and 474c, respectively. are.

[0270] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, applying a constant potential to the conductor 474a can turn on the transistor It is also possible to control electrical properties such as the threshold voltage of 3300. 474a and the conductor 404 which is the top gate electrode of the transistor 3300 are electrically connected. This can increase the on-state current of the transistor 3300. In addition, punch-through phenomenon can be suppressed, so the transistor 3300 This makes it possible to stabilize the electrical characteristics in the saturated region.

[0271] The insulator 492 is connected to one of the source and drain electrodes of the transistor 3300. An opening through one conductor 516b to conductor 474b and transistor 3300 The other of the source electrode and the drain electrode is overlapped with the conductor 516a via the insulator 511. conductor 514, which is the gate electrode of transistor 3300; 04 and the other of the source electrode or drain electrode of the transistor 3300. An opening extending through one conductor 516a to the conductor 474c. The portions are respectively provided with a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496 However, each opening is filled with transistors 3300 and the like. This may be via any of the components.

[0272] The insulator 494 also has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b. 496c, an opening that reaches conductor 496d, and an opening that reaches conductor 496e. The openings are provided with a conductor 498a, a conductor 498b, a conductor 498c, or a conductor Electrical body 498d is embedded.

[0273] Insulator 464, insulator 466, insulator 468, insulator 490, insulator 492 or insulator At least one of the components 494 has an insulator that blocks impurities such as hydrogen and oxygen. It is preferable to add impurities such as hydrogen and oxygen to the vicinity of the transistor 3300. By disposing an insulator having a locking function, the electrical characteristics of the transistor 3300 are It can stabilize gender.

[0274] The conductor 498d may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, Thorium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more of tungsten and cerium may be used in a single layer or a multilayer. , alloys or compounds, and conductors containing aluminum, conductors containing copper and titanium Conductors containing copper and manganese, conductors containing indium, tin and oxygen, titanium and conductors containing nitrogen may also be used.

[0275] The source or drain of transistor 3200 is connected to conductor 480b, conductor 478b, and , the conductor 476a, the conductor 474b, and the conductor 496c. The conductor 516b is electrically connected to one of the source and drain electrodes of the MOSFET 00. The conductor 454, which is the gate electrode of the transistor 3200, is connected to the conductor 480c. Conductor 478c, conductor 476b, conductor 474c, and conductor 496d. The conductor 516a, which is the other of the source electrode or drain electrode of the transistor 3300, is electrically connected to the Connect to the target.

[0276] The capacitor 3400 is connected to the other of the source electrode and the drain electrode of the transistor 3300. The electrode is electrically connected to the conductor 514, and the insulator 511. 1 is made through the same process as the insulator 512 that functions as the gate insulator of the transistor 3300. Since the conductive material 51 can be formed by the above-mentioned method, productivity can be improved, which is preferable in some cases. 4, the same process as that for the conductor 504 which functions as the gate electrode of the transistor 3300 is performed. The use of a layer formed through this process may be preferable in some cases, since it can increase productivity.

[0277] For other structures, please refer to the descriptions in Figure 25 etc. as appropriate.

[0278] The semiconductor device shown in FIG. 30 is the same as the transistor 3200 of the semiconductor device shown in FIG. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The figure shows the case where the transistor 200 is a fin type. For details, refer to the description of the transistor 2200 shown in FIG. 26. The case where the transistor 2200 is a p-channel transistor has been described. The transistor 3200 may be an n-channel transistor.

[0279] 31 is a circuit diagram of the semiconductor device shown in FIG. 29. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 200 is provided on a semiconductor substrate 450, which is an SOI substrate. The transistor 3200 provided on the semiconductor substrate 450 is shown in FIG. Please refer to the description of the transistor 2200. Note that in FIG. 27, the transistor 2200 is p The case where the transistor 3200 is an n-channel transistor has been described. It may also be a transistor of the NAND type.

[0280] <Imaging device> An imaging device according to one aspect of the present invention will be described below.

[0281] 32A is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) are arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 are each The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0282] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0283] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the same substrate as the pixel portion 210. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280, and peripheral circuit 290. One or more of these may be omitted.

[0284] As shown in FIG. 32B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the images captured.

[0285] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each sub-pixel The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0286] FIG. 33(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in 33(A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") receives light in the green (G) wavelength band. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") is provided with a color filter that transmits light. A sub-pixel 212 is provided with a color filter that transmits light in the wavelength bands of blue (B) and blue (C). (hereinafter also referred to as "sub-pixel 212B"). It can be made to function.

[0287] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, in the nth line (n is an integer between 1 and p), The wiring 248 and the wiring 249 connected to the pixel 211 of and wiring 249[n]. For example, in the m-th column (m is an integer between 1 and q), The wiring 253 connected to the pixel 211 is referred to as wiring 253[m]. ), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the m-th column is connected to the wiring 2 53[m]R, the wiring 253 connected to the sub-pixel 212G is the wiring 253[m]G, and the sub-pixel The wiring 253 connected to the subpixel 212B is indicated as wiring 253[m]B. , and are electrically connected to the peripheral circuits via the wiring.

[0288] In addition, the imaging device 200 detects color filters of adjacent pixels 211 that transmit light in the same wavelength band. The sub-pixels 212 provided with the filters are electrically connected to each other via switches. FIG. 33B shows a pixel 211 arranged in n rows and m columns, and a sub-pixel 212 of the pixel 211. 11 shows an example of connection of a sub-pixel 212 included in a pixel 211 arranged in the n+1th row and mth column adjacent to the pixel 211 shown in FIG. In FIG. 33(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the n+1th row and mth column are The sub-pixels 212R arranged in n rows and m columns are connected via the switches 201. The subpixel 212G arranged in the n+1th row and the mth column is connected to the switch 202. The sub-pixels 212B arranged in the nth row and the mth column are connected via the The sub-pixel 212B arranged at the center is connected via the switch 203.

[0289] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 211 may have sub-pixels for detecting light of three different wavelength bands. By providing 212, a full color image can be obtained.

[0290] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Pixel 211 may be used with pixel 212. Alternatively, cyan (C), yellow (Y), In addition to the sub-pixel 212 provided with a color filter that transmits light of blue (Y) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. One pixel 211 may have sub-pixels 2 that detect light in four different wavelength bands. By providing the lens 12, the color reproducibility of the acquired image can be further improved.

[0291] Also, for example, in FIG. 33A, the sub-pixel 212 for detecting the red wavelength band, the sub-pixel 213 for detecting the green wavelength band, The ratio of the number of sub-pixels 212 detecting the blue wavelength band to the number of sub-pixels 212 detecting the blue wavelength band ( For example, the pixel ratio (or light receiving area ratio) does not have to be 1:1:1. ) may be a Bayer array with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0292] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that there are two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0293] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0294] In addition, an ND (Neutral Density) filter (neutral density filter) is used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows for a wider dynamic range of the device.

[0295] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 34(A), a lens 255 and a filter 25 formed in the pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0296] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is reflected by the wiring 257. Therefore, as shown in Figure 34(B), A lens 255 and a filter 254 are arranged on the conversion element 220 side, and the photoelectric conversion element 220 It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. can be done.

[0297] As the photoelectric conversion element 220 shown in FIG. 34, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0298] The photoelectric conversion element 220 is made of a material that has the function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be a ceramic. Lead, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0299] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0300] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2. The pixel 212 may have a first filter.

[0301] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of configuring a pixel using the above will be described.

[0302] 35(A) and 35(B) are cross-sectional views of elements constituting the imaging device. The imaging device shown in FIG. 1 includes a silicon transistor 35 provided on a silicon substrate 300. 1. Transistor 35 using an oxide semiconductor stacked over transistor 351 2 and transistor 353, and a photodiode provided on the silicon substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 370. and is electrically connected to the wiring 371. 61 has an electrical connection with plug 370 through low resistance region 363 .

[0303] The imaging device also includes a transistor 351 and a photodiode 352 provided on the silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and a layer 320, which are provided in contact with the layer 320 and have a transistor 352 and a transistor 353. and a layer 330 provided in contact with the layer 330 and having wiring 372 and wiring 373. It has 40.

[0304] In the example of the cross-sectional view of FIG. 35(A), the transistor 35 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the surface opposite to the surface on which the photodiode 1 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light receiving surface of 360 may be the same as the surface on which the transistor 351 is formed.

[0305] In addition, when a pixel is configured using only transistors using an oxide semiconductor, the layer 31 Alternatively, the layer 310 may be omitted. Alternatively, a pixel may be formed using only a transistor including an oxide semiconductor.

[0306] If a pixel is constructed using only silicon transistors, layer 330 can be omitted. An example of a cross-sectional view in which the layer 330 is omitted is shown in FIG.

[0307] The silicon substrate 300 may be an SOI substrate. Instead, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide The substrate has aluminum gallium, indium phosphide, gallium nitride, or an organic semiconductor. You can also be there.

[0308] Here, a layer 310 having a transistor 351 and a photodiode 360, An insulator 380 is provided between the layer 330 having the resistor 352 and the transistor 353. However, the position of the insulator 380 is not limited.

[0309] The hydrogen in the insulator provided near the channel forming region of the transistor 351 is converted into silicon dioxide. This has the effect of terminating the ring bonds and improving the reliability of the transistor 351. , hydrogen in an insulator provided near the transistor 352 and the transistor 353, etc. This is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 52 and the transistor 353. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the capacitors are stacked, an insulator 380 having a function of blocking hydrogen is provided between them. By confining hydrogen below the insulator 380, the transistor The reliability of the insulator 351 can be improved. Since hydrogen diffusion to the layer above 380 can be suppressed, the transistor 352 and the transistor The reliability of the transistor 353 can be improved.

[0310] As the insulator 380, for example, an insulator having a function of blocking oxygen or hydrogen is used. There are.

[0311] In the cross-sectional view of FIG. 35(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0312] As shown in FIG. 36(A1) and FIG. 36(B1), a part or the whole of the imaging device may be 36(A1) shows the state where the imaging device is bent in the direction of the dashed line X1-X2 in the figure. 36(A2) shows the state where the bent portion is located along the dashed line X1-X in FIG. 36(A3) is a cross-sectional view of the portion indicated by the dashed line Y1-2 in FIG. This is a cross-sectional view of the portion indicated by Y2.

[0313] FIG. 36(B1) shows the case where the imaging device is bent in the direction of the dashed line X3-X4 in the same figure, and 36(B2) shows the state where the lens is bent in the direction of the dashed line Y3-Y4 in the figure. 36(B1) is a cross-sectional view of the portion indicated by the dashed line X3-X4 in FIG. 36(B1) is a cross-sectional view of a portion indicated by a dashed line Y3-Y4 in FIG.

[0314] By curving the imaging device, it is possible to reduce field curvature and astigmatism. This makes it easier to design the optical system, such as lenses, that are used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, which contributes to the miniaturization of electronic devices that use imaging devices. It is possible to achieve a lighter weight and improve the quality of the captured image. .

[0315] <cpu> The following describes a CPU including semiconductor devices such as the above-mentioned transistors and the above-mentioned memory devices. and explain.

[0316] FIG. 37 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0317] The CPU shown in FIG. 37 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in Figure 37 is merely an example of a simplified configuration. There are various configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 37 A configuration including the above is considered as one core, and multiple cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is For example, it can be 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0318] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0319] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0320] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0321] In the CPU shown in FIG. 37, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0322] In the CPU shown in FIG. 37, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in the register 1196. That is, the register 1196 In the memory cell of the Select whether to hold data by flip-flop. If the power supply voltage is set to 0, the power supply voltage is supplied to the memory cells in the register 1196. If data retention in the capacitor is selected, the data is rewritten to the capacitor. This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped.

[0323] FIG. 38 is a circuit diagram of an example storage element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 that prevents stored data from volatilizing when turned off, a switch 1203, and a switch 1204. , a logic element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. 10. The memory element 1200 may include a diode, a resistor, It may further include other elements such as an inductor.

[0324] Here, the above-described memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential that turns off the transistor 1209 is continuously input. For example, the gate of the transistor 1209 is configured to be grounded via a load such as a resistor. .

[0325] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conducting or non-conducting state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD input to the first terminal determines whether or not the first terminal is electrically connected to the second terminal. The conducting or non-conducting state of transistor 1214 is selected.

[0326] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0327] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0328] A control signal WE is input to the gate of the transistor 1209. The switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. The conduction or non-conduction state between the first and second terminals of one switch is selected. When the terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. This becomes:

[0329] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 38, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0330] In FIG. 38, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0331] In addition, in FIG. 38, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed by a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon film or The transistor may have a channel formed in a silicon substrate. All transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements in addition to the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor.

[0332] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0333] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0334] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of transistors whose channels are formed in silicon. By using this transistor as the transistor 1209, the memory element 120 The signal held in the capacitor 1208 is maintained for a long period of time even when power supply voltage is not supplied to the capacitor 1208. In this way, the storage element 1200 maintains its stored contents (data) even when the supply of power supply voltage is stopped. ) can be held.

[0335] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0336] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The signal can be converted into a conducting state or a non-conducting state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0337] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0338] Although the storage element 1200 has been described as being used in a CPU, the storage element 1200 can also be used in a DSP ( Digital Signal Processor), custom LSI, PLD (Pr LSIs such as programmable logic devices, RF (Radio Frequency It can also be applied to high-speed (high-speed) devices.

[0339] <Display device> A display device according to one embodiment of the present invention will be described below with reference to FIGS. 39 and 40. do.

[0340] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, and the like. The light-emitting element can be a light-emitting display element. Therefore, the category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) These include organic EL displays, etc. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section explains the display device.

[0341] The display device described below is a panel in which a display element is sealed, and a connector for the panel. This includes modules in which ICs including controllers are mounted.

[0342] The display device shown below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC, modules with TCP attached, and printers at the end of TCP The IC (integrated circuit) is directly mounted on the module or display element with a main board using the COG method. All mounted modules are also included in the display device.

[0343] 39A and 39B show an example of an EL display device according to one embodiment of the present invention. FIG. 39(B) is a top view showing the entire EL display device. FIG. 39(C) is a cross section of MN corresponding to a part of the dashed line MN in FIG. 39(B). .

[0344] FIG. 39(A) is an example of a circuit diagram of a pixel used in an EL display device.

[0345] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of elements such as capacitors and resistors, the connection destination must be specified. However, a person skilled in the art may be able to compose an aspect of the invention. Even if the destination is not specified, one aspect of the invention can be said to be clear. When the content is described in this specification, etc., one aspect of the invention that does not specify the connection destination is In particular, if the terminal is connected to multiple If multiple locations are expected, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations of only some of the terminals possessed by devices such as It may be possible to configure a different embodiment.

[0346] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, specifying the connection destination can be considered an aspect of an invention. and can constitute one aspect of the invention. Even if the connection destination of a certain circuit is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an aspect of the invention.

[0347] The EL display device shown in FIG. 39(A) includes a switch element 743, a transistor 741, and a capacitor. The light emitting element 719 includes a capacitor 742 and a light emitting element 719 .

[0348] Note that FIG. 39(A) is an example of a circuit configuration, and therefore, if a transistor is added, Conversely, at each node in FIG. 39(A), it is possible to It is also possible to avoid adding passive elements.

[0349] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitor element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. and electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to the signal line 7 The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0350] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. The switching element 743 is a transistor manufactured through the same process as the transistor 741. The use of transistor 74 can improve the productivity of the EL display device. 1 and / or the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0351] 39(B) is a top view of the EL display device. The EL display device is made up of a substrate 700 and a substrate 7 50, a sealing material 734, a driving circuit 735, a driving circuit 736, a pixel 737, and an FP The sealing material 734 covers the pixel 737, the driving circuit 735, and the driving circuit The driving circuit 735 is disposed between the substrate 700 and the substrate 750 so as to surround the driving circuit 736. Alternatively, the driving circuit 736 may be disposed outside the sealing material 734 .

[0352] FIG. 39(C) is a cross-sectional view of the EL display device corresponding to a part of the dashed line MN in FIG. 39(B). is.

[0353] In FIG. 39C, a conductor 704a and a conductor Insulator 712a on body 704a, insulator 712b on insulator 712a, and insulator 712 semiconductor 706a and semiconductor 706b that are on top of conductor 704b and overlap with conductor 704a; Conductors 716a and 716b in contact with semiconductor 706a and semiconductor 706b, respectively. 6b, an insulator 718a on the conductor 716a and the conductor 716b, and an insulator 718a an insulator 718b on the insulator 718b; an insulator 718c on the insulator 718c; The transistor 706b has a structure including a conductor 714a overlapping with the semiconductor 706b. The structure of 41 is an example, and it may be a structure different from that shown in FIG. 39(C).

[0354] Therefore, in the transistor 741 shown in FIG. 39C, the conductor 704a is The insulators 712a and 712b function as gate insulators. The conductor 716a functions as a source electrode, and the conductor 716b functions as a drain electrode. The insulators 718a, 718b, and 718c function as gate electrodes. The conductor 714a functions as a gate insulator, and the conductor 714b functions as a gate electrode. The electrical characteristics of the semiconductors 706a and 706b may change when exposed to light. Therefore, the conductor 704a, the conductor 716a, the conductor 716b, and the conductor 714a It is preferable that at least one of them has a light-blocking property.

[0355] The interface between the insulator 718a and the insulator 718b is shown by a dashed line. For example, the insulators 718a and 718b may be Therefore, when the same type of insulator is used, it may be difficult to distinguish between the two depending on the observation method.

[0356] In FIG. 39C, a conductor 704b on a substrate and a conductor 704b an insulator 712a on the insulator 712a, an insulator 712b on the insulator 712a, and a A conductor 716a overlapping the conductor 704b, an insulator 718a on the conductor 716a, and an insulating Insulator 718b on insulator 718a, insulator 718c on insulator 718b, and insulator 718 and a conductor 714b that is on the conductor 714c and overlaps the conductor 716a. In the overlapping region of the insulator 714b, a part of the insulator 718a and the insulator 718b is removed. The structure shown is:

[0357] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. The conductor 716a functions as the other electrode.

[0358] Therefore, the capacitor 742 can be formed using the same film as that of the transistor 741. It is also preferable that the conductors 704a and 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b can be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. .

[0359] A capacitor 742 shown in FIG. 39C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 39(C) has high display quality. The capacitor element 742 shown in FIG. 1 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulators 718a and 718b have a structure in which parts of the insulators 718a and 718b are removed. The capacitive element according to one embodiment is not limited to this. A structure in which a part of the insulator 718c is removed to thin the overlapping area of ​​the conductor 714b is used. It's okay to have it.

[0360] An insulator 720 is provided over the transistor 741 and the capacitor 742. The insulator 720 extends to the conductor 716a, which serves as the source electrode of the transistor 741. The insulator 720 may have an opening. A conductor 781 is disposed on the insulator 720. 1 may be electrically connected to the transistor 741 through an opening in the insulator 720.

[0361] A partition 784 having an opening that reaches the conductor 781 is disposed over the conductor 781. A light-emitting layer 782 is disposed on the wall 784 and is in contact with the conductor 781 at the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the conductor 783 becomes the light-emitting element 719 .

[0362] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. do.

[0363] 40(A) is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. A transistor 751, a capacitor 752, and an element in which liquid crystal is filled between a pair of electrodes (liquid crystal) It has a crystal element 753.

[0364] In the transistor 751, one of the source and the drain is electrically connected to a signal line 755. The gate is electrically connected to a scan line 754 .

[0365] In the capacitor 752, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0366] In the liquid crystal element 753, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. a common potential applied to a wiring to which the other electrode of the capacitor 752 is electrically connected; The common potential applied to the other electrode of the liquid crystal element 753 may be different from the common potential applied to the other electrode of the liquid crystal element 753 .

[0367] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dotted-chain line MN is shown in FIG. In this case, the FPC 732 is connected to the wiring 733a via the terminal 731. 3a is a conductor or semiconductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0368] For the transistor 751, refer to the description of the transistor 741. For 752, refer to the description of the capacitor 742. Note that in FIG. Although the structure of the capacitor 752 corresponding to the capacitor 742 in (C) is shown, the present invention is not limited to this. stomach.

[0369] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be Therefore, the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. By doing so, power for the operation of the transistor 751 is not required, and a liquid crystal display with low power consumption is obtained. In addition, the area occupied by the capacitor 752 can be reduced; It is possible to provide a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device.

[0370] An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening that reaches the transistor 751. On the insulator 721, a conductive The conductor 791 is disposed on the transistor through the opening of the insulator 721. 751 and electrically connected.

[0371] An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is disposed on the liquid crystal layer 793. An insulator 794, which functions as an alignment film, is disposed on the liquid crystal layer 793. 94 is disposed on the insulator 794. A spacer 795 is disposed on the insulator 794. A conductor 796 is disposed on the insulator 794. The substrate 79 7 is placed.

[0372] By having the above-described structure, it is possible to provide a display device having a capacitor element with a small occupation area. Alternatively, a display device with high display quality can be provided. It is possible to provide a display device.

[0373] For example, in this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device may include, for example, For example, a light-emitting diode (LED) such as white, red, green, or blue ting Diode), transistor (transistor that emits light according to the current), electron Output element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV) , plasma displays (PDP), MEMS (microelectromechanical systems) display elements using a digital micromirror device (DMD), a digital micromirror device (DMS), Micro Shutter), IMOD (Interference Modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electro Wetting elements, piezoelectric ceramic displays, and displays using carbon nanotubes In addition to these, there are also other types of devices that can be used for electrical or magnetic functions. The display medium may have a variable contrast, brightness, reflectance, transmittance, etc.

[0374] An example of a display device using an EL element is an EL display. An example of a display device using this is a field emission display (FED) or is a SED (Surface-conduction E) flat panel display. LCD displays include liquid crystal displays. An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). LCD, reflective LCD, direct view LCD, projection LCD) An example of a display device using electronic ink or electrophoretic elements is an electronic pen. In addition, there are also other LCDs that can be used to realize semi-transmissive LCDs and reflective LCDs. In this case, a part or all of the pixel electrodes should function as a reflective electrode. For example, a part or all of the pixel electrodes may be made of aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM can be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0375] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form a nitride layer on the graphene or graphite. Semiconductors, such as n-type GaN semiconductors having crystals, can be easily formed into films. Furthermore, a p-type GaN semiconductor with crystals can be placed on top of it to form an LED. It is possible to form a crystalline n-type GaN semiconductor with graphene or graphite. An AlN layer may be provided. The GaN semiconductor in the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED can be It is also possible to form the film by a tartering method.

[0376] <Electronic equipment> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0377] FIG. 41A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908 The portable game machine shown in FIG. 41A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0378] FIG. 41(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 9 13, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 and a display having a function as a position input device added to at least one of the first display unit 914 and the second display unit 915. The function as a position input device can be achieved by touching the display device. Alternatively, the function as a position input device can be added by providing a touch panel. It can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It is possible.

[0379] FIG. 41C shows a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard, and a keyboard. The computer has a keyboard 923, a pointing device 924, and the like.

[0380] FIG. 41(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 93. He holds the third prize.

[0381] FIG. 41(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0382] FIG. 41(F) shows an automobile, which includes a body 951, wheels 952, a dashboard 953, and lights. It has 954 etc.

[0383] As described above, one embodiment of the present invention has been described in this embodiment. One embodiment is not limited to the above. For example, a semiconductor such as semiconductor 406b may contain fluorine. However, the present invention is not limited to this example. The semiconductor may contain elements other than fluorine. Alternatively, in some cases, the semiconductor 406 Semiconductors such as b may not contain fluorine. [Example]

[0384] In this example, fluorine was added to an oxide semiconductor film, and the fluorine concentration in the oxide semiconductor film was investigated. The results will be explained below.

[0385] The sample was prepared by forming a 100 nm thick silicon oxide layer on a silicon substrate by thermal oxidation. Then, an oxide semiconductor film was formed by In-Ga-Zn-O (atomic ratio In:Ga:Zn=1:1) 1) IGZO film was deposited to a thickness of 100 nm by sputtering using a target. It was formed and produced.

[0386] The prepared sample was implanted with 1.0×10 15 ions / cm 2 and 1 .0×10 16 ions / cm 2 fluorine ions ( 19 F + ) was added. The accelerating voltage was set to 20 kV. The amount of fluorine added in the depth direction at this time was measured by SIMS. The results of this investigation are shown in Figure 42.

[0387] From the results shown in Figure 42, fluorine was added at 1.0 × 10 15 ions / cm 2 When added, IG 3.0 × 10 on ZO membrane 20 atoms / cm 3 It was also found that fluorine was included in the 1.0×10 16 ions / cm 2 When added, the IGZO film 21 a toms / cm 3 It was found that it contains some [Example]

[0388] In this example, fluorine was added to an oxide semiconductor film, and the sheet resistance of the oxide semiconductor film was investigated. The results will be explained below.

[0389] The sample was an oxide semiconductor film of In-Ga-Zn-O (atomic ratio In:G) on a quartz substrate. IGZO film was deposited by sputtering using a target (a:Zn=1:1:1). It was fabricated with a thickness of 1000 nm.

[0390] The prepared sample was implanted with 1.0×10 14 ions / cm 2 , 1.0 x10 15 ions / cm 2 and 1.0 × 10 16 ions / cm 2 Fluorine at a dose of elementary ions ( 19 F + The accelerating voltage was set to 20 kV. The results of measuring the sheet resistance of the prepared sample are shown in Figure 43. The upper limit of measurement is 1 x 10 6 It is Ω / □.

[0391] The results shown in Figure 43 show that the more fluorine is added to the IGZO film, the higher the sheet resistance. It was also confirmed that fluorine was 1.0 × 10 16 ions / cm 2 When added, IG The sheet resistance of the ZO film is 1×10 6 The value was over Ω / □. By adding fluorine to the film, the carrier concentration of the IGZO film decreases, making it closer to an i-type semiconductor. I found out that... [Example]

[0392] In this example, fluorine is added to the oxide semiconductor film, and defects in the oxide semiconductor film are detected by ESR. The results of the survey will be explained below.

[0393] The sample was an oxide semiconductor film of In-Ga-Zn-O (atomic ratio In:G) on a quartz substrate. IGZO film was deposited by sputtering using a target (a:Zn=1:1:1). It was fabricated with a thickness of 1000 nm.

[0394] The prepared sample was implanted with 1.0×10 14 ions / cm 2 , 1.0 x10 15 ions / cm 2 or 1.0 × 10 16 ions / cm 2 Fluorine at a dose of elementary ions ( 19 F + The accelerating voltage was set to 20 kV. The results of ESR measurements of the prepared samples are shown in FIG.

[0395] The ESR spectrum is shown in Figure 44(A). From the results shown in Figure 44(A), it is clear that the IGZO film It was found that the signal at a g value of around 1.93 became smaller as more fluorine was added. In addition, Figure 44(B) compares the spin densities of signals observed around a g value of 1.93. As shown in Figure 44(B), the g value of 1.93 increases with the amount of fluorine added to the IGZO film. It was found that the spin density of the signal observed in the vicinity was reduced.

[0396] In the IGZO film, the signal seen at a g value of around 1.93 is due to oxygen vacancies. Therefore, by adding fluorine to the IGZO film, oxygen vacancies in the IGZO film can be reduced. It was found that it is possible to reduce [Explanation of symbols]

[0397] 100 transistors 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 transistors 353 Transistor 360 photodiode 361 Anode 363 Low resistance region 370 Plug 371 Wiring 372 Wiring 373 Wiring 380 Insulator 400 boards 401 Insulator 402 Insulator 404 Conductors 406a Semiconductors 406b Semiconductors 406c Semiconductors 412 Insulator 413 Conductors 416a Conductor 416b Conductor 434 Conductors 436c Semiconductors 442 Insulator 450 Semiconductor Substrate 452 Insulator 454 Conductors 456 areas 460 areas 462 Insulator 464 Insulator 466 Insulator 468 Insulator 472a area 472b area 474a Conductor 474b Conductor 474c Conductor 476a Conductors 476b Conductor 478a Conductor 478b Conductor 478c Conductor 480a Conductor 480b Conductor 480c conductor 490 Insulator 492 Insulators 494 Insulators 496a Conductors 496b Conductor 496c Conductor 496d Conductor 498a Conductors 498b Conductor 498c Conductor 498d Conductor 500 boards 502 Insulator 503 Insulator 504 Conductors 506a Semiconductors 506b Semiconductors 506c Semiconductor 511 Insulator 512 Insulator 513 Conductors 514 Conductors 516 Conductors 516a Conductor 516b Conductor 534 Conductors 536a Semiconductors 536b Semiconductors 536c Semiconductors 542 Insulator 700 boards 704a Conductor 704b Conductor 706a Semiconductors 706b Semiconductors 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c Insulator 719 Light-emitting element 720 Insulator 721 Insulator 731 terminal 732 FPC 733a wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitor 743 Switching Elements 744 signal line 750 board 751 Transistor 752 Capacitor 753 Liquid crystal elements 754 scan lines 755 signal line 781 Conductors 782 luminescent layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid Crystal Layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2100 transistors 2200 transistors 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 5100 pellets 5120 board 5161 area< / cpu>

Claims

1. a first transistor having a first channel formation region including silicon; a second transistor including a second channel formation region having an oxide semiconductor, a first gate electrode located below the second channel formation region, and a second gate electrode located above the second channel formation region, a first insulating layer having a region located above the first channel formation region; a first conductive layer having a region located above the first insulating layer and functioning as the first gate electrode; an oxide semiconductor layer having a region located above the first conductive layer and having the second channel formation region; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as the second gate electrode; the second conductive layer is electrically connected to one of a source region and a drain region of the first transistor; the second conductive layer has a region overlapping one of a source region and a drain region of the first transistor and a region overlapping the first conductive layer; the third conductive layer is electrically connected to a gate electrode of the first transistor; The third conductive layer has a region overlapping with the second conductive layer.

2. a first transistor having a first channel formation region including silicon; a second transistor including a second channel formation region having an oxide semiconductor, a first gate electrode located below the second channel formation region, and a second gate electrode located above the second channel formation region, a first insulating layer having a region located above the first channel formation region; a first conductive layer having a region located above the first insulating layer and functioning as the first gate electrode; an oxide semiconductor layer having a region located above the first conductive layer and having the second channel formation region; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer and functioning as the second gate electrode; the second conductive layer is electrically connected to one of a source region and a drain region of the first transistor; the second conductive layer has a region overlapping with one of a source region and a drain region of the first transistor, a region overlapping with the first channel formation region, and a region overlapping with the first conductive layer; the third conductive layer is electrically connected to a gate electrode of the first transistor; The third conductive layer has a region overlapping with the second conductive layer.

Images