Photoelectric conversion device and driving method thereof

Abstract

To provide a technique to achieve multifunctionality and an improvement in image quality in a photoelectric conversion device including a column parallel AD converter.SOLUTION: A photoelectric conversion device has: a plurality of pixels that are arranged to form a plurality of columns; a plurality of comparator circuits that are provided in correspondence with the plurality of columns, and each have a first input node receiving input of pixel signals output from the pixels in the corresponding column and a second input node receiving input of a reference signal; a plurality of buffer circuits that are provided between a reference signal line supplied with the reference signal and respective second input nodes of the plurality of comparator circuits; and a first switch circuit that sets the state of connection between output nodes of the plurality of buffer circuits.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a driving method thereof. [Background technology]

[0002] Imaging devices equipped with column-parallel AD converters, each of which has an analog-to-digital (AD) conversion unit for each pixel column, are known. A typical column-parallel AD converter converts a pixel signal into digital data by using a comparator circuit to compare the pixel signal with a reference signal whose level changes over time and counting the time from the start of the comparison until the output signal of the comparator circuit is inverted. Patent Document 1 describes an imaging device configured to shorten the settling time of the reference signal by connecting a buffer circuit between the reference signal line and the comparator circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 076127 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the applications of photoelectric conversion devices, such as imaging devices, have expanded, creating a demand for photoelectric conversion devices with a variety of functions suited to each application. Furthermore, in imaging devices equipped with column-parallel AD converters, it is important to suppress changes in the amount of fluctuation in power supply voltage caused by differences in the number of comparator circuits whose output signal levels are inverted at the same time. However, in Patent Document 1, no particular consideration was given to fluctuations in power supply voltage in a configuration having a buffer circuit between a reference signal line and a comparator circuit.

[0005] An object of the present invention is to provide a technique for realizing multi-functionality and improved image quality in a photoelectric conversion device equipped with a column-parallel AD converter. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a pixel switching device includes a plurality of pixels arranged in a plurality of columns, a plurality of comparison circuits provided corresponding to each of the plurality of columns, each having a first input node to which a pixel signal output from a pixel of the corresponding column is input, and a second input node to which a reference signal is input, a plurality of buffer circuits provided between a reference signal line to which the reference signal is supplied and each of the second input nodes of the plurality of comparison circuits, and a first switch circuit that sets a connection state between each of the output nodes of the plurality of buffer circuits. a plurality of output lines provided corresponding to each of the plurality of columns, through which the pixel signals are output from the pixels of the corresponding columns; and a second switch circuit configured to set a connection state between the plurality of output lines; With the plurality of buffer circuits include a first set including some of the plurality of buffer circuits and a second set including other some of the plurality of buffer circuits, and the second switch circuit includes a first circuit that sets a connection state between the output lines of a column in which the buffer circuits of the first set are arranged, and a second circuit that sets a connection state between the output lines of a column in which the buffer circuits of the second set are arranged, independently of the first circuit. A photoelectric conversion device is provided.

[0007] According to another disclosure of the present specification, there is provided a photoelectric conversion device comprising: a plurality of pixels arranged in a plurality of columns; a plurality of comparison circuits provided corresponding to each of the plurality of columns, each having a first input node to which a pixel signal output from a pixel of the corresponding column is input via a first capacitor and a second input node to which a reference signal is input via a second capacitor; a plurality of buffer circuits provided between a reference signal line to which the reference signal is supplied and each of the second input nodes of the plurality of comparison circuits; a switch circuit configured to be able to switch a connection state between the output nodes of the plurality of buffer circuits; and a control circuit for controlling the switch circuit, wherein the comparison circuit is capable of performing an offset clamp operation to set an offset based on voltages input to the first input node and the second input node, and the control circuit is configured to connect the output nodes of the plurality of buffer circuits together during at least a part of a period during which the offset clamp operation is being performed.

[0009] Furthermore, according to yet another disclosure of the present specification, there is provided a method for driving a photoelectric conversion device having a plurality of pixels arranged in a plurality of columns, a plurality of comparison circuits each having a first input node provided corresponding to each of the plurality of columns and receiving a pixel signal output from the pixel of the corresponding column, a second input node provided corresponding to a reference signal, and a reset switch configured to reset a threshold voltage to a voltage corresponding to a potential difference between the first input node and the second input node, a plurality of buffer circuits provided between a reference signal line to which the reference signal is supplied and each of the second input nodes of the plurality of comparison circuits, and a switch circuit configured to be able to switch a connection state between the output nodes of each of the plurality of buffer circuits, the method comprising: turning on the switch circuit to connect the output nodes of each of the plurality of buffer circuits; and turning on the switch circuit for at least a part of a period during which the reset switch is turned on. [Effects of the Invention]

[0010] According to the present invention, it is possible to realize multi-functionality and improved image quality in a photoelectric conversion device equipped with a column-parallel AD converter. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Figure 2] 1 is a circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to a first embodiment of the present invention. [Figure 3] 2 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 4] 2 is a circuit diagram showing an example of the configuration of a buffer circuit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 5] 1 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Figure 6] FIG. 3 is a timing chart (part 1) showing a method for driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 7] FIG. 2 is a timing chart (part 2) showing the method of driving the photoelectric conversion device according to the first embodiment of the present invention. [Figure 8] FIG. 10 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 9] FIG. 10 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a third embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 12] FIG. 10 is a timing chart (part 1) showing a method for driving a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a sixth embodiment of the present invention. [Figure 14] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a seventh embodiment of the present invention. [Figure 15] FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving body according to an eighth embodiment of the present invention. [Figure 16] FIG. 13 is a block diagram showing a schematic configuration of a device according to a ninth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIG. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment. FIG. 2 is a circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. FIG. 3 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment. FIG. 4 is a circuit diagram showing an example of the configuration of a buffer circuit in the photoelectric conversion device according to this embodiment. FIG. 5 is a schematic diagram showing an example of the configuration of the photoelectric conversion device according to this embodiment. FIGS. 6 and 7 are timing charts showing a method of driving the photoelectric conversion device according to this embodiment.

[0013] First, the structure of the photoelectric conversion device according to this embodiment will be described with reference to FIGS. 1, a photoelectric conversion device 100 according to this embodiment includes a pixel array unit 10, a vertical scanning circuit 20, readout circuits 30A and 30B, reference signal generation circuits 38A and 38B, and counter circuits 48A and 48B. The photoelectric conversion device 100 also includes horizontal scanning circuits 60A and 60B, output circuits 70A and 70B, and a control circuit 80.

[0014] The pixel array unit 10 has a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit made up of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel array unit 10 is not particularly limited. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel array unit 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like.

[0015] Control lines 14 are arranged in each row of the pixel array section 10, extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 aligned in the first direction, and serves as a signal line common to these pixels 12. The first direction in which the control lines 14 extend is sometimes referred to as the row direction or horizontal direction. The control lines 14 are connected to a vertical scanning circuit 20.

[0016] In each column of the pixel array section 10, a vertical output line 16A or a vertical output line 16B is arranged, extending in a second direction (the vertical direction in FIG. 1 ) intersecting the first direction. The vertical output lines 16A and 16B are arranged alternately in each column. For example, the vertical output lines 16A are arranged in odd-numbered columns, and the vertical output lines 16B are arranged in even-numbered columns. Each of the vertical output lines 16A and 16B is connected to the pixels 12 aligned in the second direction and serves as a common signal line for these pixels 12. The second direction in which the vertical output lines 16A and 16B extend is sometimes referred to as the column direction or vertical direction. The vertical output line 16A is connected to a readout circuit 30A. The vertical output line 16B is connected to a readout circuit 30B.

[0017] The vertical scanning circuit 20 is a control circuit that receives control signals output from the control circuit 80, generates control signals for driving the pixels 12, and supplies the control signals to the pixels 12 via the control lines 14. The vertical scanning circuit 20 may include logic circuits such as a shift register and an address decoder. The vertical scanning circuit 20 sequentially supplies control signals to the control lines 14 of each row, thereby sequentially driving the pixels 12 in the pixel array section 10 row by row. The signals read out from the pixels 12 row by row are input to the readout circuit 30A or readout circuit 30B via the vertical output line 16A or vertical output line 16B provided for each column of the pixel array section 10.

[0018] The readout circuit 30A has a plurality of column circuits 32, the number of which corresponds to the number of columns on which the vertical output lines 16A are arranged. The column circuits 32 of the readout circuit 30A are connected to the vertical output lines 16A of the corresponding columns. The readout circuit 30B has a plurality of column circuits 32, the number of which corresponds to the number of columns on which the vertical output lines 16B are arranged. The column circuits 32 of the readout circuit 30B are connected to the vertical output lines 16B of the corresponding columns. The column circuits 32 are processing circuits that perform predetermined processing, such as amplification and analog-to-digital conversion (AD conversion), on pixel signals read out from the pixels 12 of the corresponding columns. The column circuits 32 have a signal holding circuit (memory) for holding the processed pixel signals.

[0019] The reference signal generation circuit 38A is connected to the readout circuit 30A. The reference signal generation circuit 38A has a function of receiving a control signal output from the control circuit 80, generating a reference signal to be used for AD conversion, and supplying it to the readout circuit 30A. Similarly, the reference signal generation circuit 38B is connected to the readout circuit 30B. The reference signal generation circuit 38B has a function of receiving a control signal output from the control circuit 80, generating a reference signal to be used for AD conversion, and supplying it to the readout circuit 30B.

[0020] The reference signal used for AD conversion may be a signal having a predetermined amplitude according to the range of the pixel signal and whose signal level changes over time. The reference signal is not particularly limited, but for example, a ramp signal whose signal level monotonically increases or decreases over time may be applied. Note that the change in signal level does not necessarily have to be continuous, but may be step-like. Furthermore, the change in signal level does not necessarily have to be linear with respect to time, but may be curved with respect to time (for example, a sine wave or cosine wave).

[0021] The counter circuit 48A is connected to the readout circuit 30A. The counter circuit 48A performs a counting operation in response to a control signal output from the control circuit 80, and has the function of outputting a count signal indicating the count value to the readout circuit 30A. The counter circuit 48A starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal generation circuit 38A starts to change. Similarly, the counter circuit 48B is connected to the readout circuit 30B. The counter circuit 48B performs a counting operation in response to a control signal output from the control circuit 80, and has the function of outputting a count signal indicating the count value to the readout circuit 30B. The counter circuit 48B starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal generation circuit 38B starts to change.

[0022] The horizontal scanning circuit 60A is a control circuit that receives control signals output from the control circuit 80, generates control signals for reading pixel signals from the column circuits 32 of the readout circuit 30A, and supplies the control signals to the readout circuit 30A. The horizontal scanning circuit 60A sequentially scans the column circuits 32 of the readout circuit 30A and outputs the pixel signals held therein to the output circuit 70A via horizontal output lines 62A. Similarly, the horizontal scanning circuit 60B is a control unit that receives control signals output from the control circuit 80, generates control signals for reading pixel signals from the column circuits 32 of the readout circuit 30B, and supplies the control signals to the readout circuit 30B. The horizontal scanning circuit 60B sequentially scans the column circuits 32 of the readout circuit 30B and outputs the pixel signals held therein to the output circuit 70B via horizontal output lines 62B. Logic circuits such as shift registers and address decoders may be used in the horizontal scanning circuits 60A and 60B.

[0023] The output circuit 70A is a processing circuit that is configured with a buffer amplifier, a differential amplifier, etc., and performs predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 60A, and outputs the processed pixel data. Similarly, the output circuit 70B is a processing circuit that is configured with a buffer amplifier, a differential amplifier, etc., and performs predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 60B, and outputs the processed pixel data. Examples of signal processing performed by the output circuits 70A and 70B include correction processing using correlated double sampling (CDS) and amplification processing.

[0024] The control circuit 80 generates control signals that control the operation of the vertical scanning circuit 20, the readout circuits 30A and 30B, the reference signal generation circuits 38A and 38B, the counter circuits 48A and 48B, and the horizontal scanning circuits 60A and 60B, and supplies the control signals to the respective functional blocks. Note that at least some of the control signals that control the operation of the vertical scanning circuit 20, the readout circuits 30A and 30B, the reference signal generation circuits 38A and 38B, the counter circuits 48A and 48B, and the horizontal scanning circuits 60A and 60B may be supplied from outside the photoelectric conversion device 100.

[0025] 1 shows an example in which two readout circuit blocks are provided: a readout circuit block including a readout circuit 30A, a horizontal scanning circuit 60A, an output circuit 70A, etc., and a readout circuit block including a readout circuit 30B, a horizontal scanning circuit 60B, an output circuit 70B, etc. However, the number of readout circuit blocks does not necessarily have to be two, and one readout circuit block may also be provided.

[0026] Each of the plurality of pixels 12 constituting the pixel array unit 10 may be configured with a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in FIG. 2. Each pixel 12 may have a microlens and a color filter arranged on the optical path of incident light leading to the photoelectric conversion element PD. The microlens focuses the incident light onto the photoelectric conversion element PD. The color filter selectively transmits light of a predetermined color.

[0027] The photoelectric conversion element PD is, for example, a photodiode, and has an anode connected to a reference voltage node and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A node FD, to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called floating diffusion region. The floating diffusion region includes a capacitance component (floating diffusion capacitance) and functions as a charge storage region. The floating diffusion capacitance may include pn junction capacitance and wiring capacitance. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the vertical output line 16A (or vertical output line 16B).

[0028] In the pixel configuration of FIG. 2, the control line 14 for each row includes three signal lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal PTX is supplied to the gate of the transfer transistor M1 from the vertical scanning circuit 20. A control signal PRES is supplied to the gate of the reset transistor M2 from the vertical scanning circuit 20. A control signal PSEL is supplied to the gate of the selection transistor M4 from the vertical scanning circuit 20. When each transistor is an N-type MOS transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical scanning circuit 20. On the other hand, the corresponding transistor turns off when a low-level control signal is supplied from the vertical scanning circuit 20.

[0029] In this embodiment, the description will be made assuming that electrons, among the electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is opposite to that described in this embodiment. Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be referred to by the reverse names.

[0030] The photoelectric conversion element PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the node FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD due to charge-voltage conversion by the floating diffusion capacitance.

[0031] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the vertical output line 16A (or vertical output line 16B). The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source (current source 34, described later) (not shown) via the selection transistor M4, forming an amplification unit (source follower circuit) with its gate as an input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of node FD to the vertical output line 16A (or vertical output line 16B) via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 form an output unit that outputs a pixel signal according to the amount of charge held at node FD.

[0032] The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the FD node for resetting the node FD as a charge storage unit. When the reset transistor M2 is turned on, it resets the node FD to a voltage corresponding to the voltage VDD.

[0033] Each of the multiple column circuits 32 that make up the readout circuit 30A can be composed of a current source 34, a buffer circuit 36, a comparison circuit 44, memories 52W, 52R, capacitances C1, C2, and switches SW1, SW2, SW3, as shown in FIG. 3, for example.

[0034] The vertical output line 16A is connected to a current source 34 and one electrode of a capacitor C1. The current source 34 serves as a load current source for the amplifier transistor M3 of the pixel 12.

[0035] The buffer circuit 36 ​​has an input node and an output node. The input node of the buffer circuit 36 ​​is connected to a reference signal line 40. A reference signal VRAMP is supplied to the input node of the buffer circuit 36 ​​from a reference signal generation circuit 38A via the reference signal line 40. The output node of the buffer circuit 36 ​​is connected to one electrode of a capacitor C2. The connection node between the buffer circuit 36 ​​and the capacitor C2 is connected to the connection node between the buffer circuit 36 ​​and the capacitor C2 of an adjacent column circuit 32 via a switch SW1. The switch SW1 is controlled by a control signal SHT supplied from the control circuit 80 via a SHT signal line 42.

[0036] The comparison circuit 44 is configured, for example, by a differential amplifier circuit and has a non-inverting input node (+), an inverting input node (-), a non-inverting output node (+), and an inverting output node (-). The inverting input node of the comparison circuit 44 is connected to the other electrode of the capacitor C1. The inverting input node of the comparison circuit 44 is supplied with a signal VOUT from the vertical output line 16A via the capacitor C1. The non-inverting input node of the comparison circuit 44 is connected to the other electrode of the capacitor C2. The non-inverting input node of the comparison circuit 44 is supplied with a reference signal VRAMP from the reference signal line 40 via the buffer circuit 36 ​​and the capacitor C2. A switch SW2 is connected between the inverting input node and the non-inverting output node of the comparison circuit 44. A switch SW3 is connected between the non-inverting input node and the inverting output node of the comparison circuit 44. The switches SW2 and SW3 are controlled by a control signal AZ supplied from the control circuit 80 via an AZ signal line 46. The switches SW2 and SW3 are reset switches for resetting the threshold voltage of the comparator circuit 44.

[0037] The comparator circuit 44 compares the level of the signal VOUT supplied from the vertical output line 16A via the capacitor C1 with the level of the reference signal VRAMP supplied from the reference signal line 40 via the buffer circuit 36 ​​and the capacitor C2, and outputs a signal according to the comparison result. For example, the comparator circuit 44 outputs a high-level signal when the level of the reference signal VRAMP is lower than the level of the signal VOUT. On the other hand, the comparator circuit 44 outputs a low-level signal when the level of the reference signal VRAMP is higher than the level of the signal VOUT. Note that the relationship between the magnitude of the input signal and the level of the output signal may be reversed.

[0038] The comparison circuit 44 is not limited to the configuration shown in the figure, as long as it has a node to which a pixel signal is input and a node to which a reference signal is input, and is capable of performing an offset clamp operation to set an offset based on the voltages of the pixel signal and the reference signal.

[0039] The memory 52W has two input nodes and one output node. One input node of the memory 52W is connected to the non-inverting output node of the comparison circuit 44. The other input node of the memory 52W is connected to a count signal line 50. A count signal COUNT is supplied to the other input node of the memory 52W from the counter circuit 48A via the count signal line 50. The memory 52R has two input nodes and one output node. One input node of the memory 52R is connected to the output node of the memory 52W. The other input node of the memory 52R is connected to the horizontal scanning circuit 60A. The output node of the memory 52R is connected to the horizontal output line 62A.

[0040] The memory 52W holds, as digital data of the pixel signal, the count value indicated by the count signal COUNT supplied from the counter circuit 48A when the level of the non-inverting output node of the comparator circuit 44 is inverted. The memory 52R holds the digital data of the pixel signal transferred from the memory 52W. The digital data held in the memory 52R is transferred to the output circuit 70A via the horizontal output line 62A sequentially for each column in response to a control signal supplied from the horizontal scanning circuit 60A. By providing the memory 52R subsequent to the memory 52W, it is possible to perform AD conversion in parallel with the transfer operation to the output circuit 70A.

[0041] Instead of providing the counter circuit 48A, the memory 52W of the column circuit 32 may have the function of a counter circuit. In this case, the memory 52W of the column circuit 32 of each column receives a common clock signal output from the control circuit 80 and counts pulses of the clock signal. The count value at the timing when the level of the output signal of the comparison circuit 44 is inverted becomes digital data held in the memory 52W.

[0042] The column circuits 32 of the readout circuit 30B are the same as the column circuits 32 of the readout circuit 30A except that they are arranged in a different column from the column in which the column circuits 32 of the readout circuit 30A are arranged, so a description thereof will be omitted. The following description will focus on the column circuits 32 of the readout circuit 30A, but the same applies to the column circuits 32 of the readout circuit 30B.

[0043] As shown in FIG. 4, the buffer circuit 36 ​​includes P-type transistors MP1, MP2, and MP3, a capacitor C3, and a switch SW4. The source of the P-type transistor MP1 is connected to a node to which a power supply voltage (voltage VDD) is supplied. The drain of the P-type transistor MP1 is connected to a source of the P-type transistor MP2. The drain of the P-type transistor MP2 is connected to a source of the P-type transistor MP3. The drain of the P-type transistor MP3 is connected to a reference voltage node. A bias voltage VB is supplied to the gate of the P-type transistor MP1 via the switch SW4. A capacitor C3 is connected between the node to which the power supply voltage (voltage VDD) is supplied and the gate of the P-type transistor MP1. A bias voltage VC is supplied to the gate of the P-type transistor MP2. The gate of the P-type transistor MP3 is the input node IN of the buffer circuit 36. The connection node between the drain of the P-type transistor MP2 and the source of the P-type transistor MP3 is the output node OUT of the buffer circuit 36.

[0044] The P-type transistor MP1 operates as a current source, with a bias voltage VB supplied to its gate via a switch SW4. A capacitor C3 is connected between the power supply voltage node and the gate of the P-type transistor MP1, allowing the P-type transistor MP1 to operate even when the bias voltage VB is sampled and held by the capacitor C3. The P-type transistor MP2 operates as a cascode transistor, with a bias voltage VC supplied to its gate. The P-type transistor MP3, together with the P-type transistor MP1 operating as a current source, forms a source follower, buffering the signal (reference signal VRAMP) supplied from the input node IN and outputting it from the output node OUT. That is, the buffer circuit 36 ​​buffers the reference signal VRAMP and outputs it to the comparison circuit 44.

[0045] A switch SW1 is provided between the output nodes of the buffer circuits 36 of adjacent column circuits 32 (see FIG. 3). These multiple switches SW1 form a switch circuit that switches the connection state between the output nodes of the buffer circuits 36 of each column. The switch SW1 can be configured to switch its connection state depending on the mode prioritized during operation of the photoelectric conversion device. That is, by connecting the output nodes of the buffer circuits 36 of each column to each other, random noise generated by the buffer circuits 36 can be averaged and reduced. On the other hand, connecting the output nodes of the buffer circuits 36 of each column can increase the likelihood of interference between columns. Therefore, the switch SW1 can be set to on (connected, conductive) in a mode prioritizing low noise and off (disconnected, non-conductive) in a mode prioritizing low interference. Thus, providing the switch SW1 between the output nodes of the buffer circuits 36 of each column enables the photoelectric conversion device to have multiple functions.

[0046] The photoelectric conversion device 100 of this embodiment may be configured so that all of the above-mentioned circuit blocks are arranged on a single substrate, or may be configured so that multiple substrates are stacked together and different circuit blocks are created on each substrate.

[0047] 5(a) is a schematic diagram of a case where a pixel substrate 110 on which the pixel array section 10 is arranged is stacked on a circuit substrate 120 on which other circuit blocks are arranged. By arranging the pixel substrate 110 and the circuit substrate 120 on separate substrates, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0048] 5(b) is a schematic diagram showing a case where a pixel substrate 110 on which the pixel array section 10 is arranged is stacked with circuit substrates 120 and 130 on which other circuit blocks are arranged. In this case as well, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0049] It should be noted that the circuit elements that make up one functional block do not necessarily have to be arranged on the same substrate, and may be arranged on separate substrates.

[0050] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Figures 6 and 7. Figures 6 and 7 are timing charts showing an example of the operation of the photoelectric conversion device according to this embodiment.

[0051] The photoelectric conversion device according to this embodiment can use switch SW1 to switch between the above-mentioned operating modes, and can also distribute the operation timing of the comparison circuits 44 for each column to suppress fluctuations in the power supply voltage and reference voltage, thereby improving image quality. This point will be explained below while showing an example of the operation of the photoelectric conversion device. Here, the operation of readout circuit 30A will be explained, but the operation of readout circuit 30B is similar.

[0052] Fig. 6 is a timing diagram showing an example of operation when the switch SW1 is not driven (always in a non-conducting state). In Fig. 6, the waveforms of the control signals PTX, PRES, AZ, SHT and signal VOUT are shown by solid lines, and the waveform of the reference signal VRAMP is shown by a dashed line. Here, when the control signals PTX, PRES, AZ, SHT are at a high level, the corresponding transistor or switch is turned on, and when the control signals PTX, PRES, AZ, SHT are at a low level, the corresponding transistor or switch is turned off.

[0053] Just before time t0, the control signal PSEL (not shown) for the row to be read is at a high level. This turns on the selection transistors M4 of the pixels 12 in that row, and each of these pixels 12 is ready to output a pixel signal to the vertical output line 16A of the corresponding column. Also, just before time t0, the control signals PTX, PRES and control signals SHT, AZ for the row to be read are at a low level, and the reference signal VRAMP is at a predetermined reference voltage.

[0054] During the period from time t0 to time t1, the vertical scanning circuit 20 controls the control signal PRES of the row to be readout to high level. This turns on the reset transistor M2 of the pixel 12 belonging to that row, and resets the node FD to a voltage corresponding to the voltage VDD. A signal VOUT (pixel signal at reset level) having a voltage corresponding to the reset voltage of the node FD is output to the vertical output line 16A.

[0055] Furthermore, during the period from time t0 to time t2, the control circuit 80 controls the control signal AZ to a high level. This turns on the switches SW2 and SW3 of the column circuit 32 of each column, and the inverting input node and the non-inverting input node of the comparison circuit 44 are reset to a reset level voltage. That is, at time t2, one electrode of the capacitor C1 is at the reset level voltage of the signal VOUT, and the other electrode of the capacitor C1 is at the reset level voltage of the comparison circuit 44. Furthermore, one electrode of the capacitor C2 is at the reference voltage of the reference signal VRAMP, and the other electrode of the capacitor C2 is at the reset level voltage of the comparison circuit 44. The threshold voltage of the comparison circuit 44 is reset to a voltage corresponding to the potential difference between the reset level voltage of the signal VOUT and the reference voltage of the reference signal VRAMP.

[0056] The threshold voltage of the comparison circuit 44 is a voltage corresponding to the difference between the signal level of the pixel signal and the signal level of the reference signal when the level of the comparison signal output from the comparison circuit 44 changes. That is, the comparison circuit 44 outputs a comparison signal that indicates a different level when the difference between the signal level of the pixel signal and the signal level of the reference signal is smaller than the threshold voltage and when it is larger than the threshold voltage.

[0057] At the next time t2, the control circuit 80 controls the control signal AZ to a low level, which turns off the switches SW2 and SW3 of the column circuit 32 of each column, clamps the reset level of the signal VOUT to the capacitor C1, and clamps the reference level corresponding to the reference voltage of the reference signal VRAMP to the capacitor C2.

[0058] At the next time t4, the reference signal generation circuit 38A increases the reference signal VRAMP from the base voltage to a predetermined start voltage. Then, at the next time t5, the reference signal generation circuit 38 starts a slope operation in which the voltage of the reference signal VRAMP changes over time. The counter circuit 48A also starts counting up at the same time as the slope operation starts, and supplies a count signal COUNT indicating the count value to the column circuit 32 of each column via the count signal line 50.

[0059] The comparator circuit 44 compares the level of the signal VOUT input via the capacitor C1 with the level of the reference signal VRAMP input via the capacitor C2. The comparator circuit 44 then inverts the level of its output signal when the magnitude relationship between the level of the signal VOUT and the level of the reference signal VRAMP changes, for example, at time t6 in FIG. 6. Note that when comparing the reset level signal VOUT with the reference signal VRAMP, the levels of the output signals of multiple comparators 44 may invert simultaneously. If multiple comparators 44 invert simultaneously, the amount of current flowing at one time increases, which may cause fluctuations in the power supply voltage and reference voltage.

[0060] The memory 52W holds, as digital data of the pixel signal, the count value indicated by the count signal COUNT supplied from the counter circuit 48A at the timing when the level of the output signal of the comparison circuit 44 is inverted. In this manner, AD conversion is performed on the pixel signal at the reset level. The digital data held in the memory 52W is transferred to the memory 52R and then transferred to the output circuit 70A in response to a control signal from the horizontal scanning circuit 60A.

[0061] At the following time t7, the reference signal generating circuit 38A resets the reference signal VRAMP to the level of the reference voltage.

[0062] During the subsequent period from time t8 to time t9, the vertical scanning circuit 20 controls the control signal PTX for the row to be readout to high level. This turns on the transfer transistor M1 of the pixel 12 belonging to that row, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. This causes the voltage of the node FD to decrease in accordance with the amount of charge transferred from the photoelectric conversion element PD, and the voltage of the signal VOUT output to the vertical output line 16A also decreases. A signal VOUT (pixel signal at the optical signal level) with a voltage corresponding to the voltage of the node FD is output to the vertical output line 16A.

[0063] At the next time t10, the reference signal generation circuit 38A increases the reference signal VRAMP from the base voltage to a predetermined start voltage. Then, at the next time t11, the reference signal generation circuit 38 starts a slope operation in which the voltage of the reference signal VRAMP changes over time. The counter circuit 48A also starts counting up at the same time as the slope operation starts, and supplies a count signal COUNT indicating the count value to the column circuit 32 of each column via the count signal line 50.

[0064] The comparator circuit 44 compares the level of the signal VOUT input via the capacitor C1 with the level of the reference signal VRAMP input via the capacitor C2. The comparator circuit 44 then inverts the level of its output signal at the timing when the magnitude relationship between the level of the signal VOUT and the level of the reference signal VRAMP changes, for example, at time t12 in FIG.

[0065] The memory 52W holds, as digital pixel signal data, the count value indicated by the count signal COUNT supplied from the counter circuit 48A when the level of the output signal from the comparator circuit 44 is inverted. In this manner, AD conversion is performed on the pixel signal at the optical signal level. The digital data held in the memory 52W is transferred to the memory 52R and then transferred to the output circuit 70A in response to a control signal from the horizontal scanning circuit 60A.

[0066] The digital data of the pixel signals obtained in this way is subjected to a correction process using correlated double sampling in the output circuit 70A at the subsequent stage. In the correction process using correlated double sampling, the digital data of the pixel signals at the reset level is subtracted from the digital data of the pixel signals at the optical signal level, and noise components superimposed on the pixel signals at the optical signal level are removed.

[0067] Fig. 7 is a timing diagram showing an example of operation when driving switch SW1. In Fig. 7, the waveforms of the control signals PTX, PRES, AZ, SHT and signal VOUT are shown by solid lines, and the waveform of the reference signal VRAMP is shown by dashed lines. Here, when the control signals PTX, PRES, AZ, SHT are at a high level, the corresponding transistor or switch is turned on, and when the control signals PTX, PRES, AZ, SHT are at a low level, the corresponding transistor or switch is turned off.

[0068] 7 differs from the timing diagram of FIG. 6 in that the control signal SHT is controlled to a high level during the period from time t0 to time t3. Controlling the control signal SHT to a high level turns on the switch SW1, electrically connecting the output nodes of the buffer circuits 36 of each column. In other words, the reset of the comparator circuit 44 and the clamping of the reset level of the signal VOUT and the reference level of the reference signal VRAMP are performed while the output nodes of the buffer circuits 36 of each column are connected, and then the connection between the output nodes of the buffer circuits 36 of each column is released.

[0069] Generally, buffer circuits 36 have their own offsets due to variations in the performance of each element and variations in wiring resistance, and the output of each buffer circuit 36 ​​in each column contains its own offset component. Between time t0 and time t2, switch SW1 is turned on, electrically connecting the output nodes of the buffer circuits 36 in each column. This causes the average offset of these buffer circuits 36 to appear in the output of each buffer circuit 36. Meanwhile, when the output nodes of the buffer circuits 36 in each column are disconnected at time t3, each buffer circuit 36's output node exhibits its own offset. As a result, the inversion timing of the comparator circuits 44 at time t6 is shifted by the amount of change from the average offset to the individual offset. This allows the inversion timing of the comparator circuits 44 in each column circuit 32 to be distributed, thereby reducing the number of comparator circuits 44 whose output signals are inverted at any one time. This reduces the peak current and ultimately suppresses fluctuations in the power supply voltage and reference voltage. The deviation in the count value due to the deviation in the inversion timing of the comparator circuit 44 of each column can be removed as an offset component by performing digital CDS processing in the output circuit 70A.

[0070] Note that the operation mode of the switch SW1 may be switched depending on the gain, such as by keeping the control signal SHT always at a low level when the slope of the reference signal VRAMP is reduced to increase the AD conversion gain. Also, in FIG. 7, the control signal AZ is set to a low level at time t2, and then the control signal SHT is set to a low level at time t3. However, the control signal AZ and the control signal SHT may be set to a low level simultaneously. Alternatively, the control signal SHT may be set to a low level immediately before the control signal AZ is set to a low level at time t2. The timing at which the control signal SHT is set to a low level may be adjusted depending on the slope of the reference signal VRAMP. It is sufficient that at least the period during which the control signal AZ is at a high level overlaps with the period during which the control signal SHT is at a high level. From another perspective, it is sufficient that the control signal SHT is at a high level for at least a portion of the period during which the control signal AZ is at a high level. In other words, it is sufficient that the switch SW1 is on for at least a portion of the period during which the switches SW2 and SW3 are on. In this way, by turning on the switch SW1 for at least a part of the period during which the offset clamping operation is performed, the average value of the offsets of the plurality of buffer circuits 36 can be obtained, and noise can be reduced.

[0071] As described above, according to this embodiment, in a photoelectric conversion device including a column-parallel AD converter, it is possible to realize multi-functionality and suppress fluctuations in the power supply voltage to improve image quality.

[0072] [Second embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Fig. 8. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 8 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment.

[0073] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the column circuit 32. In this embodiment, the differences between the column circuit 32 of this embodiment and the column circuit 32 of the first embodiment will be mainly described, and descriptions of the parts common to the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0074] In the photoelectric conversion device of the first embodiment, the buffer circuits 36 of the column circuits 32 of each column are connected in parallel to the reference signal line 40 (see FIG. 2). In contrast, in the photoelectric conversion device of this embodiment, as shown in FIG. 8, a plurality of buffer circuits 36 are connected in series to a path to which a reference signal is supplied. The capacitance C2 of the column circuits 32 of each column is connected to the reference signal line 40 at a node between the buffer circuits 36 of adjacent column circuits 32. As in the first embodiment, the output nodes of the buffer circuits 36 of adjacent column circuits 32 are connected via a switch SW1.

[0075] Even with this configuration of the column circuit 32, turning on the switch SW1 can reduce the influence of random noise generated by the buffer circuit 36. That is, a low-noise operation mode can be implemented. Furthermore, by performing driving similar to that shown in the timing diagram of FIG. 7, the inversion timings of the comparators 44 in the column circuits 32 of each column can be dispersed, suppressing fluctuations in the power supply voltage and reference voltage, thereby improving image quality. That is, by turning on the switch SW1 during the clamping period from time t0 to time t2, the offsets of the buffer circuits 36 of each column can be averaged. Then, by setting the control signal SHT to low level after clamping ends, the inversion timings of the comparators 44 in the column circuits 32 of each column can be dispersed.

[0076] In the photoelectric conversion device of the first embodiment, the buffer circuits 36 are connected in parallel between the reference signal line 40 and the comparison circuits 44 of each column, so that there is a single buffer circuit 36 ​​between the reference signal generation circuit 38A and the comparison circuits 44 of each column. Therefore, the photoelectric conversion device of the first embodiment has the advantage that it is easier to unify the characteristics of each column compared to the photoelectric conversion device of this embodiment.

[0077] As described above, according to this embodiment, in a photoelectric conversion device including a column-parallel AD converter, it is possible to realize multi-functionality and suppress fluctuations in the power supply voltage to improve image quality.

[0078] [Third embodiment] A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Fig. 9. Components similar to those of the photoelectric conversion device according to the first or second embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 9 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment.

[0079] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the column circuit 32. In this embodiment, the differences between the column circuit 32 of this embodiment and the column circuit 32 of the first embodiment will be mainly described, and descriptions of the parts common to the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0080] In the photoelectric conversion device of the first embodiment, a switch SW1 is provided between the output nodes of the buffer circuits 36 of adjacent column circuits 32 (see FIG. 2). In contrast, in the photoelectric conversion device of this embodiment, as shown in FIG. 9, a switch SW11 is provided between the output node of the buffer circuit 36a of the column circuit 32a and the output node of the buffer circuit 36c of the column circuit 32c. Furthermore, a switch SW12 is provided between the output node of the buffer circuit 36b of the column circuit 32b and the output node of the buffer circuit 36d of the column circuit 32d. Here, it is assumed that the column circuits 32a, 32b, 32c, and 32d are arranged adjacent to each other in this order. The switch SW11 is controlled by a control signal SHT1 supplied from a SHT signal line 42. The switch SW12 is controlled by a control signal SHT2 supplied from a SHT signal line 42.

[0081] In other words, in this embodiment, the column circuits 32 arranged in each column are divided into a first group including the column circuits 32a and 32c and a second group including the column circuits 32b and 32d. The switch SW11 constitutes a switch circuit configured to be able to switch the connection state between the output nodes of the buffer circuits 36 in the first group. The switch SW12 constitutes a switch circuit configured to be able to switch the connection state between the output nodes of the buffer circuits 36 in the second group independently of the switch circuit including the switch SW11.

[0082] In the photoelectric conversion device of this embodiment, by controlling only one of the control signals SHT1 and SHT2 to a high level, it is possible to drive only one of the switches SW11 and SW12 to be turned on. This configuration of the photoelectric conversion device facilitates operation modes such as powering off the buffer circuits 36b and 36d to save power, for example, when thinning out every other column of the column circuit 32. When the buffer circuits 36b and 36d are powered off, their outputs become floating. Therefore, if potential fluctuations occur due to the on / off switching of the switch SW12, it takes time for the signals to settle, generating noise and ultimately resulting in image quality degradation. In such cases, image quality degradation in the power-saving mode can be suppressed by driving only the control signal SHT1 in the same manner as the control signal SHT in the timing diagram of FIG. 7 and setting the control signal SHT2 to a low level to keep the switch SW12 off.

[0083] The set of column circuits 32 connected by the switch SW11 and the set of column circuits 32 connected by the switch SW12 can be set as appropriate. Furthermore, the number of sets of column circuits 32 connected by the switch SW1 does not necessarily have to be two, and three or more sets may be provided.

[0084] As described above, according to this embodiment, in a photoelectric conversion device including a column-parallel AD converter, it is possible to suppress fluctuations in the power supply voltage and improve image quality.

[0085] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Fig. 10. Components similar to those of the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 10 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment.

[0086] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the third embodiment except for the configuration of the column circuit 32. In this embodiment, the differences between the column circuit 32 of this embodiment and the column circuit 32 of the third embodiment will be mainly described, and descriptions of the parts common to the photoelectric conversion device of the third embodiment will be omitted as appropriate.

[0087] 10, the photoelectric conversion device of this embodiment further includes a switch SW51 provided between the vertical output line 16A connected to the column circuit 32a and the vertical output line 16A connected to the column circuit 32c. The photoelectric conversion device of this embodiment also includes a switch SW52 provided between the vertical output line 16A connected to the column circuit 32b and the vertical output line 16A connected to the column circuit 32d. The switch SW51 is controlled by a control signal SHT3 supplied from the SHT signal line 42. The switch SW52 is controlled by a control signal SHT4 supplied from the SHT signal line 42.

[0088] The switches SW51 and SW52 constitute a switch circuit that switches the connection state between the vertical output lines 16A of each column. The switch SW51 constitutes a switch circuit configured to be able to switch the connection state between the vertical output lines 16A of a column in which a first set of column circuits 32 including the column circuits 32a and 32c are arranged. The switch SW52 constitutes a switch circuit configured to be able to switch the connection state between the vertical output lines 16A of a column in which a second set of column circuits 32 including the column circuits 32b and 32d are arranged.

[0089] In the photoelectric conversion device of this embodiment, the control signals SHT1, SHT2, SHT3, and SHT4 are controlled in the same manner as the control signal SHT in the timing diagram of Fig. 7. Driving the photoelectric conversion device in this manner distributes the inversion timing of the comparator circuits 44 in the column circuits 32 of each column, and makes it possible to change the potential of the vertical output line 16A corresponding to the column circuit 32 of each column during the clamp period from time t0 to time t2. This makes it possible to further suppress fluctuations in the power supply voltage and reference voltage, thereby improving image quality.

[0090] As described above, according to this embodiment, in a photoelectric conversion device including a column-parallel AD converter, it is possible to suppress fluctuations in the power supply voltage and improve image quality.

[0091] [Fifth embodiment] A photoelectric conversion device according to a fifth embodiment of the present invention will be described with reference to Figs. 11 and 12. Components similar to those in the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 11 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment. Fig. 12 is a timing chart showing a method for driving the photoelectric conversion device according to this embodiment.

[0092] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the fourth embodiment except for the configuration of the column circuit 32. In this embodiment, the differences between the column circuit 32 of this embodiment and the column circuit 32 of the fourth embodiment will be mainly described, and descriptions of the parts common to the photoelectric conversion device of the fourth embodiment will be omitted as appropriate.

[0093] In the photoelectric conversion devices according to the first to fourth embodiments, the reset switches SW2 and SW3 of the comparison circuits 44 of the column circuits 32 of each column are controlled by a common control signal AZ. In contrast, in the photoelectric conversion device of this embodiment, the reset switches SW2 and SW3 of the comparison circuits 44 of the column circuits 32a and 32c are controlled by a control signal AZ1. The reset switches SW2 and SW3 of the comparison circuits 44 of the column circuits 32b and 32d are controlled by a control signal AZ2.

[0094] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to FIG. 12. FIG. 12 is a timing diagram showing an example of operation when switches SW11, SW12, SW51, and SW52 are not driven (always in a non-conductive state). In FIG. 12, the waveforms of control signals PTX, PRES, AZ1, AZ2, SHT1, SHT2, SHT3, and SHT4 and signal VOUT are shown by solid lines, and the waveform of reference signal VRAMP is shown by dashed lines. Here, when control signals PTX, PRES, AZ1, AZ2, SHT1, SHT2, SHT3, and SHT4 are at a high level, the corresponding transistors or switches are turned on. Also, when control signals PTX, PRES, AZ1, AZ2, SHT1, SHT2, SHT3, and SHT4 are at a low level, the corresponding transistors or switches are turned off.

[0095] Just before time t0, the control signal PSEL (not shown) for the row to be read is at a high level. This turns on the selection transistors M4 of the pixels 12 in that row, and each of these pixels 12 is ready to output a pixel signal to the vertical output line 16A of the corresponding column. Also, just before time t0, the control signals PTX, PRES and control signals SHT1, SHT2, SHT3, SHT4, AZ1, and AZ2 for the row to be read are at a low level, and the reference signal VRAMP is at a predetermined reference voltage (first reference voltage).

[0096] During the period from time t0 to time t1, the vertical scanning circuit 20 controls the control signal PRES of the row to be readout to high level. This turns on the reset transistor M2 of the pixel 12 belonging to that row, and resets the node FD to a voltage corresponding to the voltage VDD. A signal VOUT (pixel signal at reset level) having a voltage corresponding to the reset voltage of the node FD is output to the vertical output line 16A.

[0097] Furthermore, during the period from time t0 to time t2, the control circuit 80 controls the control signal AZ1 to a high level. This turns on the switches SW2 and SW3 of the column circuits 32a and 32c, and resets the inverting input node and the non-inverting input node of the comparison circuit 44 to a reset level voltage. That is, at time t2, one electrode of the capacitor C1 is at the reset level voltage of the signal VOUT, and the other electrode of the capacitor C1 is at the reset level voltage of the comparison circuit 44. Furthermore, one electrode of the capacitor C2 is at the first reference voltage of the reference signal VRAMP, and the other electrode of the capacitor C2 is at the reset level voltage of the comparison circuit 44.

[0098] At time t2, the control circuit 80 controls the control signal AZ1 to a low level, which turns off the switches SW2 and SW3 of the column circuits 32a and 32c, clamping the reset level of the signal VOUT to the capacitor C1 of the column circuits 32a and 32c, and clamping the first reference level corresponding to the first reference voltage of the reference signal VRAMP to the capacitor C2.

[0099] In the period from time t2 to time t3, the reference signal generating circuit 38A switches the reference signal VRAMP from the first reference voltage to a predetermined reference voltage (second reference voltage) different from the first reference voltage.

[0100] Furthermore, during the period from time t0 to time t3, the control circuit 80 controls the control signal AZ2 to a high level. This turns on the switches SW2 and SW3 of the column circuits 32b and 32d, and resets the inverting input node and the non-inverting input node of the comparison circuit 44 to a reset level voltage. That is, at time t3, one electrode of the capacitor C1 is at the reset level voltage of the signal VOUT, and the other electrode of the capacitor C1 is at the reset level voltage of the comparison circuit 44. Furthermore, one electrode of the capacitor C2 is at the second reference voltage of the reference signal VRAMP, and the other electrode of the capacitor C2 is at the reset level voltage of the comparison circuit 44.

[0101] At time t3, the control circuit 80 controls the control signal AZ2 to a low level, which turns off the switches SW2 and SW3 of the column circuits 32b and 32d, clamping the reset level of the signal VOUT to the capacitor C1 of the column circuits 32b and 32d, and clamping the second reference level corresponding to the second reference voltage of the reference signal VRAMP to the capacitor C2.

[0102] As described above, the reference signal VRAMP is at the first reference level at time t2 and at the second reference level at time t3, and the comparison circuits 44 in the column circuits 32a and 32c and the comparison circuits 44 in the column circuits 32b and 32d clamp the reference signal VRAMP to different reference levels. As a result, the comparison circuits 44 in the column circuits 32a and 32c and the comparison circuits 44 in the column circuits 32b and 32d invert the output signal levels at different times for the same signal VOUT. For example, the output of the comparison circuits 44 in the column circuits 32a and 32c inverts at time t6, and the output of the comparison circuits 44 in the column circuits 32b and 32d inverts at time t7. This allows the timing at which the output of the comparison circuits 44 in the column circuits 32a and 32c inverts to differ from the timing at which the output of the comparison circuits 44 in the column circuits 32b and 32d inverts to be different, thereby suppressing fluctuations in the power supply voltage and the reference voltage and ultimately improving image quality.

[0103] Although an operation example in which the switches SW11, SW12, SW51, and SW52 are not driven has been shown here, the switches SW11, SW12, SW51, and SW52 may be driven in combination, as in the third or fourth embodiment. In this case, for example, as shown in FIG. 11 , a switch SW11 is provided corresponding to the column circuits 32a and 32c that use the control signal AZ1, and a switch SW12 is provided corresponding to the column circuits 32b and 32d that use the control signal AZ2. With this configuration, the timing at which the output of the comparison circuit 44 in the column circuits 32a and 32c is inverted and the timing at which the output of the comparison circuit 44 in the column circuits 32b and 32d is inverted can be further separated from each other, thereby more effectively suppressing fluctuations in the power supply voltage and the reference voltage.

[0104] As described above, according to this embodiment, in a photoelectric conversion device including a column-parallel AD converter, it is possible to suppress fluctuations in the power supply voltage and improve image quality.

[0105] [Sixth embodiment] A photoelectric conversion device according to a sixth embodiment of the present invention will be described with reference to Fig. 13. Components similar to those in the photoelectric conversion devices according to the first to fifth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 13 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment.

[0106] In the first to fifth embodiments, a configuration has been described in which one type of reference signal VRAMP is supplied from the reference signal generation circuit 38A to the column circuit 32 of each column, but two or more types of reference signals VRAMP may be supplied to the column circuit 32 of each column. As an example, in the present embodiment, a configuration example will be described in which two types of reference signals VRAMP are supplied from the reference signal generation circuit 38A via separate reference signal lines.

[0107] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the column circuit 32. In this embodiment, the differences between the column circuit 32 of this embodiment and the column circuit 32 of the first embodiment will be mainly described, and descriptions of the parts common to the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0108] 13, the column circuit 32 of the photoelectric conversion device of this embodiment further includes a dummy buffer circuit 36D and switches SW61, SW62, SW63, and SW64. A reference signal VRAMP1 is supplied from the reference signal generation circuit 38A via a reference signal line 40a, and a reference signal VRAMP2 is supplied via a reference signal line 40b to the column circuit 32 of each column. One node of each of the switches SW61 and SW63 is connected to the reference signal line 40a. One node of each of the switches SW62 and SW64 is connected to the reference signal line 40b. The other node of each of the switches SW61 and SW62 is connected to the input node of the buffer circuit 36. The other node of each of the switches SW63 and SW64 is connected to the input node of the dummy buffer circuit 36D. The output node of the dummy buffer circuit 36D is open.

[0109] By configuring the column circuit 32 of each column in this manner, it is possible to select one of two types of reference signals VRAMP1 and VRAMP2 as the reference signal to be input to the comparison circuit 44. That is, by setting the switch SW61 on and the switch SW62 off, the reference signal VRAMP1 is input to the comparison circuit 44. On the other hand, by setting the switch SW61 off and the switch SW62 on, the reference signal VRAMP2 is input to the comparison circuit 44.

[0110] The switches SW63 and SW64 are driven complementarily to the switches SW61 and SW62. That is, when the switch SW61 is turned on and the switch SW62 is turned off to select the reference signal VRAMP1, the switch SW63 is turned off and the switch SW64 is turned on. In this case, the reference signal line 40a is connected to the buffer circuit 36, and the reference signal line 40b is connected to the dummy buffer circuit 36D. On the other hand, when the switch SW61 is turned off and the switch SW62 is turned on to select the reference signal VRAMP2, the switch SW63 is turned on and the switch SW64 is turned off. In this case, the reference signal line 40a is connected to the dummy buffer circuit 36D, and the reference signal line 40b is connected to the buffer circuit 36. That is, regardless of whether the reference signal VRAMP1 or VRAMP2 is selected as the reference signal input to the comparison circuit 44, the buffer circuit 36 ​​or the dummy buffer circuit 36D is connected to each of the reference signal lines 40a and 40b. Therefore, by driving the switches SW61, SW62, SW63, and SW64 in this manner, it is possible to suppress fluctuations in the capacitance associated with the reference signal lines 40a and 40b.

[0111] In the configuration example of FIG. 13, a switch SW1 is not provided between the output nodes of the dummy buffer circuit 36D in order to reduce the area, but a switch SW1 may be provided between the output nodes of the dummy buffer circuit 36D, similar to the case between the output nodes of the buffer circuit 36.

[0112] As described above, according to this embodiment, in a photoelectric conversion device including a column-parallel AD converter, it is possible to suppress fluctuations in the power supply voltage and improve image quality.

[0113] [Seventh embodiment] An imaging system according to the seventh embodiment of the present invention will be described with reference to Fig. 14. Fig. 14 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0114] The photoelectric conversion device 100 described in the first to sixth embodiments can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in imaging systems. Fig. 14 illustrates a block diagram of a digital still camera as an example of such systems.

[0115] 14 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to sixth embodiments, and converts the optical image formed by the lens 202 into image data.

[0116] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed on a semiconductor substrate different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor substrate as the imaging device 201.

[0117] The imaging system 200 further includes a buffer memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 also includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out imaging data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or may be removable.

[0118] The imaging system 200 further includes an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0119] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0120] As described above, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to sixth embodiments is applied.

[0121] [Eighth embodiment] An imaging system and a moving object according to an eighth embodiment of the present invention will be described with reference to Fig. 15. Fig. 15 is a diagram showing the configuration of the imaging system and the moving object according to this embodiment.

[0122] FIG. 15(a) shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to sixth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the imaging device 310. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0123] The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force on the vehicle based on the determination result of a collision determination unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0124] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 15(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0125] Although the above describes an example of control to prevent collision with other vehicles, the system can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0126] [Ninth embodiment] A device according to a ninth embodiment of the present invention will be described with reference to Fig. 16. Fig. 16 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0127] FIG. 16 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 of any of the first to sixth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0128] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0129] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0130] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0131] The device EQP shown in FIG. 16 can be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can also be transportation equipment (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP can also be medical equipment such as an endoscope or a CT scanner. The device EQP can also be medical equipment such as an endoscope or a CT scanner.

[0132] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0133] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0134] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0135] Furthermore, in the above first to sixth embodiments, one vertical output line 16 is provided for each column of the pixel array section 10, but the number of vertical output lines 16 provided for each column of the pixel array section 10 is not limited to one, and may be two or more.

[0136] Furthermore, the circuit configuration of the pixel 12 shown in FIG. 2 is an example and can be modified as appropriate. For example, each pixel 12 may have two or more photoelectric conversion elements. In this case, a configuration in which multiple photoelectric conversion elements share one FD node may be used. Also, a pupil-divided pixel in which multiple photoelectric conversion elements share one microlens may be used, enabling detection of a phase difference. Also, the pixel 12 does not necessarily have to include a selection transistor M4. Also, the capacitance value of the node FD may be configured to be switchable.

[0137] Furthermore, the imaging systems shown in the seventh and eighth embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 14 and 15.

[0138] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0139] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0140] SW1, SW11, SW12, SW2, SW3, SW51, SW52...Switches 10...Pixel array section 16A,16B…Vertical output line 32...Column circuit 36...Buffer circuit 36D...Dummy buffer circuit 40...Reference signal line 44…Comparison circuit 80...Control circuit 100...Photoelectric conversion device

Claims

1. a plurality of pixels arranged in a plurality of columns; a plurality of comparison circuits provided corresponding to the plurality of columns, each having a first input node to which a pixel signal output from a pixel in the corresponding column is input, and a second input node to which a reference signal is input; a plurality of buffer circuits provided between a reference signal line to which the reference signal is supplied and each of the second input nodes of the plurality of comparison circuits; a first switch circuit that sets a connection state between output nodes of the plurality of buffer circuits; a plurality of output lines provided corresponding to the plurality of columns, through which the pixel signals are output from the pixels of the corresponding columns; a second switch circuit that sets a connection state between the plurality of output lines; and the plurality of buffer circuits include a first set including some of the plurality of buffer circuits and a second set including other some of the plurality of buffer circuits; The second switch circuit includes a first circuit that sets a connection state between the output lines of the column in which the first set of buffer circuits is arranged, and a second circuit that sets a connection state between the output lines of the column in which the second set of buffer circuits is arranged, independently of the first circuit. A photoelectric conversion device characterized by:

2. The first switch circuit has a first circuit that sets a connection state between the output nodes of the first set of buffer circuits, and a second circuit that sets a connection state between the output nodes of the second set of buffer circuits independently of the first circuit.

2. The photoelectric conversion device according to claim 1.

3. The buffer circuits of the first set and the buffer circuits of the second set are alternately arranged.

3. The photoelectric conversion device according to claim 1 or 2.

4. a control circuit for controlling the plurality of comparison circuits; each of the plurality of comparison circuits has a reset switch that resets a threshold voltage to a voltage according to a potential difference between the first input node and the second input node; The control circuit is configured to turn on the reset switch during at least a portion of the period during which the first switch circuit is on.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. a control circuit for controlling the plurality of comparison circuits; each of the plurality of comparison circuits has a reset switch that resets a threshold voltage to a voltage according to a potential difference between the first input node and the second input node; The control circuit is configured to turn on the reset switch and switch it from on to off during a period when the first circuit of the first switch circuit is on and the second circuit is off.

4. The photoelectric conversion device according to claim 2 or 3.

6. the plurality of comparison circuits include a first set arranged in the same column as the first set of buffer circuits and a second set arranged in the same column as the second set of buffer circuits; The voltage of the reference signal line is different between the timing when the reset switch of the comparison circuit of the first set is switched from on to off and the timing when the reset switch of the comparison circuit of the second set is switched from on to off.

6. The photoelectric conversion device according to claim 5.

7. a plurality of dummy buffer circuits provided corresponding to each of the plurality of columns; a third switch circuit provided between the reference signal line and the plurality of buffer circuits and the plurality of dummy buffer circuits, the reference signal lines include a first reference signal line that supplies a first reference signal and a second reference signal line that supplies a second reference signal; The third switch circuit is configured to connect the first reference signal line to one of the buffer circuit and the dummy buffer circuit, and to connect the second reference signal line to the other of the buffer circuit and the dummy buffer circuit, in each of the plurality of columns.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

8. The plurality of buffer circuits are provided in parallel between the reference signal line and the plurality of comparison circuits.

8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

9. The plurality of buffer circuits are provided in series on a path to which the reference signal is supplied.

8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

10. a first capacitance connected between the output line and the first input node; 10. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

11. a second capacitance connected between the buffer circuit and the second input node; 11. The photoelectric conversion device according to claim 1.

12. Each of the plurality of comparison circuits is configured to compare the pixel signal with the reference signal, the level of which changes over time, and output a comparison signal that indicates a different level when the difference between the pixel signal and the reference signal is smaller than a threshold value and when the difference is larger than a threshold value.

12. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

13. a plurality of pixels arranged in a plurality of columns; a plurality of comparison circuits provided corresponding to the plurality of columns, each having a first input node to which a pixel signal output from a pixel in the corresponding column is input via a first capacitance, and a second input node to which a reference signal is input via a second capacitance; a plurality of buffer circuits provided between a reference signal line to which the reference signal is supplied and each of the second input nodes of the plurality of comparison circuits; a switch circuit configured to be able to switch a connection state between output nodes of the plurality of buffer circuits; a control circuit for controlling the switch circuit, the comparison circuit is capable of performing an offset clamp operation to set an offset based on voltages input to the first input node and the second input node, The control circuit is configured to connect the output nodes of each of the plurality of buffer circuits during at least a portion of a period during which the offset clamp operation is being performed. A photoelectric conversion device characterized by:

14. The control circuit is configured to disconnect the output nodes of the plurality of buffer circuits after the offset clamp operation is completed.

14. The photoelectric conversion device according to claim 13.

15. a plurality of comparison circuits each including: a first input node provided corresponding to each of the plurality of columns and receiving a pixel signal output from a pixel of the corresponding column; a second input node provided corresponding to a reference signal; and a reset switch configured to reset a threshold voltage to a voltage corresponding to a potential difference between the first input node and the second input node; a plurality of buffer circuits provided between a reference signal line to which the reference signal is supplied and each of the second input nodes of the plurality of comparison circuits; and a switch circuit configured to be able to switch a connection state between each of the output nodes of the plurality of buffer circuits, turning on the switch circuit to connect the output nodes of the plurality of buffer circuits; The switch circuit is turned on during at least a part of the period during which the reset switch is turned on. A method for driving a photoelectric conversion device.

16. During the period in which the switch circuit is on, the reset switch is turned on.

16. The method for driving a photoelectric conversion device according to claim 15.

17. The photoelectric conversion device according to any one of claims 1 to 14, a signal processing device that processes a signal output from the photoelectric conversion device; An imaging system comprising:

18. A mobile object, The photoelectric conversion device according to any one of claims 1 to 14, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

19. The photoelectric conversion device according to any one of claims 1 to 14, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

Images