Photoelectric conversion devices and equipment

Abstract

To reduce noise or power consumption in reading signals from pixels.SOLUTION: A photoelectric conversion device comprises: pixels that each include a photoelectric conversion part accumulating electric charges according to incident light, generate photoelectric conversion signals according to the accumulated electric charges, and output the generated photoelectric conversion signals; sample and hold units that each sample and hold a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; and over-sampling type conversion units that each perform analog-digital (AD) conversion of the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample and hold unit. In processing from when the first photoelectric conversion signal and the second photoelectric conversion signal are generated until when the AD conversion of the first photoelectric conversion signal and the second photoelectric conversion signal is performed, a gain set in correspondence with the first photoelectric conversion signal and a gain set in correspondence with the second photoelectric conversion signal, are different from each other.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and equipment. [Background technology]

[0002] There is a solid-state imaging device that has a delta-sigma (ΔΣ) type AD conversion circuit, which is one of the oversampling type analog-to-digital (AD) conversion circuits. Patent Document 1 discloses a solid-state imaging device that can accommodate a wide input voltage range by providing two capacitance elements that store signals from pixels and outputting a weighted average of the voltages stored in the two capacitance elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO2019 / 069614 issue Summary of the Invention [Problem to be solved by the invention]

[0004] However, in photoelectric conversion devices having an oversampling AD conversion circuit, such as the ΔΣ AD conversion circuit shown in Patent Document 1, there is room for improvement in optimizing the AD conversion operation.

[0005] An object of the present invention is to provide a photoelectric conversion device that can reduce noise or power consumption when reading out a signal from a pixel. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a photoelectric conversion unit that accumulates charges in response to incident light is included, and a photoelectric conversion unit that accumulates charges in response to the accumulated charges is included. Lighta sample-and-hold unit that samples and holds a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; and an oversampling type conversion unit that performs analog-to-digital (AD) conversion on the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit, wherein the first photoelectric conversion signal and the second photoelectric conversion signal are Output from the pixel The present invention provides a photoelectric conversion device characterized in that, in the processing from when the first photoelectric conversion signal and the second photoelectric conversion signal are input to when they are AD converted, the gain set corresponding to the first photoelectric conversion signal is different from the gain set corresponding to the second photoelectric conversion signal. [Effects of the Invention]

[0007] According to the present invention, it is possible to reduce noise or power consumption when reading out a signal from a pixel. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 3] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 4] 1 is a driving timing chart illustrating a photoelectric conversion device according to a first embodiment; [Figure 5] 1 is a circuit diagram illustrating a reference photoelectric conversion device. [Figure 6] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a modification of the first embodiment. [Figure 7] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 8] 10 is a driving timing chart illustrating a photoelectric conversion device according to a second embodiment. [Figure 9] Schematic diagram illustrating a device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar components are given the same reference numerals, and redundant description will be omitted. Also, in the following embodiments, an imaging sensor will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging sensor and can be applied to other examples of photoelectric conversion devices. Examples include an imaging device, a range finder (a device for measuring distance using focus detection or TOF (Time Of Flight)), and a photometric device (a device for measuring the amount of incident light).

[0010] In this specification, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is acceptable as long as they are electrically connected.

[0012] First Embodiment A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG.

[0013] FIG. 1 is an example of a block diagram of a photoelectric conversion device according to this embodiment.

[0014] The photoelectric conversion device has a pixel substrate 1 and a circuit board 2 on which a circuit is mounted. A pixel section 5 is arranged on the pixel substrate 1. A plurality of pixels 10, each including a photoelectric conversion section that generates electric charges in response to incident light, are arranged in a matrix in the pixel section 5. Output from the plurality of pixels is output to the circuit board 2 via vertical signal lines 30. The circuit board 2 may be stacked on the pixel substrate 1, or the components arranged on the pixel substrate 1 and the circuit board 2 may be arranged on the same substrate. Note that the column direction here refers to the vertical direction in FIG. 1, and refers to the vertical direction in which the vertical signal lines 30 extend from the pixel substrate 1 to the circuit board 2. The row direction refers to the horizontal direction in FIG. 1, and is a direction perpendicular to the vertical signal lines 30.

[0015] The circuit board 2 is provided with a current source 40, a sample and hold unit 50, a conversion unit 60, a data processing unit 90, and an output unit 100. The current sources 40 are arranged corresponding to the respective vertical signal lines 30. The current sources 40 supply bias currents to the pixels 10 selected to read out pixel signals via the vertical signal lines 30. The vertical signal lines 30 transfer pixel signals corresponding to charges generated by the photoelectric conversion units of the pixels 10 from the pixels 10 to the sample and hold units 50.

[0016] The sample and hold unit 50 samples and holds pixel signals generated by each pixel 10 from the pixel unit 5 via the vertical signal lines 30. In this embodiment, the sample and hold unit 50 has two sample and hold circuits. The first sample and hold circuit samples and holds a pixel signal corresponding to a reset level when the photoelectric conversion unit is reset (hereinafter referred to as a reset level signal). The second sample and hold circuit samples and holds a pixel signal corresponding to an imaging signal obtained when the photoelectric conversion unit performs a photoelectric conversion operation (hereinafter referred to as a photoelectric conversion signal). The first sample and hold circuit and the second sample and hold circuit are provided on each of the vertical signal lines 30.

[0017] Each of the plurality of conversion units 60 includes an AD conversion circuit that performs AD conversion on the pixel signals output from the sample-and-hold unit 50. One of the plurality of conversion units 60 is connected to each of the plurality of vertical signal lines 30. Here, the AD conversion circuit may be, but is not limited to, a slope type AD conversion circuit, a successive approximation type AD conversion circuit, a ΔΣ type AD conversion circuit, or the like. In this embodiment, a configuration using an oversampling type AD conversion circuit will be described.

[0018] The data processing unit 90 processes the digital signal output from the conversion unit 60. The data processing unit 90 can perform digital processing such as correction processing and interpolation processing on the digital signal output from the conversion unit 60. The output unit 100 outputs the signal processed by the data processing unit 90 to the outside.

[0019] 2 is an example of a circuit diagram of a pixel 10 included in the photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0020] The pixel 10 includes a photoelectric conversion unit 400, a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. The photoelectric conversion unit 400 is, for example, a photodiode. One of the main electrodes of the photoelectric conversion unit 400 is connected to a reference voltage 450, and photoelectrically converts received light into charges (for example, photoelectrons) of an amount corresponding to the amount of light, and stores the converted charges.

[0021] The other of the main electrodes of the photoelectric conversion unit 400 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 410. A node 420 to which the gate electrode of the amplification transistor 430 is electrically connected functions as a floating diffusion (FD). The floating diffusion unit (FD unit) receives the charges generated in the photoelectric conversion unit 400 and functions as a charge-voltage converter that converts the input charges into a signal voltage. Hereinafter, the node 420 may also be referred to as the FD unit 420.

[0022] A transfer signal TX is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 becomes conductive in response to the transfer signal TX, the charge accumulated in the photoelectric conversion unit 400 is transferred to a node 420, which is an FD unit.

[0023] The reset transistor 455 is connected between a power supply voltage 460 and a node 420. When a transistor is said to be connected between A and B, it means that one of the main electrodes (source and drain) of the transistor is connected to A and the other of the main electrodes is connected to B. The gate electrode of the transistor is not connected to A or B.

[0024] A reset signal RES is supplied to the gate electrode of the reset transistor 455. When the reset transistor 455 becomes conductive in response to the reset signal RES, the charge held in the FD section 420 is swept out. Therefore, the voltage of the node 420 is reset to the power supply voltage 460. This reset operation resets the pixel.

[0025] The amplifier transistor 430 has a gate electrode connected to the node 420, one of its main electrodes connected to a power supply voltage 460, and the other of its main electrodes connected to the selection transistor 440. The gate electrode of the amplifier transistor 430 serves as the input of a source follower circuit that reads out a signal obtained by photoelectric conversion in the photoelectric conversion unit 400. The other of the main electrodes of the amplifier transistor 430 is connected to the vertical signal line 30 via the selection transistor 440. The amplifier transistor 430 and the current source 40 connected to the vertical signal line 30 form a source follower that converts the voltage of the node 420 into the voltage of the vertical signal line 30.

[0026] The selection transistor 440 is connected between the amplification transistor 430 and the vertical signal line 30. A selection signal SEL is supplied to the gate electrode of the selection transistor 440. The selection transistor 440 becomes conductive in response to the selection signal SEL, thereby selecting the pixel 10. In the selected state, a signal based on the voltage of the node 420 is output as a pixel signal to the vertical signal line 30 via the amplification transistor 430.

[0027] The circuit configuration of the pixel 10 is not limited to the configuration shown in FIG. 2 . For example, the selection transistor 440 may be connected between the power supply voltage 460 and the amplification transistor 430. Furthermore, when multiple vertical signal lines 30 are arranged in one pixel column, one pixel 10 may have multiple selection transistors 440 connected to different vertical signal lines 30. Furthermore, in the configuration shown in FIG. 2 , the pixel 10 has a so-called four-transistor (4Tr.) configuration, which includes a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. However, this is not limited to this. For example, a three-transistor configuration may be used in which the selection transistor 440 is omitted and the amplification transistor 430 also functions as a selection transistor by controlling the voltage of the node 420. Furthermore, a five-transistor or more configuration with an increased number of transistors may be used.

[0028] When the pixel 10 is given a control signal RES, the reset transistor 455 resets the voltage of the node 420. When the pixel is reset, the pixel can output a signal of a reset level corresponding to the reset level when the photoelectric conversion unit 400 is reset. Furthermore, the pixel can output a photoelectric conversion signal that can correspond to an imaging signal and that is generated by performing photoelectric conversion on light incident on the photoelectric conversion unit 400.

[0029] 3 is an example of a circuit diagram of the sample-and-hold unit 50 and the conversion unit 60 included in the photoelectric conversion device according to this embodiment. The sample-and-hold unit 50 and the conversion unit 60 are shown in FIG. 3, which are arranged corresponding to the vertical signal lines 30. In this embodiment, one sample-and-hold unit 50 and one conversion unit 60 are arranged for each vertical signal line 30.

[0030] The sample and hold unit 50 includes a first sample and hold circuit 210 and a second sample and hold circuit 211. As will be described later, the first sample and hold circuit 210 samples and holds a reset level signal output from a pixel when the photoelectric conversion unit 400 is reset. The second sample and hold circuit 211 samples and holds a photoelectric conversion signal generated in response to light incident on the photoelectric conversion unit.

[0031] The first sample-and-hold circuit 210 includes a capacitive element 120 and an inverting amplifier 220. The switch 110 controls the connection between the vertical signal line 30 and the capacitive element 120 in accordance with a control signal Smp_n. The inverting amplifier 220 can be configured by combining a common-source circuit and a source follower circuit. The inverting amplifier 220 includes transistors 130, 140, 150, 160, and 230, switches 170, 180, and 190, and a current source 200. The switch 170 is connected between the input and output of the common-source circuit configured by the transistors 130, 140, 150, and 160, and is controlled by a control signal Smpa_n. A reset-level signal is output via the inverting amplifier 220 in accordance with the control signal Hld_n.

[0032] The second sample and hold circuit 211 may have a configuration similar to that of the first sample and hold circuit 210, but differs from the first sample and hold circuit 210 mainly in that switches 112 and 192 and a capacitive element 122 are added. The second sample and hold circuit 211 includes capacitive elements 121 and 122 that hold pixel signals from the vertical signal line 30, and an inverting amplifier 221. The switches 111 and 112 control the connections between the vertical signal line 30 and the capacitive element 121 and the capacitive element 122, respectively, in accordance with control signals Smp_s1 and Smp_s2.

[0033] Similar to the inverting amplifier 220, the inverting amplifier 221 can be configured by combining a common-source circuit and a source follower circuit. The inverting amplifier 221 includes transistors 131, 141, 151, 161, and 231, switches 171, 181, 191, and 192, and a current source 201. The switch 171 is connected between the input and output of the common-source circuit configured by the transistors 131, 141, 151, and 161, and is controlled by a control signal Smpa_s. A photoelectric conversion signal is output via the inverting amplifier 221 in accordance with control signals Hld_s1 and Hld_s2.

[0034] A resistive element 240 is electrically connected between the output terminal of the first sample and hold circuit 210 and the output terminal of the second sample and hold circuit 211. Consider a case where the first sample and hold circuit 210 outputs a reset level signal and the second sample and hold circuit 211 outputs a photoelectric conversion signal. The voltage at the output terminal of the first sample and hold circuit 210, i.e., the voltage of the reset level signal, is set to Vn, and the voltage at the output terminal of the second sample and hold circuit 211, i.e., the voltage of the photoelectric conversion signal, is set to Vs. The resistance value of the resistive element 240 is set to R. As a result, the current I flowing through the resistive element 240 is expressed by the following (Equation 1). I=(Vn-Vs) / R (Equation 1)

[0035] This current I is input to the conversion unit 60. At this time, the current I flowing through the resistance element 240 is proportional to the difference between the voltage Vn of the reset level signal and the voltage Vs of the photoelectric conversion signal, as shown in Equation 1. Therefore, CDS (Correlated Double Sampling) is being performed at the stage when the current I is input to the conversion unit 60.

[0036] The conversion unit 60 is an oversampling AD conversion circuit, for example, a ΔΣ AD conversion circuit. The ΔΣ AD conversion circuit includes a first integrator, a second integrator, a quantizer 370, and a decimation filter 380. In the conversion unit 60, the first integrator includes an integral capacitor 320. The second integrator includes a voltage-to-current conversion circuit (Gm cell) 330 that converts voltage into current, and an integral capacitor 360. An AD converter 305 including a current source 300 and a switch 310 is connected to the input node of the first integrator.

[0037] AD converter 305 controls the current to the first integrator in response to the digital signal transmitted through the second integrator and quantizer 370. An input node of the second integrator is connected to AD converter 345, which includes a current source 340 and a switch 350. AD converter 345 controls the current to the second integrator in response to the result of quantizing the output of the second integrator by quantizer 370.

[0038] In the conversion unit 60, the quantizer 370 feeds back the previous quantized value to the second integrator and the first integrator via the AD converters 305 and 345. In this way, second-order noise shaping characteristics can be obtained by passing the previous quantized value through the integrators twice while feeding it back to the AD converters 305 and 345. Furthermore, high-frequency noise can be removed by the decimation filter 380 arranged after the quantizer 370, thereby obtaining a highly accurate AD conversion output.

[0039] FIG. 4 is an example of a drive timing chart showing the operation timing of the sample-and-hold unit 50 and the conversion unit 60 included in the photoelectric conversion device according to this embodiment. In FIG. 4, the horizontal axis represents time and the vertical axis represents voltage. The control signal RES is a signal that resets the pixel 10. The transfer signal TX controls the readout of signals from the photoelectric conversion unit 400. The control signals Smpa_n, Smp_n, Smpa_s, Smp_s1, Smp_s2, Hld_n, Hld_s, Hld_s1, and Hld_s2 control the switches of the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. In the following description, it is assumed that, in the waveforms of FIG. 4, when the control signal is at a high level (e.g., the state of the waveform of RES between times t1 and t2), the corresponding switch is in an on state, and when the control signal is at a low level, the corresponding switch is in an off state. Note that the on state of a switch refers to a state in which the input node and output node of the switch are in a conductive state. On the other hand, the off state of a switch refers to a state in which there is no conduction between the input node and the output node of the switch.

[0040] Between times t1 and t2, the control signal RES in FIG. 2 goes high, turning on the reset transistor 455 and resetting the FD unit 420. The control signal SEL shown in FIG. 2 is also controlled, and accordingly, the voltage of the vertical signal line 30 goes to the reset level voltage Vn. Also, at time t1, the control signals Smp_n and Smpa_n go high, turning on the switches 110 and 170 of the first sample-and-hold circuit 210. Next, at time t3 when the control signal Smpa_n transitions from high to low, the reset level voltage Vn is sampled and stored in the capacitive element 120. Next, at time t4, the control signal Smp_n transitions from high to low, turning off the switch 110, and disconnecting the capacitive element 120 from the vertical signal line 30.

[0041] Between times t5 and t6, the control signal TX in FIG. 2 goes high, turning on the transfer transistor 410. During this time, the charges generated in the photoelectric conversion unit 400 by the light incident between times t2 and t6 are transferred to the FD unit 420. In other words, the period from time t2 to time t6 is an exposure period. The voltage of the FD unit 420 decreases according to the amount of charge. In response to the control signal SEL, the voltage of the FD unit 420 is output to the vertical signal line 30 via the amplification transistor 430.

[0042] As a result, the voltage of the vertical signal line 30 becomes the voltage Vs1 of the first photoelectric conversion signal. Also, at time t5, the control signals Smp_s and Smpa_s1 become high level, and in the second sample-and-hold circuit 211 for photoelectric conversion signals, the switches 111 and 171 are turned on. Next, at time t7 when the control signal Smpa_s transitions from high level to low level, the switch 171 is turned off, and the voltage Vs1 of the first photoelectric conversion signal is sampled and stored in the capacitor 121. Next, at time t8, the control signal Smp_s1 transitions from high level to low level, the switch 111 is turned off, and the capacitor 121 is disconnected from the vertical signal line 30.

[0043] Note that when the switch 171 is turned off at time t7, the voltage across the switch 171 is always substantially the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off the switch 171, and no voltage that causes an error in the voltage Vs1 of the first photoelectric conversion signal stored in the capacitance element 121 is generated. Furthermore, when the switch 111 is turned off at time t8, both ends of the capacitance element 121 are in a high impedance state. Therefore, there is no effect due to the switch 111 being turned off. In this way, it is possible to suppress the generation of an error voltage in the voltage Vs1 of the first photoelectric conversion signal.

[0044] Between times t9 and t10, the control signal TX in FIG. 2 again goes high, turning on the transfer transistor 410. During this time, the charges generated in the photoelectric conversion unit 400 by the light incident between times t6 and t10 are additionally transferred to the FD unit 420. That is, in addition to the period from time t2 to t6, the period from time t6 to t10 is the exposure period. The voltage of the FD unit 420 further decreases according to the amount of charge. As a result, the voltage of the vertical signal line 30 decreases to the voltage Vs2 of the second photoelectric conversion signal. Also, at time t9, the control signals Smp_s and Smpa_s2 go high, turning on the switches 112 and 171 in the second sample-and-hold circuit 211 for photoelectric conversion signals.

[0045] Next, at time t11 when the control signal Smpa_s transitions from high level to low level, the voltage Vs2 of the second photoelectric conversion signal is sampled and stored in the capacitive element 122. Next, at time t12, the control signal Smp_s2 transitions from high level to low level, the switch 112 is turned off, and the capacitive element 122 is disconnected from the vertical signal line 30.

[0046] Note that when the switch 171 is turned off at time t11, the voltage across the switch 171 is always substantially the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off the switch 171, and no voltage is generated that causes an error in the voltage Vs2 of the second photoelectric conversion signal stored in the capacitance element 122. Furthermore, when the switch 112 is turned off at time t12, both ends of the capacitance element 122 are in a high impedance state. Therefore, there is no effect due to the switch 112 being turned off. In this way, it is possible to suppress the generation of an error voltage in the voltage Vs2 of the second photoelectric conversion signal.

[0047] At time t13, the control signal Hld_n goes high and the switches 180 and 190 turn on, causing the capacitive element 120 to output voltage Vn of a reset level signal in the first sample and hold circuit 210. At the same time, at time t13, the control signals Hld_s1 and Hld_s go high and the switches 181 and 191 turn on, causing the capacitive element 121 in the second sample and hold circuit 211 to output voltage Vs1 of the first photoelectric conversion signal.

[0048] As described above, the input current to the conversion unit 60 is a current corresponding to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample and hold circuit 210 and the voltage Vs1 of the first photoelectric conversion signal at the output terminal of the second sample and hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between the voltage Vn and the voltage Vs1.

[0049] At time t14, the control signal Hld_s1 goes low, turning off the switch 191. Thereafter, at time t15, the control signal Hld_s2 goes high, turning on the switch 192, causing the capacitive element 122 in the second sample-and-hold circuit 211 to output the voltage Vs2 of the second photoelectric conversion signal.

[0050] As described above, the input current to the conversion unit 60 is a current corresponding to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample and hold circuit 210 and the voltage Vs2 of the second photoelectric conversion signal at the output terminal of the second sample and hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between the voltage Vn and the voltage Vs2.

[0051] Then, at time t16, the control signal Hld_n goes low, turning off the switches 180 and 190. At the same time, the control signal Hld_s goes low, turning off the switch 181. At the same time, the control signal Hld_s2 goes low, turning off the switch 192.

[0052] Here, the first photoelectric conversion signal and the second photoelectric conversion signal are pixel signals corresponding to different accumulation times, and therefore are unlikely to have the same output amplitude except in dark conditions where no exposure is present. The exposure period (t2 to t10) during which charge corresponding to the second photoelectric conversion signal is accumulated is longer than the exposure period (t2 to t6) during which charge corresponding to the first photoelectric conversion signal is accumulated. Therefore, when there is no significant change in the amount of light incident on the photoelectric conversion unit 400, voltage Vs2 becomes a signal with a larger output amplitude than voltage Vs1. In other words, the first photoelectric conversion signal and the second photoelectric conversion signal have different output amplitude ranges. As such, this embodiment can read multiple photoelectric conversion signals (first photoelectric conversion signal and second photoelectric conversion signal) with different lengths of charge accumulation time, thereby obtaining signals with a wide dynamic range. Furthermore, high dynamic range images (HDR images) and high dynamic range videos (HDR videos) can be generated using signals with a wide dynamic range. The output amplitude here corresponds to the voltage difference from the reference voltage, which is the voltage of the signal output by the pixel 10 when the FD unit 420 is reset. Unless otherwise specified, the reference voltage for the output amplitude below can also be the signal output by the pixel 10 when the FD unit 420 is reset. Typically, this signal level is close to the voltage of the power supply voltage 460.

[0053] Furthermore, as described above, this embodiment suppresses the occurrence of error voltages in the first photoelectric conversion signal and the second photoelectric conversion signal, thereby suppressing quality degradation of signals with a wide dynamic range, and thus suppressing degradation of the image quality of HDR images and HDR videos generated using signals with a wide dynamic range.

[0054] The resistive element 240 electrically connected between the output terminal of the first sample-and-hold circuit 210 and the output terminal of the second sample-and-hold circuit 211 may be a variable resistive circuit. That is, the output amplitude level of the signal input to the conversion unit 60 may be adjusted according to the resistance value. In this case, the resistive element 240 functions as a gain setting unit. The resistance value of the resistive element 240 is changed between times t13 and t14 when the capacitive element 121 reads out the voltage Vs1 of the first photoelectric conversion signal and times t15 and t16 when the capacitive element 122 reads out the voltage Vs2 of the second photoelectric conversion signal. By changing the resistance value and changing the set gain, noise reduction or power reduction according to the output amplitude level can be achieved. This will be described below.

[0055] If the resistance value is relatively smaller from time t13 to t14 than from time t15 to t16, it is possible to reduce noise in the voltage Vs1 of the first photoelectric conversion signal by reducing thermal noise generated in the resistive element 240. On the other hand, if the resistance value is relatively larger from time t13 to t14 than from time t15 to t16, it is possible to reduce the output current to the conversion unit 60 and reduce power. In this way, the gain set corresponding to the first photoelectric conversion signal is larger than the gain set corresponding to the second photoelectric conversion signal, thereby achieving the above-mentioned effects.

[0056] In this embodiment, during the process from generation of the first photoelectric conversion signal and the second photoelectric conversion signal to AD conversion, the gain set corresponding to the first photoelectric conversion signal and the gain set corresponding to the second photoelectric conversion signal can be made different. In other words, multiple photoelectric conversion signals can be read out with different gains, thereby reducing noise or power consumption. Note that the gains may be made different by means other than varying the resistance of the resistor element 240. For example, the gains may be made different by varying the current value output from the current source 300. However, when the current value output from the current source 300 is switched, it takes a certain amount of time for the current value to settle after the current value is switched. Therefore, signal processing can be performed faster when the resistance of the resistor element 240 is switched than when the current value output from the current source 300 is switched.

[0057] In addition, in this embodiment, the capacitive element 121 and the capacitive element 122 share the second sample-and-hold circuit 211, making it possible to read out the first photoelectric conversion signal and the second photoelectric conversion signal without increasing the operating power.

[0058] Furthermore, in this embodiment, by reading out the first photoelectric conversion signal and the second photoelectric conversion signal using a common resistor element 240, level fluctuations due to temperature and process variations are easily linked. This makes it possible to suppress, for example, superposition of different variations in the first photoelectric conversion signal and the second photoelectric conversion signal, thereby suppressing quality degradation of signals with a high dynamic range. This also makes it possible to suppress degradation of the image quality of HDR images and HDR videos generated using signals with a high dynamic range.

[0059] Furthermore, in this embodiment, a resistive element 240 that sets a gain when the first photoelectric conversion signal and the second photoelectric conversion signal are read out is disposed after the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. With this configuration, even if the resistance value of the resistive element 240 is variable when the first photoelectric conversion signal and the second photoelectric conversion signal are read out, highly accurate CDS can be performed. This will be described below.

[0060] A reference example is shown in FIG. 5. The photoelectric conversion device shown in FIG. 5 includes a gain setting circuit 1000, a capacitor 1030 that stores a reset level signal, a capacitor 1040 that stores a first photoelectric conversion signal, and a capacitor 1050 that stores a second photoelectric conversion signal. The gain setting circuit 1000 includes an operational amplifier 1001, a resistor 1002, and a variable resistor 1003. A switch 1060 is electrically connected between the gain setting circuit 1000 and the capacitor 1030. When the switch 1060 is on, the signal output from the gain setting circuit 1000 is input to the capacitor 1030 via the switch 1060. A switch 1070 is electrically connected between the gain setting circuit 1000 and the capacitor 1040. When the switch 1070 is on, the signal output from the gain setting circuit 1000 is input to the capacitor 1040 via the switch 1070. Furthermore, a switch 1080 is electrically connected between the gain setting circuit 1000 and the capacitive element 1050, and when the switch 1080 is in an on state, a signal output from the gain setting circuit 1000 is input to the capacitive element 1050 via the switch 1080. That is, in the configuration of FIG. 5, the gain setting circuit 1000 is arranged in front of the capacitive elements 1030, 1040, and 1050, rather than in rear of them. Note that the capacitive elements 1030, 1040, and 1050 correspond to the capacitive elements 120, 121, and 122 shown in FIG. 3, respectively. Note that the switches 1060, 1070, and 1080 correspond to the switches 110, 111, and 112 shown in FIG. 3, respectively.

[0061] Consider the case where CDS is performed on the first and second photoelectric conversion signals read out using different gains in the configuration shown in FIG. 5 using a common reset level signal. In this case, because the gain setting circuit 1000 is located before the capacitive element 1030, it is not possible to change the gain corresponding to the reset level signal stored in the capacitive element 1030. Therefore, the gain corresponding to at least one of the first and second photoelectric conversion signals is different from the gain corresponding to the reset level signal. This reduces the accuracy of CDS using at least one of the first and second photoelectric conversion signals corresponding to a gain different from the gain corresponding to the reset level signal. For example, if the reset level signal and the first photoelectric conversion signal are read out using a first gain and the second photoelectric conversion signal is read out using a second gain, the accuracy of CDS for the second photoelectric conversion signal is reduced. This is due to the fact that different gains are applied to the pixel signal and the offset component of the operational amplifier 1001 when reading out the reset level signal and the second photoelectric conversion signal.

[0062] 3, consider a case where CDS is performed on a first photoelectric conversion signal and a second photoelectric conversion signal read out using different gains, using a common reset level signal. In this case, the resistive element 240 that sets the gain is disposed after the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211, so the gain corresponding to the reset level signal stored in the capacitive element 120 can be changed. Therefore, even if the gains corresponding to the first photoelectric conversion signal and the second photoelectric conversion signal are made different, the gain corresponding to the reset level signal can be set to the same gain as the gains corresponding to the first photoelectric conversion signal and the second photoelectric conversion signal. Therefore, even when CDS is performed on a first photoelectric conversion signal and a second photoelectric conversion signal read out using different gains, using a common reset level signal, CDS using the first photoelectric conversion signal and the second photoelectric conversion signal can be performed with high accuracy.

[0063] A photoelectric conversion device according to a modified example of the first embodiment of the present invention will be described with reference to Fig. 6. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0064] The modified example of the first embodiment differs from the first embodiment in the configuration of the pixel circuit. Fig. 6 is an example of a circuit diagram of a pixel 10 included in a photoelectric conversion device according to this modified example.

[0065] 6, the pixel 10 may have a transistor 456 (floating diffusion capacitance switching transistor 456 (FD capacitance switching transistor 456)) that switches the capacitance value of the FD section 420. During the readout period, for example, at time t9 in FIG. 4, the capacitance value of the FD 420 changes by switching the FD capacitance switching transistor 456 on and off using a signal FDINC. At this time, the FD capacitance switching transistor 456 functions as a gain change unit (gain setting unit) that changes the capacitance value of the FD section 420, and switches the capacitance value of the FD section 420 when outputting the first photoelectric conversion signal and the second photoelectric conversion signal.

[0066] Alternatively, another capacitive element may be connected to the FD unit 420 via a transistor, and the capacitance value may be changed by switching the transistor on and off. Pixel signals with different voltage conversion gains can be output to and held by the gain change unit in the capacitive elements 121 and 122. HDR images and HDR videos can then be acquired using the signals with different voltage gains.

[0067] Note that a relatively larger gain can be set for the high-gain pixel signal output by turning off the FD capacitance switching transistor 456 by further switching the resistance value of the resistor element 240. In this case, a signal with a wider dynamic range can be acquired. HDR images and HDR videos can then be generated using the signal with a wider dynamic range.

[0068] Second Embodiment A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 7 and 8. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0069] This embodiment differs from the first embodiment in that one pixel has multiple photoelectric conversion units. Fig. 7 is an example of a circuit diagram of a pixel 10 included in a photoelectric conversion device according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0070] 7, the pixel 10 further includes a photoelectric conversion unit 401 and a transfer transistor 411. The photoelectric conversion unit 401 is, for example, a photodiode. One of the main electrodes of the photoelectric conversion unit 401 is connected to a reference voltage 450, and photoelectrically converts received light into charges (for example, photoelectrons) of an amount corresponding to the amount of light, and stores the charges.

[0071] The other of the main electrodes of the photoelectric conversion unit 401 is electrically connected to the gate electrode of the amplification transistor 430 via the transfer transistor 411. A node 420 electrically connected to the gate electrode of the amplification transistor 430 functions as an FD. The FD unit functions as a charge-voltage converter that converts the charge generated in the photoelectric conversion unit 400 into a signal voltage. The pixel 10 is configured so that the FD unit 420 is shared between the photoelectric conversion unit 400 and the photoelectric conversion unit 401. If each pixel is considered to have two photoelectric conversion units lined up in the column direction and one FD unit, the pixel 10 in FIG. 7 corresponds to, for example, two pixels in which two of the pixels 10 in FIG. 2 are lined up in the column direction.

[0072] A transfer signal TXA is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 becomes conductive in response to the transfer signal TXA, the charge accumulated in the photoelectric conversion unit 400 is transferred to the FD unit 420. A transfer signal TXB is supplied to the gate electrode of the transfer transistor 411. When the transfer transistor 411 becomes conductive in response to the transfer signal TXB, the charge accumulated in the photoelectric conversion unit 401 is transferred to the FD unit 420.

[0073] In this embodiment, pixel signals output from the photoelectric conversion unit 400 are held in the capacitance element 121, and pixel signals output from the photoelectric conversion unit 401 are held in the capacitance element 122. With this configuration, it becomes possible to read out pixel signals for two rows during a unit readout period, thereby increasing the readout speed.

[0074] The circuit configuration of the pixel 10 is not limited to the configuration shown in FIG. 7 . For example, the selection transistor 440 may be connected between the power supply voltage 460 and the amplification transistor 430. Furthermore, when multiple vertical signal lines 30 are arranged in one pixel column, one pixel 10 may have multiple selection transistors 440 connected to different vertical signal lines 30. Furthermore, in the configuration shown in FIG. 2 , the pixel 10 has a so-called four-transistor (4Tr.) configuration, which includes a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. However, this is not limited to this. For example, a three-transistor configuration may be used in which the selection transistor 440 is omitted and the amplification transistor 430 also functions as a selection transistor by controlling the voltage of the node 420. Furthermore, a five-transistor or more configuration with an increased number of transistors may be used.

[0075] FIG. 8 is an example of a drive timing chart showing the operation timing of the sample-and-hold unit 50 and the conversion unit 60 included in the photoelectric conversion device according to this embodiment. In FIG. 8, the horizontal axis represents time and the vertical axis represents voltage. The control signal RES is a signal that resets the pixel 10. The transfer signal TXA controls the readout of a signal from the photoelectric conversion unit 400, and the transfer signal TXB controls the readout of a signal from the photoelectric conversion unit 401. The control signals Smpa_n, Smp_n, Smpa_s, Smp_s1, Smp_s2, Hld_n, Hld_s, Hld_s1, and Hld_s2 control the switches of the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. In the following description, it is assumed that, in the waveforms of FIG. 8, when the control signal is at a high level (e.g., the state of the waveform of RES between times t1 and t2), the corresponding switch is in an on state, and when the control signal is at a low level, the corresponding switch is in an off state. The on state of a switch means that the switch is in a conducting state, and the off state of a switch means that the switch is in a non-conducting state.

[0076] Between times t1 and t2, the control signal RES in FIG. 7 goes high, turning on the reset transistor 455 and resetting the FD unit 420. The control signal SEL shown in FIG. 7 is also controlled, and accordingly, the voltage of the vertical signal line 30 goes to the reset level voltage Vn. Also, at time t1, the control signals Smp_n and Smpa_n go high, turning on the switches 110 and 170 of the first sample-and-hold circuit 210. Next, at time t3 when the control signal Smpa_n transitions from high to low, the reset level voltage Vn is sampled and stored in the capacitive element 120. Next, at time t4, the control signal Smp_n transitions from high to low, turning off the switch 110, and disconnecting the capacitive element 120 from the vertical signal line 30.

[0077] Between times t5 and t6, the control signal TXA in FIG. 7 goes high, turning on the transfer transistor 410. During this time, the charges generated in the photoelectric conversion unit 400 by the light incident between times t2 and t6 are transferred to the FD unit 420. In other words, the period from time t2 to time t6 is an exposure period. The voltage of the FD unit 420 decreases according to the amount of charge. In response to the control signal SEL, the voltage of the FD unit 420 is output to the vertical signal line 30 via the amplification transistor 430.

[0078] As a result, the voltage of the vertical signal line 30 becomes the voltage Vs1 of the first photoelectric conversion signal. Also, at time t5, the control signals Smp_s and Smpa_s1 become high level, and in the second sample-and-hold circuit 211 for photoelectric conversion signals, the switches 111 and 171 are turned on. Next, at time t7 when the control signal Smpa_s transitions from high level to low level, the switch 171 is turned off, and the voltage Vs1 of the first photoelectric conversion signal is sampled and stored in the capacitor 121. Next, at time t8, the control signal Smp_s1 transitions from high level to low level, the switch 111 is turned off, and the capacitor 121 is disconnected from the vertical signal line 30.

[0079] Note that when the switch 171 is turned off at time t7, the voltage across the switch 171 is always substantially the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off the switch 171, and no voltage that causes an error in the voltage Vs1 of the first photoelectric conversion signal stored in the capacitance element 121 is generated. Furthermore, when the switch 111 is turned off at time t8, both ends of the capacitance element 121 are in a high impedance state. Therefore, there is no effect due to the switch 111 being turned off. In this way, it is possible to suppress the generation of an error voltage in the voltage Vs1 of the first photoelectric conversion signal.

[0080] Between times t9 and t10, the control signal TXB in FIG. 7 goes high, turning on the transfer transistor 411. During this time, the charges generated in the photoelectric conversion unit 401 by the light incident between times t2 and t10 are transferred to the FD unit 420. The voltage of the FD unit 420 further decreases according to the amount of charge. As a result, the voltage of the vertical signal line 30 decreases to the voltage Vs2 of the second photoelectric conversion signal. Also, at time t9, the control signals Smp_s and Smpa_s2 go high, turning on the switches 112 and 171 in the second sample-and-hold circuit 211 for photoelectric conversion signals.

[0081] Next, at time t11 when the control signal Smpa_s transitions from high level to low level, the voltage Vs2 of the second photoelectric conversion signal is sampled and stored in the capacitive element 122. Next, at time t12, the control signal Smp_s2 transitions from high level to low level, the switch 112 is turned off, and the capacitive element 122 is disconnected from the vertical signal line 30. That is, the voltage Vs2 of the second photoelectric conversion signal based on the charges generated in the photoelectric conversion units 400 and 401 is stored in the capacitive element 122.

[0082] Note that when the switch 171 is turned off at time t11, the voltage across the switch 171 is always substantially the same regardless of the voltage of the vertical signal line 30. Therefore, no charge injection occurs due to turning off the switch 171, and no voltage is generated that causes an error in the voltage Vs2 of the second photoelectric conversion signal stored in the capacitance element 122. Furthermore, when the switch 112 is turned off at time t12, both ends of the capacitance element 122 are in a high impedance state. Therefore, there is no effect due to the switch 112 being turned off. In this way, it is possible to suppress the generation of an error voltage in the voltage Vs2 of the second photoelectric conversion signal.

[0083] At time t13, the control signal Hld_n goes high and the switches 180 and 190 turn on, causing the capacitive element 120 to output voltage Vn of a reset level signal in the first sample and hold circuit 210. At the same time, at time t13, the control signals Hld_s1 and Hld_s go high and the switches 181 and 191 turn on, causing the capacitive element 121 in the second sample and hold circuit 211 to output voltage Vs1 of the first photoelectric conversion signal.

[0084] As described above, the input current to the conversion unit 60 is a current corresponding to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample and hold circuit 210 and the voltage Vs1 of the photoelectric conversion signal at the output terminal of the second sample and hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between the voltage Vn and the voltage Vs1.

[0085] At time t14, the control signal Hld_s1 goes low, turning off the switch 191. Thereafter, at time t15, the control signal Hld_s2 goes high, turning on the switch 192, causing the capacitive element 122 in the second sample-and-hold circuit 211 to output the voltage Vs2 of the second photoelectric conversion signal.

[0086] As described above, the input current to the conversion unit 60 corresponds to the difference between the voltage Vn of the reset level signal at the output terminal of the first sample and hold circuit 210 and the voltage Vs2 of the photoelectric conversion signal at the output terminal of the second sample and hold circuit 211. The conversion unit 60 performs AD conversion on the current corresponding to the difference between the voltage Vn and the voltage Vs2.

[0087] Then, at time t16, the control signal Hld_n goes low, turning off the switches 180 and 190. At the same time, the control signal Hld_s goes low, turning off the switch 181. At the same time, the control signal Hld_s2 goes low, turning off the switch 192.

[0088] Here, the first photoelectric conversion signal corresponds to the charge generated by the photoelectric conversion unit 400, and the second photoelectric conversion signal corresponds to the charge generated by the photoelectric conversion unit 400 and the photoelectric conversion unit 401. In other words, the first photoelectric conversion signal is output from one of the multiple photoelectric conversion units, and the second photoelectric conversion signal is output from the multiple photoelectric conversion units. After time t16, a digital signal corresponding to the charge generated by the photoelectric conversion unit 401 is obtained by calculating the difference between a digital signal corresponding to a current corresponding to the difference between voltages Vn and Vs1 and a digital signal corresponding to a current corresponding to the difference between voltages Vn and Vs2. Note that the first photoelectric conversion signal may correspond to the charge generated by the photoelectric conversion unit 400, and the second photoelectric conversion signal may correspond to the charge generated by the photoelectric conversion unit 401. In other words, the first photoelectric conversion signal may be output from one of the multiple photoelectric conversion units, and the second photoelectric conversion signal may be output from the other of the multiple photoelectric conversion units.

[0089] In this way, in this embodiment, pixel signals corresponding to two rows of pixels can be read out during a unit read period, thereby speeding up the read operation. Note that the pixel signals that can be read out during a unit read period may be pixel signals corresponding to multiple rows of pixels or pixel signals corresponding to multiple columns of pixels, depending on the pixel configuration.

[0090] Furthermore, as described above, this embodiment suppresses the occurrence of error voltages in the first photoelectric conversion signal and the second photoelectric conversion signal, thereby making it possible to suppress degradation of signal quality.

[0091] The resistive element 240 electrically connected between the output terminal of the first sample-and-hold circuit 210 and the output terminal of the second sample-and-hold circuit 211 may be a variable resistive circuit. That is, the output amplitude level of the signal input to the conversion unit 60 may be adjusted according to the resistance value. In this case, the resistive element 240 functions as a gain setting unit. The resistance value of the resistive element 240 is changed between times t13 and t14 when the capacitive element 121 reads out the voltage Vs1 of the first photoelectric conversion signal and times t15 and t16 when the capacitive element 122 reads out the voltage Vs2 of the second photoelectric conversion signal. As with the first embodiment, this embodiment is capable of reading out a plurality of photoelectric conversion signals with different gains, thereby reducing noise or power consumption.

[0092] Note that the gain may be varied by means other than varying the resistance value of the resistive element 240. For example, the gain may be varied by varying the current value output from the current source 300. However, when the current value output from the current source 300 is switched, it takes a certain amount of time for the current value to settle after the current value is switched. Therefore, signal processing can be performed faster when the resistance value of the resistive element 240 is switched than when the current value output from the current source 300 is switched.

[0093] In addition, in this embodiment, the capacitive element 121 and the capacitive element 122 share the second sample-and-hold circuit 211, making it possible to read out the first photoelectric conversion signal and the second photoelectric conversion signal without increasing the operating power.

[0094] Furthermore, in this embodiment, level fluctuations due to temperature and process variations are easily linked by reading out the first photoelectric conversion signal and the second photoelectric conversion signal using a common resistor element 240. This makes it possible to suppress, for example, superposition of different variations on both the first photoelectric conversion signal and the second photoelectric conversion signal, thereby suppressing degradation of signal quality.

[0095] Furthermore, in this embodiment, a resistive element 240 that sets a gain when the first photoelectric conversion signal and the second photoelectric conversion signal are read out is disposed after the first sample-and-hold circuit 210 and the second sample-and-hold circuit 211. With this configuration, even if the resistance value of the resistive element 240 is variable when the first photoelectric conversion signal and the second photoelectric conversion signal are read out, highly accurate CDS can be performed.

[0096] Note that one microlens may be provided for one pixel 10, i.e., the photoelectric conversion unit 400 and the photoelectric conversion unit 401. In this case, the photoelectric conversion unit 400 and the photoelectric conversion unit 401 may function as a pixel for phase difference detection. By having the photoelectric conversion unit 400 and the photoelectric conversion unit 401 function as a pixel for phase difference detection, focus detection of a subject can be performed. In this case, the first photoelectric conversion signal described above serves as an autofocus (AF) signal, and the second photoelectric conversion signal serves as an imaging signal. Note that even when the photoelectric conversion unit 400 and the photoelectric conversion unit 401 function as a pixel for phase difference detection, multiple photoelectric conversion signals can be read out with different gains. For example, by relatively increasing the gain corresponding to the first photoelectric conversion signal, AF accuracy can be improved. However, if the resistance value of the resistive element 240 is reduced to increase the gain, the current output to the conversion unit 60 may exceed the current value of the current source 300. Furthermore, if the current output to the conversion unit 60 exceeds the current value of the current source 300, the current output to the conversion unit 60 may exceed the range of current values ​​that can be AD converted. The output amplitude range of the second photoelectric conversion signal, which corresponds to two photoelectric conversion units, is generally larger than the output amplitude range of the first photoelectric conversion signal, which corresponds to one photoelectric conversion unit. Therefore, even if the current corresponding to the first photoelectric conversion signal using a certain gain does not exceed the range of current values ​​that can be AD converted, the current corresponding to the second photoelectric conversion signal using the same gain may exceed the range of current values ​​that can be AD converted. Therefore, by increasing the gain when reading out the first photoelectric conversion signal and decreasing the gain when reading out the second photoelectric conversion signal, AF accuracy can be improved while preventing the signal from deviating from the range of current values ​​that can be AD converted. Therefore, this embodiment allows multiple photoelectric conversion signals to be read out with different gains, thereby improving AF accuracy while preventing the signal from deviating from the range of current values ​​that can be AD converted.

[0097] 7, the photoelectric conversion units 400 and 401 may have different areas. A photoelectric conversion unit with a large area and a photoelectric conversion unit with a small area can hold different amounts of charge. That is, a photoelectric conversion unit with a large area and a photoelectric conversion unit with a small area generate different amounts of charge in response to light incident thereon during the same period. Therefore, the photoelectric conversion units 400 and 401 can output signals with different output amplitude ranges.

[0098] 7, the pixel 10 may further include an FD capacitance switching transistor 456, and pixel signals with different voltage conversion gains may be read out by switching the FD capacitance switching transistor 456 on and off during the pixel signal readout period. In this case, the photoelectric conversion unit 400 and the photoelectric conversion unit 401 may also output signals with different output amplitude ranges. This is due to, for example, the difference in threshold between the reset transistor 455 and the FD capacitance switching transistor 456. When the threshold of the reset transistor 455 is relatively high, the FD capacitance switching transistor 456 is on, and the pixel signal with a lower voltage conversion gain has a wider output amplitude range. This is because the voltage of the FD unit 420 can drop from the reset level to a lower level.

[0099] Third Embodiment The third embodiment is applicable to the first and second embodiments. FIG. 9(a) is a schematic diagram illustrating a device 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device (imaging device) of each of the above-described embodiments can be used as the semiconductor device 930. The device 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 may include a semiconductor device 910. The semiconductor device 930 may include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 may include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0100] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0101] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0102] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0103] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0104] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft, etc.). The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0105] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0106] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0107] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 9(b) and 9(c).

[0108] FIG. 9(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 80, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 80. For example, multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The photoelectric conversion units receive light beams that have passed through different positions of the pupil of the optical system, and the photoelectric conversion device 80 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. The parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. The distance information includes information about the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of this distance information to determine the possibility of a collision. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be implemented by dedicated hardware or a software module. Furthermore, it may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or may be realized by a combination of these.

[0109] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0110] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 9(c) shows the photoelectric conversion system 8 when capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0111] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the photoelectric conversion system 8 is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0112] As used herein, expressions such as "A or B," "at least one of A and B," "at least one of A or / and B," "one or more of A or / and B," and the like, include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, including cases containing at least one A, cases containing at least one B, and cases containing both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0113] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0114] The disclosure of this embodiment includes the following configurations.

[0115] (Configuration 1) A photoelectric conversion device comprising: a pixel including a photoelectric conversion unit that accumulates electric charges in response to incident light, generates a photoelectric conversion signal in response to the accumulated electric charges, and outputs the generated photoelectric conversion signal; a sample-and-hold unit that samples and holds a first photoelectric conversion signal and a second photoelectric conversion signal output from the pixel; and an oversampling type conversion unit that performs analog-to-digital (AD) conversion of the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit, wherein in the processing from when the first photoelectric conversion signal and the second photoelectric conversion signal are generated to when the first photoelectric conversion signal and the second photoelectric conversion signal are AD converted, a gain set corresponding to the first photoelectric conversion signal and a gain set corresponding to the second photoelectric conversion signal are different.

[0116] (Configuration 2) 2. The photoelectric conversion device according to configuration 1, wherein the first photoelectric conversion signal and the second photoelectric conversion signal have different output amplitude ranges.

[0117] (Configuration 3) The photoelectric conversion device according to configuration 1 or 2, characterized in that the first photoelectric conversion signal has a smaller output amplitude range than the second photoelectric conversion signal, and the first photoelectric conversion signal is set to have a larger gain than the second photoelectric conversion signal.

[0118] (Configuration 4) The photoelectric conversion device according to any one of configurations 1 to 3, characterized in that the time for which the photoelectric conversion unit accumulates the charge is different, and the time for which the charge corresponding to the first photoelectric conversion signal is accumulated is different from the time for which the charge corresponding to the second photoelectric conversion signal is accumulated.

[0119] (Configuration 5) The photoelectric conversion device according to any one of configurations 1 to 4, characterized in that the first photoelectric conversion signal has a shorter time for accumulating the charge than the second photoelectric conversion signal, and the first photoelectric conversion signal has a larger gain set than the second photoelectric conversion signal.

[0120] (Configuration 6) The photoelectric conversion device according to any one of configurations 1 to 5, wherein the conversion unit performs AD conversion on the differences between the first photoelectric conversion signal and the second photoelectric conversion signal and the reset level signal of the photoelectric conversion unit.

[0121] (Configuration 7) The photoelectric conversion device according to any one of configurations 1 to 6, characterized in that the sample-and-hold unit includes a first sample-and-hold circuit that samples and holds the reset level signal, and a second sample-and-hold circuit that samples and holds the first photoelectric conversion signal and the second photoelectric conversion signal, respectively.

[0122] (Configuration 8) 8. The photoelectric conversion device according to any one of configurations 1 to 7, wherein the first photoelectric conversion signal and the second photoelectric conversion signal are held in two capacitors included in the second sample-and-hold circuit, respectively.

[0123] (Configuration 9) The photoelectric conversion device according to any one of configurations 1 to 8, wherein the sample-and-hold unit includes an inverting amplifier, and the first photoelectric conversion signal and the second photoelectric conversion signal are output via the inverting amplifier.

[0124] (Configuration 10) The photoelectric conversion device according to any one of configurations 1 to 9, further comprising a gain setting unit that sets the gain, wherein the gain setting unit sets the gain corresponding to the first photoelectric conversion signal and the gain corresponding to the second photoelectric conversion signal, respectively.

[0125] (Configuration 11) 11. The photoelectric conversion device according to any one of configurations 1 to 10, wherein the gain setting section is electrically connected between output terminals of a plurality of sample-hold circuits included in the sample-hold section.

[0126] (Configuration 12) The photoelectric conversion device according to any one of configurations 1 to 11, characterized in that the gain setting unit includes a variable resistance circuit, and the gain corresponding to the first photoelectric conversion signal and the gain corresponding to the second photoelectric conversion signal are each set by changing the resistance value of the variable resistance circuit.

[0127] (Configuration 13) The photoelectric conversion device described in any one of configurations 1 to 12, characterized in that the pixel includes a floating diffusion portion to which the charge is input and a floating diffusion capacitance switching portion that switches the capacitance value of the floating diffusion portion, and the capacitance values ​​of the floating diffusion portion are switched when the pixel outputs the first photoelectric conversion signal and the second photoelectric conversion signal.

[0128] (Configuration 14) The photoelectric conversion device described in any one of configurations 1 to 13, characterized in that the pixel includes a plurality of photoelectric conversion units, a photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and a photoelectric conversion signal output from the other of the plurality of photoelectric conversion units is the second photoelectric conversion signal.

[0129] (Configuration 15) The photoelectric conversion device described in any one of configurations 1 to 14, characterized in that the pixel includes a plurality of photoelectric conversion units, a photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and a photoelectric conversion signal output from the plurality of photoelectric conversion units is the second photoelectric conversion signal.

[0130] (Configuration 16) 16. The photoelectric conversion device according to any one of configurations 1 to 15, wherein microlenses are arranged corresponding to the pixels, and the plurality of photoelectric conversion units are arranged corresponding to the microlenses.

[0131] (Configuration 17) 17. The photoelectric conversion device according to any one of configurations 1 to 16, wherein the plurality of photoelectric conversion units generate different amounts of electric charges in response to light incident thereon during the same period.

[0132] (Configuration 18) 18. The photoelectric conversion device according to any one of configurations 1 to 17, wherein the plurality of pixels are arranged in row and column directions, and the plurality of photoelectric conversion units are arranged in the column direction.

[0133] (Configuration 19) An apparatus comprising a photoelectric conversion device according to any one of configurations 1 to 18, further comprising at least one of an optical device that guides light to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. [Explanation of symbols]

[0134] 10 pixels 50 Sample and hold section 60 Conversion unit 400 Photoelectric conversion unit

Claims

1. a pixel including a photoelectric conversion unit that accumulates charges in response to incident light, and that outputs a plurality of photoelectric conversion signals and a reset level signal of the photoelectric conversion unit in response to the accumulated charges; a sample-and-hold unit that samples and holds the first photoelectric conversion signal and the second photoelectric conversion signal output from the pixel; an oversampling type conversion unit that performs analog-to-digital (AD) conversion on the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit; A photoelectric conversion device comprising: a first gain set corresponding to the first photoelectric conversion signal and a second gain set corresponding to the second photoelectric conversion signal are different in a process from when the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel until when the first photoelectric conversion signal and the second photoelectric conversion signal are AD converted; the reset level signal is set to the first gain and the second gain, The conversion unit performs AD conversion on a difference between the first photoelectric conversion signal and the signal at the reset level to which the first gain is set, and a difference between the second photoelectric conversion signal and the signal at the reset level to which the second gain is set. A photoelectric conversion device characterized by:

2. The photoelectric conversion device described in Claim 1, characterized in that the pixel outputs the reset level signal, the first photoelectric conversion signal, and the second photoelectric conversion signal in this order, and does not output the reset level signal during the period from when the output of the first photoelectric conversion signal ends to when the output of the second photoelectric conversion signal begins.

3. A pixel including a plurality of photoelectric conversion units that accumulate electric charges in response to incident light and microlenses arranged corresponding to the plurality of photoelectric conversion units, and outputting a photoelectric conversion signal in response to the accumulated electric charges; a sample-and-hold unit that samples and holds a first photoelectric conversion signal output from one of the plurality of photoelectric conversion units and a second photoelectric conversion signal output from the plurality of photoelectric conversion units; an oversampling type conversion unit that performs analog-to-digital (AD) conversion on the first photoelectric conversion signal and the second photoelectric conversion signal output from the sample-and-hold unit; A photoelectric conversion device comprising: In a process from when the first photoelectric conversion signal and the second photoelectric conversion signal are output from the pixel until the first photoelectric conversion signal and the second photoelectric conversion signal are AD converted, a first gain set corresponding to the first photoelectric conversion signal and a second gain set corresponding to the second photoelectric conversion signal are different. A photoelectric conversion device characterized by:

4. 4. The photoelectric conversion device according to claim 1, wherein the first photoelectric conversion signal and the second photoelectric conversion signal have different output amplitude ranges.

5. 5. The photoelectric conversion device according to claim 4, wherein the first photoelectric conversion signal has a smaller range of output amplitude than the second photoelectric conversion signal, and the first gain is larger than the second gain.

6. The photoelectric conversion device according to claim 1, characterized in that the time for which the photoelectric conversion unit accumulates the charge is different, and the time for accumulating the charge corresponding to the first photoelectric conversion signal is different from the time for accumulating the charge corresponding to the second photoelectric conversion signal.

7. 7. The photoelectric conversion device according to claim 6, wherein the first photoelectric conversion signal has a shorter time for accumulating the charges than the second photoelectric conversion signal, and the first gain is greater than the second gain.

8. 4. The photoelectric conversion device according to claim 3, wherein the conversion section performs AD conversion on the differences between the first photoelectric conversion signal and the second photoelectric conversion signal and the reset level signal of the photoelectric conversion section.

9. The photoelectric conversion device according to claim 1 or 8, characterized in that the sample-and-hold unit includes a first sample-and-hold circuit that samples and holds the reset level signal, and a second sample-and-hold circuit that samples and holds the first photoelectric conversion signal and the second photoelectric conversion signal, respectively.

10. 10. The photoelectric conversion device according to claim 9, wherein the first photoelectric conversion signal and the second photoelectric conversion signal are held in two capacitors included in the second sample-and-hold circuit, respectively.

11. The photoelectric conversion device according to claim 8, characterized in that the reset level signal includes a first reset level signal corresponding to the first photoelectric conversion signal and a second reset level signal corresponding to the second photoelectric conversion signal, and a gain set corresponding to the first reset level signal is different from a gain set corresponding to the second reset level signal.

12. 4. The photoelectric conversion device according to claim 1, wherein the sample-and-hold unit includes an inverting amplifier, and the first photoelectric conversion signal and the second photoelectric conversion signal are output via the inverting amplifier.

13. 4. The photoelectric conversion device according to claim 1, further comprising a gain setting unit that sets the first gain and the second gain, the gain setting unit setting the first gain and the second gain, respectively.

14. 14. The photoelectric conversion device according to claim 13, wherein the gain setting section is electrically connected between output terminals of a plurality of sample-hold circuits included in the sample-hold section.

15. 14. The photoelectric conversion device according to claim 13, wherein the gain setting section includes a variable resistance circuit, and the first gain and the second gain are each set by changing a resistance value of the variable resistance circuit.

16. The photoelectric conversion device according to claim 1 or 3, characterized in that the pixel includes a floating diffusion portion to which the charge is input and a floating diffusion capacitance switching portion that switches the capacitance value of the floating diffusion portion, and when the pixel outputs the first photoelectric conversion signal and the second photoelectric conversion signal, the capacitance values ​​of the floating diffusion portion are switched, respectively.

17. The photoelectric conversion device according to claim 1, characterized in that the pixel includes a plurality of photoelectric conversion units, a photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and a photoelectric conversion signal output from the other of the plurality of photoelectric conversion units is the second photoelectric conversion signal.

18. The photoelectric conversion device according to claim 1, characterized in that the pixel includes a plurality of photoelectric conversion units, a photoelectric conversion signal output from one of the plurality of photoelectric conversion units is the first photoelectric conversion signal, and a photoelectric conversion signal output from the plurality of photoelectric conversion units is the second photoelectric conversion signal.

19. 19. The photoelectric conversion device according to claim 17, wherein microlenses are arranged corresponding to the pixels, and the plurality of photoelectric conversion units are arranged corresponding to the microlenses.

20. 19. The photoelectric conversion device according to claim 3, 17 or 18, wherein the plurality of photoelectric conversion units generate different amounts of electric charges in response to light incident thereon during the same period.

21. 19. The photoelectric conversion device according to claim 3, 17 or 18, wherein the plurality of pixels are arranged in row and column directions, and the plurality of photoelectric conversion units are arranged in the column direction.

22. An apparatus comprising the photoelectric conversion device according to claim 1 or 3, an optical device that guides light to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

Images