Semiconductor device having an electrostatically bounded active area - Patent Application 20070122997

Abstract

A semiconductor device is provided having a substrate with a surface, a mesa disposed on the surface of the substrate, the mesa having a perimeter, and one or more gate electrodes. The mesa is obtained by selective area growth and has a semiconductor heterostructure for hosting a two-dimensional electron gas or a two-dimensional hole gas. The one or more gate electrodes are configured to electrically deplete a portion of the semiconductor heterostructure to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from the perimeter of the mesa. By using the selective area grown mesa to electrostatically define the boundary of the active region, improved electronic properties can be obtained, for example by avoiding diffuse scattering of charge carriers. Methods of manufacturing the device and the use of one or more gate electrodes to define an active region of a semiconductor component are also provided.

Description

[Background technology]

[0001] Topological quantum computing is based on the phenomenon that non-abelian anyons in the form of "Majorana zero modes" (MZMs) can form in regions where semiconductors are coupled to superconductors. Non-abelian anyons are a type of quasiparticle, meaning excitations in an electron liquid that are not strictly particles but behave at least partially like particles. MZMs are specific bound states of such quasiparticles.

[0002] Under certain conditions, MZMs can form near the interface between a semiconductor and a superconductor. For example, MZMs can be formed in devices with semiconductor nanowires coated with a superconductor. The nanowires have lengths many times greater than their diameters and can be considered one-dimensional systems. MZMs can also be formed in two-dimensional systems with a superconductor coupled to a quantum well hosting a two-dimensional electron gas, as described, for example, in Suominen et al., Phys. Rev. Lett. 119, 176805 (2017) and Nichele et al., Phys. Rev. Lett. 119, 136803 (2017).

[0003] When MZMs are induced in a structure, the structure is said to be in the "topological regime," which requires the cooling of the structure to a temperature that induces superconducting behavior in the superconductor material, along with a magnetic field, which is traditionally applied externally.

[0004] Topological devices are useful for creating quantum bits (qubits), which can be manipulated for the purposes of quantum computing. A quantum bit, also called a qubit, is an element on which a measurement can be performed that has two possible outcomes, but which at any given time (when not measured) can actually be in a quantum superposition of two states corresponding to those distinct outcomes.

[0005] To induce MZMs, the device is cooled to a temperature where the superconductor (e.g., aluminum) exhibits superconducting behavior. The superconductor induces a proximity effect in the adjacent semiconductor, which causes the region of the semiconductor near the interface with the superconductor to also exhibit superconducting properties, i.e., inducing topological phase behavior in the superconductor and the adjacent semiconductor. It is within this region of the semiconductor that MZMs form.

[0006] Another condition for inducing a topological phase in which MZM can occur is the application of a magnetic field to lift (or break) spin degeneracy in a semiconductor. Degeneracy, in the context of quantum systems, refers to when different quantum states have the same energy levels. Breaking degeneracy refers to forcing the states to adopt different energy levels. Spin degeneracy refers to when different spin states have the same energy levels. Spin degeneracy can be lifted by a magnetic field, resulting in energy level splitting between differently spin-polarized electrons. This is known as the Zeeman effect. Typically, the magnetic field is applied by an external electromagnet. Summary of the Invention

[0007] In one aspect, the present invention provides a semiconductor device comprising: a substrate having a surface; a mesa disposed on the surface of the substrate, the mesa having a periphery; and one or more gate electrodes, the mesa being obtained by selective area growth and including a semiconductor heterostructure for hosting a two-dimensional electron gas or a two-dimensional hole gas, the one or more gate electrodes being configured to electrically deplete a portion of the semiconductor heterostructure to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from the periphery of the mesa.

[0008] In another aspect, the present invention provides a method of fabricating a semiconductor device, the method comprising growing a mesa on a surface of a substrate by selective area growth, the mesa having a semiconductor heterostructure suitable for hosting a two-dimensional electron gas or a two-dimensional hole gas, and then fabricating one or more gate electrodes configured to, in use, electrically deplete a portion of the semiconductor heterostructure so as to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from the periphery of the mesa.

[0009] In a still further aspect, the present invention provides the use of one or more gate electrodes for defining an active area of ​​a semiconductor component by electrically depleting a boundary of said active area, said semiconductor component being obtained by selective area growth, said boundary being spaced from an edge of said semiconductor component.

[0010] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all of the disadvantages discussed herein. [Brief explanation of the drawings]

[0011] To assist in understanding embodiments of the present disclosure and to show how those embodiments may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which: [Figure 1] 1 is a schematic cross-sectional view of a first example of a semiconductor device. [Figure 2] FIG. 2 is a schematic plan view of a second example of a semiconductor device. [Figure 3a] FIG. 10 is a schematic plan view of a third example of a semiconductor device. [Figure 3b] FIG. 3b is a schematic cross-sectional view of the device of FIG. 3a. [Figure 4]FIG. 10 is a schematic plan view of a fourth example of a semiconductor device. [Figure 5] 1 is a scanning electron microscope (SEM) photograph of a semiconductor heterostructure on a substrate. [Figure 6] 6 is a transmission electron microscope (TEM) photograph taken along a portion of line AA in FIG. 5. [Figure 7] 1 is an elemental map showing the distribution of gallium in a semiconductor component having indium gallium arsenide. [Figure 8] 1 is a flowchart outlining a method for manufacturing a semiconductor device. [Figure 9] 1 is a flowchart outlining a method of operating a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0012] As used herein, the verb 'have' is used as shorthand for 'comprise or consist of.' In other words, although the verb 'have' is intended to be an open term, particularly when used in connection with chemical compositions, replacement of this term with the closed term 'consisting of' is expressly contemplated.

[0013] Directional terms such as "top," "bottom," "left," "right," "upper," "lower," "horizontal," and "vertical" are used herein for convenience of explanation, with the substrate at the "bottom" of the device. For the avoidance of doubt, this terminology is not intended to limit the orientation of the device in an external coordinate system.

[0014] The abbreviation "2DEG" stands for two-dimensional electron gas. "2DHG" stands for two-dimensional hole gas.

[0015] The term "superconductor" refers to a material with a critical temperature T c Refers to a material that becomes superconducting when cooled to a lower temperature. The use of this term is not intended to limit the temperature of the device.

[0016] A "semiconductor-superconductor hybrid structure" comprises a semiconductor component and a superconductor component that can be coupled together under certain operating conditions. In particular, the term refers to a structure capable of exhibiting topological behavior, such as Majorana zero modes, or other excitations useful in quantum computing applications. The operating conditions generally include cooling the structure below the critical temperature Tc of the superconductor component, applying a magnetic field to the structure, and applying electrostatic gating to the structure. Typically, at least a portion of the semiconductor component is in intimate contact with the superconductor component; for example, the superconductor component may be epitaxially grown on the semiconductor component. However, certain device structures have been proposed that have one or more additional components between the semiconductor component and the superconductor component.

[0017] A comparable technique for forming semiconductor heterostructures involves growing a stack of multiple semiconductor layers, each covering the entire surface of a substrate, and then etching the layers into the desired shape. The substrate may have a surface area of ​​several square centimeters. When using this comparative technique, a very good lattice match between adjacent material layers is essential to obtain a crystal of sufficient quality. In other words, the adjacent materials must have approximately the same lattice constants. This limits the combinations of materials that can be used.

[0018] Another limitation of this comparative technique when applied to hybrid device fabrication relates to faceting: generally, high-quality, flat semiconductor layers are grown on {001} crystal facets due to the favorable growth kinetics of faceting.

[0019] However, most high-quality superconductors are grown on {111} facets. For hybrid devices, it is desirable to grow high-quality semiconductors on {111} facets. In the case of selective area growth, the growth kinetics are quite different, allowing for the growth of high-quality semiconductors on {111} facets, which results in higher-quality hybrid devices.

[0020] Semiconductor devices are provided herein that are configured to allow the use of a wider range of material combinations and can be fabricated on a wider range of crystal planes while still having good electronic performance.

[0021] A first example semiconductor device 100 is shown in cross section in Figure 1. Example device 100 is a semiconductor-superconductor hybrid device. Example device 100 may be useful as a component of a topological qubit.

[0022] The example device includes semiconductor heterostructures 122, 124, and 126. The semiconductor heterostructures are in the form of mesas extending from the surface of the substrate 110.

[0023] The substrate 110 provides a base on which the semiconductor heterostructures 122, 124, 126 are grown. The substrate 110 typically comprises a wafer, i.e., a piece of single crystal material. One example of a wafer material is indium phosphide. Other examples of wafer materials include gallium arsenide, indium antimonide, indium arsenide, and silicon. The substrate may also be a more sophisticated workpiece having additional structures disposed on or over the wafer. The substrate may also comprise two or more layers of material.

[0024] The substrate can have a {111} crystal plane, and therefore the top surface of the mesa can also have a {111} crystal plane, which can be useful in implementations where superconductor components are formed on the mesa, because superconductors such as lead and aluminum grow best on {111} facets.

[0025] The semiconductor heterostructure has a bottom barrier 122 epitaxially disposed on the substrate 110, a quantum well 124 epitaxially disposed on the bottom barrier 122, and a top barrier layer 126 epitaxially disposed on the quantum well 124. This structure is called a heterostructure because the quantum well has a different material than the bottom and top barriers. The materials of the bottom and top barrier layers can each be selected independently.

[0026] The bottom barrier 122, the quantum well 124, and the top barrier 126 are each in the form of a layer. It is understood that overgrowth can occur at the edge of the mesa. For example, the top barrier 126 can wrap around the edge of the mesa.

[0027] The quantum well 124 may include a layer of semiconductor material with a relatively small bandgap compared to the materials of the lower barrier 122 and the upper barrier 126. Exemplary materials useful for forming quantum wells are described, for example, in Odoh and Njapba, “A Review of Semiconductor Quantum Well Devices,” Advances in Physics Theories and Applications, vol. 46, 2015, pp. 26-32, and in S. Kasap and P. Capper (eds.), “Springer Handbook of Electronic and Photonic Materials,” DOI 10.1007 / 978-3-319-48933-9_40.

[0028] The quantum well 124 is typically a few atomic layers thick. For example, the quantum well 124 may have a thickness in the range of 2 nm to 7 nm.

[0029] The configuration of the upper and lower barriers is not particularly limited as long as it allows the formation of a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) in the quantum well layer. The lower barrier may have one or more layers of one or more different materials. The upper barrier may have one or more layers of one or more different materials. Constructing the barriers from multiple layers can provide defect filtering, i.e., reduce the effects of dislocations in the crystal structure of the materials used.

[0030] In use, a 2DEG or 2DHG is formed within the quantum well layer 124, more specifically within the active region 124a, as will be described in more detail below. Excitations of interest, such as Majorana zero modes, can be induced within the 2DEG. The upper and lower barriers act as insulating components to localize charge within the quantum well 124.

[0031] The semiconductor heterostructures provided herein are fabricated by selective area growth. Selective area growth involves forming an amorphous mask on a substrate and then growing the semiconductor heterostructure within the openings in the mask. In other words, the amorphous mask is used to control the location where the semiconductor heterostructure is grown. The amorphous mask 112 typically remains in the completed device and surrounds the bottom of the mesa.

[0032] Efficient strain relaxation can occur during growth around the periphery of selective area grown structures, and therefore differences between the lattice constants of adjacent materials can be fully tolerated, resulting in a very wide range of combinations of different materials being used.

[0033] Strain relaxation is particularly efficient when the mesa has a relatively small width w. Typically, the mesa width w is 2 μm or less, and more preferably 1 μm or less.

[0034] It has been found that strain relaxation introduces inhomogeneities in the semiconductor material in areas close to the mesa edge. The stoichiometry of the semiconductor material may change. The thickness of the quantum wells may change. The inhomogeneities may degrade the charge transport properties of the material by causing diffuse scattering, for example, of electrons in the case of structures hosting a 2DEG, or of holes in the case of structures hosting a 2DHG. In areas away from the periphery, the material has good uniformity.

[0035] The effects of non-uniformities can be avoided by electrostatically defining the boundaries of the active region 124a rather than relying on material boundaries, which in this example are defined using gate stacks 140, 142 with superconductor components that shield the active region 124a from the electrostatic fields applied by the gate stacks.

[0036] The superconductor component 130 is disposed on the upper barrier layer 126. The edges of the superconductor component 130 are separated from the edges of the mesa by distances S1 and S2. The superconductor component can be configured to undergo energy level hybridization with the semiconductor material of the quantum well. In other words, the device can be a semiconductor-superconductor hybrid device. The upper barrier layer 126 can serve to adjust the strength of the interaction between the superconductor component 130 and the quantum well layer 124, as described in U.S. Patent Application Publication No. 2021 / 0126181.

[0037] The nature of the superconductor is not particularly limited and can be selected appropriately. The superconductor is typically an s-wave superconductor. Any of a variety of s-wave superconductors known in the art may be used. Examples include aluminum, indium, tin, and lead, with aluminum being preferred in some circumstances. In embodiments in which aluminum is used, the superconductor component may have a thickness in the range of, for example, 3 nm to 20 nm.

[0038] The gate stack is disposed on the mesa and includes a gate dielectric 140 and a gate electrode 142 disposed on the gate dielectric 140. The gate dielectric serves to prevent current flow between the gate electrode 142 and the superconductor component 130. The gate dielectric 140 also prevents current flow between the gate electrode 142 and the semiconductor heterostructures 122, 124, 126.

[0039] In operation, gate electrode 142 is used to apply an electrostatic field that electrically depletes regions 124b, 124c of quantum well layer 124, thereby defining the boundaries of active region 124a. Gate electrode 142 is sometimes referred to as the "depletion gate." Active region 124a is not depleted.

[0040] In this example, the superconductor component 130 shields the active region 124a from the electrostatic field. Alternatively, the gate electrode may be configured so that it does not extend over the active region 124a.

[0041] As will be appreciated, when the semiconductor heterostructure hosts a 2DEG, the voltage applied to the gate electrode 142 is a negative voltage, and when the semiconductor heterostructure hosts a 2DHG, the voltage applied to the gate electrode 142 is a positive voltage.

[0042] The active region 124a is effectively electrically isolated from the peripheral regions of the device by the depletion regions 124b, 124c. The material in the peripheral regions, which is less homogeneous than the material toward the center of the mesa, is therefore not used as the active part of the device. This can improve electrical performance, for example, by avoiding diffuse scattering of charge carriers.

[0043] The configuration of the depletion region is not particularly limited, so long as it separates the active region from the inhomogeneous material at the edge of the mesa. It has been found that the inhomogeneous region created by strain relaxation has a relatively small spatial extent. The spacing between the periphery of the mesa and the edge of the active region 124a can be, for example, at least 10 nm, optionally in the range of 10 nm to 200 nm, and further optionally in the range of 100 nm to 200 nm. The depletion region can extend to the periphery of the mesa, as shown by depletion region 124b. Alternatively, the depletion region can be between the active region 124a and the periphery of the mesa without necessarily extending all the way to the periphery, as shown by depletion region 124c.

[0044] A second example semiconductor device 200 will now be described with reference to Figure 2. Figure 2 shows a plan view of the device.

[0045] Similar to the device of FIG. 1, the device of FIG. 2 has a semiconductor heterostructure in the form of a selectively grown mesa disposed on a substrate. An example mesa is rectangular in plan view. The mesa is narrow, typically having a width of 2 μm or less, to allow for strain relaxation during growth of the mesa's crystalline layers. The length L of the mesa is not particularly limited and can be many times greater than its width w.

[0046] A superconductor component 230 is disposed on the top surface of the mesa. The superconductor component 230 includes a contact pad area at one end and an elongated portion extending along the length L of the mesa. The contact pads are for connecting the superconductor component to additional components, for example via wire bonds. The superconductor component may include two or more contact pads. For example, there may be contact pads on both ends of the superconductor component.

[0047] The device of Figure 2 differs from the device of Figure 1 with respect to the configuration of the gate electrodes: Device 200 includes multiple depletion gates 242a, 242b, 242c, and 242d.

[0048] The depletion gates include a first pair of gate electrodes 242a, 242b configured to define the boundaries of the first active region 224a. A second pair of gate electrodes 242c, 242d is configured to define the boundaries of the second active region 224b. These boundaries are defined by applying voltages to the gate electrodes to electrically deplete the quantum wells in the regions below the electrodes. The quantum well active region 224 underlies the superconductor component.

[0049] The devices provided herein may include any number of active regions, each defined by any number of gate electrodes, as desired.

[0050] In the illustrated example, the two active regions 224 are spaced apart. This spacing provides a junction between the active regions. Such a junction can serve various purposes. For example, an additional electrode can be provided to implant an electrode at the junction.

[0051] In this example, gate electrode 242 does not extend over superconductor component 230. This can allow, in some embodiments, a gate dielectric as shown in Figure 1 to be omitted, with the upper barrier of the semiconductor heterostructure acting to prevent current flow from the gate electrode to the active region of the quantum well. Because including a gate dielectric can more effectively prevent current flow between the gate electrode and the quantum well, a gate dielectric is typically present between gate electrode 242 and the upper barrier of the semiconductor heterostructure.

[0052] A third example device 300 is shown in plan view in Figure 3a and in cross section in Figure 3b. The devices of Figures 3a and 3b may be useful as spin qubit devices or components of high mobility field effect transistors.

[0053] 1 and 2, example device 300 includes a mesa disposed on a substrate 310 and having semiconductor heterostructures 322, 324, and 326. The mesa is as described above and has a narrow width w, e.g., a width of 2 μm or less. The mesa is selective area grown and is surrounded by a mask 312.

[0054] The device 300 further includes a plurality of depletion gate electrodes 342 disposed on the top surfaces of the mesas to define the boundaries of the active region of the device. An optional dielectric 340 is disposed between the depletion gates 342 and the upper barrier 326 of the semiconductor heterostructure.

[0055] At one end of the mesa, the device includes a pair of depletion gates 342a, 342b. A further pair of depletion gates 342c, 342d is located at the opposite end of the mesa. Depletion gates 342a, 342b, 342c, 342d are as described with reference to electrode 242 of the device in FIG. 2.

[0056] The device includes further depletion gates 342e-342n that, in use, deplete charge carriers from portions of the semiconductor heterostructure, thereby defining the perimeters of two active regions 324a, 324b. The perimeter of the first active region 324a is defined by electrodes 342e, 342f, 342g, 342j, 342k, and 324l. The perimeter of the second active region 324b is defined by electrodes 342g, 342h, 342i, 342l, 342m, and 342n. The active regions 324a, 324b are in the form of quantum dots.

[0057] 3b, the device in this example includes a further dielectric 370 disposed over the depletion gate and an additional electrode 372 disposed over the further dielectric 370. In this example, the additional electrode overlaps the depletion gate 342f and extends over the first active region 324a. Because the additional electrode 372 extends over the active region, the additional electrode 372 is useful for gating the active region. This illustrates that the devices provided herein can include additional electrodes in addition to the depletion gate.

[0058] To implement a spin qubit using a quantum dot, a magnetic field is required to break the spin degeneracy, and the device can include one or more ferromagnetic components to apply the magnetic field to the quantum dot.

[0059] For example, one or more of the gate electrodes that define the perimeter of the quantum dot can comprise a ferromagnetic material, such as cobalt, and in such an implementation, the one or more gate electrodes can act as the ferromagnetic component.

[0060] Alternatively, or in addition, the device may further include a ferromagnetic component that is not a gate electrode, as shown in Figure 4, which shows a schematic plan view of device 400. Device 400 differs from device 300 by including a dedicated ferromagnetic material and by using a differently positioned gate electrode to define each quantum dot.

[0061] Device 400 includes a semiconductor heterostructure as described above with reference to FIGS. 1-3.

[0062] The device 400 further includes a ferromagnetic material 460 having a shape selected to apply a magnetic field to the active quantum dot regions 424a, 424b of the device. The ferromagnetic material 460 in this example comprises a ferromagnetic metal, such as cobalt.

[0063] In devices containing multiple active regions, it may be useful to apply individually selected magnetic fields to individual active regions. For example, to implement a spin qubit, it may be necessary to apply a non-uniform magnetic field across two or more quantum dots. In this example, the portion of ferromagnetic material 460 aligned with the first quantum dot region 424a has a smaller width than the portion of ferromagnetic material 460 aligned with the second quantum dot region 424b. Thus, the two quantum dot regions experience different magnetic fields.

[0064] Gate electrodes 442a, 442b in the form of strips extend over portions of the ferromagnetic material 460. The gate electrodes 442a, 442b provide confinement of charge carriers in the width direction, i.e., they define the lateral boundaries of the quantum dots 424a, 424b. The gate electrodes 442a, 442b are separated from the ferromagnetic material 460 by a dielectric, which may be as described with reference to the dielectric 140 of the device of FIG.

[0065] Because the gate electrodes 442 a, 442 b extend over the ferromagnetic material, which in this example comprises a ferromagnetic metal, the ferromagnetic material 460 shields regions of the semiconductor component below the ferromagnetic material from the electrostatic field applied by the gate electrodes 442 a, 442 b. These shielded regions are the active regions of the device 400. The ferromagnetic material 460 also applies a magnetic field to the active region.

[0066] In an alternative implementation where the gate electrode does not extend over the active region, the ferromagnetic body may comprise a ferromagnetic insulator material.

[0067] The example device 400 further includes tunnel gates 470a, 470b, and 470c. A pair of the tunnel gates defines the longitudinal boundaries of the quantum dots 424a and 424b. The lateral boundaries of the first quantum dot 424a are defined by tunnel gates 470a and 470b. The lateral boundaries of the second quantum dot 424b are defined by tunnel gates 470b and 470c. The tunnel gates may also be useful for controlling the operation of the device.

[0068] In the illustrated example, tunnel gates 470a, 470b, and 470c overlap ferromagnet 460. In the overlap region, ferromagnet 460 has a relatively narrow width. The width of the ferromagnet in the overlap region is selected to allow partial depletion of charge carriers from the quantum well below the ferromagnet when an operating voltage is applied to the tunnel gate. Applying an operating voltage can suppress conductivity in these regions, thereby forming a tunnel barrier. In a variation, the tunnel barrier may be omitted. In such a variation, the ferromagnet may be located only over the active region of the device.

[0069] It is understood that example devices 300 and 400 do not include a superconductor component configured to undergo energy level hybridization with a quantum well of a semiconductor heterostructure. In other words, example devices 300 and 400 are not topological devices. This illustrates that the concepts provided herein may be applied to devices that are not necessarily semiconductor-superconductor hybrid devices.

[0070] Various modifications can be made to the illustrated device.

[0071] The shape of the gate electrode is not particularly limited, so long as the gate electrode is operable to define the boundaries of the active region of the semiconductor heterostructure. The gate electrode may include straight and / or curved portions in any desired configuration.

[0072] The number of depletion gates is not particularly limited. Any given active area can be defined by a single gate electrode or by multiple gate electrodes.

[0073] The device may include any number of additional electrodes to perform additional functions. The additional electrodes may be fabricated simultaneously with the depletion gate, i.e., located in the same layer as the depletion gate. The inclusion of such additional gates is optional.

[0074] Alternatively, or in addition, a dielectric may be provided over the depletion gate, and a further electrode may be disposed on the dielectric. In other words, the device may include a further layer of electrodes. In such implementations, the further electrode may overlap the depletion electrode and be separated from the depletion electrode by the dielectric.

[0075] If present, further electrodes may include, for example, electrodes for gating the active area of ​​the device.

[0076] The shape of the mesa is also not particularly limited. The illustrated mesa is rectangular in plan view, but other shapes are possible because selective area growth allows mesas of any shape to be fabricated. For example, the mesa may have a branched structure. Electrodes may be disposed on the branches. One such branched structure is shown in the scanning electron microscope image shown in Figure 5.

[0077] The width of a mesa may be defined as the length of the shortest line passing from a point on the periphery of the mesa through the active region to another point on the periphery of the mesa. The width is measured parallel to the surface of the substrate. In areas away from the active region, the mesa may have any shape.

[0078] The illustrated example shows the gate electrode located on top of the mesa; in other words, the device is top-gated. Another variation may be a side-gated device, with the gate stack located on the sidewall of the mesa. As will be appreciated, the depth to which the semiconductor is depleted varies depending on the gating voltage applied. The operating voltage of the gate electrode can be chosen to selectively deplete the edges of the quantum well layer. Bottom-gated devices are also contemplated.

[0079] The device may include any number of additional electrodes, which may provide a variety of functions. Examples of additional electrodes include electrodes for selectively gating the active region, electrodes for injecting electrons into the active region, electrodes for receiving electrons from the active region, and electrodes for connecting one or more portions of the device to one or more additional devices. Such additional electrodes may be present in any suitable combination.

[0080] In particular, the active region may be configured to operate as the channel of a field effect transistor by providing a source electrode and a drain electrode at each end of the active region. One or more gate electrodes defining the boundary of the active region may be operable to gate the channel by varying a voltage applied to the gate electrode. The gate electrode may deplete the active region when operated with a voltage having a large amplitude. Alternatively, a separate gate electrode may be provided for gating the channel. In particular, a device of the type shown in FIG. 2 may be configured as a field effect transistor.

[0081] The devices provided herein can be incorporated into circuits and coupled to additional components, for example, a device can be in communication with an amplifier circuit to enable readout of a signal from the device.

[0082] In devices including a ferromagnet, the top barrier of the semiconductor heterostructure may prevent current flow between the quantum well and the ferromagnet 460. An optional additional dielectric may be disposed between the ferromagnet and the top barrier, such as silicon oxide SiO x , silicon nitride SiN x , aluminum oxide AlO x , and hafnium oxide HfO x The layer may have a material selected from:

[0083] In devices that include ferromagnetic components, the ferromagnetic components are not necessarily configured to shield the active region of the device from applied electrostatic fields. In such implementations, one or more gate electrodes do not extend over the active region. This is because the ferromagnetic material is, for example, EuS, EuO, GdN, Y3Fe5O 12 , Bi3Fe5O 12 , YFeO3, Fe2O3, Fe3O4, Sr2CrReO6, CrBr3 / CrI3, and YTiO3.

[0084] The example of Figure 4 includes a single ferromagnetic material. Devices including two or more ferromagnetic materials are also contemplated. For example, each active region may be associated with a respective individual ferromagnetic component.

[0085] One or more additional components may be disposed on the surface of the substrate. For example, the substrate may have one or more shadow walls disposed thereon. Shadow walls are useful for controlling material deposition during device fabrication. In particular, shadow walls may enable controlled deposition of metal components, such as superconductor components and electrodes. This allows metal components of controlled shapes to be fabricated without the use of etching. Avoiding etching can help avoid damage to semiconductor portions of the device and / or allow for better interfaces between components. Shadow walls and their uses are described in detail, for example, in U.S. Patent Application Publication No. 2020 / 0243742.

[0086] The nature of the semiconductor heterostructure is not particularly limited. One illustrative example will now be described with reference to Figure 6, which is a transmission electron microscope (TEM) micrograph taken along a portion of line AA in Figure 5.

[0087] The heterostructure is disposed on a substrate 610, which in this example comprises indium phosphide. A bottom barrier 622 in the form of a layer of indium gallium arsenide is disposed on the substrate. Disposed on the bottom barrier are a quantum well, which comprises a layer of indium arsenide, and a top barrier, which also comprises a layer of indium gallium arsenide. The quantum well and top barrier together are labeled 628. The top barrier is covered by a layer of native oxide, which is visible as dark stripes in the TEM micrograph. The native oxide layer of the top barrier is hafnium oxide, HfO, in this example. x The dielectric layer 640 has a thickness of 100 Å.

[0088] The approximate thicknesses of the bottom barrier, quantum well, and top barrier are 35 nm, 2 nm, and 7 nm, respectively.

[0089] It will be appreciated that the layer thicknesses can be chosen appropriately and that many other combinations of materials are possible.

[0090] The heterostructure may comprise III-V semiconductor materials, which may be compounds or alloys each containing at least one group III element selected from indium, aluminum, and gallium, and at least one group V element selected from arsenic, phosphorus, and antimony. The heterostructure materials may, for example, each independently be represented by Formula 1: Al x In y Ga z As where the values ​​of x, y, and z are independently selected and range from 0 to 1. x, y, and z may sum to 1. Examples of particularly useful materials include indium arsenide, aluminum indium arsenide, indium gallium arsenide, aluminum gallium arsenide, and aluminum indium gallium arsenide. As will be appreciated, the electronic properties of the materials in the heterostructure can be controlled by varying their composition and stoichiometry. Typically, when the heterostructure comprises a material of Formula 1, the heterostructure hosts a 2DEG.

[0091] The use of other classes of semiconductor materials is also contemplated. For example, the heterostructure may comprise a II-VI semiconductor material. Examples of II-VI semiconductor materials include cadmium telluride, mercury telluride, lead telluride, and tin telluride. The heterostructure may comprise a Group IV semiconductor material. For example, the heterostructure may comprise silicon, germanium, and / or a silicon-germanium alloy. A heterostructure comprising a Group IV semiconductor material may host a 2DHG.

[0092] Figure 7 is an elemental map showing the distribution of gallium in an example of a selective area grown semiconductor heterostructure. The brightness at a given location is proportional to the amount of gallium present at that location. As can be seen, the left and right regions of the heterostructure have relatively higher concentrations of gallium compared to the center of the device. This indicates that the distribution of elements in semiconductor components is non-uniform, and that the edges of the device may have a different composition than the center of the device.

[0093] An example of a method for manufacturing a semiconductor device will now be described with reference to Figure 8. Figure 8 is a flow chart outlining the method.

[0094] At block 801, a mesa having a semiconductor heterostructure suitable for hosting a 2DEG is grown on the surface of a substrate by selective area growth.

[0095] The substrate may be as described above with reference to Figure 1. In particular, the substrate may be an indium phosphide wafer.

[0096] The surface of the substrate may be a {111} crystal plane, particularly in implementations where the device will include a superconductor component. Crystals of superconductor materials, such as aluminum, have been found to grow particularly well on {111} planes.

[0097] Selective area growth involves forming a mask on the surface of the substrate, the mask having openings that define the locations where the mesas will be grown. The mask may be formed by depositing a layer of masking material and then forming the openings by lithography and etching.

[0098] The mask may comprise any material that provides selectivity during growth, and in particular may comprise an amorphous dielectric material. An example of a dielectric material useful for forming the mask is silicon oxide SiO x , silicon nitride SiN x , aluminum oxide AlO x , and hafnium oxide HfO x Includes.

[0099] After forming the mask, a mesa is epitaxially grown on the surface of the substrate within the opening. Examples of techniques useful for growing semiconductor components include, for example, molecular beam epitaxy ("MBE"), metalorganic vapor phase epitaxy ("MOVPE"), etc. Because the mesa has a heterostructure, layers of different materials are built up sequentially. For example, growing the mesa may include growing a bottom barrier within the opening, growing a quantum well grown on the bottom barrier, and growing a top barrier on the quantum well.

[0100] The openings in the mask are configured to narrow the mesas, e.g., have a width of 2 μm or less, which allows for strain relaxation within the grown crystal.

[0101] Optionally, after growing the semiconductor heterostructure, a superconductor component may be formed on the semiconductor heterostructure, which may involve globally depositing a layer of superconductor material and then patterning the layer, for example using selective etching, to obtain the superconductor component.

[0102] Alternatively, shadow walls may be used to control the deposition of superconductor material, as described in U.S. Patent Application Publication No. 2020 / 0243742. In such implementations, the shadow walls may be formed prior to growing the mesa on the substrate.

[0103] Optionally, a gate dielectric is deposited over the semiconductor heterostructure. In implementations where a superconductor component is formed, this process may be performed after fabrication of the superconductor component.

[0104] After growing the semiconductor heterostructure, one or more gate electrodes are fabricated in block 802. Any suitable technique may be used to fabricate the gate electrodes.

[0105] For example, an electrode material can be globally deposited over the entire surface of the substrate and subsequently patterned to form the gate electrode. Patterning the electrode can include forming a mask over the electrode material and then selectively etching portions of the electrode material. Another possibility is to pattern the gate electrode using a lift-off process.

[0106] Another possibility is to selectively deposit electrode material onto desired portions of the substrate, which may be controlled by the use of shadow walls, as described, for example, in U.S. Patent Application Publication No. 2020 / 0243742.

[0107] The method may include further steps as required, for example, connecting one or more parts of the device to further components.

[0108] In implementations where the device includes a superconductor component that is not overlapped by a gate electrode, such as the device of FIG. 2, the gate electrode and the superconductor component may be fabricated at the same time and from the same material.

[0109] An example of a method of operating a semiconductor device is shown in Figure 9. The semiconductor device may be any semiconductor device described herein.

[0110] In block 901, a two-dimensional electron gas or two-dimensional hole gas is generated in a quantum well located in a selective area grown mesa.

[0111] At block 902, one or more gate electrodes are used to apply an electrostatic field to the quantum well to selectively deplete regions of the quantum well to define the boundaries of the active region of the quantum well, the active region being spaced from the periphery of the mesa.

[0112] It will be understood that the above embodiments have been described by way of example only.

[0113] More generally, according to one aspect disclosed herein, a semiconductor device is provided, the semiconductor device including a substrate having a surface, a mesa disposed on the surface of the substrate, the mesa having an outer periphery, and one or more gate electrodes. The mesa is obtained by selective area growth and includes a semiconductor heterostructure for hosting a two-dimensional electron gas or a two-dimensional hole gas. The one or more gate electrodes are configured to electrically deplete a portion of the semiconductor heterostructure to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from the outer periphery of the mesa. It has been found that the use of selective area grown mesas allows for strain relaxation toward the periphery of the mesa during growth, thereby enabling heterostructures to be obtained from a wider range of material combinations. Using electrostatic gating to define the boundary of the active region of the mesa, rather than relying on material boundaries, can improve the electrical characteristics of the device by excluding inhomogeneous material near the periphery of the mesa from the active region.

[0114] Depending on the choice of materials selected, the semiconductor heterostructure can be configured to host a two-dimensional electron gas or a two-dimensional hole gas.

[0115] At least one of the gate electrodes may be disposed on top of the mesa such that when the gate electrode applies an electrostatic field to the mesa, the region of the semiconductor heterostructure below the electrode is depleted.

[0116] At least one of the gate electrodes may be disposed on a side of the mesa, and by adjusting a voltage applied to the one or more gate electrodes, material within a selectable distance from the gate electrode may be electrically depleted.

[0117] The semiconductor heterostructure may have a quantum well disposed between a lower barrier and an upper barrier.

[0118] The mesa may have a width of 2 μm or less, optionally 1 μm or less. There is no particular lower limit to the mesa width, as long as the gate electrode can be fabricated with sufficient precision to define the boundaries of the active region. For example, the mesa may be at least 100 nm wide.

[0119] The boundary of the active region can be separated from the periphery of the mesa by at least 10 nm, and optionally by at least 25 nm. Strain relaxation during growth results in inhomogeneity in the composition of the material near the periphery of the mesa. The spatial extent of the inhomogeneous region is generally small. A spacing of 10 nm or more can be effective to exclude all inhomogeneous material from the active region.

[0120] The semiconductor device may further include a superconductor component disposed over the active region. In other words, the semiconductor device may be a semiconductor-superconductor hybrid device. Such hybrid devices may be useful as components of topological quantum computers.

[0121] The surface of the substrate can be a {111} crystallographic plane. The device can further include a superconductor component, which grows particularly well on a {111} crystallographic plane. Because the mesa is grown by selective area growth and because strain relaxation is possible, the mesa may be formed on a substrate with any desired crystallographic orientation.

[0122] In implementations in which the device includes a superconductor component, at least one of the one or more gate electrodes may extend over the superconductor component. The semiconductor device may further include a gate dielectric disposed between the one or more gate electrodes and the superconductor component. In such implementations, the superconductor component may shield the active region from electrostatic fields applied by the at least one gate electrode. In a variant, a ferromagnetic metal component replaces the superconductor component.

[0123] The active region may be in the form of a nanowire. In other words, the active region may be an elongated region having a nanoscale width and a length-to-width ratio of at least 10, at least 100, or at least 500, or at least 1000. Nanowires typically have widths in the range of 10-500 nm, optionally 50-100 nm, 40-200 nm, or 75-125 nm. Nanowires can be treated as one-dimensional systems and can exhibit interesting behavior.

[0124] Alternatively, the active region may be a quantum dot with boundaries defined by one or more gate electrodes. Quantum dots are useful in spin qubit devices.

[0125] The device may include multiple active regions, particularly in implementations where the active regions are quantum dots.

[0126] The device may include a ferromagnetic component that can apply a magnetic field to an active region of the device, particularly when the active region is a quantum dot.

[0127] At least one of the gate electrodes may be configured as a ferromagnetic component. In other words, at least one of the gate electrodes may have a ferromagnetic material. The ferromagnetic metal may be cobalt. By forming one or more gate electrodes from a ferromagnetic material, the gate electrodes apply a magnetic field to the active region in addition to electrostatically defining the boundary of the active region.

[0128] Additionally or alternatively, the device may include a ferromagnetic component that is not a gate electrode.

[0129] The ferromagnetic component may include a ferromagnetic insulator component, and in such implementations, the gate electrode typically does not overlap the ferromagnetic insulator component.

[0130] Alternatively, the ferromagnetic component may include a ferromagnetic metal disposed between at least one of the gate electrodes and the active region, the ferromagnetic metal being capable of shielding the active region from the electric field applied by the gate to define the quantum dots while simultaneously applying a magnetic field to the quantum dots.

[0131] In implementations in which the device includes two or more active regions, the ferromagnetic components can be configured to apply individually selected magnetic fields to individual ones of the active regions. There may be more than one ferromagnetic component, and each ferromagnetic component may be associated with a respective active region.

[0132] In another aspect, there is provided a qubit device comprising a plurality of semiconductor devices provided herein. The qubits may be topological qubits or spin qubits.

[0133] In yet a further aspect, there is provided a method of fabricating a semiconductor device, the method comprising growing a mesa on a surface of a substrate by selective area growth, the mesa having a semiconductor heterostructure suitable for hosting a two-dimensional electron gas or a two-dimensional hole gas, and then fabricating one or more gate electrodes configured to electrically deplete a portion of the semiconductor heterostructure so as to define, in use, a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from the periphery of the mesa.

[0134] Selective area growth involves forming a mask on the surface of the substrate and growing semiconductor material in the openings of the mask, the mask controlling the location(s) at which the semiconductor material is grown.

[0135] Growing the mesa may include growing a bottom barrier on the surface of the substrate, then growing a quantum well on the bottom barrier, and then growing a top barrier on the quantum well.

[0136] The mesa may have a width of 2 μm or less, optionally 1 μm or less, which may allow for more effective strain relaxation during growth of the semiconductor heterostructure.

[0137] The method may further include fabricating a superconductor component or a ferromagnetic body. The superconductor component or ferromagnetic body may be fabricated after growing the mesa and before fabricating the one or more gate electrodes. The method may further include fabricating a gate dielectric covering the superconductor component or the ferromagnetic body before fabricating the one or more gate electrodes. The one or more gate electrodes may be fabricated on the gate dielectric and on the superconductor component. In implementations where the ferromagnetic body is fabricated before fabricating the one or more gate electrodes and the one or more gate electrodes extend over the ferromagnetic body, the ferromagnetic body comprises a ferromagnetic metal.

[0138] The one or more gate electrodes may be fabricated from a ferromagnetic material, which may be cobalt.

[0139] A still further aspect provides the use of one or more gate electrodes to define an active region of a semiconductor heterostructure by electrically depleting the boundary of the active region, where the semiconductor heterostructure can be obtained by selective area growth, and the boundary is spaced from the edge of the semiconductor heterostructure. By electrostatically defining the active region rather than relying on a physical material boundary to define the active region, the electron transport properties of the active region can be improved. For example, diffuse scattering of charge carriers, e.g., electrons, can be avoided.

[0140] Such use may be in the context of a device as defined herein.

[0141] The semiconductor heterostructure may have a width of 2 μm or less, optionally 1 μm or less.

[0142] The one or more gate electrodes may comprise a ferromagnetic material, and in such implementations, the one or more gate electrodes may also be used to apply a magnetic field to the active region.

[0143] A related aspect provides a method of operating a semiconductor device, particularly a semiconductor device as defined herein. The method includes generating a two-dimensional electron gas or a two-dimensional hole gas in a quantum well disposed within a selectively grown mesa, and applying an electrostatic field to the quantum well to selectively deplete regions of the quantum well to define a boundary of an active region of the quantum well, the active region being spaced from the periphery of the mesa. By electrostatically defining the boundary of the active region, rather than relying on a material boundary at the physical edge of the quantum well, charge transport properties may be improved. For example, diffuse scattering of electrons or holes due to disorder near the material boundary may be avoided.

[0144] The mesa may be as described above. In particular, the mesa may have a width of 2 μm or less. Providing a narrow mesa allows for strain relaxation during mesa growth. Strain relaxation allows for a higher quality crystal structure to be obtained. Strain relaxation may allow a wider range of material combinations to be used. Without wishing to be bound by theory, it is believed that the narrow mesa may allow for strain relief through geometric deformation. In traditional planar structures, strain is usually relieved instead through defect creation. Defect creation significantly limits the amount of lattice mismatch that traditional systems can tolerate.

[0145] The method may further include applying a magnetic field to at least the active region of the device. In such implementations, the electrostatic field may be applied using a gate electrode comprising a ferromagnetic material. Thus, the gate electrode can apply both the electrostatic field and the magnetic field.

[0146] The semiconductor device may include a superconductor component, and in such implementations, the semiconductor device is operated at a temperature below the critical temperature of the superconductor component.

[0147] Given the disclosure herein, other variations or use cases of the disclosed technologies may become apparent to one of ordinary skill in the art. The scope of the present disclosure is not limited by the described embodiments, but rather only by the appended claims.

Claims

1. a substrate having a surface; a mesa disposed on the surface of the substrate, the mesa having a periphery; one or more gate electrodes; and the mesa is obtained by selective area growth and comprises a semiconductor heterostructure for hosting a two-dimensional electron gas or a two-dimensional hole gas; the one or more gate electrodes are configured to electrically deplete a portion of the semiconductor heterostructure to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from at least two opposite edges of the periphery of the mesa; Semiconductor devices.

2. 2. The semiconductor device of claim 1, wherein at least one of the one or more gate electrodes is disposed on a top surface of the mesa and / or at least one of the one or more gate electrodes is disposed on a side surface of the mesa.

3. 3. The semiconductor device of claim 1, wherein the mesa has a width of 2 [mu]m or less.

4. 4. The semiconductor device of claim 1, wherein the boundary of the active region is spaced from the periphery of the mesa by 10 nm or more.

5. 5. The semiconductor device of claim 1, wherein the surface of the substrate is a {111} crystal plane.

6. 6. The semiconductor device of claim 1, further comprising a superconductor component disposed over the active region, wherein at least one of the one or more gate electrodes extends over the superconductor component, and wherein the semiconductor device further comprises a gate dielectric disposed between the one or more gate electrodes and the superconductor component.

7. 7. The semiconductor device of claim 1, wherein the active region is in the form of a nanowire or the active region is in the form of a quantum dot.

8. the semiconductor device includes a ferromagnetic component; i) at least one of the one or more gate electrodes is a ferromagnetic component and comprises a ferromagnetic metal; or ii) the ferromagnetic component comprises a ferromagnetic metal and is disposed between at least one of the gate electrodes and the active region; 8. The semiconductor device according to claim 1.

9. A quantum bit device comprising a plurality of semiconductor devices according to claim 1 .

10. 1. A method for manufacturing a semiconductor device, comprising: growing a mesa on a surface of a substrate by selective area growth, the mesa having a semiconductor heterostructure suitable for hosting a two-dimensional electron gas or a two-dimensional hole gas; Thereafter, fabricating one or more gate electrodes. Having that, the one or more gate electrodes are configured to electrically deplete a portion of the semiconductor heterostructure so as to define, in use, a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from at least two opposite edges of a periphery of the mesa; method.

11. The method of claim 10 , wherein the mesa has a width of 2 μm or less.

12. the method further comprises fabricating a superconductor component, the superconductor component being fabricated after growing the mesa and before fabricating the one or more gate electrodes, the method further comprising fabricating a gate dielectric overlying the superconductor component before fabricating the one or more gate electrodes; the one or more gate electrodes are fabricated on the gate dielectric and on the superconductor component; 12. The method according to claim 10 or 11.

13. 13. The method of any one of claims 10 to 12, wherein the method comprises manufacturing a ferromagnetic component, and at least one of the one or more gate electrodes is manufactured from a ferromagnetic metal.

14. 1. Use of one or more gate electrodes for defining an active region of a semiconductor component by electrically depleting the boundary of said active region, said semiconductor component being obtained by selective area growth, said boundary being spaced from at least two opposite edges of the periphery of said semiconductor component, said semiconductor component being a semiconductor heterostructure hosting a two-dimensional electron gas or a two-dimensional hole gas.

15. the semiconductor component has a width of 2 μm or less; and / or the one or more gate electrodes comprise a ferromagnetic material, and the one or more gate electrodes are further used to apply a magnetic field to the active region.

15. The use according to claim 14.

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