Wafers and Chips

Abstract

To provide a wafer and a chip.SOLUTION: A wafer 100 according to the present invention includes: a plurality of chips 110, at least one scribe line 120, a metal layer 130, and an inhibition member 140 made of a nonconductive material. The metal layer is provided on the scribe line and is extended to a chip located next to the scribe line. The inhibition member covers the scribe line and the chip next to the scribe line. The inhibition member includes a first removed part 141 and an inhibition part 142. The first removed part and the inhibition part are located above a second removed part 131 and a residual part 132 of the metal layer, respectively. During a scribing process, the scribe line, the first removed part and the second removed part are removed, and the inhibition part and the residual part are retained on each of the chips. During the scribing process, the inhibition member is used to prevent the residual part from being lifted up or to prevent formation of a metal burr.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a wafer and a chip, and more particularly to a wafer and a chip that prevent a situation in which a metal layer is peeled up or a metal burr is generated during a scribing process. [Background technology]

[0002] In the prior art, a conventional wafer 10 includes a plurality of chips 11, a plurality of scribe lines 12, and at least one metal layer 13. The scribe lines 12 are located between adjacent chips 11, and the metal layer 13 is disposed on the scribe lines 12 and extends to the chips 11 adjacent to the scribe lines 12. The metal layer 13 may be a test pad, markings, or circuitry (see FIGS. 1 to 3). Summary of the Invention [Problem to be solved by the invention]

[0003] In the scribing process, the wafer 10 is cut along the scribe lines 12 to separate the chips 11. The cut metal layer 13 leaves a residual portion 13a on the chip 11, and because the metal layer 13 is malleable, the residual portion 13a may curl up or metal burrs 13b may be formed.

[0004] As shown in Figure 3, when the leads 21 of the circuit board were joined to the respective bumps 14 of the chip 11, the leads 21 came into contact with the curled-up residual portions 13a and metal burrs 13b, causing short circuits and electrical abnormalities in the chip 11 and the circuit board.

[0005] Therefore, the present inventors believed that the above drawbacks could be improved, and as a result of extensive research, they came up with the proposal of the present invention, which effectively improves the above problems through rational design.

[0006] The present invention has been made in view of the above, and its object is to provide a wafer and a chip, in which a suppressing member covers the scribe line and the chip near the scribe line, thereby enhancing the tensile strength of the metal layer located at the scribe line and extending to the chip, and preventing the remaining portion from curling up or the formation of metal burrs when the metal layer is cut. [Means for solving the problem]

[0007] To solve the above problems, one embodiment of the present invention provides a wafer comprising a plurality of chips, at least one scribe line, a metal layer, and a suppressing member. The scribe line is located between adjacent chips, and the metal layer is provided at the scribe line and extends to the chips near the scribe line. The suppressing member is formed of a non-conductive material and covers the scribe line and the chips near the scribe line. The suppressing member has a first removed portion and a suppressing portion, the first removed portion being located above a second removed portion of the metal layer, and the suppressing portion being located above a remaining portion of the metal layer. In a scribing process, the scribe line and the first removed portion and the second removed portion located at the scribe line are removed, and the suppressing portion and the remaining portion are retained on the chips. Each active surface of the chip has a bump placement area, and an axis extends from the bump placement area toward the suppression member, along the axis, the scribe line has a first width, the metal layer has a second width, and the suppression member has a third width, the first width being narrower than the second width, and the second width being narrower than the third width.

[0008] Another aspect of the present invention is a chip comprising a suppression portion and a remaining portion. The suppression portion is formed of a non-conductive material and is retained on the active surface of the chip after removing a first removed portion of the suppression member. The suppression portion has a first cross section and a first sidewall relative to the first cross section, and the first cross section is exposed on the sidewall of the chip. The remaining portion is retained on the chip after removing a second removed portion of the metal layer, and the suppression portion is located above the remaining portion. The remaining portion has a second cross section and a second sidewall relative to the second cross section, and the second cross section is exposed on the sidewall of the chip.

[0009] The suppressing member covers the scribe line and the chip near the scribe line to enhance the tensile strength of the metal layer and prevents the remaining portion from being lifted up by a cutting tool or metal burrs from being formed when the scribe line and the first and second removal portions located at the scribe line are removed. In addition, the suppressing portion retained on the chip supports the leads of the circuit board (not shown) bonded to the chip, preventing the leads from coming into contact with the first end of the suppressing portion and the second end of the remaining portion, which could cause a short circuit or electrical abnormality.

[0010] At least the following points will become clear from the description and drawings to be described later. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a conventional wafer. [Figure 2] FIG. 1 is a cross-sectional view showing a conventional wafer. [Figure 3] FIG. 1 is a cross-sectional view showing a conventional chip. [Figure 4] 1 is a plan view of a portion showing a wafer according to an embodiment of the present invention; [Figure 5] 1 is a cross-sectional view showing a wafer according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional view showing a wafer according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view showing a chip according to an embodiment of the present invention. [Figure 8] 1 is a cross-sectional view showing a chip according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. It should be noted that the present invention is not limited to the following embodiments and may take various forms as long as they fall within the technical scope of the present invention.

[0013] First, a wafer 100 according to the present invention will be described with reference to FIGS.

[0014] The wafer 100 includes a plurality of chips 110, at least one scribe line 120, a metal layer 130, and at least one constraining member 140. The constraining member 140 is formed of a non-conductive material, such as a polymeric material, although the present invention is not limited thereto. The scribe line 120 is located between adjacent chips 110. Each chip 110 includes a protective layer 111, at least one conductive pad 112, a seal ring 113, and at least one bump 114. The seal ring 113 surrounds the conductive pads 112. The active surface 110a of each chip 110 is the surface of the protective layer 111, which covers the seal ring 113 but not the conductive pads 112. Each active surface 110 a of the chip 110 has a bump placement area 110 b , conductive pads 112 are placed on the bump placement area 110 b , and bumps 114 are electrically connected to the conductive pads 112 .

[0015] In the examples of Figures 5 and 6, the metal layer 130 is disposed on the scribe line 120 and extends to the chip 110 near the scribe line 120, and the metal layer 130 is a test pad, a mark (see Figure 5), or a circuit (see Figure 6). The metal layer 130 has a second removed portion 131 and a remaining portion 132, with the second removed portion 131 located on the scribe line 120 and the remaining portion 132 located on the chip 110. The protective layer 111 covers the remaining portion 132. Referring to Figure 5, if the metal layer 130 is a test pad or a mark, the protective layer 111 does not cover the second removed portion 131. Referring to Figure 6, if the metal layer 130 is a circuit, the protective layer 111 covers the second removed portion 131.

[0016] 4 to 6, the suppressing member 140 covers the scribe line 120 and the chip 110 near the scribe line 120. As shown in FIG. 4, the wafer 100 preferably has a plurality of suppressing members 140, with openings 143 between adjacent suppressing members 140, and the openings 143 communicate with the bump mounting area 110b. The underfill (not shown) flows from the openings 143 into the bump mounting area 110b, sealing the bumps 114 and the leads (not shown) bonded to the bumps 114. The axis X extends from the bump mounting area 110b toward the suppressing member 140. When the metal layer 130 is a test pad or marking, the scribe line 120 has a first width W1, the metal layer 130 has a second width W2, and the suppression member 140 has a third width W3 along the axis X, where the first width W1 is narrower than the second width W2, and the second width W2 is narrower than the third width W3. Along a direction perpendicular to the axis X, the suppression member 140 has a length L, which is 60 μm or more, to strengthen the adhesive force of the suppression member 140 to the wafer 100.

[0017] 5 and 6 , the suppression member 140 has a first removed portion 141 and a suppression portion 142. The first removed portion 141 is located above the second removed portion 131 of the metal layer 130, and the suppression portion 142 is located above the remaining portion 132 of the metal layer 130. In the example of FIG. 5 , if the metal layer 130 is a test pad or marking, the first removed portion 141 covers the second removed portion 131. In the example of FIG. 6 , if the metal layer 130 is a circuit, the first removed portion 141 covers the protective layer 111, and the protective layer 111 covers the second removed portion 131. The suppression member 140 covers the protective layer 111, and the protective layer 111 is located between the suppression portion 142 and the remaining portion 132.

[0018] 5 and 6 again, the suppression portion 142 has a first height H1, and the protective layer 111 has a second height H2, where the first height H1 is greater than the second height H2, and the suppression portion 142 strengthens the flexural strength of the protective layer 111. The bump 114 protruding from the protective layer 111 has a third height H3, which is greater than or equal to the first height H1. Preferably, the third height H3 is greater than the first height H1, and the difference between the third height H3 and the first height H1 is 7 μm or less.

[0019] 5 and 6 again, the suppression portion 142 has a first side wall 142a adjacent to the seal ring 113, and the remaining portion 132 has a second side wall 132a adjacent to the seal ring 113. A first imaginary line S1 extends along the first side wall 142a, and a second imaginary line S2 extends along the second side wall 132a. A first distance D1 between the first imaginary line S1 and the second imaginary line S2 is 5 μm or more, and a second distance D2 between the seal ring 113 and the first imaginary line S1 is 1 μm or more.

[0020] 5 to 8. In the scribing process, a tool (not shown) cuts the wafer 100 along the scribe lines 120 to separate the chips 110, each of which has a sidewall 110c. In the example of FIGS. 7 and 8, in the scribing process, the tool removes the scribe lines 120 and the first removed portion 141 and the second removed portion 131 located at the scribe lines 120, leaving the suppression portion 142 and the remaining portion 132 in the chip 110. The suppression portion 142 covers the protective layer 111, and has a first cross section 142b exposed at the sidewall 110c, where the first cross section 142b is located opposite the first sidewall 142a of the suppression portion 142. The remaining portion 132 has a second cross section 132b exposed at the sidewall 110c, where the second cross section 132b is located opposite the second sidewall 132a of the remaining portion 132. The first cross section 142b, the second cross section 132b, and the sidewall 110c are aligned flat. Preferably, each of the chips 110 has a plurality of suppression portions 142, with openings 143 between adjacent suppression portions 142.

[0021] 7 and 8 . During the scribing process, the first removal portion 141 is removed, and the suppression portion 142 is retained on the active surface 110a of the chip 110, so that the length of the suppression portion 142 is the same as the length L of the suppression member 140. The suppression member 140 covers the scribe line 120 and the chip 110 near the scribe line 120, thereby strengthening the tensile strength of the metal layer 130 and preventing the remaining portion 132 from being peeled off by the tool or forming metal burrs. Because the suppression portion 142 is retained on the chip 110 and the first height H1 of the suppression portion 142 is less than the third height H3 of the bump 114, the suppression portion 142 can support the lead 210 of the circuit board (not shown) bonded to the bump 114, preventing the lead 210 from contacting the first cross section 142b of the suppression portion 142 and the second cross section 132b of the remaining portion 132, which could cause a short circuit or electrical abnormality.

[0022] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0023] 10 wafers 11 chips 12 Scribe line 13 Metal layer 13a Residual part 13b Metal burr 14 Bump 21 Lead 100 wafers 110 chips 110a active surface 110b Bump installation area 110c side wall 111 Protective layer 112 Conductive Pad 113 Seal ring 114 Bump 120 scribe lines 130 Metal layer 131 2nd removal section 132 Residual part 132a 2nd side wall 132b 2nd cross section 140 Restraining member 141 1st removal section 142 Suppression part 142a 1st side wall 142b 1st section 143 Opening D1 First distance D2 2nd distance S1 First virtual line S2 Second virtual line H1 First height H2 Second height H3 Third height L length W1 1st width W2 Second width W3 3rd width X-axis

Claims

1. Multiple chips and at least one scribe line located between adjacent chips; a metal layer disposed on the scribe line and extending to the chip in the vicinity of the scribe line; a restricting member made of a non-conductive material, the restricting member covering the scribe line and the chip in the vicinity of the scribe line, the restricting member having a first removal portion and a restricting portion, the first removal portion being located above a second removal portion of the metal layer, the restricting portion being located above a remaining portion of the metal layer, the scribe line, the first removal portion and the second removal portion located at the scribe line being removed in a scribing process, and the restricting portion and the remaining portion being retained on the chip; A wafer characterized in that each active surface of the chip has a bump installation area, an axis extends from the bump installation area toward the suppression member, and along the direction of the axis, the scribe line has a first width, the metal layer has a second width, and the suppression member has a third width, the first width being narrower than the second width, and the second width being narrower than the third width.

2. 2. The wafer of claim 1, wherein each of the chips has a protective layer, the protective layer covers the remaining portion and does not cover the second removed portion, the first removed portion covers the second removed portion, the suppression member covers the protective layer, the protective layer is located between the suppression portion and the remaining portion, the suppression portion has a first height, the protective layer has a second height, and the first height is higher than the second height.

3. 2. The wafer of claim 1, wherein each of the chips has at least one conductive pad and a seal ring, the seal ring surrounds the conductive pad, the suppression portion has a first sidewall adjacent to the seal ring, the remaining portion has a second sidewall adjacent to the seal ring, a first imaginary line extends along the first sidewall, a second imaginary line extends along the second sidewall, and a first distance between the first imaginary line and the second imaginary line is 5 μm or more.

4. 4. The wafer of claim 3, wherein the second distance between the seal ring and the first imaginary line is 1 [mu]m or more.

5. 3. The wafer of claim 2, wherein each of the chips further comprises at least one bump, the bump protruding into the protective layer having a third height, the third height being equal to or greater than the first height.

6. 6. The wafer according to claim 5, wherein the third height is higher than the first height, and the difference between the third height and the first height is 7 [mu]m or less.

7. 2. The wafer of claim 1, further comprising a plurality of suppression members, each of said suppression members having an opening between them, each of said active surfaces of said chips having a bump mounting area, said openings being in communication with said bump mounting area.

8. 2. The wafer according to claim 1, wherein the suppression member has a length along a direction perpendicular to the axis, the length being 60 [mu]m or more.

9. a suppression portion formed of a non-conductive material, the suppression portion being retained on the active surface of the chip after removing a first removal portion of the suppression member, the suppression portion having a first cross section and a first sidewall relative to the first cross section, the first cross section being exposed on the sidewall of the chip; A chip characterized by comprising: a residual portion retained on the chip after removing a second removed portion of the metal layer, wherein the suppression portion is located above the residual portion, the residual portion having a second cross section and a second sidewall relative to the second cross section, and the second cross section being exposed to the sidewall of the chip.

10. The chip described in claim 9, further comprising a protective layer covering the remaining portion, wherein the suppression portion covers the protective layer, the protective layer is located between the suppression portion and the remaining portion, the suppression portion has a first height, and the protective layer has a second height, and the first height is higher than the second height.

11. 10. The chip of claim 9, wherein a first imaginary line extends along the first sidewall, a second imaginary line extends along the second sidewall, and a first distance between the first imaginary line and the second imaginary line is 5 μm or more.

12. 10. The chip of claim 9, wherein the first cross section, the second cross section, and the sidewall are aligned flat.

13. 12. The chip of claim 11, further comprising at least one conductive pad and a seal ring, the seal ring surrounding the conductive pad, and a second distance between the seal ring and the first imaginary line being 1 μm or greater.

14. 11. The chip of claim 10, further comprising a bump, the bump protruding into the protective layer having a third height, the third height being equal to or greater than the first height.

15. 15. The chip according to claim 14, wherein the third height is greater than the first height, and the difference between the third height and the first height is 7 [mu]m or less.

16. 10. The chip of claim 9, further comprising a plurality of suppression portions, each having an opening between adjacent suppression portions, the active surface having a bump installation area, and the opening communicating with the bump installation area.

17. The chip according to claim 9 , wherein the suppression portion has a length, and the length is 60 μm or more.

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