Dual Contact and Power Rails for High Performance Standard Cells

Abstract

Standard cell layouts are disclosed that can be implemented in FinFET or nanosheet FET devices. The standard cell layouts include power connections from both top and bottom metal layers. Devices within the standard cells can be connected to both top and bottom metal layers. Various cell layouts can include control signal paths that go from a first device into the bottom layer and then under a second device. Various implementations of back and top side routing of bit and word lines in a memory array are also disclosed.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The embodiments described herein relate to semiconductor devices, and more particularly to layouts for making connections to transistors on a semiconductor substrate. [Background technology]

[0002] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logic functions, memory functions, etc. The current trend in standard cell methodology is to reduce the size of the standard cell while increasing the complexity (e.g., circuit density and number of components) within the standard cell. However, as standard cell designs become smaller, it becomes more difficult to provide access (e.g., connections) to the components within the standard cell.

[0003] Furthermore, the performance of a standard cell can become more affected by characteristics within the cell as the size of the standard cell decreases. For example, resistance within a standard cell, such as a metal trace or an interface between a diffusion region and a metal trace within the cell, can reduce the performance of the cell, and as cells become smaller, the impact on performance becomes more of an issue. Therefore, reducing the resistance within a standard cell can improve the performance of the cell. [Brief explanation of the drawings]

[0004] The features and advantages of the method and apparatus of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred, but nevertheless exemplary, embodiments in accordance with the embodiments described in this disclosure, taken in conjunction with the accompanying drawings.

[0005] [Figure 1] 1 illustrates a top view of one embodiment of a standard cell with topside connections.

[0006] [Figure 2] 2 illustrates a cross-sectional view of one embodiment of a standard cell along the cut line shown in FIG. 1.

[0007] [Figure 3] FIG. 1 illustrates a bottom view of one embodiment of a standard cell with backside power connections.

[0008] [Figure 4] 4 illustrates a cross-sectional view of one embodiment of a standard cell along the cut line shown in FIG. 3.

[0009] [Figure 5] 1 illustrates a bottom view of one embodiment of a standard cell having both topside and backside connections.

[0010] [Figure 6] 6 illustrates a cross-sectional view of one embodiment of a standard cell taken along section line 6-6 shown in FIG. 5.

[0011] [Figure 7] 7 illustrates a cross-sectional view of one embodiment of a standard cell taken along section line 7-7 shown in FIG. 5.

[0012] [Figure 8] 1 illustrates a cross-sectional view of one embodiment of a system having two standard cells with via programming.

[0013] [Figure 9] 1 illustrates a bottom view of one embodiment of a cell with both topside and backside power connections along with backside signal routing connections.

[0014] [Figure 10] 1 illustrates a bottom view of a layout according to some embodiments.

[0015] [Figure 11] 1 illustrates a top view of a layout according to some embodiments.

[0016] [Figure 11] 1 illustrates a top view of a layout according to some embodiments.

[0017] [Figure 12] 12 illustrates a cross-sectional view of one embodiment of a layout along section line 12-12 of FIGS. 10 and 11, according to some embodiments.

[0018] [Figure 13] 13 illustrates a cross-sectional view of one embodiment of a layout along section line 13-13 of FIGS. 10 and 11, according to some embodiments.

[0019] [Figure 14] 14 illustrates a cross-sectional view of one embodiment of a layout along section line 14-14 of FIGS. 10 and 11, according to some embodiments.

[0020] [Figure 15] 1 illustrates a top view of a memory array showing bit cells and bit lines according to some embodiments.

[0021] [Figure 16] 1 illustrates a top view of a memory array with single-ended bit lines in the bit cells according to some embodiments.

[0022] [Figure 17] 1 illustrates a top view of a memory array showing bit cells and word lines according to some embodiments.

[0023] [Figure 18] 1 illustrates a top view of a memory array having both bit lines and word lines in top and bottom metal layers according to some embodiments.

[0024] [Figure 19] 1 illustrates a top view of a large memory megacell that replaces two smaller memory megacells, according to some embodiments.

[0025] [Figure 20] 1 illustrates a top view of a tall memory megacell that replaces a wide memory megacell, according to some embodiments.

[0026] [Figure 21] 1 illustrates a top view of a memory array with hierarchical bit lines according to some embodiments.

[0027] [Figure 22] FIG. 1 is a block diagram of one embodiment of an exemplary system.

[0028] While the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, the present application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure, as defined by the appended claims. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present disclosure is directed to the use of backside metal layers to provide power and / or control signal connections to transistors in integrated circuit cells (such as standard cells). As used herein, the term "standard cell" refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. Integrated circuit cells may also include custom circuit design cells individually designed for specific implementations. Many current designs of cells provide connections and routing for power or signals to transistors (or other structures) above transistors. For example, connections and routing for power or signals may be provided in an upper layer of a device (e.g., a layer above the active layer of a transistor in a device when viewed in a typical cross-sectional view). As used herein, the term "topside" refers to a region within a device that is vertically above the active layer of the device (e.g., above the transistor region of the device). For example, the topside may refer to components such as contacts or layers that are above the transistor region in the vertical dimension, as shown in the figures and described herein. In some cases, the term "front side" may be used interchangeably with the term "upper side."

[0030] 1 shows a top view of one embodiment of a standard cell 100 with topside connections. For simplicity of illustration, the representation of the cell disclosed herein shows only components relevant to the present disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein.

[0031] In the illustrated embodiment of FIG. 1 , standard cell 100 includes gate 102, device 104, source / drain contacts 106, and metal layer 108. Gate 102 (e.g., gates 102A, 102B, 102C) may be a polyline (e.g., a polysilicon layer or a metal layer). In various embodiments, illustrations of gates in this disclosure include gate spacers 103. Device 104 may be a transistor, such as, for example, a FinFET device, a nanosheet FET (NSH) device, or a GAAFET ("gate-all-around" FET) device. Other embodiments of transistor devices may also be contemplated. In various embodiments, contacts 106 or vias 107 provide connections between device 104 and metal layer 108. Metal layer 108 may include one or more metal layers with contacts 106 and vias 107 providing various connections to different metal layers in embodiments having multiple metal layers. For example, contacts 106 can provide connections between regions within device 104 (e.g., source / drain regions within the device) and a first metal layer (e.g., a ground metal layer), and vias 107 provide connections between regions within the device and other, higher metal layers (e.g., layers above the first metal layer). In particular embodiments, metal layer 108 provides routing from device 104 to Vdd (e.g., a supply voltage) and Vss (e.g., ground). Metal layer 108 may also provide routing for connections to control signals to / from device 104, as described herein.

[0032] FIG. 2 shows a cross-sectional view of an embodiment of standard cell 100 along the cut line shown in FIG. 1 , according to some embodiments. In the illustrated embodiment, standard cell 100 includes a substrate 200 having an insulating layer 202 formed over gate 102. In some embodiments, gate 102B is an active gate, and gates 102A and 102C are isolation gates on either side of the active gate, as shown in FIG. 2 . In particular embodiments, substrate 200 is a silicon substrate, and insulating layer 202 is an oxide layer. In various embodiments, substrate 200 may include additional components or features for implementation in device 104. For example, substrate 200 may include an insulating layer, a diffusion (e.g., oxide diffusion) region, or a doped region for implementation in device 104.

[0033] For simplicity of illustration, the substrate 200 and the insulating layer 202 are shown as a single layer. In some embodiments, the insulating layer 202 comprises one or more insulating layers formed on a substrate. For example, the substrate 200 may be a silicon substrate with one or more oxide layers formed thereon. The insulating layer 202 may comprise a single insulating layer or multiple insulating layers. For example, the insulating layer 202 may comprise multiple oxide layers. In various embodiments, the insulating layer 202 at least partially surrounds or encapsulates regions of the device 104 (e.g., the gate 102, the source / drain regions 204, the contacts 106, etc.).

[0034] 2, the source / drain regions 204 of the device 104 are disposed above a substrate 200 in the standard cell 100. The source / drain regions 204 may be, for example, fins or nanosheet stacks in a FinFET or NSH device. Various embodiments may also be contemplated in which the source / drain regions 204 are within the substrate 200 or portions of the source / drain regions are within the substrate.

[0035] 2, contact 106, via 107, and metal layer 108 are in the upper layer of device 104 above source / drain region 204 and gate 102. In various embodiments, via 107 provides a signal connection to source / drain region 204A, and contact 106 provides a power signal connection to source / drain region 204B. For example, in the embodiment shown in FIGS. 1 and 2, contact 106B connects source / drain region 204B to Vdd via routing in metal layer 108 (note that contact 106B extends horizontally from device 104 to the portion of metal layer 108 that is coupled to Vdd, as shown in FIG. 1), and via 107 connects source / drain region 204A to signal routing in metal layer 108 (via contact 106A). Thus, metal layer 108 may include routing for both power and control signal connections. As shown in Figures 1 and 2, using contacts 106 and vias 107 to provide connections and routing for both power and control signals above device 104 may have an area cost above the device within standard cell 100.

[0036] Some contemplated embodiments for standard cell design move connections and routing for power connections to metal layers below the transistors. For example, connections and routing for power may be provided in a backside layer of the device (e.g., a layer below the active layer of the transistor in the device when viewed in a typical cross-sectional view). As used herein, the term "backside" refers to an area within a device that is vertically below the active layer of the device (e.g., below the transistor region of the device). For example, backside may refer to components such as contacts or layers that are below the transistor region in the vertical dimension, as shown in the figures and described herein. Note that, as used herein, backside elements disposed below the active layer may be located on, within, or below the silicon substrate in which the active layer is fabricated. That is, as used herein, "backside" refers to the active layer, not the silicon substrate.

[0037] FIG. 3 shows a bottom view of one embodiment of a standard cell 300 having backside layer power connections. In the illustrated embodiment of FIG. 3, the standard cell 300 includes a gate 302, a device 304, a backside via 306, and a backside metal layer 308. The gate 302 and the device 304 may be substantially similar to the gate 102 and the device 104 shown in FIG. 1. The via 306 provides a connection between the device 304 (e.g., a source / drain region within the device) and the backside metal layer 308. The backside metal layer 308 may include one or more metal layers that provide power routing from the device 304 to Vdd (e.g., a supply voltage) and Vss (e.g., ground).

[0038] FIG. 4 illustrates a cross-sectional view of an embodiment of a standard cell 300 along the cut line shown in FIG. 3 , according to some embodiments. In the illustrated embodiment, the standard cell 300 includes a substrate 200 having a gate 302, a gate spacer 303, and source / drain regions 404 formed within a device 304. As shown in FIG. 4 , the source / drain regions 404 of the device 304 are disposed above the substrate 200 and below the insulating layer 202 within the device. The source / drain regions 404 may be, for example, fins or nanosheet stacks in a FinFET, NSH, or GAAFET device. Power connection to the source / drain regions 404B is made by a backside via 306 from a backside metal layer 308. Thus, in the illustrated embodiment of FIG. 4 , the backside via 306 routes from the source / drain regions 404B to the backside metal layer 308, which replaces the power routing in metal layer 108 to provide power connection to the device 304.

[0039] As shown in FIG. 4 , backside via 306 and backside metal layer 308 are disposed below device 304 (e.g., within a backside layer of the device below source / drain regions 404). In particular embodiments, backside via 306 comprises a buried via through substrate 200 to connect between source / drain regions 404 and backside metal layer 308. In some embodiments, as shown in the illustrated embodiment, backside metal layer 308 is formed at or near the bottom surface of substrate 200. In particular embodiments, backside metal layer 308 is one or more backside layers of an active layer of device 304 (e.g., backside metal layer 308 is vertically below a transistor region of device 304). In some embodiments, backside metal layer 308 is one or more buried layers within substrate 200 (e.g., a metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, backside metal layer 308 is buried below a carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments may be contemplated in which the backside metal layer 308 is not disposed within the substrate 200 .

[0040] 3 and 4, moving the power connections to the source / drain regions 404 below the device 304 increases the available area above the device. Note that the contacts 106 and metal layer 108 are shown above the source / drain regions 404 in the device 304 in FIG. 4 because the upper metal layer may be utilized for other connections within the standard cell 300 (e.g., control signal connections). For example, in some embodiments, the power connection to the source / drain region 404B may be made using the backside via 306 and the backside metal layer 108, while the control signal connection to the source / drain region 404A is made using the contact 106A to the metal layer 308. In some embodiments, the space for the contact 106 above the source / drain region 404B may be left empty to increase the available area above the source / drain regions and the device 304. This empty area may be left empty or may be used for routing other resources (such as additional contacts for control signals or contacts for other signals).

[0041] 3 and 4 can improve area utilization within the cell layout, as discussed above. However, interfacial resistance within the cell (e.g., resistance at the interface between the source / drain regions 404 and the backside vias 306) can present a problem within the cell, especially as the size of the cell decreases. This disclosure recognizes that redundant power connections can be made above and below the device to reduce interfacial resistance in the standard cell layout.

[0042] Certain embodiments disclosed herein have three broad elements: 1) a transistor having a gate region, a source region, and a drain region, the transistor being disposed above the substrate in a vertical dimension perpendicular to the substrate; 2) a first metal layer disposed above the transistor in the vertical dimension (e.g., above the transistor); and 3) a second metal layer disposed below the transistor in the vertical dimension (e.g., behind the transistor). In some embodiments, one or more rails (such as a power rail) are connected to both the first metal layer and the second metal layer. For example, both a supply voltage rail and a ground rail may be connected to both the first metal layer and the second metal layer (the metal layers having separate routing for the supply voltage and ground). In certain embodiments, either the source region or the drain region of the transistor is connected to both the first metal layer and the second metal layer. Connecting the source / drain region to both the first metal layer and the second metal layer provides redundant connections between the source / drain region and the supply voltage rail, the ground rail, or both rails.

[0043] In a particular embodiment, the source region is connected to a supply voltage rail and the drain region is connected to a ground rail through both the first and second metal layers. For example, the source region is connected to supply voltage routing in both the first and second metal layers, with routing in both metal layers connecting to the supply voltage rail. Similarly, the drain region is connected to ground routing in both the first and second metal layers, with routing in both metal layers connecting to the ground rail.

[0044] In various embodiments, the rails connected to the first and second metal layers may be signal rails. For example, embodiments may be contemplated in which the rails provide bitcell signals. Providing redundant signal connections between source / drain regions and signal rails may allow signals to escape from devices with less resistance than a single connection. In some embodiments, source or drain regions from adjacent devices (e.g., adjacent transistors) may be selectively connected to the first or second metal layer. For example, via programming may be implemented in a multi-transistor layout to alternate connections from source / drain regions between the first and second metal layers in alternating transistors.

[0045] In summary, the inventors have recognized that providing connections to devices both above and below the device in a cell layout improves cell performance. By providing redundant connections above and below the device, interfacial resistance within the cell is reduced. For example, the interfacial resistance between a diffusion region and metal within the cell is reduced using redundant connections, thereby improving cell performance. The inventors have also recognized that while providing redundant connections above and below the device has an area cost for the connections above the device, the reduction in interfacial resistance within the cell still improves cell performance relative to cells having connections only below the device (as shown in FIGS. 3 and 4 ). Furthermore, the redundant connections can reduce interfacial resistance within the cell and improve cell performance without having to increase the size of the cell or provide extra power to the cell.

[0046] FIG. 5 shows a bottom view of one embodiment of a standard cell 500 having both topside and backside power connections. In the illustrated embodiment, the standard cell 500 includes a gate 502 and a device 504. The gate 502 and device 504 may be similar to other embodiments described herein. In a particular embodiment, the gate 502 is a polyline formed from a polysilicon or metal layer, and the device 504 is a transistor (e.g., a FinFET device or a nanosheet FET device). The standard cell 500 includes a topside (source / drain) contact 506, an topside via 507 to a topside metal layer 508, and a backside via 510 to a backside metal layer 512. Note that while the topside via 507 is shown in FIG. 5, the topside via is typically hidden by the topside contact 506 in the bottom view. In some embodiments, the top contact 506 provides a control signal connection between the device 504 and the top metal layer 508, and the top via 507 and backside via 510 provide a power connection from the device to the top metal layer 508 and backside metal layer 512, respectively.

[0047] In particular embodiments, power routing within top metal layer 508 and power routing within back metal layer 512 are coupled to rails 514 and 516. In the illustrated embodiment, rail 514 is a supply voltage rail, and rail 516 is a ground rail for the power supply coupled to the rail. Other embodiments in which rails 514 and 516 are coupled to different power supplies or carry different potentials may be contemplated. In various embodiments, top metal layer portion 508A and back metal layer portion 512A provide routing from device 504 to Vdd (e.g., a supply voltage). Similarly, top metal layer portion 508B and back metal layer portion 512B provide routing from device 504 to Vss (e.g., a ground voltage). It should be noted that rails 514 and 516 and the coupling to / from the rails are shown schematically in the illustrated embodiment, and that the actual implementation of the rails and the coupling to / from the rails may be done through various designs based on the desired functionality for standard cell 500. Additionally, although the top via 507 and the backside via 510 are shown in FIG. 5 as not overlapping vertically, various embodiments may be contemplated in which there is partial or complete overlap between the top and backside vias in the vertical direction.

[0048] As shown in FIG. 5 , device 504 is connected to rails 514 and 516 using both top metal layer 508 and backside metal layer 512. FIG. 6 shows a cross-sectional view of an embodiment of standard cell 500 along section line 6-6 shown in FIG. 5 . In the illustrated embodiment, standard cell 500 includes substrate 200 having gate 502, gate spacer 503, and source / drain region 604 formed thereon. Source / drain region 604 is the source / drain region of device 504. Source / drain region 604 may be, for example, a fin or nanosheet stack in a FinFET or NSH device. In a particular embodiment, top contact 506A couples to source / drain region 604A, and top contact 506B and top via 507 couple source / drain region 604B to top metal layer 508. In some embodiments, as described herein, upper contact 506B and upper via 507 connect source / drain region 604B to power routing in upper metal layer 508 (e.g., routing to rail 514 or rail 516), and upper contact 506A provides signal routing to source / drain region 604A (e.g., via connected control signal routing in upper metal layer 508). For example, in the embodiment shown in FIGS. 5 and 6, upper contact 506B and upper via 507 connect source / drain region 604B to upper metal layer portion 508A for routing to rail 514 and Vdd. As shown in FIG. 6, there is no connection (e.g., via or contact) between source / drain region 604 and backside metal layer 512 along the path of cut line 6-6 in FIG. 5.

[0049] FIG. 7 shows a cross-sectional view of an embodiment of standard cell 500 along section line 7-7 shown in FIG. 5. In the illustrated embodiment, backside via 510 and backside metal layer 512 are disposed below source / drain regions 604 of device 504 (e.g., within the backside layer of the device). In a particular embodiment, backside via 510 is a buried via through substrate 200 to connect source / drain regions 604B to backside metal layer 512. In various embodiments, as shown in FIG. 7 and described herein, backside metal layer 512 is formed at or near the bottom surface of substrate 200. In some embodiments, backside metal layer 512 is a buried layer within substrate 200 (e.g., a metal layer is buried or embedded below the bottom surface of the substrate). Additional embodiments may be contemplated in which backside metal layer 512 is not disposed within substrate 200.

[0050] In particular embodiments, backside via 510 connects source / drain region 604B to power routing within backside metal layer 512 (e.g., routing to rail 514 or rail 516). For example, in the embodiment shown in Figures 5 and 7, backside via 510 connects source / drain region 604B to backside metal layer portion 512A for routing to rail 514 and Vdd. As shown in Figure 7, there is no vertical connection (e.g., via) between source / drain regions 604A, 604B and upper metal layer 508 along the path of cut line 7-7 in Figure 5.

[0051] In various embodiments, as shown in FIGS. 5-7 , standard cell 500 includes power connections between device 504 and rails 514 and 516 using connections both above and below the device in the standard cell (e.g., both the top and bottom layers of the device). For example, rail 514 connects to source / drain region 604B through both top via 507 and top metal layer portion 508A and backside via 510 and backside metal layer portion 512A. Providing power connections both above and below device 504 may reduce interface resistance between diffusion regions (e.g., source / drain region 604B) and metal layers (e.g., top via 507 and backside via 510) in standard cell 500. For example, interface resistance is reduced by using connections to rails 514 and 516 from both above and below device 504 to increase the connection area between the diffusion regions and metal layers, reducing resistance in the path between the rails and the device. In some embodiments, the interface resistance in standard cell 500 is reduced to approximately half of the interface resistance in either standard cell 100 or standard cell 300 because standard cell 500 doubles the number of power connections to rails 514 and 516.

[0052] Providing redundant power connections above and below device 504 in standard cell 300 may have an increased area cost compared to standard cell 500 due to the connections above the device. However, reducing the interface resistance in standard cell 500 improves the performance of standard cell 500 compared to standard cell 300. For example, standard cell 500 may have an improvement in performance of about 5% or more over standard cell 300. Furthermore, standard cell 500 has better performance than standard cell 100 while having the same area cost. Thus, standard cell 500 can have improved performance without having to increase the size of the cell or provide extra power to the cell.

[0053] In some embodiments, the properties of the metal in the upper via 507 and upper metal layer 508 versus the metal in the backside via 510 and backside metal layer 512 are used in controlling the properties of the power source supplying power to the device 504. For example, the resistance of the metal in the upper via 507 and upper metal layer 508 can be characterized relative to the resistance of the metal in the backside via 510 and backside metal layer 512 to determine the relative proportions of power supplied through the upper and backside metal layers. The power source supplying power to the standard cell 500 can then be controlled using programming or modeling based on the relative proportions. In some embodiments, one or more tie cells can be coupled to the upper and backside metal layers to couple the upper and backside metal layers to each other.

[0054] In some embodiments, a power supply may be connected to the upper and lower metal layers without programming or modeling, such that the power supply distributes power to the upper and lower metal layers based on their relative resistances. In such embodiments, the mismatch between the resistance in the upper and lower metal layers may be small. Small differences may be within acceptable limits so that programming or modeling of the power supply is not required. For example, the difference in voltage on the upper and lower metal layers may be on the order of a few millivolts.

[0055] In some embodiments, standard cell 500 may be implemented within multiple standard cells using via programming between the cells. Figure 8 illustrates a cross-sectional view of one embodiment of a system having two standard cells 500 with via programming. System 800 includes a first standard cell 500A and a second standard cell 500B. While two standard cells are shown, it should be understood that system 800 may include multiple alternating standard cells similar to first standard cell 500A and second standard cell 500B.

[0056] The system 800 can include routing between two voltage sources Vdd1 and Vdd2 to the first standard cell 500A and the second standard cell 500B. In the illustrated embodiment, Vdd1 is routed to the backside metal layer 512 in the first standard cell 500A, and Vdd2 is routed to the topside metal layer 508 in the second standard cell 500B. Via programming is implemented in the system 800 to alternate connections to Vdd1 and Vdd2 in the first standard cell 500A and the second standard cell 500B.

[0057] 8, in a first standard cell 500A, there is no connection (no contact vias) between the upper metal layer 508 (routed to Vdd2) and the source / drain regions 604A, 604B, but there is a connection between the backside metal layer 512 (routed to Vdd1) and the source / drain regions 604B using the backside via 510. Conversely, in a second standard cell 500B, there is a connection by the via 507 between the upper metal layer 508 (routed to Vdd2) and the source / drain regions 604B, but there is no connection between the backside metal layer 512 (routed to Vdd1) and the source / drain regions 604A, 604B. Thus, the first standard cell 500A receives Vdd1, and the second standard cell 500B receives Vdd2 based on programming determined by the presence or absence of contact vias in the standard cells.

[0058] 5-8 provide reduced interface resistance for power connections by having connections both above and below device 504. Various embodiments may also be contemplated to provide signal (e.g., control signal) connections for both the top and bottom gates of a transistor device (such as device 504), potentially providing additional benefits for signal transmission within a cell (such as standard cell 500). For example, providing additional signal connections or routing through the cell may reduce RC delays that typically result from resistance in via connections in upper layers of the cell.

[0059] However, providing a signal connection to the gate within a backside metal layer (e.g., a backside via 510 connection to the backside metal layer 512) can be unreliable, difficult, or expensive to implement. For example, placing the signal connection to the gate within a backside layer can place the signal and power connections in close proximity, thereby creating parasitic problems that reduce device reliability. Furthermore, forming the signal connection to the gate in a backside layer can require a highly controlled process to enable the signal and power connections to be placed in close proximity, thereby increasing costs and reducing device yield. The present disclosure contemplates providing a routing path for the signal connection within the backside layer to reduce resistance in transmitting the signal without requiring a backside layer connection to the gate in close proximity to the power connection. The disclosed techniques can improve the performance of an integrated circuit cell over previous cell layouts, such as those shown in FIGS. 1-4, by reducing the RC delay within the cell.

[0060] Certain embodiments disclosed herein have three broad elements: 1) a first transistor and a second transistor disposed in a transistor region of an integrated circuit; 2) a via structure on the side of the first transistor opposite the second transistor; and 3) a control signal routed from the second transistor to the first transistor, from the second transistor into a backside metal layer, through the via structure to an upper metal layer, and through the upper metal layer to the gate of the first transistor. In certain embodiments, the control signal path passes under the first transistor in the backside metal layer. In some embodiments, the control signal path passes between a signal output of the second transistor and a signal input of the first transistor.

[0061] In various embodiments, the via structure includes inactive (e.g., "dummy") source / drain regions and one or more vias connecting the backside metal layer to the upper metal layer. In some embodiments, two or more via structures are implemented to transmit control signals between the backside metal layer and the upper metal layer. The two or more via structures can transmit control signals in parallel between the backside metal layer and the upper metal layer. The via structures can then be connected (e.g., "shorted") to each other within the metal layer to transmit the control signals.

[0062] In essence, the inventors have recognized that by using a via structure on the opposite side of the transistor from the connecting transistor, it is possible to provide a routing connection for a control signal through a back layer without providing an additional gate connection on the back layer. The via structure may be, for example, an inactive (e.g., "dummy") transistor. Providing a routing connection through a via structure, through the back layer, underneath the transistor, provides a control signal path in addition to other paths to reduce RC delay in signal transmission. While the addition of such a via structure may have an area cost, the improvement in performance of cells with control signals routed through the via structure may provide a substantial return in signal transmission that is worth the area cost.

[0063] FIG. 9 shows a bottom view of one embodiment of a cell 900 with both topside and backside power connections along with backside signal routing connections. Cell 900 may be, for example, a standard cell or a custom circuit design cell. In the illustrated embodiment, cell 900 includes a gate 902 and a device 904. Gate 902 and device 904 may be similar to other embodiments of gates and devices described herein. In a particular embodiment, gate 902 is a polyline formed from a polysilicon or metal layer, and device 904 is a transistor (e.g., a FinFET device, a nanosheet FET device, or a GAAFET device). Device 904 also includes topside (source / drain) power contacts 906 and both an topside via 907 to a topside metal layer 908 and a backside via 910 to a backside metal layer 912. The topside vias 907 provide power connections (e.g., Vdd / Vss connections) between the devices 904 and the topside metal layer 908, while the backside vias 910 provide power connections between the devices and the backside metal layer 912.

[0064] As described herein, the top metal layer 908 and the back metal layer 912 may be coupled to power rails to provide power connections to the device 904. For example, the top metal layer portion 908A and the back metal layer portion 912A may provide routing from the device 904 to Vdd (e.g., a supply voltage), and the top metal layer portion 908B and the back metal layer portion 912B provide routing from the device 904 to Vss (e.g., a ground voltage). For simplicity of illustration, power rails are not shown in the embodiment of the cell 900 of FIG.

[0065] In particular embodiments, backside metal layer 912 includes backside metal layer portion 912C. Backside metal layer portion 912C may be implemented to provide a routing connection for control signals through cell 900, as described herein. Backside metal layer portion 912C may be in the same backside metal layer as backside metal layer portion 912A and backside metal layer portion 912B, or may be in a different backside metal layer. In various embodiments, backside metal layer portion 912C includes the first backside metal layer or the second backside metal layer.

[0066] 9, backside via 910 does not contact backside metal layer portion 912C to avoid shorts between power and signal connections routed through backside metal layer 912. As discussed above, locating a gate connection within backside metal layer 912 can be difficult, unreliable, and expensive given the power connections within the backside metal layer (e.g., backside via 910 and backside metal layer portions 912A and 912B). Therefore, the present disclosure contemplates providing a routing connection through backside metal layer portion 912C without providing a connection through backside via 910 below (e.g., within a vertical region of) device 904. In various embodiments, as shown in FIGS. 10-13, a “dummy” cell can be placed adjacent to cell 900 to provide routing for control signals.

[0067] FIG. 10 illustrates a bottom view of a layout 1000 according to some embodiments. In the illustrated embodiment, layout 1000 includes cell 1001. Cell 1001 includes inactive (“dummy”) gates 1002, with via structures 1010A, 1010B, and 1010C disposed between the inactive gates to form inactive (“dummy”) devices 1004. In various embodiments, cell 1001 may be disposed adjacent to an active cell and gate (e.g., cell 900 and gate 902A shown in FIG. 9). In particular embodiments, cell 1001 is a unique cell included adjacent to the edge of an active cell (e.g., the edge of the cell layout) or another signal termination point within the cell layout. Cell 1001 includes paths for extensions of three backside metal layer portions 912A, 912B, and 912C. In particular embodiments, the extension for backside metal layer portion 912C provides a routing path for a control signal associated with an active cell (e.g., device 904). It should be understood that each of metal layer portions 912A, 912B, 912C may be disposed on a single backside metal layer, different backside metal layers, or a combination of backside metal layers.

[0068] In particular embodiments, the cell 1001 includes one or more via structures 1010. In the illustrated embodiment, the cell 1001 includes three via structures 1010A, 1010B, and 1010C, although any number of via structures 1010 may be contemplated. As described herein, the via structures 1010 may include backside vias 910, top vias 907 (shown in FIG. 11 ), and inactive (e.g., “dummy”) and source / drain regions 1214 (shown in FIGS. 12 and 13 ) connecting the backside metal layer portion 912C to the top metal layer 908. The backside vias 910A, 910B, and 910C provide connections between the source / drain regions (e.g., source / drain regions 1214 shown in FIGS. 12 and 13 ) of the device 1004 and the backside metal layer portion 912C.

[0069] FIG. 11 shows a top view of a layout 1000, according to some embodiments. In the illustrated embodiment, the via structure 1010 includes upper vias 907A, 907B, 907C that connect source / drain regions of the device 1004 (e.g., source / drain regions 1214 shown in FIGS. 12 and 13 ) to the upper metal layer portion 908C. In some embodiments, the upper metal layer portion 908C includes multiple portions (e.g., paths). These multiple paths can be connected (e.g., shorted) to each other to provide a connection between the upper via 907 and the active cell, as shown schematically in FIG. 11 . For example, a gate via can connect the upper metal layer portion 908C to a gate in the active cell (such as gate 902 in FIG. 9 ). In some embodiments, the upper metal layer portion 908C is disposed in a first metal layer within the upper metal layer 908, although other metal layers may be implemented.

[0070] 10 and 11 , the top metal layer portions 908A, 908B and the back metal layer portions 912A, 912B are not connected to any portion of the device 1004 in the cell 1001. For example, there are no top vias 907 or back vias 910 connecting source / drain regions in the device 1004 (e.g., source / drain regions 1214 shown in FIGS. 12 and 13 ) to the top metal layer portions 908A, 908B or back metal layer portions 912A, 912B. Without these connections, no power connection is provided to the device 1004, and the device 1004 is an inactive (e.g., “dummy”) device. When the device 1004 is inactive, a control signal path (e.g., the control signal path 1220 shown in FIGS. 12 and 13 ) can pass through the device 1004 without any interference from power signals.

[0071] FIG. 12 shows a cross-sectional view of one embodiment of layout 1000 along section line 12-12 in FIGS. 10 and 11 , according to some embodiments. In the illustrated embodiment, the path (dotted line) of control signal path 1200 is shown between source / drain regions 1214A, 1214C and the active cell. Control signal path 1200 proceeds, for example, from source / drain regions 1214A and 1214C through contact 906 and upper vias 907A and 907C to upper metal layer portion 908C, where it then routes to the active cell. In the cross-section of cell 1001 shown in FIG. 12 , via structures 1010A and 1010C provide a path for control signal path 1200 to upper metal layer portion 908C above backside metal layer portion 912A (including power routing). Backside vias 910A, 910C are also located along the cross-section shown in FIG. 12 . Note, however, that backside vias 910A, 910C in via structures 1010A, 1010C, respectively (as also shown in FIG. 10 ), provide a connection path to backside metal layer portion 912C rather than backside metal layer portion 912A. Thus, in the illustrated embodiment of FIG. 12 , control signal path 1200 has a path from source / drain regions 1214A, 1214C to backside vias 910A, 910C and then to backside metal layer portion 912C (which then routes to the active cell), but backside vias 910A, 910C are not connected to backside metal layer portion 912A. Thus, as shown in FIG. 12 , control signal path 1200 has a path between upper layer metal layer portion 908C and backside metal layer portion 912C that passes through both source / drain regions 1214A and 1214C.

[0072] Various embodiments of metal routing between backside vias 910A, 910C and backside metal layer portion 912C may be contemplated. The metal routing may include, for example, any combination of metal vias, metal wires, metal traces, etc. that provide a path / path between two structures. For example, in one embodiment, backside vias 910A, 910C may extend vertically down into substrate 200 from source / drain regions 1214A, 1214C, respectively (as shown in FIG. 12), with additional metal routing connecting the backside vias to backside metal layer portion 912C.

[0073] FIG. 13 shows a cross-sectional view of one embodiment of layout 1000 along section line 13-13 in FIGS. 10 and 11 , according to some embodiments. In the cross-section of cell 1001 shown in FIG. 13 , via structure 1010B provides a path for control signal path 1200 between source / drain region 912C and backside metal layer portion 1214B. Similar to the cross-section of FIG. 12 , in the cross-section of FIG. 13 , backside metal layer portion 912B (e.g., power routing) is located below transistor region 1230. However, backside via 910B in via structure 1010B (also shown in FIG. 10 ) provides a connection path for source / drain region 1214B to backside metal layer portion 912C instead of backside metal layer portion 912B. Thus, control signal path 1200 travels from source / drain region 1214B through backside via 910B to backside metal layer portion 912C (which then routes to the active cell). As mentioned above, various embodiments of metal routing between the bottom of backside via 910B and backside metal layer portion 912C may be contemplated. For example, in one embodiment, backside via 910B extends vertically into substrate 200, with additional metal routing connecting the backside via to backside metal layer portion 912C.

[0074] 14 shows a cross-sectional view of one embodiment of a layout 1000 along section line 14-14 in FIGS. 10 and 11 , according to some embodiments. In the cross-section of cell 1001 shown in FIG. 14 , via structures 1010A, 1010B, and 1010C provide a path for control signal path 1200 between source / drain regions 1214A, 1214B, 1214C and the active cell through backside metal layer portion 912C. In the illustrated embodiment of the cross-section, backside metal layer portion 912C is disposed below transistor region 1230 in device 1004. Thus, backside vias 910A, 910B, 910C in via structures 1010A, 1010B, 1010C provide direct down connections into backside metal layer portion 912C for source / drain regions 1214A, 1214B, 1214C, respectively. Control signal path 1200 then runs from source / drain regions 1214A, 1214B, 1214C to backside metal layer portion 912C and then to the active cell.

[0075] 12-14, device 1004 is formed in transistor region 1230 of cell 1001. Transistor region 1230 typically includes structures implemented in the active layer of the device (such as in an adjacent active cell). For example, transistor region 1230 may include gate 1002, gate spacer 1003, and source / drain regions 1214 found in the active layer of a transistor device. Source / drain regions 1214 may be doped regions of device 1004 that form, for example, a fin or nanosheet stack in a FinFET or NSH device.

[0076] As mentioned above, in cell 1001, gate 1002 and source / drain region 1214 are not connected to any power supplies; therefore, transistor region 1230 of device 1004 can be considered an inactive (e.g., "dummy") transistor region. Because transistor region 1230 of device 1004 is inactive, source / drain region 1214 can be implemented within control signal path 1200, as shown in FIGS. 12-14. Thus, as shown in the illustrated embodiment, control signal path 1200 can provide a path between the source / drain region and gate of the active cell, including a path through backside metal layer portion 912C, via structure 1010 (e.g., backside via 910, source / drain region 1214, and via 907), and top metal layer portion 908C.

[0077] In a typical cell layout, routing from the output of an active cell device (e.g., device 904 shown in FIG. 9 has an output at gate 902A) travels from the gate through the top metal layer 908 to the input of a source / drain region within the active cell device. As described herein, such routing can have high resistance, creating RC delays. However, the control signal path 1200 shown in FIGS. 12-14 is a path that includes additional use of the backside metal layer 912 by routing the control signal between top metal layer portion 908C and backside metal layer portion 912C through a structure within cell 1001 (e.g., via structure 1010). Thus, in various embodiments, the via structure 1010 within cell 1001 provides a path for the control signal on the opposite side of an active device (e.g., device 904) from other active devices.

[0078] In a particular embodiment, cell 1001 includes three via structures 1010A, 1010B, and 1010C. As described above, the three via structures 1010A, 1010B, and 1010C may be coupled in parallel between top metal layer portion 908C and backside metal layer portion 912C, with the via structures connected (e.g., shorted) to each other in the top and backside metal layer portions. Thus, control signal path 1200 may "split" (e.g., split) going from backside metal layer portion 912C to via structures 1010A, 1010B, and 1010C and run in parallel through via structures 1010A, 1010B, and 1010C. In top metal layer portion 908C, the control signal may then "recombine" (e.g., couple back together) and connect to a gate in an active cell. 10-14 show three via structures 1010A, 1010B, 1010C, it should be noted that the number of via structures may be varied within cell 1001. For example, the number of via structures 1010 may be varied to balance area cost (due to the physical presence of the via structures) and performance (more via structures provide higher performance).

[0079] Running the control signals through the backside metal layer 912 provides a low resistance path (e.g., a "highway" path) for the control signals compared to routing the control signals only through the top metal layer 908, which has relatively small metal structures (traces). Thus, sending the control signals through the backside metal layer 912 and the control signal path 1200 reduces the RC delay in the transmission of the control signals. Note that the control signals may be routed through any backside metal layer that provides a low resistance path underneath the device 904.

[0080] 10-14, a control signal can be transmitted to an active device (e.g., device 904) along control signal path 1200. Control signal path 1200 passes through a backside metal layer (e.g., backside metal layer portion 912C) having low resistance, then passes through multiple via structures 1010 in parallel before reaching a top metal layer (e.g., top metal layer portion 908C). The combination of the low-resistance path in the backside metal layer path and the parallel path through the via structures 1010 can provide a significant reduction in RC delay for transmitting control signals to / from device 904, thereby improving the performance of the device in cell layout 1000 compared to previous cell layouts.

[0081] One example where providing control signals through both the top and bottom metal layers may be useful is the implementation of layout 1000 in a bitcell erase process. In such an embodiment, the bitcell erase signal may be generated in device 904. Device 904 may be precharged to provide the bitcell erase signal. With lower interface resistance, the same driver power may drive the bitcell erase signal to a greater distance within the layout. For example, device 904 may be able to send the bitcell erase signal to a larger group of bitcells (such as four bitcells instead of two bitcells). As another example, embodiments may be contemplated in which control signals through both the top and bottom metal layers to / from device 904 may be implemented to provide a differential structure embodiment in layout 1000. In such an embodiment, signals may be routed in parallel to the top and bottom metal layers, with signals escaping from the top on one side of layout 1000 and escaping from the bottom on the other side of the layout. Signals may be routed in parallel so that both the top and bottom metal layers see the same common mode. Additional cell layouts that combine the control signal path 1200 with redundant power connections in the top and bottom metal layers can be designed to provide improved performance in both signal and power transmission over previous cell layouts.

[0082] The above-described embodiments are directed to utilizing a backside metal layer to provide additional connections for power and / or control signals in an integrated circuit cell layout. Various embodiments of implementations of these additional connections are also contemplated in this disclosure. For example, standard memory array (e.g., SRAM array) designs may be contemplated to utilize additional connections for power and / or control signals in the backside metal layer to improve power, performance, and area (PPA) metrics in the SRAM array. Current designs of SRAM arrays typically provide connections and routing for power or signals to transistors (or other structures) above transistors. As described herein, some embodiments may be contemplated having connections to power (alone or in combination with upper metal layer power connections) in the backside metal layer of the SRAM array.

[0083] While providing power connections within the back metal layer of an SRAM array provides additional benefits for power transmission, the present disclosure recognizes that additional benefits can be achieved by placing some signal connection paths for bit lines and / or word lines within the back layer. For example, moving some signal connection paths for bit lines to the back layer can enable capacitance (cap) reduction on the bit lines, which improves performance and power utilization in the SRAM array, while moving some signal connection paths for word lines to the back layer can improve power utilization in the SRAM array. Further improvements in area cost can also be realized by placing bit lines or word lines on the back layer.

[0084] Certain embodiments disclosed herein have three broad elements: 1) a plurality of adjacently arranged bit cells in an array; 2) a first bit line or a first pair of bit lines spanning alternating bit cells in the array; and 3) a second bit line or a second pair of bit lines spanning every other bit cell from the first bit line or the first pair of bit lines. In various embodiments, the first bit line is a metal wire located in a first metal layer on the top side of the device (e.g., the front side or above the bit cells), and the second bit line is a metal wire located in a second metal layer on the back side of the device (e.g., below the bit cells). Alternating the first bit line(s) and second bit line(s) between adjacent bit cells in a memory array can significantly reduce capacitance in the memory array by increasing the separation between different bit lines in the same metal layer. Reducing capacitance in a memory array can provide leverage for improving other parameters in the memory array, such as leakage, as described herein.

[0085] Another embodiment disclosed herein has three broad elements: 1) a plurality of adjacently arranged bit cells in an array; 2) a first word line spanning the bit cells in the array, the first word line being a first wire in a first metal layer disposed above the bit cells; and 3) a second word line spanning the bit cells in the array, the second word line being a second wire in a second metal layer disposed below the bit cells. In various embodiments, the first word line and the second word line connect to alternating bit cells in the array. For example, a memory array may have four adjacent bit cells, with both word lines spanning the four bit cells. The first word line connects to the first and third bit cells, and the second word line connects to the second and fourth bit cells in the memory array.

[0086] Alternating connections between two separate word lines can provide independent control of bit cells. For example, a first word line controls the toggling of the first and third bit cells, and a second word line controls the toggling of the second and fourth bit cells. Thus, instead of toggling all four bit cells, only half of the bit cells need to be toggled when a single bit is changed, thereby reducing dynamic power consumption in the memory array. Placing wires for word lines in the back metal layer can also provide an area-cost advantage because two word lines can be placed in a similar vertical area (above / below the bit cell) through two separate metal layers (e.g., a top metal layer and a back metal layer), thereby doubling the word line capacity without an area cost.

[0087] In summary, the inventors have recognized that wiring in the backside metal layer can be advantageously implemented in memory arrays (e.g., SRAM arrays). Utilizing wiring in the backside metal layer for bitline and / or wordline routing can provide various PPA improvements in memory arrays. For example, performance and power improvements can be provided by reducing bitline capacitance, which can be further leveraged for other improvements in memory arrays, including area reduction opportunities.

[0088] FIG. 15 illustrates a top view of a memory array 1600 showing bit cells and bit lines, according to some embodiments. In the illustrated embodiment, memory array 1600 includes four bit cells: bit cell 1510A, bit cell 1510B, bit cell 1510C, and bit cell 1510D. While four bit cells are shown in FIG. 15, it should be understood that memory array 1500 may include any number of bit cells. In various embodiments, bit cell 1510A, bit cell 1510B, bit cell 1510C, and bit cell 1510D are adjacently positioned (e.g., adjacent to one another) within memory array 1500. For example, as shown in FIG. 15, bit cells 1510A-D are positioned vertically adjacent to one another (e.g., vertically "stacked" on top of one another).

[0089] In particular embodiments, memory array 1500 includes a pair of bit lines spanning each bit cell 1510. For example, in the illustrated embodiment, bit line 1520A spans bit cell 1510A, bit line 1520B spans bit cell 1510B, bit line 1520C spans bit cell 1510C, and bit line 1520D spans bit cell 1510D. Each pair of bit lines may be a complementary pair of bit lines (e.g., one bit line is a positive bit line and the other bit line is a negative bit line). In various embodiments, bit lines 1520 extend perpendicular to the direction in which bit cells 1510 are arranged adjacent to one another (e.g., the direction in which bit cells 1510A-D are stacked in FIG. 15). In particular embodiments, bit lines 1520 are wires (e.g., metal paths, metal traces, metal structures, etc.) formed within a metal layer of a memory device.

[0090] In particular embodiments, bit lines 1520 (e.g., wires within a bit line) are connected to respective bit cells 1510 by via connections 1530. For example, in the illustrated embodiment, bit line 1520A is connected to bit cell 1510A by via connection 1530A, bit line 1520B is connected to bit cell 1510B by via connection 1530B, bit line 1520C is connected to bit cell 1510C by via connection 1530C, and bit line 1520D is connected to bit cell 1510D by via connection 1530D. Note that although via connection 1530 is depicted in FIG. 15 as spanning the bit line pair, each wire within the bit line pair may have its own individual via connection. Thus, via connections 1530A-D may each include two or more via connections. Additionally, in embodiments having multiple via connections 1530 within a single bitcell, the via connections may be aligned or offset within the bitcell as required by the design rules.

[0091] To improve PPA over typical SRAM arrays, the present disclosure contemplates placing pairs of different bit lines 1520 in different metal layers above and below bit cells 1510, as shown in FIG. 15. In the illustrated embodiment, bit lines 1520A and 1520C are wires in the back metal layer of memory array 1500 (e.g., the metal layer below the transistor regions of bit cells 1510A and 1510C). Conversely, bit lines 1520B and 1520D are wires in the top metal layer of memory array 1500 (e.g., the metal layer above the transistor regions of bit cells 1510B and 1510D). Thus, as shown in FIG. 15, bit lines alternate between the back metal layer and the top metal layer in adjacent bit cells. For example, bitline 1520A in bitcell 1510A is in the back metal layer, then bitline 1520B in bitcell 1510B switches to the top metal layer, bitline 1520C in bitcell 1510C switches back to the back metal layer, and then bitline 1520D in bitcell 1510D switches back to the top metal layer.

[0092] In various embodiments, the bit lines 1520 may be placed in the top metal layer or the bottom metal layer using the techniques described herein. Note that the bit lines 1520 may be placed in the bottom metal layer without requiring a gate connection because the bit lines connect to drains in the memory array 1500. Additional embodiments may be contemplated in which each pair of bit lines includes one bit line in the top metal layer and one bit line in the bottom metal layer. In such embodiments, additional design considerations may be implemented to maintain symmetry between the bit lines in each pair of bit lines.

[0093] In some embodiments of a memory array, single-ended bit lines within the bit cells may be contemplated. FIG. 16 shows a top view of a memory array 1600 having single-ended bit lines within the bit cells, according to some embodiments. In the illustrated embodiment, the memory array 1600 includes bit cells 1610A-D, with a single bit line 1620A-D spanning the bit cells. As with the embodiment of FIG. 15, the bit lines 1620A-D may alternate between the back metal layer and the top metal layer between adjacent bit cells 1610A-D. While four bit cells are shown in FIG. 16, it should be understood that the memory array 1600 may include any number of bit cells. In various embodiments, via connections 1630A-D provide connections between the bit lines 1620A-D and the respective bit cells 1610A-D.

[0094] In a typical SRAM array, the bitlines are wires in a metal layer on the top (e.g., front) side of the bitcell (e.g., the bitlines are in a metal layer above the transistor region of the bitcell). However, placing the bitlines in the same metal layer requires high shielding requirements between the bitlines, which can increase bitline capacitance in the memory array and reduce the performance of the memory array.

[0095] In the present disclosure, bitline capacitance in a memory array is reduced by alternating bitlines between backside and top metal layers in adjacent bitcells, as shown in FIGS. 15 and 16 . For example, alternating bitlines results in a greater separation distance between bitlines (or bitline pairs) in the same metal layer. This increased separation distance reduces the shielding requirements for the bitlines, reducing bitline capacitance. Reducing bitline capacitance can be further leveraged in other characteristics of the memory array. For example, lower shielding requirements can reduce area utilization by shielding structures, thereby increasing area availability in the memory array for other structures. As another example, bitcells in a memory array can be slowed down with reduced bitline capacitance while providing the same performance. Slowing down the bitcells can reduce leakage in the memory array.

[0096] FIG. 17 illustrates a top view of a memory array 1700 showing bit cells and word lines, according to some embodiments. In the illustrated embodiment, memory array 1700 includes four bit cells: bit cell 1710A, bit cell 1710B, bit cell 1710C, and bit cell 1710D. While four bit cells are shown in FIG. 17, it should be understood that memory array 1700 may include any number of bit cells. In various embodiments, bit cell 1710A, bit cell 1710B, bit cell 1710C, and bit cell 1710D are adjacently positioned (e.g., adjacent to one another) within memory array 1700. For example, as shown in FIG. 17, bit cells 1710A-D are positioned vertically adjacent to one another (e.g., vertically "stacked" on top of one another).

[0097] In a particular embodiment, memory array 1700 includes a pair of parallel word lines, word line 1720A and word line 1720B, that span bit cells 1710A-D. Word line 1720A and word line 1720B can therefore be considered to span memory array 1700. In various embodiments, word line 1720A and word line 1720B span bit cells 1710A-D in the same direction that the bit cells are arranged adjacently (e.g., the vertical direction shown in FIG. 17). Word lines 1720A and 1720B therefore span memory array 1700 along their lengths to provide access to bit cells 1710A-D. In a particular embodiment, word line 1720A is a wire in the back metal layer of memory array 1700, and word line 1720B is a wire in the top metal layer of the memory array. Placing word line 1720A on the back metal layer and word line 1720B on the top metal layer allows two word lines to be placed over the same group of bit cells (e.g., bit cells 1710A-D) in memory array 1700. Placing two word lines over the same group of bit cells provides area utilization advantages, as described below.

[0098] 17, access to (e.g., connection to) bit cells 1710A-D is provided by via connections 1730A-D. Via connections 1730 may be, for example, metal vias that penetrate an insulating layer disposed between the transistor region containing bit cell 1710 and the metal layer containing word line 1720. In various embodiments, via connections 1730A-D selectively provide connection between bit cells 1710A-D and either word line 1720A or word line 1720B as the word line passes through the bit cell. In particular embodiments, connection to bit cells 1710A-D is alternated between word line 1720A and word line 1720B of adjacent bit cells by alternating the connection provided by via connections 1730A-D. For example, in the illustrated embodiment, via connection 1730A provides a connection between bit cell 1710A and word line 1720B, which in turn provides a connection between bit cell 1710B and word line 1720A, via connection 1730C in turn provides a connection between bit cell 1710C and word line 1720B, and via connection 1730D provides a connection between bit cell 1710D and word line 1720A. Thus, the connections to word line 1720A at bit cells 1710B and 1710D alternate with the connections to word line 1720B at bit cells 1710A and 1710C.

[0099] In a typical SRAM array, only a single word line in the upper layer is available for an array of adjacent bit cells. For example, only a single word line can be implemented in the upper metal layer because there is insufficient area to place two parallel word lines spanning multiple vertical (as shown) bit cells. With a single word line, when a command (e.g., a control signal) is provided to toggle a single bit cell, all bit cells along the word line receive the command to toggle. Because all bit cells are toggled, power consumption is unnecessarily increased over toggling only a selected number of bit cells.

[0100] In various embodiments, the word lines 1720 are disposed in a top or back metal layer using techniques described herein. Note that word lines 1720 disposed in a back metal layer typically require a gate connection (e.g., to a pass gate). Thus, embodiments may be contemplated in which a connection to a gate through the back layer described herein is implemented for the word lines 1720.

[0101] In the present disclosure, the placement of word lines in both the top metal layer and the bottom metal layer may allow connections to bit cells to be alternated between parallel word lines that simultaneously provide access to the same group of bit cells. For example, as shown in FIG. 17, word line 1720A (in the bottom metal layer) and word line 1720B (in the top metal layer) have alternating connections to adjacent bit cells 1710 in memory array 1700. Thus, a single word line (e.g., either word line 1720A or word line 1720B) can provide control signals to a reduced number of bit cells 1710 (e.g., half of the bit cells) in memory array 1700. For example, when a control signal to toggle is sent via word line 1720A, only bit cells 1710A and 1710C are toggled, while bit cells 1710B and 1710D remain in their current state. Similarly, when a toggling control signal is sent over word line 1720B, only bit cells 1710B and 1710D are toggled, while bit cells 1710A and 1710C remain in their current state.

[0102] Reducing the number of bitcells toggled by a single control signal can reduce dynamic power consumption in memory array 1700 compared to a memory array with a single wordline. Providing reduced dynamic power consumption is also achieved at a lower area cost because the wordline count is doubled in the vertical region above the bitcells, instead of having to increase the bitcell area to accommodate multiple wordlines. The embodiments of the technique described in FIG. 17 for doubling wordlines can also be applied to other control signal lines implemented within an integrated circuit, such as a memory array. For example, control signals such as bitline precharge signals, column select signals, column select signals, and cross-coupled PMOS structure signals are control signals that can utilize line doubling in the top and bottom metal layers. Applying the disclosed techniques to these control signals can further reduce power because these signals are full-power signals, unlike wordline control signals.

[0103] Various embodiments of memory arrays utilizing both bit lines and word lines disposed in top and bottom metal layers may also be contemplated. FIG. 18 illustrates a top view of a memory array 1800 having both bit lines and word lines in top and bottom metal layers, according to some embodiments. In the illustrated embodiment, memory array 1800 includes four bit cells: bit cell 1810A, bit cell 1810B, bit cell 1810C, and bit cell 1810D. While four bit cells are shown in FIG. 18, it should be understood that memory array 1800 may include any number of bit cells. In various embodiments, bit cell 1810A, bit cell 1810B, bit cell 1810C, and bit cell 1810D are adjacently disposed within memory array 1800 (e.g., adjacent to one another). For example, as shown in FIG. 18, bit cells 1810A-D are vertically adjacent to one another (e.g., vertically "stacked" on top of one another).

[0104] The illustrated embodiment of memory array 1800 essentially includes the bit lines of memory array 1500 shown in Figure 15 overlapped with the word lines of memory array 1700 shown in Figure 17. Thus, memory array 1800 includes bit line 1820A spanning bit cell 1810A, bit line 1820B spanning bit cell 1810B, bit line 1820C spanning bit cell 1810C, and bit line 1820D spanning bit cell 1810D. Memory array 1800 further includes word lines 1830A and 1830B spanning bit cells 1810A-D.

[0105] As described in previous embodiments, bitlines 1820A-D can comprise bitline pairs in either the top metal layer or the bottom metal layer. For example, in the illustrated embodiment, bitline 1820A and bitline 1820C are in the bottom metal layer, and bitline 1820B and bitline 1820D are in the top metal layer. Similarly, wordline 1830A can be in the bottom metal layer, and wordline 1830B can be in the top metal layer. Via connections 1840A-D then provide alternating connections from bitcells 1810A-D to wordline 1830A and wordline 1830B, and via connections 1850A-D provide alternating connections between bitlines 1820A-D and bitcells 1810A-D, as described herein.

[0106] Although the bit lines 1820 and word lines 1830 are shown crossing each other and are described as both being in the "back (or upper) metal layer," it should be understood that the bit lines and word lines may be implemented in different metal layers in both the upper and back layers. For example, the bit line 1820A may be implemented in a first metal layer in the back metal layer, and the word line 1830A is implemented in a second metal layer in the back metal layer. Additional embodiments may be contemplated in which the bit lines and word lines are routed through multiple metal layers to accommodate spacing between the lines. The embodiment of the memory array 1800 shown in FIG. 18 can benefit from various advantages described herein in connection with having both bit lines and word lines simultaneously in the back metal layer and the upper metal layer.

[0107] In various embodiments, word lines in both the top and bottom metal layers may be implemented in large cells (e.g., "megacells") of a memory array to improve area utilization in such cells. FIG. 19 shows a top view of a large memory megacell that replaces two smaller memory megacells, according to some embodiments. In the illustrated embodiment, megacells 1910A and 1910B are combined into a single megacell, megacell 1900. Megacell 1910A includes memory array bank 1912A and memory array bank 1912B separated by bit line logic circuit 1916A, and word line logic circuit 1914A is disposed adjacent to the memory array bank and bit line logic circuit. Memory array banks 1912A and 1912B may include any of the various memory cells or memory arrays disclosed herein, in addition to other contemplated embodiments of memory cells and memory arrays. Bit line logic circuitry 1914A may include sense amplifiers or other logic for reading data from memory array banks 1912A and 1912B. Word line logic circuitry 1916A may include word line decoder logic, word line selection logic, or multiplexer logic for interacting with word lines in memory array banks 1912A and 1912B.

[0108] In various embodiments, megacell 1910A also includes global input / output (I / O) circuitry 1918A and global control circuitry 1920A. Global I / O circuitry 1918A may include, for example, write drivers or sense amplifiers. Global control circuitry 1920A may include, for example, clock or decoder logic. Megacell 1910B may be similar to megacell 1910A by including memory array bank 1912C, memory array bank 1912D, bit line logic circuitry 1914B, word line logic circuitry 1916B, global input / output (I / O) circuitry 1918B, and global control circuitry 1920B.

[0109] 19, megacells 1910A and 1910B may be combined to form megacell 1900. Megacell 1900 includes memory array banks 1912A-D with a single instance of bit line logic circuitry 1914, word line logic circuitry 1916, global input / output (I / O) circuitry 1918, and global control circuitry 1920. Thus, megacell 1900 may have a reduced area cost compared to the combination of megacells 1910A and 1910B.

[0110] Megacell 1900 can be formed by implementing word lines in both top and bottom metal layers. For example, in the illustrated embodiment, megacell 1900 includes word line 1930A and word line 1930B for connecting to memory array bank 1912A and memory array bank 1912C, respectively. Similar word lines can be provided for memory array banks 1912B and 1912D.

[0111] In a particular embodiment, word line 1930A is disposed in an upper metal layer, and word line 1930B is disposed in a back metal layer. As shown in FIG. 19 , word line 1930B travels a longer distance to connect to a memory cell in memory array bank 1912C than word line 1930A must travel to connect to a memory cell in memory array bank 1912A. Because of this longer distance, word line 1930B may be disposed in a back metal layer because back metal layers typically have lower resistance metal wiring than upper metal layers. Using a low-resistance back metal layer for word line 1930B also eliminates the need for repeaters that may be required for upper metal layer word lines connecting to memory array bank 1912C or memory array bank 1912D. Thus, megacell 1900 provides better area utilization and better performance and power metrics compared to the combination of megacells 1910A and 1910B.

[0112] In various embodiments, wide memory megacells, which may have a large area cost, can be converted to taller, narrower memory megacells to reduce area requirements. FIG. 20 shows a top view of a tall memory megacell that replaces a wide memory megacell, according to some embodiments. In the illustrated embodiment, megacell 2000 is a wide memory megacell. Megacell 2000 includes memory array bank 2012A, memory array bank 2012B, memory array bank 2012C, and memory array bank 2012D. Memory array bank 2012A and memory array bank 2012B are separated by and connected to bit line logic circuit 2014A, and memory array bank 2012C and memory array bank 2012D are separated by and connected to bit line logic circuit 2014B.

[0113] Megacell 2000 includes a single instance of wordline logic circuitry 2016 (integrated with each of memory array banks 2012A-D), global I / O circuitry 2018, and global control circuitry 2020. As shown in Figure 20, megacell 2000 may be converted into megacell 2050. Megacell 2050 may have a structure similar to memory array 1800 shown in Figure 18, with memory array banks 2012A-D and single instances of bitline logic circuitry 2014, wordline logic circuitry 2016, global I / O circuitry 2018, and global control circuitry 2020.

[0114] Conversion to megacell 2050 can be provided by implementing wordlines in both the top metal layer and the back metal layer, similar to memory array 1800. For example, in the illustrated embodiment, megacell 2050 includes wordline 2030A in the top metal layer for connecting to memory array bank 2012A and wordline 2030B in the back metal layer for connecting to memory array bank 2012C. Megacell 2050 therefore provides better area utilization and better performance and power metrics compared to megacell 2000. Further area savings are also seen in megacell 2050 due to the reduced width of wordline logic 2016 compared to megacell 2000.

[0115] Based on this disclosure of bitline implementations in both the top and bottom metal layers, various embodiments of hierarchical bitline layouts may also be contemplated. Figure 21 shows a top view of a memory array with hierarchical bitlines, according to some embodiments. In the illustrated embodiment, memory array 2100 is a memory array having bitlines spanning bitcells 2110 in two top metal layers. For example, bitline 2120A may be in a first metal layer and bitline 2120B may be in a second metal layer.

[0116] Hierarchical routing of bitlines may be implemented by jumping from bitline 2120A to bitline 2120B at the transition between bitcell bank 2130A and bitcell bank 2130B, as shown in Figure 21. Bitcells 2110 within bitcell bank 2130 may share resources (such as sense amplifiers) to reduce bitline capacitance for large caches of data (e.g., caches with 512 wordlines). Resource sharing may also reduce the number of local I / O connections required within memory array 2100.

[0117] Adding bitline routing to the backside metal layer can further reduce bitline capacitance. For example, memory array 2150 includes three bitlines 2170A, 2170B, and 2170C that span bitcell 2160. Bitline 2170A is in a first metal layer in the backside metal layer, bitline 2170B is in a first metal layer, and bitline 2170C is in a second metal layer in the topside metal layer. Thus, three bitcell banks 2180A, 2180B, and 2180C can be created by the hierarchy of bitlines 2170A, 2170B, and 2170C. Exemplary Computer System

[0118] 22 , a block diagram of one embodiment of a system 2200 is shown, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 2200 includes at least one instance of a system-on-chip (SoC) 2206, which may include multiple types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or other units, a communications fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 2206 include multiple execution lanes and similar instruction issue queues. In various embodiments, the SoC 2206 is coupled to external memory 2202, peripherals 2204, and a power supply 2208.

[0119] A power supply 2208 is also provided to provide a supply voltage to the SoC 2206 and to provide one or more supply voltages to the memory 2202 and / or peripherals 2204. In various embodiments, the power supply 2208 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet computer, or other device). In some embodiments, more than one instance of the SoC 2206 is included (and more than one external memory 2202 is also included).

[0120] The memory 2202 may be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be connected to a circuit board to form a memory module, such as a single in-line memory module (SIMM), dual in-line memory module (DIMM), etc. Alternatively, devices may be mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0121] The peripherals 2204 may include any desired circuitry, depending on the type of system 2200. For example, in one embodiment, the peripherals 2204 include devices for various wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, the peripherals 2204 may also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripherals 2204 may also include user interface devices, such as a display screen, including a touch or multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc.

[0122] As shown, system 2200 is shown to have a wide range of applications. For example, system 2200 may be utilized as part of a chip, circuit, component, etc. in a desktop computer 2210, a laptop computer 2220, a tablet computer 2230, a cellular or mobile phone 2240, or a television 2250 (or a set-top box coupled to a television). Also illustrated is a smartwatch and a health monitoring device 2260. In some embodiments, a smartwatch may include various general-purpose computing-related functions. For example, a smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, a health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, a health monitoring device may monitor a user's vital signs, track a user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any health monitoring-related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, and glasses designed to provide an augmented and / or virtual reality experience.

[0123] System 2200 may further be used as part of cloud-based service(s) 2270. For example, the aforementioned devices and / or other devices may access computing resources (i.e., remotely located hardware and / or software resources) in the cloud. Additionally, system 2200 may be utilized in one or more devices in a home 2280 other than those described above. For example, appliances in a home may monitor and detect noteworthy conditions. For example, various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the device status and alert the homeowner (or a repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the home's temperature and automate adjustments to the heating / cooling system based on the homeowner's historical responses to various conditions. FIG. 22 also illustrates the application of system 2200 to various transportation modes 2290. For example, system 2200 may be used in control and / or entertainment systems for airplanes, trains, buses, rental vehicles, private cars, watercraft ranging from private boats to cruise ships, scooters (rented or owned), etc. In various cases, system 2200 can be used to provide automated guidance (e.g., for autonomous vehicles), general system control, and other methods. Many other embodiments of any of these are possible and contemplated. Note that the devices and applications illustrated in Figure 22 are illustrative only and are not intended to be limiting. Other devices are possible and contemplated. ***

[0124] The present disclosure includes references to "one embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different implementations or examples of the disclosed concepts. References to "one embodiment," "one embodiment," "particular embodiment," etc. do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, as well as modifications or alternatives that are within the spirit or scope of the present disclosure, are contemplated.

[0125] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all of the potential advantages. Whether advantages are realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation within the scope of the claims may not exhibit some or all of any disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure that, in conjunction with one of the disclosed embodiments, negates or reduces one or more of the disclosed advantages. Furthermore, suboptimal design practices of a particular implementation (e.g., implementation techniques or tools) may also negate or reduce a disclosed advantage. Even assuming skilled practice, realization of advantages may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, resulting in the benefits of that solution not being realized. Given the existence of factors external to the present disclosure that may arise, it is expressly intended that any potential advantages described herein should not be construed as claim limitations that must be met in order to demonstrate infringement. Rather, the identification of such potential advantages is intended to illustrate the type(s) of improvement available to a designer having the benefit of the present disclosure. The fact that such advantages are permissibly described (e.g., a statement that a particular advantage "may result") is not intended to convey any doubt as to whether such advantage can actually be realized, but rather to recognize the technological reality that realization of such advantages often depends on additional factors.

[0126] Unless otherwise specified, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative, not limiting, unless a statement to the contrary is present in the present disclosure. The above description is intended to enable claims that cover not only the disclosed embodiments, but also alternatives, modifications, and equivalents that will be apparent to those skilled in the art having the benefit of this disclosure.

[0127] For example, features of the present application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority to this application) for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of other dependent claims as appropriate, including claims that are dependent on other independent claims. Similarly, features from each independent claim may be combined as appropriate.

[0128] Thus, the accompanying dependent claims may each be drafted to depend on a single other claim, although additional dependencies are also contemplated. Any combination of features in the dependent claims consistent with this disclosure is contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically recited in the accompanying claims.

[0129] Where appropriate, it is contemplated that a claim drafted in one format or statutory type (e.g., apparatus) is also intended to support a corresponding claim in another format or statutory type (e.g., method). ***

[0130] Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The public is hereby notified that the definitions provided in the following paragraphs, as well as throughout this disclosure, will be used in interpreting the claims made based on this disclosure.

[0131] Reference to a singular item (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more" unless the context clearly indicates otherwise. Thus, a reference to an "item" in a claim does not exclude additional instances of the item without context. A "plurality" of an item refers to a set of two or more items.

[0132] The word "may" is used herein in a permissive sense (i.e., having the possibility, being able to do), not in an obligatory sense (i.e., not required).

[0133] The terms "comprising" and "including" and their variations are open-ended and mean "including, but not limited to."

[0134] When the term "or" is used in this disclosure in reference to a list of alternatives, it will generally be understood to be used in an inclusive sense unless the context clearly indicates otherwise. Thus, a list of "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase "either x or y, but not both" makes clear that "or" is used in an exclusive sense.

[0135] The enumeration of "w, x, y, z, or any combination thereof," or "...at least one of w, x, y, and z" is intended to encompass all possibilities, including single elements, up to the total number of elements in the set. For example, for the set [w, x, y, z], these expressions encompass any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase should not be interpreted as requiring that there be at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0136] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context clearly indicates otherwise, various labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Furthermore, when applied to features, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0137] As used herein, the phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision. That is, the decision may be based solely on the specified factors, or on the specified factors as well as other unspecified factors. Consider the phrase "determining A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0138] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either together with the particular factor or independently of the specified factor. That is, the effect may depend only on these factors, or on the specified factor as well as other unspecified factors. Consider the phrase "performing A in response to B." By this phrase, B is a factor that triggers the execution of A or triggers a particular result for A. This phrase does not exclude that the execution of A may also be in response to other factors, such as C. This phrase also does not exclude that performing A may be in response to both B and C. This phrase is intended to cover an embodiment in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to." ***

[0139] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This phrase "entity" configured to perform one or more tasks is used herein to refer to a structure (i.e., a physical thing). More specifically, this phrase is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently operating. In this manner, an entity described or explained as being "configured" to perform a task refers to a physical thing, such as a device, a circuit, a system having a processor unit and a memory storing executable program instructions to perform the task. This phrase is not used herein to refer to an intangible thing.

[0140] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations, and even if not specifically described, it will be understood that those entities are "configured to" perform those tasks / operations.

[0141] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered to be "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After appropriate programming, the FPGA can then be said to be "configured" to perform a particular function.

[0142] For purposes of filing a U.S. patent application based on this disclosure, reciting a structure as "configured to" perform one or more tasks in a claim is not expressly intended to invoke 35 U.S.C. §112(f) for that claim element. If an applicant wishes to invoke 35 U.S.C. §112(f) during prosecution of a U.S. patent application based on this disclosure, it would recite a claim element using "means for" [performing a function].

[0143] Various "circuits" may be described in this disclosure. These circuits or "circuitry" comprise hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Particular types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry.

[0144] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform this function. This specification of this function is sufficient to suggest a set of possible configurations of the circuit to one skilled in the computer arts.

[0145] In various embodiments, as described in the previous paragraph, circuits, units, and other elements are defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to one another and the way they interact form a microarchitecture definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with a microarchitecture definition provided in accordance with this disclosure can, without undue experimentation, implement the structure by coding the circuit / unit / component description into a hardware description language (HDL), such as Verilog or VHDL, using ordinary skill. HDL descriptions are often expressed in a manner that appears to be functional. However, to those skilled in the art, this HDL description is the method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions may take the form of behavioral-level code (which is typically not synthesizable), register transfer language (RTL) code (which is typically synthesizable, as opposed to behavioral-level code), or structural code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology and modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate masks and ultimately manufacture the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuit. An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and the circuit elements.Some embodiments may implement multiple integrated circuits connected together to realize the hardware circuit, and / or some embodiments may use discrete elements. Alternatively, the HDL design may be integrated into and implemented in a programmable logic array, such as a field programmable gate array (FPGA). This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits generally results in a scenario where the circuit or logic designer does not specify any particular set of structures for the low-level implementation other than a description of how the circuit is organized, since this process is performed at a different stage in the circuit implementation process.

[0146] The fact that many different low-level combinations of circuit elements can be used to implement the same specification for a circuit results in numerous equivalent structures for that circuit. As noted above, these low-level circuit implementations may vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methods to generate these different implementations may be arbitrary.

[0147] Furthermore, for a given embodiment, it is common for a single implementation of a circuit's particular functional specifications to include a large number of devices (e.g., millions of transistors). Thus, this absolute amount of information makes it impractical to exhaustively enumerate the low-level structures used to implement a single embodiment, let alone the vast number of equivalent possible implementations. For this reason, this disclosure describes the structure of a circuit using functional abbreviations used in the industry.

Claims

1. A semiconductor device, A substrate; a transistor having a gate region, a source region, and a drain region disposed above the substrate in a vertical dimension perpendicular to the substrate; a first metal layer disposed above the transistor in the vertical dimension; a second metal layer disposed below the transistor in the vertical dimension; a first via providing a vertical connection between the source region and the first metal layer; a second via providing a vertical connection between the source region and the second metal layer; a first rail connected to both the first metal layer and the second metal layer; a second rail connected to both the first metal layer and the second metal layer; the source region is coupled to at least one of the first rail and the second rail through both the first metal layer and the second metal layer; The semiconductor device, wherein the source region is disposed between the first via and the second via.

2. The semiconductor device according to claim 1 , wherein the first metal layer is disposed above the substrate.

3. The semiconductor device of claim 1 , wherein the second metal layer is disposed on a backside of the substrate.

4. The semiconductor device of claim 1 , wherein the first rail and the second rail are power rails connected to one or more power sources.

5. 2. The semiconductor device of claim 1, wherein the first rail and the second rail are signal rails for the source region.

6. 2. The semiconductor device of claim 1, wherein the source region is coupled to the first rail through the first via and the first metal layer and through the second via and the second metal layer.

7. a third via providing a vertical connection between the drain region and the first metal layer; a fourth via providing a vertical connection between the drain region and the second metal layer; The semiconductor device according to claim 1 , further comprising:

8. 8. The semiconductor device of claim 7, wherein the drain region is coupled to the second rail through the third via and the first metal layer and through the fourth via and the second metal layer.

9. The semiconductor device of claim 1 , further comprising at least one via connecting said gate region to at least one of said first metal layer and said second metal layer.

10. 1. A system configured to execute a plurality of instructions located on a computer-readable storage medium to produce an integrated circuit device, the integrated circuit device comprising: a semiconductor substrate; a transistor having a gate region, a source region, and a drain region disposed above the substrate in a vertical dimension perpendicular to the substrate; a first metal layer disposed above the transistor in the vertical dimension; a second metal layer disposed below the transistor in the vertical dimension; a first via providing a vertical connection between the source region and the first metal layer; a second via providing a vertical connection between the source region and the second metal layer; a third via providing a vertical connection between the drain region and the first metal layer; a fourth via providing a vertical connection between the drain region and the second metal layer; a first rail connected to both the first metal layer and the second metal layer; a second rail connected to both the first metal layer and the second metal layer; the source region is coupled to the first rail through the first via and the first metal layer and through the second via and the second metal layer; the drain region is coupled to the second rail through the third via and the first metal layer and through the fourth via and the second metal layer; the source region is disposed between the first via and the second via; The system, wherein the drain region is disposed between the third via and the fourth via.

11. 11. The system of claim 10, wherein the source region receives a first portion of current from a power source providing a supply voltage through the first metal layer and a second portion of the current from the power source providing the supply voltage through the second metal layer.

12. The system of claim 11 , wherein the first portion of the current and the second portion of the current are controlled based on resistances of the first metal layer and the second metal layer.

13. 11. The system of claim 10, wherein the first metal layer includes power routing coupled to the first rail and ground routing coupled to the second rail, the source region being coupled to the power routing in the first metal layer and the drain region being coupled to the ground routing in the first metal layer.

14. 11. The system of claim 10, wherein the second metal layer includes power routing coupled to the first rail and ground routing coupled to the second rail, the source region being coupled to the power routing in the second metal layer and the drain region being coupled to the ground routing in the second metal layer.

15. 1. An integrated circuit device comprising: a semiconductor substrate; a transistor having a gate region, a source region, and a drain region; a first metal layer disposed toward an upper side of the substrate and vertically above the transistor, the first metal layer having power and ground routing; a second metal layer disposed vertically below the transistor toward a backside of the substrate, the second metal layer having power and ground routing; a first contact between the power routing and the source region in the first metal layer; a second contact between the ground routing and the drain region in the first metal layer; a third contact between the power routing and the source region in the second metal layer; a fourth contact between the ground routing in the second metal layer and the drain region; the source region is disposed between the first contact and the third contact; the drain region is disposed between the second contact and the fourth contact.

16. 16. The device of claim 15, wherein the power routing and the ground routing in the first metal layer are coupled to a power supply.

17. 17. The device of claim 16, wherein the power routing and the ground routing in the second metal layer are coupled to the power supply.

18. 18. The device of claim 17, wherein the source region is configured to receive a first portion of the current from the power source via the power routing in the first metal layer, and the source region is configured to receive a second portion of the current from the power source via the power routing in the second metal layer.

19. 16. The device of claim 15, wherein the first contact and the second contact are disposed in a first insulating layer vertically above the transistor, and the third contact and the fourth contact are disposed in a second insulating layer vertically below the transistor.

20. 16. The device of claim 15, wherein the gate region is coupled to at least one of the first metal layer and the second metal layer using a via through an insulating layer above the transistor.

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