Imaging devices and electronic devices

Abstract

[Problem] To provide an imaging device and an electronic apparatus in which a decrease in aperture ratio is avoided while achieving size reduction. [Solution] An imaging device comprising: a plurality of pixels each including a photoelectric conversion portion; a floating diffusion that outputs a voltage corresponding to charge obtained by photoelectric conversion in the photoelectric conversion portion in the pixel; a current amplification portion for amplifying a current corresponding to the voltage of the floating diffusion; a storage portion for storing a signal corresponding to the current amplified by the current amplification portion; an analog-to-digital converter which is provided for each area pixel consisting of two or more pixels among the plurality of pixels, and which converts signals stored in two or more storage portions corresponding to the two or more pixels in the area pixel, into digital signals; a plurality of stacked regions in which the plurality of photoelectric conversion portions in the plurality of pixels, a plurality of the analog-digital converters, a plurality of the floating diffusions, a plurality of the current amplification portions, and a plurality of the storage portions are disposed; and a signal transfer portion for transmitting and receiving signals between the plurality of regions. The region in which the plurality of photoelectric conversion portions in the area pixel are disposed and the region in which the plurality of current amplification portions are disposed transmit and receive the voltages of the plurality of floating diffusions via respectively corresponding signal transfer portions.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and an electronic device. [Background technology]

[0002] Conventional image sensors generally use a rolling shutter method, in which image signals photoelectrically converted by the photoelectric conversion unit of each pixel are converted from analog to digital (hereinafter referred to as AD conversion) on a column-by-column basis, but this method poses the problem of image distortion due to differences in readout times for each column.To address this problem, a global shutter image sensor has been proposed, in which an AD conversion unit is provided for each pixel and AD conversion is performed simultaneously for all pixels (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-148528 Summary of the Invention [Problem to be solved by the invention]

[0004] However, global shutter image sensors require an AD conversion unit for each pixel, which increases pixel size and makes it difficult to miniaturize pixels. To address this issue, imaging devices have been proposed that perform area AD conversion, in which multiple pixels share an AD conversion unit.

[0005] Recently, as described in Patent Document 1, a technology has been put into practical use in which a photoelectric conversion unit and an AD conversion unit are arranged on separate substrates or separate layers, and signals are transmitted between the two substrates or multiple layers using vias, Cu-Cu connections, or the like. However, as the number of signals transmitted and received between multiple substrates or layers increases, the number of wirings on each substrate or layer increases, reducing the area allocated to the photoelectric conversion unit and the AD conversion unit. When the area allocated to the photoelectric conversion unit and the AD conversion unit decreases, problems arise, such as a decrease in the aperture ratio of the photoelectric conversion unit and difficulty in miniaturizing the photoelectric conversion unit and the AD conversion unit, making it difficult to increase the number of pixels.

[0006] When imaging devices that perform area AD conversion are arranged on multiple substrates or multiple layers, it is necessary to prevent the above-mentioned problems from occurring.

[0007] Therefore, the present disclosure provides an imaging device and electronic device that can suppress a decrease in aperture ratio and also enable miniaturization. [Means for solving the problem]

[0008] In order to solve the above problems, according to the present disclosure, there is provided a liquid crystal display device including: a plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; An imaging device, wherein a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units.

[0009] The current amplifiers, the storage units, and the analog-to-digital converters may be arranged in the same region among the regions.

[0010] The current amplifiers, the memory units, and the analog-to-digital converters may be arranged on the same layer within the same region.

[0011] The two or more current amplifiers and the two or more storage units belonging to the same area pixel may be arranged symmetrically along two opposing sides of the corresponding analog-to-digital converter.

[0012] The current amplifiers and analog-to-digital converters may be arranged on different layers from the storage units within the same region.

[0013] The plurality of storage units may be arranged in a wiring layer within the same region.

[0014] a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers, the plurality of memory units, and the plurality of analog-to-digital converters are arranged, The first region and the second region may transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission sections.

[0015] a first substrate having the first region; a second substrate having the second region; The first substrate and the second substrate may transmit and receive the voltage of the floating diffusion for each pixel via different signal transmission sections.

[0016] (9) The imaging device described in (1), wherein the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of memory units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions.

[0017] The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers and the plurality of memory units are arranged; a third region in which the plurality of analog-to-digital converters are disposed; The first region and the second region may transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission sections.

[0018] (11) The imaging device according to (10), wherein the plurality of current amplifiers and the plurality of memory units are arranged in the same layer within the second region.

[0019] a first substrate on which the first region and the second region are stacked; a second substrate having the third region; The first substrate and the second substrate may transmit and receive the signals stored in the storage units for each pixel via the signal transmission units that are different from each other.

[0020] The photoelectric conversion units, the current amplification units, the storage units, and the analog-to-digital converters may be arranged in different regions from each other among the regions.

[0021] The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers are arranged; a third area in which the plurality of storage units are arranged; a fourth region in which the plurality of analog-to-digital converters are disposed; The first region and the second region may transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission sections.

[0022] a first substrate on which the first region, the second region, and the third region are stacked; a second substrate having the fourth region; The first substrate and the second substrate may transmit and receive signals stored in the plurality of storage units via different signal transmission units for each pixel.

[0023] a first substrate on which the first region and the second region are stacked; a second substrate having the third region and the fourth region; The first substrate and the second substrate may transmit and receive the currents amplified by the plurality of current amplifiers via the signal transmission sections that are different for each pixel.

[0024] The photoelectric conversion units, the current amplification units, the storage units, and the analog-to-digital converters may be arranged in different regions from each other among the regions.

[0025] The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers are arranged; a third region in which the plurality of storage units and the plurality of analog-to-digital converters are arranged; The first region and the second region may transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission sections.

[0026] a first substrate on which the first region and the second region are stacked; a second substrate having the third region; The first substrate and the second substrate may transmit and receive the currents amplified by the plurality of current amplifiers for each pixel via the signal transmission sections that are different from each other.

[0027] The plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of analog-to-digital converters, and the plurality of storage units may be arranged in different regions among the plurality of regions.

[0028] The first region, the second region, and the third region may be stacked on the same substrate.

[0029] The photoelectric conversion portion may have a semiconductor layer made of silicon or a semiconductor layer made of a material other than silicon.

[0030] The signal transmission section may transmit and receive the signal through a via, a bump, or a Cu-Cu joint.

[0031] According to the present disclosure, an imaging device that outputs a digital signal for each pixel that has been photoelectrically converted; a signal processing unit that performs signal processing on the digital signal, The imaging device is a plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; An electronic device is provided in which the region in the area pixel where the multiple photoelectric conversion units are arranged and the region in which the multiple current amplification units are arranged transmit and receive the voltages of the multiple floating diffusions via the corresponding signal transmission units. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an imaging device according to an embodiment of the present technology. [Figure 2] FIG. 1 is a diagram showing an example of the configuration of a vertical drive unit according to an embodiment of the present technology. [Figure 3] FIG. 2 is a diagram showing an example of the configuration of a horizontal control unit according to an embodiment of the present technology. [Figure 4] FIG. 1 is a diagram showing an example of the configuration of an area pixel according to an embodiment of the present technology. [Figure 5] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion unit according to an embodiment of the present technology. [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a comparison unit according to an embodiment of the present technology. [Figure 7] FIG. 10 is a diagram showing an example of the configuration of a comparison output processing unit according to an embodiment of the present technology. [Figure 8] FIG. 2 is a diagram showing an example of the configuration of a conversion result holding unit according to an embodiment of the present technology. [Figure 9] FIG. 2 is a diagram showing an example of the configuration of a time code transfer unit according to an embodiment of the present technology. [Figure 10] FIG. 2 is a timing diagram of one frame period of the imaging device according to the present disclosure. [Figure 11] FIG. 3 is a circuit diagram of an area pixel according to a first example. [Figure 12]FIG. 3 is a cross-sectional view of an area pixel according to a first example. [Figure 13A] 13 is a plan view taken along line AA in FIG. 12. [Figure 13B] FIG. 13 is a plan view taken along line BB in FIG. 12. [Figure 14] FIG. 10 is a circuit diagram of an area pixel according to a second example. [Figure 15] FIG. 10 is a cross-sectional view of an area pixel according to a second example. [Figure 16A] 15. Plan view in the direction of line AA in FIG. [Figure 16B] FIG. 16 is a plan view taken along line BB in FIG. 15 . [Figure 17] FIG. 10 is a circuit diagram of an area pixel according to a third example. [Figure 18] FIG. 10 is a cross-sectional view of an area pixel according to a third example. [Figure 19A] Plan view in the direction of line AA in Figure 18. [Figure 19B] FIG. 19 is a plan view taken along line BB in FIG. 18. [Figure 20] FIG. 10 is a circuit diagram of an area pixel according to a fourth example. [Figure 21] FIG. 10 is a cross-sectional view of an area pixel according to a fourth example. [Figure 22A] Plan view in the direction of line AA in Figure 21. [Figure 22B] 22 is a plan view taken along line BB in FIG. 21. [Figure 23] FIG. 10 is a circuit diagram of an area pixel according to a fifth example. [Figure 24] FIG. 10 is a cross-sectional view of an area pixel according to a fifth example. [Figure 25A] Plan view in the direction of line AA in Figure 24. [Figure 25B] 25 is a plan view taken along line BB in FIG. 24. [Figure 25C] 25 is a plan view taken along line CC in FIG. 24. [Figure 26] FIG. 13 is a circuit diagram of an area pixel according to a sixth example. [Figure 27] FIG. 13 is a cross-sectional view of an area pixel according to a sixth example. [Figure 28A] Plan view in the direction of line AA in Figure 27. [Figure 28B] 28 is a plan view taken along line BB in FIG. 27. [Figure 28C]28 is a plan view taken along line CC in FIG. 27. [Figure 29] FIG. 13 is a circuit diagram of an area pixel according to a seventh example. [Figure 30] FIG. 13 is a cross-sectional view of an area pixel according to a seventh example. [Figure 31A] Plan view in the direction of line AA in Figure 30. [Figure 31B] 31 is a plan view taken along line BB in FIG. 30. [Figure 31C] 31 is a plan view taken along line CC in FIG. 30. [Figure 32] FIG. 13 is a circuit diagram of an area pixel according to an eighth example. [Figure 33] FIG. 13 is a cross-sectional view of an area pixel according to an eighth example. [Figure 34A] Plan view in the direction of line AA in Figure 33. [Figure 34B] 33. Plan view in the direction of line BB in FIG. [Figure 34C] Plan view in the direction of line CC in Figure 33. [Figure 35A] FIG. 10 is a circuit diagram of a photoelectric conversion unit, a current amplification unit, and a storage unit according to a first modified example. [Figure 35B] FIG. 10 is a circuit diagram of a photoelectric conversion unit, a current amplification unit, and a storage unit according to a second modified example. [Figure 35C] FIG. 10 is a circuit diagram of a photoelectric conversion unit, a current amplification unit, and a storage unit according to a third modified example. [Figure 35D] FIG. 10 is a circuit diagram of a photoelectric conversion unit, a current amplification unit, and a storage unit according to a fourth modified example. [Figure 36] FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 37] FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0033] Hereinafter, embodiments of an imaging device and an electronic device will be described with reference to the drawings. The following description will focus on the main components of the imaging device and the electronic device, but the imaging device and the electronic device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0034] [Configuration of imaging device] 1 is a diagram showing an example configuration of an imaging device 1 according to an embodiment of the present technology. The imaging device 1 includes a pixel array unit 10, a time code generation unit 20, a reference signal generation unit 30, a vertical drive unit 40, and a horizontal control unit 50.

[0035] The pixel array unit 10 includes a plurality of area pixels 100, and pixel signals are analog-to-digital converted (hereinafter referred to as AD conversion) for each area pixel 100. The area pixel 100 includes a plurality of pixels. Each pixel has a photoelectric conversion unit. As will be described later, the area pixel 100 includes one analog-to-digital conversion unit (hereinafter referred to as AD conversion unit). The AD conversion unit sequentially AD-converts analog pixel signals captured by each pixel in the area pixel 100, and outputs corresponding digital signals. Note that the area pixel 100 can also be called a pixel, and each photoelectric conversion unit in a pixel can also be called a sub-pixel or a color pixel.

[0036] The pixel array unit 10 includes area pixels 100 arranged in a two-dimensional matrix to generate pixel signals, and multiple time code transfer units 200 arranged between the multiple area pixels 100 arranged in the column direction. The area pixels 100 output time codes that are the result of pixel signal AD conversion of the analog pixel signals of each pixel. The time code transfer units 200 sequentially transfer these time codes in the column direction. The transferred time codes are input to the horizontal control unit 50. The signal line 101 connects the area pixels 100 and the time code transfer units 200. Details of the configurations of the area pixels 100 and the time code transfer units 200 will be described later.

[0037] The time code generation unit 20 generates a time code and outputs it to the time code transfer unit 200. Here, the time code is a code that indicates the elapsed time since the start of AD conversion in the area pixel 100. This time code has a size equal to the number of bits of the digital pixel signal after conversion, and a Gray code, for example, can be used. The time code is output to the time code transfer unit 200 via a signal line 21.

[0038] The reference signal generation unit 30 generates a reference signal and outputs it to the area pixel 100. This reference signal is a signal that serves as a reference for AD conversion in the area pixel 100, and can be, for example, a signal whose voltage decreases linearly over time (a ramp signal). This reference signal is output via a signal line 31. The time code generation unit 20 generates and outputs a time code in synchronization with the reference signal generation unit 30. This ensures a one-to-one correspondence between the time code and the reference signal output from the time code generation unit 20 and the reference signal generation unit 30, making it possible to obtain the voltage of the reference signal from the time code. The time code decoding unit 52, described later, performs decoding by obtaining the voltage of the reference signal from the time code.

[0039] The vertical driving section 40 generates and outputs control signals and the like for the area pixels 100. These control signals are output to the area pixels 100 via signal lines 41. The configuration of the vertical driving section 40 will be described in detail later.

[0040] The horizontal control unit 50 processes the time code transferred by the time code transfer unit 200. The time code is input to the horizontal control unit 50 via a signal line 11. The configuration of the horizontal control unit 50 will be described in detail later.

[0041] [Vertical control section configuration] 2 is a diagram showing an example of the configuration of the vertical drive unit 40 according to an embodiment of the present technology. The vertical drive unit 40 includes a control signal generation unit 42 and a power supply unit 43.

[0042] The control signal generation unit 42 generates and outputs control signals for the area pixels 100. The power supply unit 43 supplies power necessary for the operation of the area pixels 100. These control signals and power are transmitted via signal lines 41. As shown in the figure, the signal lines 41 are composed of multiple signal lines (OFG, OFD, TX, SEL1, SEL2, SEL3, SEL4, Vb, INI, WORD) and multiple power lines (VDDH, VBIAS). The signal lines (OFG, OFD, TX, SEL1, SEL2, SEL3, SEL4, Vb, INI, WORD) are connected to the control signal generation unit 42 and transmit control signals for the area pixels 100. Meanwhile, the power supply lines (VDDH, VBIAS) are connected to the power supply unit 43 and are used to supply power. Details of these signal lines will be described later.

[0043] [Configuration of horizontal control section] 3 is a diagram showing an example of the configuration of the horizontal control unit 50 according to an embodiment of the present technology. The horizontal control unit 50 includes a time code decoding unit 52, a column signal processing unit 53, and a clock signal generating unit .

[0044] The time code decoder 52 decodes the time code. This decoding generates a digital pixel signal that is the result of AD conversion. A plurality of time code decoders 52 are arranged in the horizontal control unit 50, and they correspond one-to-one to the time code transfer units 200 arranged in the pixel array unit 10. Time codes are simultaneously input to these time code decoders 52 from the corresponding time code transfer units 200. The input time codes are decoded simultaneously by these time code decoders 52 in parallel. The decoded digital pixel signals are then input to the column signal processor 53.

[0045] The column signal processing unit 53 processes the digital pixel signals output by the time code decoding unit 52. This processing can involve correlated double sampling (CDS), which will be described later. The column signal processing unit 53 also performs horizontal transfer of the processed digital pixel signals. This involves sequentially transferring and outputting processed pixel signals corresponding to the multiple digital pixel signals simultaneously input by the multiple time code decoding units 52. The pixel signals output from the column signal processing unit 53 are output signals of the imaging device 1 and correspond to digital pixel signals.

[0046] [Pixel configuration] 4 is a diagram showing a configuration example of an area pixel 100 according to an embodiment of the present technology. The area pixel 100 includes four photoelectric conversion units 110 (110a, 110b, 110c, and 110d) corresponding to four pixels, four current amplification units 90 (90a, 90b, 90c, and 90d), four storage units 92 (92a, 92b, 92c, and 92d), and an AD conversion unit (AD conversion unit) 190. As shown in FIG. 11 and other figures, which will be described later, each storage unit 92 includes a storage unit 19 that stores a P-phase signal and a storage unit 23 that stores a D-phase signal.

[0047] The photoelectric conversion unit 110 performs photoelectric conversion for each pixel to generate and store an analog pixel signal corresponding to incident light. The photoelectric conversion unit 110 is also controlled by the vertical drive unit 40 and inputs the stored analog pixel signal to the corresponding current amplifier 90. The current amplifier 90 amplifies the analog pixel signal and stores a charge corresponding to the amplified voltage in the corresponding memory unit 92. A voltage corresponding to the charge stored in the memory unit 92 is supplied to the comparison unit 150 of the AD conversion unit 190 via a signal line 102. The configuration of the photoelectric conversion unit 110 will be described in detail later. The comparison unit 150 has one input node, and voltages corresponding to the charges stored in the four memory units 92 corresponding to the four pixels are input to the comparison unit 150 sequentially.

[0048] The AD conversion unit 190 performs AD conversion on the analog pixel signals generated by the photoelectric conversion unit 110. The AD conversion unit 190 includes a comparison unit 150, a comparison output processing unit 160, and a conversion result holding unit 170.

[0049] The comparator 150 compares the reference signal generated by the reference signal generator 30 with the analog pixel signal output by the photoelectric converter 110. The comparison result is output to the comparison output processor 160 via signal line 106. The comparator 150 compares one of the multiple analog pixel signals output from the photoelectric converter 110 with the reference signal. That is, the comparator 150 compares the voltage of the analog pixel signal transmitted via one of the signal lines 102 to 105 with the voltage of the reference signal. The comparison result is output as an electrical signal. For example, the comparator 150 can output a signal with a value of "1" when the voltage of the analog pixel signal is smaller than the voltage of the reference signal, and a signal with a value of "0" when the voltage of the analog pixel signal is larger than the voltage of the reference signal. The configuration of the comparator 150 will be described in detail later.

[0050] The comparison output processing unit 160 processes the comparison result output by the comparison unit 150, and outputs the processed comparison result to the conversion result holding unit 170. The processed comparison result is output to the conversion result holding unit 170 via a signal line 107. This processing can include, for example, level conversion and waveform shaping.

[0051] The conversion result holding unit 170 holds the time code output from the time code transfer unit 200 as the result of AD conversion based on the processed comparison result output by the comparison output processing unit 160. This conversion result holding unit 170 holds the time code output from the time code transfer unit 200 when the comparison result changes, for example, from a value of "1" to a value of "0." This time code is the time code generated by the time code generation unit 20 and transferred to the area pixel 100 by the time code transfer unit 200. The conversion result holding unit 170 then outputs the held time code to the time code transfer unit 200 under the control of the vertical drive unit 40. The time code transfer unit 200 transfers this output time code to the time code decoding unit 52 of the horizontal control unit 50.

[0052] As described above, a signal that changes in a ramp pattern from high to low voltage is used as the reference signal, and the time code when the voltage of this reference signal transitions from a state higher than the voltage of the analog pixel signal to a state lower than the voltage of the analog pixel signal can be stored in the conversion result storage unit 170. In other words, the time code when the analog pixel signal and the reference signal become approximately equal is stored in the conversion result storage unit 170. The stored time code is converted into a digital signal representing the voltage of the reference signal at the corresponding time by the time code decoding unit 52. This allows AD conversion of the analog pixel signal generated by the photoelectric conversion unit 110.

[0053] [Configuration of photoelectric conversion unit] Fig. 5 is a circuit diagram showing an example of the internal configuration of the photoelectric conversion unit 110, current amplification unit 90, and memory unit 92 in each pixel in the area pixel 100. The photoelectric conversion unit 110, current amplification unit 90, and memory unit 92 in Fig. 5 show the internal configuration of one pixel, and the area pixel has four pixels each having a circuit diagram similar to Fig. 5.

[0054] The photoelectric conversion unit 110 has a photodiode 501 and transistors 502 and 503. The transistor 502 controls, using an OFG signal, to discharge excess charge generated in the photodiode 501 via an overflow drain signal line OFD. The transistor 503 controls, using a TXG signal, whether or not to temporarily store the charge generated in the photodiode 501 in a floating diffusion FD.

[0055] The current amplifier 90 has transistors 14 to 16 and a current source 17. The transistor 14 controls, using the RST signal, whether or not to initialize the floating diffusion FD connected to the gate of the charge-voltage conversion transistor 15 to a reset voltage. In this way, the node where the gate of the transistor 15 and the source of the transistor 14 are connected is the floating diffusion FD. As will be described later, the region where the photoelectric conversion unit 110 is arranged and the region where the current amplifier 90 is arranged are different regions, and these regions transmit and receive voltages of multiple floating diffusions FD.

[0056] The transistor 15 converts the charge generated by the photodiode 501 into a voltage based on the voltage of the floating diffusion FD. The source of the transistor 15 is connected to a selection transistor 16. The source of the selection transistor 16 is connected to a current source 17.

[0057] The memory unit 92 has memory units 19 and 23 each composed of a capacitor, a transistor 18 connected to the memory unit 19, and a transistor 22 connected to the memory unit 23. The source of the selection transistor 16 is connected to one end of each of the memory units 19 and 23. The drain of the transistor 18 is connected to the other end of the memory unit 19, and the drain of the transistor 22 is connected to the other end of the memory unit 23. As shown in FIG. 6, which will be described later, the sources of the transistors 18 and 22 are connected to the input node of the AD conversion unit 190 and the source of the transistor 13. The transistor 18 is controlled to be turned on or off by a signal S1, and the transistor 22 is controlled to be turned on or off by a signal S2.

[0058] The memory unit 19 is used to hold the P-phase level of the photoelectric conversion unit 110. The memory unit 23 is used to hold the D-phase level of the photodiode. The memory units 19 and 23 of all pixels simultaneously store the P-phase level and D-phase level. This enables a global shutter.

[0059] [Comparator configuration] 6 is a diagram showing an example configuration of a comparison unit 150 according to an embodiment of the present technology. The comparison unit 150 includes a signal input transistor 12, a reference input transistor 157, and MOS transistors 13, 151, and 152. Here, P-channel MOS transistors can be used for the MOS transistors 151 and 152. N-channel MOS transistors can be used for the MOS transistors 12 and 157.

[0060] Furthermore, in addition to the above-mentioned signal line 102, etc., a plurality of signal lines (Vb, REF) and a power supply line VDDH are connected to the comparison unit 150. The bias signal line Vb (Bias) is a signal line that supplies a bias voltage to the MOS transistor 158. The reference signal line REF (Reference) is a signal line that transmits a reference signal to the reference input transistor 157. The power supply line VDDH is a power supply line that supplies power to the comparison unit 150.

[0061] The sources of the MOS transistors 151 and 152 are commonly connected to the power supply line VDDH. The gate of the MOS transistor 151 is connected to the gate and drain of the MOS transistor 152 and the drain of the reference input transistor 157. The drain of the MOS transistor 151 is connected to the drain of the signal input transistor 12 and the signal line 106. The source of the signal input transistor 12 and the source of the reference input transistor 157 are commonly connected to the drain of the MOS transistor 158. The gate of the MOS transistor 158 is connected to the bias signal line Vb, and the source is grounded. The gate of the MOS transistor 12 is connected to the signal line 102. The MOS transistor 13 shorts the gate and drain of the MOS transistor 12 when the reset signal RST is at a high level. The gate of the reference input transistor 157 is connected to the reference signal line REF.

[0062] The signal input transistor 12 is a MOS transistor having a gate that serves as a control terminal to which an input signal is input. An analog pixel signal is input as an input signal to the gate of the signal input transistor 12 in the figure.

[0063] The reference input transistor 157 is a MOS transistor whose gate, which serves as a control terminal, receives a reference signal. This reference input transistor 157 forms a differential pair with the signal input transistor 12. This differential pair compares the input signal and the reference signal. Specifically, when the input signal is smaller than the reference signal, the current flowing through the reference input transistor 157 is greater than the current flowing through the signal input transistor 12. Conversely, when the input signal is greater than the reference signal, the current flowing through the reference input transistor 157 is smaller than the current flowing through the signal input transistor 12. In this way, a current corresponding to the difference between the input signal and the reference signal flows through the signal input transistor 12 and the reference input transistor 157, which form the differential pair.

[0064] When the current flowing through either the signal input transistor 12 or the reference input transistor 157 changes in accordance with the difference between the input signal and the reference signal, the MOS transistor 151 converts this change in current into a change in voltage. The MOS transistor 152 also converts a change in current flowing through the reference input transistor 157 into a change in voltage. These MOS transistors 151 and 152 form a current mirror circuit. This current mirror circuit operates so that a current equal to the current flowing through the reference input transistor 157 flows through the signal input transistor 12. This allows the input signal and the reference signal to be compared at high speed.

[0065] The MOS transistor 158 controls the current flowing through the signal input transistor 12 and the reference input transistor 157, which form a differential pair. A predetermined bias voltage is supplied to the gate of the MOS transistor 158 through a bias signal line Vb. This causes the MOS transistor 158 to operate as a constant current power supply.

[0066] In this way, the comparison unit 150 in the same figure can perform a comparison operation between the pixel signal input to the gate of the signal input transistor 12 and the reference signal input to the gate of the reference input transistor 157.

[0067] Selection Method First, the voltage of the reference signal line REF is set to 0V. This puts the reference input transistor 157 into a non-conducting state. Then, due to the action of the differential amplifier circuit formed by the signal input transistor 12, the reference input transistor 157, and the MOS transistor 158, the drain of the signal input transistor 12 has a voltage close to 0V. Next, the reset signal RST is set to high level to turn on the MOS transistor 13. This forms a feedback circuit, and the drain of the signal input transistor 12 has a voltage of approximately 0V. Then, the floating diffusion FD of the photoelectric conversion unit 110 connected to the signal line 102 is discharged, and the voltage of the signal line 102 becomes 0V.

[0068] The current mirror circuit consisting of MOS transistors 151 and 152 can further enhance the effect of setting the drain of the signal input transistor 12 to 0 V. In other words, when the voltage of the reference signal line REF is set to 0 V, the current flowing through the MOS transistor 152 becomes approximately 0 A. Because the MOS transistor 151 forms a current mirror circuit with the MOS transistor 152, the current flowing through the MOS transistor 151 also becomes approximately 0 A. This makes it possible to more accurately set the drain voltage of the signal input transistor 12 to 0 V.

[0069] The MOS transistor 13 also has the function of resetting the floating diffusion FD of the photoelectric conversion unit 110. This reset can be performed as follows. First, a voltage equivalent to the reset voltage of the floating diffusion FD is applied to the reference signal line REF. This causes the reference input transistor 157 to become conductive. Due to the actions of the differential amplifier circuit and current mirror circuit described above, the voltage at the drain of the MOS transistor 13 also becomes approximately equal to the reset voltage. Next, the reset signal RST is set to a high level, causing the MOS transistor 13 to become conductive. This applies a reset voltage to the floating diffusion FD of the photoelectric conversion unit 110, thereby resetting it.

[0070] As described above, in one embodiment of the present technology, the floating diffusion FD is reset by the MOS transistor 13. This can simplify the configuration of the AD conversion unit 190. Furthermore, by using a current mirror circuit, the gain in the differential amplifier circuit can be improved, and the floating diffusion FD can be reset more accurately.

[0071] The configuration of the comparison unit 150 is not limited to this example. For example, a resistive load or a constant current power supply can be used instead of the MOS transistors 151 and 152 that form the current mirror circuit. In this case, the resistive load or the like can be connected to either one or both of the signal input transistor 12 and the reference input transistor 157 of the differential pair.

[0072] [Configuration of comparison output processing section] FIG. 7 is a diagram illustrating a configuration example of a comparison output processing unit 160 according to an embodiment of the present technology. The comparison output processing unit 160 includes MOS transistors 511 to 517. Here, the MOS transistors 511, 513, and 515 can be configured as P-channel MOS transistors. Furthermore, the MOS transistors 512, 514, 516, and 517 can be configured as N-channel MOS transistors. The MOS transistor 511 configures a pre-amplifier unit 161. The MOS transistor 512 configures a level converter unit 162. The MOS transistors 513 to 517 configure a waveform shaping unit 163. In addition to the signal lines 106 and 107 described above, an initialization signal line INI (Initialize) and power supply lines (VDDH and VBIAS) are connected to the comparison output processing unit 160. The initialization signal line INI is a signal line that transmits a control signal to the MOS transistors 513 and 516. The power supply lines VDDH and VBIAS are power supply lines that supply power to the comparison output processing unit 160.

[0073] The source and gate of MOS transistor 511 are connected to the power supply line VDDH and signal line 106, respectively. The drain of MOS transistor 511 is connected to the drain of MOS transistor 512. The gate of MOS transistor 512 is connected to the power supply line VBIAS, and the source is connected to the drains of MOS transistors 514 and 516 and the gates of MOS transistors 515 and 517. The gates of MOS transistors 513 and 516 are commonly connected to an initialization signal line INI. The source and drain of MOS transistor 513 are connected to the power supply line VBIAS and the source of MOS transistor 514, respectively. The source of MOS transistor 516 is grounded. The gate of MOS transistor 514 is connected to the drains of MOS transistors 515 and 517 and signal line 107. The source of MOS transistor 515 is connected to the power supply line VBIAS, and the source of MOS transistor 517 is grounded.

[0074] The preamplifier 161 amplifies a signal corresponding to the comparison result output by the comparator 150. The preamplifier 161 outputs the amplified signal to the level converter 162. This amplification is performed by a MOS transistor 511.

[0075] The level conversion unit 162 converts the level of the signal output by the preamplifier unit 161. The comparator unit 150 and preamplifier unit 161 described in FIG. 6 are connected to a power supply line VDDH. To obtain high gain in the comparator unit 150 and preamplifier unit 161, the power supply line VDDH must be a relatively high voltage. On the other hand, the downstream conversion result holder unit 170 and other units handle digital signals, so a relatively low voltage power supply can be used. This relatively low power supply is supplied via a power supply line VBIAS. This reduces power consumption in the conversion result holder unit 170 and other units and enables the use of low-voltage transistors in the conversion result holder unit 170 and other units. The level conversion unit 162 is thus provided to transmit signals between circuits supplied with power supplies of different voltages. The level-converted signal is then output to the waveform shaping unit 163. The level conversion unit 162 in FIG. 6 limits the signal level to a voltage obtained by subtracting the threshold voltage of the MOS transistor 512 from the power supply voltage supplied via the power supply line VBIAS.

[0076] The waveform shaping unit 163 shapes the signal output by the level conversion unit 162 into a signal with a steep change. The operation of this waveform shaping unit 163 will be described. In the initial state, the output of the level conversion unit 162 has a value of "0." In this state, a signal with a value of "1" is input from the initialization signal line INI, causing the MOS transistor 516 to become conductive. As a result, the MOS transistor 517 becomes non-conductive, the MOS transistor 515 becomes conductive, and the value "1" is output to the signal line 107. At this time, the MOS transistors 513 and 514 become non-conductive. Thereafter, a signal with a value of "0" is input to the initialization signal line INI. As a result, the MOS transistor 513 becomes conductive, and the MOS transistor 516 becomes non-conductive. Since the MOS transistor 514 is non-conductive and the output signal of the level conversion unit 162 has a value of "0," the states of the MOS transistors 515 and 517 do not change.

[0077] Next, when the output signal of the level conversion unit 162 changes from the value "0" to "1," the MOS transistor 517 transitions to the conductive state, and the MOS transistor 515 transitions to the non-conductive state. This causes the voltage of the signal line 107 to drop. As a result, the MOS transistor 514 transitions to the conductive state, and the voltages of the gates of the MOS transistors 515 and 517 further increase. This positive feedback action causes the voltage of the signal line 107 to drop sharply. This allows the waveform to be shaped.

[0078] [Configuration of conversion result storage unit] FIG. 8 is a diagram showing an example configuration of the conversion result holding unit 170 according to an embodiment of the present technology. The conversion result holding unit 170 includes a memory control unit 171 and memory units 172 to 179. For convenience, it is assumed that the digital pixel signal after AD conversion is 8-bit data. Therefore, the size of the time code is also 8 bits. Note that the sizes of the converted digital pixel signal and time code can be changed according to the requirements of the system. For example, they can be 15 bits in size.

[0079] In addition to the signal line 107, multiple signal lines (WORD, CODE1 to 8) are connected to the conversion result holding unit 170. The word signal line WORD (Word) is a signal line that transmits control signals for the memory units 172 to 179. The code signal lines CODE (Code) 1 to 8 are signal lines that transmit time codes in both directions. These multiple code signal lines CODE1 to 8 constitute the signal line 101.

[0080] The storage units 172 to 179 store the time code input from the time code transfer unit 200. The storage units 172 to 179 each store a 1-bit time code. The configuration of the storage units 172 to 179 will be explained using the storage unit 172 as an example. The storage unit 172 includes a bit storage unit 522 and a bidirectional switch 523.

[0081] The bidirectional switch 523 is connected between the signal line 526 and the code signal line CODE1, and transmits data in both directions. The bidirectional switch 523 also has a control input terminal. A signal line 524 is connected to the control input terminal. When a value "1" is input to the control input terminal via the signal line 524, the bidirectional switch 523 becomes conductive, and data can be transmitted in both directions between the signal line 526 and the code signal line CODE1. On the other hand, when a value "0" is input to the control input terminal, the bidirectional switch 523 becomes non-conductive.

[0082] The bit storage unit 522 is a storage device that stores one bit of data. This bit storage unit 522 has input / output terminals and a control input terminal, to which signal lines 526 and 107 are connected, respectively. When a signal with a value of "1" is input to the control input terminal via signal line 107, the bit storage unit 522 stores a one-bit time code, which is a signal transmitted from the bidirectional switch 523 via signal line 526. If the one-bit time code changes, the data stored in the bit storage unit 522 is rewritten. Thereafter, when the signal input to the control input terminal changes from a value of "1" to a value of "0," the data stored in the bit storage unit 522 is retained. In other words, the data is not rewritten until the next signal input to the control input terminal becomes a value of "1." Furthermore, when the signal input to the control input terminal is a value of "0," the bit storage unit 522 outputs the retained data to the signal line 526.

[0083] The storage control unit 171 outputs a control signal via a signal line 524 to control the storage units 172 to 179. The storage control unit 171 can generate and output, as a control signal for the bidirectional switch 523, a signal obtained by the logical sum of two signals input via the word signal line WORD and the signal line 107. This can be performed by an OR gate 521.

[0084] [Configuration of time code transfer section] 9 is a diagram showing an example configuration of a time code transfer unit 200 according to an embodiment of the present technology. The time code transfer unit 200 includes code holding units 210 and 230 and clock buffers 220 and 240. The time code transfer unit 200 has the same number of code holding units and clock buffers as the number of rows of the area pixels 100 arranged in the pixel array unit 10 described in FIG. 1. For convenience, the code holding units 210 and 230 and the clock buffers 220 and 240 will be described as examples.

[0085] The code holding unit 210 holds the time code. This code holding unit 210 is composed of flip-flops 211 to 218. The flip-flops 211 and others hold one bit of the time code based on the clock signal output from the clock buffer 220. Specifically, when the clock signal is "0," the time code output from the time code generation unit 20 and input to the D input terminal in the same figure is held in an internal node, and the Q output terminal is set to a high impedance state. Next, when the clock signal becomes "1," the time code held in the internal node is output from the Q output terminal. This output time code is input to the code holding unit 230 via signal line 101. In this way, the time code transfer unit 200 operates multiple time code holding units as shift registers to transfer the time code.

[0086] The clock buffer 220 outputs the clock signal generated by the clock signal generation unit 54 described in FIG. 3 to the code holding unit 210 and also to the next-stage clock buffer. This clock buffer 220 is composed of multiple inverting gates 221 to 224 and operates as a repeater that reshapes a degraded clock signal. Furthermore, this clock buffer 220 is sequentially transferred in the reverse direction of the time code in the time code transfer unit 200. That is, the clock buffer 240 outputs a clock signal to the code holding unit 230 and also outputs a clock signal to the clock buffer 220. As a result, the clock signal input to the code holding unit 210 has a delay corresponding to the propagation delay time of two inverting gates and the delay due to the wiring to the inverting gate 224, compared to the clock signal input to the code holding unit 230. In this way, the clock buffer 220 also has a function of delaying the clock signal.

[0087] As described above, the flip-flop 211 and other devices hold the input time code at an internal node when the clock signal is at value "0." During this holding, a predetermined period of time, known as setup time, must be ensured. When the clock signal transitions to value "0" in the code holding unit 230 due to a delay in the clock signal caused by the clock buffer 220, the clock signal input to the code holding unit 210 remains at value "1." In other words, the time code held at the internal node remains in an output state. This allows the code holding unit 230 to ensure setup time, enabling the time code to be transmitted.

[0088] Code signal lines CODE1 to 8 are connected to the output of the code holding unit 210 and the input of the code holding unit 230, respectively. As a result, the time codes generated by the time code generation unit 20 and held in the code holding unit 210 are output to the conversion result holding unit 170 via these code signal lines CODE1 to 8. Furthermore, the time codes held in the conversion result holding unit 170 after AD conversion are output to the code holding unit 230 via these code signal lines CODE1 to 8. In this way, the time code transfer unit 200 transfers the time codes. Next, we will explain the internal structure of the area pixel 100. There are various possibilities for the internal structure of the area pixel 100, so below we will explain representative internal structures in order.

[0089] (Image capture timing of the image capture device) Fig. 10 is a timing diagram of one frame period of the imaging device according to the present disclosure. The imaging device according to the present disclosure exposes all pixels simultaneously using a global shutter system, and outputs the exposed pixel signals by AD converting them on an area pixel basis. The upper half of Fig. 10 shows the timing of one frame period (times T3 to T7) from the start of exposure at time T1. The lower half of Fig. 10 is a timing diagram showing the operation from times T4 to T5 in detail.

[0090] The period from time T1 to T2 is an exposure period. Just before time T1, the OFG signal goes high, turning on the transistor 502, and the charge in the photodiode 501 is discharged via the overflow drain signal line OFD. During the exposure period from T1 to T2, the photodiode 501 continues to perform photoelectric conversion and accumulates charge. At time T2, the transfer signal TXG goes high, turning on the transistor 503, and the charge photoelectrically converted by the photodiode 501 is held in the floating diffusion FD. The holding operation in the floating diffusion FD is performed simultaneously for all pixels.

[0091] After that, the four pixels in the area pixel are read out sequentially. In Fig. 10, pixel A in the area pixel is read out at times T3 to T4, pixel B in the area pixel is read out at times T4 to T5, pixel C in the area pixel is read out at times T5 to T6, and pixel D in the area pixel is read out at times T6 to T7.

[0092] The readout operation of pixel B will be described in detail below. In the timing diagram in the lower half of Fig. 10, signal RB is a reset signal RST input to the gate of transistor 13 in pixel B. Signal SEL_B is a select signal SW input to the gate of transistor 16 in pixel B. Signal S1_B is a signal S1 input to the gate of transistor 18 in pixel B. Signal S2_B is a signal S2 input to the gate of transistor 23 in pixel B.

[0093] When signal RB goes high at time t1, the drain voltage of transistor 12 in AD conversion unit 190 is initialized. Furthermore, while pixel B is being read (times t1 to t11), transistor 16 is in the on state. Thereafter, signal S1_B goes high, transistor 18 is turned on, and the P-phase signal is stored in storage unit 19. The P-phase signal stored in storage unit 19 is input to the gate of transistor 12. The period from times t1 to t6 is a period during which the P-phase signal is compared with a reference signal and converted into a digital signal.

[0094] Between times t2 and t4, a reference signal REF consisting of a ramp wave whose signal level changes linearly is input to the gate of the transistor 157. When the signal level of the P-phase signal exceeds the signal level of the reference signal REF, the drain voltage of the transistor 12 of the differential pair decreases, the drain voltage of the transistor 151 increases, and the output signal VCO of the AD conversion unit goes low (time t3).

[0095] After that, when the signal RB goes high at time t6, the drain voltage of the transistor 12 in the AD conversion unit is initialized. After that, the signal S2_B goes high, the transistor 23 is turned on, and the D-phase signal is stored in the memory unit 23.

[0096] The period from time t7 to t11 is a period during which the D-phase signal is compared with a reference signal and converted into a digital signal. Between times t7 to t9, a reference signal REF consisting of a ramp wave whose signal level changes linearly is input to the gate of transistor 157. When the signal level of the D-phase signal exceeds the signal level of reference signal REF, the drain voltage of transistor 12 of the differential pair decreases, the drain voltage of transistor 151 increases, and the output signal VCO of the AD conversion unit goes low (time t8).

[0097] In this way, the AD conversion unit compares the P-phase signal stored in the memory unit 19 and the D-phase signal stored in the memory unit 23 with the reference signal, and outputs a signal VCO that indicates timing that matches the reference signal.

[0098] (First example of area pixel 100) Fig. 11 is a circuit diagram of an area pixel 100 according to a first example, Fig. 12 is a cross-sectional view of the area pixel 100 according to the first example, Fig. 13A is a plan view taken along line AA in Fig. 12, and Fig. 13B is a plan view taken along line BB in Fig. 12. Figs. 11, 12, 13A, and 13B show examples in which the area pixel 100 has four pixels. The imaging device 1 including the area pixel 100 according to the first example employs a global shutter system, and memory units 19 and 23 are connected to the photoelectric conversion unit 110 in each pixel.

[0099] 11 includes a plurality of photoelectric conversion units 110, a plurality of current amplification units 90, a plurality of memory units 19 and 23, and an AD conversion unit 190. The plurality of photoelectric conversion units 110, the plurality of current amplification units 90, and the plurality of memory units 19 and 23 share one AD conversion unit 190. The circuit configuration within the area pixel 100 in FIG. 11 is the same as the circuit configuration in FIGS. 5 and 6.

[0100] The photoelectric conversion unit 110 in the area pixel 100 in FIG. 11 has a photodiode 501 and transistors 502 and 503, similar to FIG. 5. The current amplification unit 90 has transistors 14 to 17 and a current source 17. The gate of the transistor 15 is connected to a floating diffusion FD. The storage unit 19 is used to store a P-phase signal. The storage unit 23 is used to store a D-phase signal.

[0101] As shown in FIG. 12, an imaging device 1 having an area pixel 100 according to the first example includes a first region AR1 in which a photoelectric conversion unit 110 is disposed, and a second region AR2 in which a current amplification unit 90, memory units 19 and 23, and an AD conversion unit 190 are disposed. The first region AR1 and the second region AR2 each have a semiconductor layer made of silicon. The first region AR1 is disposed on a first substrate SUB1. The second region AR2 is disposed on a second substrate SUB2. The first region AR1 occupies the entire surface of the first substrate SUB1, and the second region AR2 occupies the entire surface of the second substrate SUB2. The first region AR1 and the second region AR2 have the same area.

[0102] 12, a wiring layer 71, a photoelectric conversion unit 110, a color filter 72, and an on-chip lens 73 are stacked on the first substrate SUB1. An element isolation layer 74 is disposed between the pixels. A wiring layer 75, a current amplification unit 90, an AD conversion unit 190, and a protective layer 76 are stacked on the second substrate SUB2. The layer configuration of the first substrate SUB1 and the second substrate SUB2 shown in FIG. 12 is one example, and various modifications are possible.

[0103] 12 and 13A, a plurality of photoelectric conversion units 110 are arranged in the first region AR1. The photoelectric conversion units 110 are arranged over the entire first region AR1. As shown in FIG. 11, a voltage signal of the floating diffusion FD is output from the first region AR1 and input to the second region AR2.

[0104] As shown in FIGS. 12 and 13B, the second region AR2 is provided with memory units 19 and 23, a current amplifier unit 90, and an AD converter unit 190. In the second region AR2, the memory units 19 and 23 and the current amplifier unit 90 are provided for each pixel, and the AD converter unit 190 is shared by multiple pixels. The memory units 19 and 23 are arranged on a layer on the second substrate SUB2 different from the layer on which the current amplifier unit 90 and the AD converter unit 190 are arranged. In this manner, the second region AR2 is formed by stacking multiple layers. As shown in FIG. 13B, on the layer on which the multiple current amplifier units 90 and the AD converter unit 190 are arranged, the multiple current amplifier units 90 are arranged separately from each other, and the AD converter unit 190 is arranged in the region where the multiple current amplifier units 90 are not arranged.

[0105] The first region AR1 and the second region AR2 transmit and receive various signals via a signal transmission section 91 extending in the stacking direction. The signal transmission section 91 transmits and receives the voltage of the floating diffusion between the first substrate AR1 and the second substrate AR2, for example, by a Cu-Cu connection 91a. Note that the signal transmission section 91 may transmit and receive the voltage of the floating diffusion using other bonding means, such as bumps, in addition to the Cu-Cu connection.

[0106] As described above, in the area pixel 100 according to the first example, the photoelectric conversion unit 110 is arranged in the first region AR1, and the memories 19 and 23, the current amplifier 90, and the AD converter 190 are arranged in the second region AR2, and the first region AR1 and the second region AR2 transmit and receive the voltage of the floating diffusion FD. Because the entire first region AR1 is used as the arrangement region for the photoelectric conversion unit 110, the area of ​​the photoelectric conversion unit 110 can be increased, which increases the aperture ratio and improves the resolution by miniaturizing the area pixel 100.

[0107] Furthermore, by forming the second region AR2 into a stacked structure, the layout area of ​​the storage units 19, 23, the current amplifier unit 90, and the AD conversion unit 190 can be increased.

[0108] (Second example of area pixel 100) Fig. 14 is a circuit diagram of the area pixel 100 according to the second example, Fig. 15 is a cross-sectional view of the area pixel 100 according to the second example, Fig. 16A is a plan view taken along line AA in Fig. 15, and Fig. 16B is a plan view taken along line BB in Fig. 15. The following description will focus on the differences from the area pixel 100 according to the first example.

[0109] The area pixel 100 according to the second example has a first region AR1 and a second region AR2 that are stacked, and is the same as the first example in that the photoelectric conversion unit 110 is disposed in the first region AR1. The second example differs from the first example in the layout arrangement of the second region AR2. The circuit diagram of the second example in FIG. 14 is the same as the circuit diagram of the first example in FIG. 11, but the cross-sectional structure and planar configuration of the second example differ from those of the first example.

[0110] 15 and 16B, in the second region AR2, the memory units 19 and 23, the current amplifier unit 90, and the AD converter unit 190 are arranged on the same layer. As shown in Fig. 16B, the current amplifier units 90 and the memory units 19 and 23 for four pixels are arranged symmetrically along two opposing sides of the rectangular range of the area pixel 100, with the AD converter unit 190 arranged in the middle thereof. Although the AD converter unit 190 is not shown in the cross-sectional view of Fig. 15, in reality, the AD converter unit 190 is arranged on the back side of the cross section of Fig. 15, as shown in Fig. 16B.

[0111] In the area pixel 100 according to the second example, the first region AR1 is also disposed on the first substrate SUB1, and the second region AR2 is also disposed on the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 transmit and receive the voltage of the floating diffusion FD of the photoelectric conversion unit 110 via a signal transmission unit 91 formed of a Cu-Cu connection 91a.

[0112] (Third example of area pixel 100) Fig. 17 is a circuit diagram of an area pixel 100 according to a third example, Fig. 18 is a cross-sectional view of the area pixel 100 according to the third example, Fig. 19A is a plan view taken along line AA in Fig. 18, and Fig. 19B is a plan view taken along line BB in Fig. 18. Figs. 17, 18, 19A, and 19B show examples in which the area pixel 100 has four pixels.

[0113] The area pixel 100 according to the third example has a photoelectric conversion unit 110 made of a material other than silicon. The material other than silicon is, for example, an organic material. Thus, the photoelectric conversion unit 110 of the third example has a semiconductor layer containing a material other than silicon. More specifically, as shown in FIG. 18, the photoelectric conversion unit 110 of the third example has a structure in which an upper electrode layer 11a, a photoelectric conversion layer 11b, an insulating layer 11d, and a lower electrode layer 11e are stacked. The material of the upper electrode layer 11a and the lower electrode layer 11e is, for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0114] The circuit diagram shown in FIG. 17 is the same as the circuit diagram in FIG. 11 except that the type of photoelectric conversion unit 110 is different.

[0115] The area pixel 100 according to the third example includes a first region AR1 and a second region AR2 that are stacked together. A photoelectric conversion unit 110 made of a material other than silicon is disposed in the first region AR1. Memory units 19 and 23, a current amplification unit 90, and an AD conversion unit 190 made of silicon are disposed in the second region AR2. As shown in FIG. 18 , the current amplification unit 90, the memory units 19 and 23, and the AD conversion unit 190 are disposed on the same layer. A wiring layer 71 is disposed below this layer, and a protective layer 76 is disposed below that.

[0116] The first area AR1 and the second area AR2 are stacked on the same substrate. In the second area AR2, the memory units 19 and 23 and the current amplifier unit 90 are provided for each pixel, and the AD conversion unit 190 is shared by multiple pixels.

[0117] The first region AR1 and the second region AR2 transmit and receive the voltage of the floating diffusion FD of the photoelectric conversion unit 110 for each pixel in the area pixel 100 via the signal transmission unit 91 made up of the via 91b.

[0118] 19A, the photoelectric conversion units 110 arranged in the first region AR1 are arranged over the entire rectangular range of the area pixel 100. In the second region AR2, as shown in FIG. 19B, current amplification units 90 and memory units 19, 23 for four pixels are arranged symmetrically along two opposing sides of the rectangular range of the area pixel 100, and an AD conversion unit 190 is arranged in the middle thereof.

[0119] (Fourth example of area pixel 100) Fig. 20 is a circuit diagram of the area pixel 100 according to the fourth example, Fig. 21 is a cross-sectional view of the area pixel 100 according to the fourth example, Fig. 22A is a plan view taken along line AA in Fig. 21, and Fig. 22B is a plan view taken along line BB in Fig. 21. The following description will focus on the differences from the area pixel 100 according to the third example.

[0120] The circuit diagram of Fig. 20 for the fourth example is the same as the circuit diagram of Fig. 17 for the third example. The area pixel 100 according to the fourth example includes a first region AR1, a second region AR2, and a third region AR3 that are stacked one on the other. A photoelectric conversion unit 110 made of a material other than silicon is disposed in the first region AR1. A current amplification unit 90 and an AD conversion unit 190 made of silicon are disposed in the second region AR2. Memory units 19 and 23 made of silicon are disposed in the third region AR3.

[0121] The first region AR1, the second region AR2, and the third region AR3 are stacked on the same substrate. The first region AR1 and the second region AR2 transmit and receive the voltage of the floating diffusion FD of the photoelectric conversion unit 110 for each pixel through the signal transmission unit 91 formed by the via 91b. The second region AR2 and the third region AR3 transmit and receive the voltage across the memory units 19 and 23 for each area pixel 100 through the signal transmission unit 91 formed by the via 91b.

[0122] In the fourth example, the memory units 19 and 23 are arranged in a third area AR3 separate from the second area AR2 in which the AD conversion unit 190 and the current amplification unit 90 are arranged, thereby making it possible to increase the arrangement area of ​​the AD conversion unit 190 and the current amplification unit 90.

[0123] (Fifth example of area pixel 100) Fig. 23 is a circuit diagram of an area pixel 100 according to a fifth example, Fig. 24 is a cross-sectional view of the area pixel 100 according to the fifth example, Fig. 25A is a plan view taken along line AA in Fig. 24, Fig. 25B is a plan view taken along line BB in Fig. 24, and Fig. 25C is a plan view taken along line CC in Fig. 24. Figs. 23, 24, 25A, and 25B show examples in which the area pixel 100 has four pixels.

[0124] The area pixel 100 according to the fifth example has a photoelectric conversion unit 110 made of a material other than silicon, similar to the third and fourth examples. The layer structure of the photoelectric conversion unit 110 is also similar to the third and fourth examples. The circuit diagram of FIG. 23 according to the fifth example differs from the circuit diagram of FIG. 20 according to the fourth example in that a signal transmission unit 91 that transmits and receives signals is provided between the storage units 19, 23 and the AD conversion unit 190.

[0125] As shown in FIG. 24, the area pixel 100 according to the fifth example includes a first region AR1, a second region AR2, and a third region AR3 that are stacked together. The first region AR1 includes a photoelectric conversion unit 110 made of a material other than silicon. The second region AR2 includes a current amplification unit 90 and memory units 19 and 23 made of silicon. The third region AR3 includes an AD conversion unit 190 made of silicon. In the second region AR2, the memory units 19 and 23 and the current amplification unit 90 are provided for each pixel, and the AD conversion unit 190 is shared by multiple pixels. The first region AR1 and the second region AR2 are stacked on a first substrate SUB1. The third region AR3 is stacked on a second substrate SUB2.

[0126] As described above, the area pixel 100 according to the fifth example differs from the area pixel 100 according to the third and fourth examples in the circuits arranged in the second area AR2 and the third area AR3.

[0127] The first region AR1 and the second region AR2 transmit and receive, for each pixel, a voltage of the floating diffusion FD of the photoelectric conversion unit 110 via a signal transmission unit 91 made of a via 91b. The second region AR2 and the third region AR3 transmit and receive, for each area pixel 100, a voltage according to the charge stored in the memory units 19 and 23 via a signal transmission unit 91 made of a Cu-Cu connection 91a.

[0128] In this way, in the area pixel 100 according to the fifth example, the AD conversion unit 190 is disposed in the third area AR3, and therefore the area in which the AD conversion unit 190 is disposed can be increased.

[0129] (Sixth example of area pixel 100) Fig. 26 is a circuit diagram of the area pixel 100 according to the sixth example, Fig. 27 is a cross-sectional view of the area pixel 100 according to the sixth example, Fig. 28A is a plan view taken along line AA in Fig. 27, Fig. 28B is a plan view taken along line BB in Fig. 27, and Fig. 28C is a plan view taken along line CC in Fig. 27. The following description will focus on the differences from the area pixel 100 according to the fifth example.

[0130] The circuit diagram of FIG. 26 for the sixth example is the same as the circuit of FIG. 23 for the fifth example. The area pixel 100 of the sixth example has a first region AR1, a second region AR2, a third region AR3, and a fourth region AR4 that are stacked together. A photoelectric conversion unit 110 made of a material other than silicon is arranged in the first region AR1. A current amplification unit 90 made of silicon is arranged in the second region AR2. Memory units 19 and 23 made of silicon are arranged in the third region AR3. An AD conversion unit 190 made of silicon is arranged in the fourth region AR4. The first region AR1, the second region AR2, and the third region AR3 are stacked on a first substrate SUB1. The fourth region AR4 is arranged on a second substrate SUB2.

[0131] As described above, the area pixel 100 according to the sixth example differs from the fourth example in that the current amplifier 90 and the storage units 19 and 23 are arranged in separate regions.

[0132] The first region AR1 and the second region AR2 transmit and receive the voltage of the floating diffusion FD of the photoelectric conversion unit 110 for each pixel via a signal transmission unit 91 formed by a via 91b. The second region AR2 and the third region AR3 transmit and receive the voltage of one end of the memory units 19, 23 for each area pixel 100 via a signal transmission unit 91 formed by a via 91b. The third region AR3 and the fourth region AR4 transmit and receive the voltage of the other end of the memory units 19, 23 for each area pixel 100 via a signal transmission unit 91 formed by a Cu-Cu connection 91a.

[0133] In this way, in the area pixel 100 according to the sixth example, the current amplifier 90 and the storage units 19 and 23 are arranged in separate regions, so that the layout area of ​​the current amplifier 90 and the storage units 19 and 23 can be increased.

[0134] (Seventh example of area pixel 100) Fig. 29 is a circuit diagram of the area pixel 100 according to the seventh example, Fig. 30 is a cross-sectional view of the area pixel 100 according to the seventh example, Fig. 31A is a plan view taken along line AA in Fig. 30, Fig. 31B is a plan view taken along line BB in Fig. 30, and Fig. 31C is a plan view taken along line CC in Fig. 30. The following description will focus on the differences from the area pixel 100 according to the sixth example.

[0135] The area pixel 100 according to the seventh example has a first region AR1, a second region AR2, a third region AR3, and a fourth region AR4 that are stacked, similar to the sixth example. The circuit portions arranged in the first region AR1 to the fourth region AR4 are also similar to the sixth example, but differ from the sixth example in that signals are transmitted and received between the current amplifier 90 and the memory units 19 and 23 via a signal transmission unit 91.

[0136] The area pixel 100 according to the seventh example has a different substrate configuration from that of the sixth example. The area pixel 100 according to the seventh example includes a first substrate SUB1 on which a first region AR1 and a second region AR2 are stacked, and a second substrate SUB2 on which a third region AR3 and a fourth region AR4 are stacked.

[0137] The first region AR1 and the second region AR2 transmit and receive the voltage of the floating diffusion FD of the photoelectric conversion unit 110 for each pixel via a signal transmission unit 91 made up of a via 91b. The second region AR2 and the third region AR3 transmit and receive the voltage of one end of the memory units 19 and 23 for each pixel via a signal transmission unit 91 made up of a Cu-Cu connection 91a. The third region AR3 and the fourth region AR4 transmit and receive the voltage of the other end of the memory units 19 and 23 for each area pixel 100 via a signal transmission unit 91 made up of a via 91b.

[0138] (Eighth example of area pixel 100) Fig. 32 is a circuit diagram of the area pixel 100 according to the eighth example, Fig. 33 is a cross-sectional view of the area pixel 100 according to the eighth example, Fig. 34A is a plan view taken along line AA in Fig. 33, Fig. 34B is a plan view taken along line BB in Fig. 33, and Fig. 34C is a plan view taken along line CC in Fig. 33. The following description will focus on the differences from the area pixel 100 according to the seventh example.

[0139] The circuit diagram of FIG. 32 for the eighth example is the same as the circuit diagram of FIG. 29 for the seventh example. The area pixel 100 of the eighth example has a first region AR1, a second region AR2, and a third region AR3 that are stacked. The first region AR1 contains a photoelectric conversion unit 110 made of a material other than silicon. The second region AR2 contains a current amplification unit 90 made of silicon. The third region AR3 contains memory units 19 and 23 and an AD conversion unit 190 made of silicon. The first region AR1 and the second region AR2 are stacked on a first substrate SUB1, and the third region AR3 is placed on a second substrate SUB2. The first region AR1 and the second region AR2 transmit and receive the voltage of the floating diffusion FD of the photoelectric conversion unit 110 for each pixel through a signal transmission unit 91 made of a via. The second area AR2 and the third area AR3 transmit and receive the voltages at one end of the storage units 19 and 23 via a signal transmission unit 91 made of a Cu-Cu connection.

[0140] The area pixel 100 according to the eighth example differs from the seventh example in that the memory units 19 and 23 and the AD conversion unit 190 are both arranged in the third area AR3. This allows the number of areas to be reduced, and the manufacturing process to be simpler than in the seventh example.

[0141] (Summary of the first to eighth examples of the area pixel 100) The area pixel 100 according to the present disclosure includes a plurality of pixels. The area pixel 100 includes a plurality of photoelectric conversion units 110, a plurality of floating diffusions FD, a plurality of current amplification units 90, and an AD conversion unit 190. Each floating diffusion FD outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit 110 in the corresponding pixel. The AD conversion unit 190 is provided for each area pixel 100, which is made up of two or more pixels among the plurality of pixels in the area pixel 100, and converts signals stored in two or more storage units 19, 23 corresponding to the two or more pixels in the area pixel 100 into digital signals.

[0142] The photoelectric conversion units 110, AD converters 190, floating diffusions FD, current amplifiers 90, and memory units 19, 23 in the pixels are arranged in multiple stacked regions. A signal transmission unit 91 transmits and receives signals between the multiple regions. Of the multiple regions, the region in which the photoelectric conversion units 110 are arranged is provided separately from the region in which the current amplifiers 90 are arranged. The region in the area pixel 100 in which the photoelectric conversion units 110 are arranged and the region in which the current amplifiers 90 are arranged transmit and receive voltages of the floating diffusions FD via the corresponding signal transmission units 91.

[0143] The area pixels 100 according to the first to eighth examples each include a separate memory unit 19 for a P-phase signal and a memory unit 23 for a D-phase signal. The circuit configurations of the global shutter photoelectric conversion unit 110, current amplifier unit 90, and memories 19 and 23 are not limited to those described above. Other representative circuit configurations of the global shutter photoelectric conversion unit 110, current amplifier unit 90, and memories 19 and 23 will be described below.

[0144] (First Modification of the Photoelectric Conversion Unit 110, the Current Amplification Unit 90, and the Storage Units 19 and 23) 35A is a circuit diagram of a photoelectric conversion unit 110, a current amplification unit 90, and storage units 19 and 23 according to a first modification. The photoelectric conversion unit 110 in FIG. 35A has a photodiode 501 and a transistor 503. The current amplification unit 90 in FIG. 35A has transistors 14, 15, 18, 22, 56, 57, 59, and 60, and current sources 17, 58, and 61. The transistor 18 switches between storing a P-phase signal in the storage unit 19 and not storing it. The transistor 22 switches between storing a D-phase signal in the storage unit 23 and not storing it.

[0145] Fig. 35B is a circuit diagram of a photoelectric conversion unit 110, a current amplification unit 90, and storage units 19 and 23 according to a second modification. The photoelectric conversion unit 110 in Fig. 35B has a photodiode 501 and a transistor 503. The current amplification unit 90 in Fig. 35B has transistors 14, 15, 18, 22, 56, and 57, and current sources 17 and 58. The storage unit 23 stores a signal that is the difference between the P-phase signal and the D-phase signal.

[0146] 35C is a circuit diagram of a photoelectric conversion unit 110, a current amplification unit 90, and storage units 19 and 23 according to a third modification. The photoelectric conversion unit 110 in FIG. 35C has a photodiode 501 and a transistor 503. The current amplification unit 90 in FIG. 35C has transistors 14, 15, 18, 22, 56, and 57 and current sources 17 and 58. The transistor 18 controls switching as to whether or not to store a P-phase signal in the capacitor 19. The transistor 22 controls switching as to whether or not to store a D-phase signal in the capacitor 23.

[0147] FIG. 35D is a circuit diagram of a photoelectric conversion unit 110, a current amplification unit 90, and memory units 19 and 23 according to a fourth modification. The circuit diagram in FIG. 35D has a function of selecting between a global shutter system and a rolling shutter system. The photoelectric conversion unit 110 in FIG. 35D has a photodiode 501 and a transistor 503. The current amplification unit 90 in FIG. 35D has transistors 14, 15, 18, 22, 56, and 57.

[0148] When the rolling shutter system is selected, the transistor 62 is turned on and the transistor 63 is turned off, whereby the source voltage of the transistor 62 changes according to the voltage of the floating diffusion FD.

[0149] When the global shutter method is selected, the transistor 63 is turned on and the transistor 62 is turned off. As a result, the source voltage of the transistor 63 changes according to the voltages of the capacitor 19 that stores the P-phase signal and the capacitor 23 that stores the D-phase signal.

[0150] <Application to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0151] FIG. 36 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0152] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 36, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0153] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0154] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0155] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0156] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0157] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0158] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0159] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0160] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0161] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 36, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0162] FIG. 37 is a diagram showing an example of the installation position of the imaging unit 12031.

[0163] In FIG. 37, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0164] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0165] 37 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0166] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0167] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0168] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0169] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0170] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above. Specifically, the imaging device 1 according to the present disclosure can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a clearer captured image can be obtained, thereby reducing driver fatigue.

[0171] The present technology can be configured as follows: (1) a plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; An imaging device, wherein a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units. (2) The imaging device according to (1), wherein the plurality of current amplifiers, the plurality of memory units, and the plurality of analog-to-digital converters are arranged in the same region among the plurality of regions. (3) The imaging device according to (2), wherein the plurality of current amplifiers, the plurality of memory units, and the plurality of analog-to-digital converters are arranged in the same layer within the same region. (4) An imaging device as described in (3), wherein two or more of the current amplifier units and two or more of the memory units belonging to the same area pixel are arranged symmetrically along two opposing sides of the corresponding analog-to-digital converter. (5) The imaging device according to (2), wherein the plurality of current amplifiers and the plurality of analog-to-digital converters, and the plurality of memory units are arranged in different layers within the same region. (6) The imaging device according to (5), wherein the plurality of memory units are arranged in a wiring layer within the same region. (7) a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers, the plurality of memory units, and the plurality of analog-to-digital converters are arranged, The imaging device described in any one of (1) to (6), wherein the first region and the second region transmit and receive the voltages of the plurality of floating diffusions for each pixel via different signal transmission units. (8) a first substrate having the first region; a second substrate having the second region; The imaging device according to (7), wherein the first substrate and the second substrate transmit and receive the voltage of the floating diffusion for each pixel via different signal transmission sections. (9) The imaging device described in (1), wherein the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of memory units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions. (10) The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers and the plurality of memory units are arranged; a third region in which the plurality of analog-to-digital converters are disposed; The imaging device according to (9), wherein the first region and the second region transmit and receive the voltages of the plurality of floating diffusions for each pixel via different signal transmission units. (11) The imaging device according to (10), wherein the plurality of current amplifiers and the plurality of memory units are arranged in the same layer within the second region. (12) a first substrate on which the first region and the second region are stacked; a second substrate having the third region; The imaging device described in (10) or (11), wherein the first substrate and the second substrate transmit and receive signals stored in the memory unit via different signal transmission units for each pixel. (13) The imaging device described in (1), wherein the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of memory units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions. (14) The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers are arranged; a third area in which the plurality of storage units are arranged; a fourth region in which the plurality of analog-to-digital converters are disposed; The imaging device according to (13), wherein the first region and the second region transmit and receive the voltages of the plurality of floating diffusions for each pixel via different signal transmission units. (15) a first substrate on which the first region, the second region, and the third region are stacked; a second substrate having the fourth region; The imaging device described in (14), wherein the first substrate and the second substrate transmit and receive signals stored in the plurality of memory units via different signal transmission units for each pixel. (16) A first substrate on which the first region and the second region are stacked; a second substrate having the third region and the fourth region; The imaging device described in (15), wherein the first substrate and the second substrate transmit and receive currents amplified by the multiple current amplifiers via different signal transmission units for each pixel. (17) The imaging device described in (1), wherein the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of memory units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions. (18) The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers are arranged; a third region in which the plurality of storage units and the plurality of analog-to-digital converters are arranged; The imaging device according to (17), wherein the first region and the second region transmit and receive the voltages of the plurality of floating diffusions for each pixel via different signal transmission units. (19) A first substrate on which the first region and the second region are stacked; a second substrate having the third region; The imaging device described in (18), wherein the first substrate and the second substrate transmit and receive currents amplified by the multiple current amplifiers via different signal transmission sections for each pixel. (20) The imaging device described in (1), wherein the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of analog-to-digital converters, and the plurality of memory units are arranged in different regions among the plurality of regions. (21) The imaging device according to (18), wherein the first region, the second region, and the third region are stacked on the same substrate. (22) The imaging device according to any one of (1) to (21), wherein the photoelectric conversion section has a semiconductor layer made of silicon or a semiconductor layer made of a material other than silicon. (23) The imaging device according to any one of (1) to (22), wherein the signal transmission unit transmits and receives the signal through a via, a bump, or a Cu-Cu joint. (24) An imaging device that outputs a digital signal for each photoelectrically converted pixel; a signal processing unit that performs signal processing on the digital signal, The imaging device is a plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; an area in the area pixel where the plurality of photoelectric conversion units are arranged and an area in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units, respectively.

[0172] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0173] 1 imaging device, 10 pixel array section, 11 signal line, 11a upper electrode layer, 11a upper electrode, 11b photoelectric conversion layer, 11d insulating layer, 11e lower electrode layer, 12 signal input transistor, 16 selection transistor, 17 current source, 19 memory section, 20 time code generation section, 23 memory section, 30 reference signal generation section, 40 vertical drive section, 42 control signal generation section, 43 power supply section, 50 horizontal control section, 52 time code decoding section, 53 column signal processing section, 54 clock signal generation section, 58 current source, 61 current source, 71 wiring layer, 72 color filter, 73 on-chip lens, 74 element isolation layer, 75 wiring layer, 76 protective layer, 90 current amplification section, 91 signal transmission section, 91a Cu-Cu connection, 91b via, 92 memory section, 100 Area pixel, 110 photoelectric conversion unit, 150 comparison unit, 160 comparison output processing unit, 161 preamplification unit, 162 level conversion unit, 163 waveform shaping unit, 170 conversion result holding unit, 171 memory control unit, 172 memory unit, 190 AD conversion unit, 200 time code transfer unit, 210 code holding unit

Claims

1. a plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units, the plurality of current amplifiers, the plurality of storage units, and the plurality of analog-to-digital converters are arranged in the same region among the plurality of regions, The imaging device, wherein the plurality of current amplifiers and the plurality of analog-to-digital converters, and the plurality of storage units are arranged in different layers within the same region.

2. The imaging device according to claim 1 , wherein the plurality of storage units are arranged in a wiring layer within the same region.

3. a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers, the plurality of memory units, and the plurality of analog-to-digital converters are arranged; The imaging device according to claim 1 , wherein the first region and the second region transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission sections.

4. a first substrate having the first region; a second substrate having the second region; The imaging device according to claim 3 , wherein the first substrate and the second substrate transmit and receive the voltage of the floating diffusion for each pixel via different signal transmission sections.

5. A plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units, the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of storage units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions; The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers and the plurality of memory units are arranged; a third region in which the plurality of analog-to-digital converters are disposed; the first region and the second region transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission units; a first substrate on which the first region and the second region are stacked; a second substrate having the third region; The imaging device, wherein the first substrate and the second substrate transmit and receive signals stored in the plurality of storage units via the signal transmission units that are different for each pixel.

6. A plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units, the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of storage units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions; The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers are arranged; a third area in which the plurality of storage units are arranged; a fourth region in which the plurality of analog-to-digital converters are arranged; the first region and the second region transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission units; a first substrate on which the first region, the second region, and the third region are stacked; a second substrate having the fourth region; The imaging device, wherein the first substrate and the second substrate transmit and receive signals stored in the plurality of storage units via the signal transmission units that are different for each pixel.

7. A plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units, the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of storage units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions; The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers are arranged; a third area in which the plurality of storage units are arranged; a fourth region in which the plurality of analog-to-digital converters are arranged; the first region and the second region transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission units; a first substrate on which the first region and the second region are stacked; a second substrate having the third region and the fourth region; an imaging device, wherein the first substrate and the second substrate transmit and receive currents amplified by the plurality of current amplifiers via the signal transmission units that are different for each pixel;

8. A plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units, the plurality of photoelectric conversion units, the plurality of current amplification units, the plurality of storage units, and the plurality of analog-to-digital converters are arranged in different regions among the plurality of regions; The plurality of regions are: a first region in which the plurality of photoelectric conversion units are arranged; a second region in which the plurality of current amplifiers are arranged; a third region in which the plurality of storage units and the plurality of analog-to-digital converters are arranged; the first region and the second region transmit and receive voltages of the plurality of floating diffusions for each pixel via different signal transmission units; a first substrate on which the first region and the second region are stacked; a second substrate having the third region; The imaging device, wherein the first substrate and the second substrate transmit and receive the currents amplified by the plurality of current amplifiers via the signal transmission units that are different for each pixel.

9. The imaging device according to claim 1 , wherein the photoelectric conversion portion has a semiconductor layer made of silicon or a semiconductor layer made of a material other than silicon.

10. 10. The imaging device according to claim 1, wherein the signal transmission section transmits and receives the signal through a via, a bump, or a Cu-Cu joint.

11. an imaging device that outputs a digital signal for each pixel that has been photoelectrically converted; a signal processing unit that performs signal processing on the digital signal, The imaging device is a plurality of pixels each having a photoelectric conversion unit; a floating diffusion that outputs a voltage corresponding to the charge photoelectrically converted by the photoelectric conversion unit in the pixel; a current amplifier that amplifies a current corresponding to the voltage of the floating diffusion; a storage unit that stores a signal corresponding to the current amplified by the current amplifier unit; an analog-to-digital converter provided for each area pixel consisting of two or more of the pixels in the plurality of pixels, and converting signals stored in two or more of the storage units corresponding to the two or more pixels in the area pixel into digital signals; a plurality of stacked regions in which the photoelectric conversion units, the analog-to-digital converters, the floating diffusions, the current amplification units, and the storage units in the plurality of pixels are arranged; a signal transmission unit that transmits and receives signals between the plurality of areas, Among the plurality of regions, a region in which the plurality of photoelectric conversion units are arranged is provided separately from a region in which the plurality of current amplification units are arranged; a region in the area pixel where the plurality of photoelectric conversion units are arranged and a region in which the plurality of current amplification units are arranged transmit and receive voltages of the plurality of floating diffusions via the corresponding signal transmission units, the plurality of current amplifiers, the plurality of storage units, and the plurality of analog-to-digital converters are arranged in the same region among the plurality of regions, The electronic device, wherein the plurality of current amplifiers and the plurality of analog-to-digital converters, and the plurality of storage units are arranged in different layers within the same region.

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