Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving an electrical characteristic by optimizing a current control.SOLUTION: A semiconductor device according to an embodiment includes: a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a first electrode provided on the interlayer insulating film; a second electrode provided below the semiconductor substrate; a plurality of gate regions that reache the semiconductor substrate from the interlayer insulating film in a first direction that is a thickness direction of the semiconductor substrate, are provided in a second direction that intersects with the first direction, and extend in a third direction that intersects with the first direction and the second direction; and a plurality of plugs provided between the gate regions in the second direction, spaced apart from one another in the third direction and electrically connecting the first electrode and the semiconductor substrate.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method. [Background technology]

[0002] A known structure involves forming a plug to electrically connect an opposing electrode and a semiconductor substrate via an insulating film. The plug is formed by filling an opening excavated by etching or the like with, for example, tungsten (W). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-198425 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of optimizing current control and improving electrical characteristics. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes: a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, a first electrode provided on the interlayer insulating film, a second electrode provided below the semiconductor substrate, gate regions provided in a first direction that is a thickness direction of the semiconductor substrate from the interlayer insulating film to the semiconductor substrate, and provided in a plurality of gate regions in a second direction that intersects the first direction, and extending in a third direction that intersects the first direction and the second direction, and a plurality of gate regions provided in the second direction between the gate regions and spaced apart from each other in the third direction; a second semiconductor region that is in contact with the third semiconductor region; and a plug that electrically connects the first electrode and the semiconductor substrate.

[0006] A method for manufacturing a semiconductor device according to an embodiment includes the steps of forming an interlayer insulating film on a semiconductor substrate, forming a plurality of openings spaced apart in a direction in which a gate region extends, penetrating the interlayer insulating film and reaching the semiconductor substrate, forming a tungsten film on the interlayer insulating film and in the openings, partially removing the tungsten film to form plugs, and forming a first electrode on the interlayer insulating film and the plugs. [Brief explanation of the drawings]

[0007] [Figure 1A] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 1B] FIG. 1B is an enlarged plan view showing region a in FIG. 1A. [Figure 2A] FIG. 2 is a cross-sectional view showing the AA′ cross section of FIG. 1B. [Figure 2B] FIG. 2 is an enlarged cross-sectional view showing the BB′ cross section of FIG. 1B. [Figure 2C] FIG. 2 is an enlarged cross-sectional view showing the CC′ cross section of FIG. 1B. [Figure 2D] FIG. 2 is another example of an enlarged cross-sectional view showing the CC′ cross section of FIG. 1B. [Figure 3] FIG. 2 is an enlarged plan view showing a first modified example of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is an enlarged plan view showing a semiconductor device according to a first reference example. [Figure 5] FIG. 5 is a cross-sectional view showing the cross section D-D′ of FIG. 4. [Figure 6] FIG. 10 is an enlarged plan view showing a semiconductor device according to a second reference example. [Figure 7] FIG. 10 is an enlarged plan view showing a semiconductor device according to a second embodiment. [Figure 8A] FIG. 8 is a cross-sectional view showing the EE′ cross section of FIG. 7. [Figure 8B] FIG. 8 is a cross-sectional view showing the FF′ cross section of FIG. 7. [Figure 9] FIG. 10 is an enlarged plan view showing a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing the cross section GG' of FIG. [Figure 11] 2 is a cross-sectional view corresponding to the AA' cross section of FIG. 1, illustrating a step of providing an interlayer insulating film in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 2 is a cross-sectional view corresponding to the AA' cross section of FIG. 1, illustrating a step of providing a resist in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] 2 is a cross-sectional view corresponding to the AA' cross section of FIG. 1, showing a step of providing an opening in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 2 is a cross-sectional view corresponding to the AA' cross section of FIG. 1, illustrating a step of forming a tungsten film in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] 2 is a cross-sectional view corresponding to the AA' cross section of FIG. 1, illustrating a step of etching back a tungsten film in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] 2 is a cross-sectional view corresponding to the AA' cross section of FIG. 1, showing a step of providing a first electrode in the method for manufacturing the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0009] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0010] In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0011] The direction from the first semiconductor region 21 to the second semiconductor region 22 is the Z direction (first direction). The Z direction is the thickness direction of the semiconductor substrate 20. The direction perpendicular to the Z direction is the X direction (second direction), and the direction intersecting the X and Z directions is the Y direction (third direction). The semiconductor device 1 shown in FIG. 2 is a cross-sectional view taken along the XZ plane. Note that, although the X direction, Y direction, and Z direction are shown as being orthogonal to each other in this embodiment, they are not limited to being orthogonal as long as they intersect with each other.

[0012] In this specification, the positive direction of the Z direction is referred to as “upper” and the other side as “lower.” The “upper” and “lower” directions are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0013] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0014] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - The shape is simply n-type, p-type + shape, p - The shape is sometimes simply referred to as p-shape.

[0015] (First embodiment) Fig. 1A is a schematic plan view illustrating the internal wiring structure of the semiconductor device 1 according to this embodiment. Fig. 1B is an enlarged plan view showing region a shown in Fig. 1A. In Figs. 1A and 1B, the first electrode 11 and the interlayer insulating film 50 are omitted in order to show the internal wiring structure.

[0016] 1A shows a schematic top view of the semiconductor device 1 and an enlarged plan view of a portion of the top view. For example, an IGBT (Insulated Gate Bipolar Transistor) is formed in an active region AR of the semiconductor device 1. The active region AR is a region through which current mainly flows when the semiconductor device 1 is in an on-state.

[0017] 1A, gate regions 30 are repeatedly provided in the X direction on a semiconductor substrate 20, extending in the Y direction. A plurality of plugs 40 are provided in the semiconductor substrate 20 between the gate regions 30 arranged in a plurality of rows in the X direction, spaced apart from one another in the Y direction. Here, it has been described that the plugs 40 are provided between the gate regions 30, but in cases where the plugs 40 are located on the outermost periphery outside the active region AR of the semiconductor device 1, for example, it is not necessary for all of the plugs 40 to be provided between the gate regions 30.

[0018] The plan view of Fig. 1A is a schematic representation of a portion of the active region AR, and the structure of the peripheral portion of the active region AR is not limited to that shown in Fig. 1A. Furthermore, when an IGBT, for example, is formed in the active region AR, the portion where the emitter electrode is formed and the portion where the gate electrode is formed may have different structures.

[0019] FIG. 1B is a further enlarged plan view of region a shown in FIG. 1A. FIG. 1B shows the internal wiring structure. The gate region 30 has, for example, a gate insulating film 31 and a gate electrode 32. The gate electrode 32 is covered by the gate insulating film 31. The gate electrodes 32 do not all need to be at the same potential. Some of the gate electrodes 32 in the gate region 30 may include dummy electrodes. Furthermore, the gate region 30 does not necessarily need to have a gate electrode 32. A portion of the gate region 30 may be formed, for example, only from an insulating material. Furthermore, a portion of the gate region 30 may be formed, for example, only from a conductive material, and may include a portion at the same potential as the semiconductor substrate 20.

[0020] The semiconductor substrate 20 has a first semiconductor region 21 of a first conductivity type (not shown in FIG. 1B), a second semiconductor region 22 of a second conductivity type, and a third semiconductor region 23 of the first conductivity type. The second semiconductor region 22 is, for example, a p-type base region. The third semiconductor region 23 is, for example, an n-type emitter region. The third semiconductor region 23 is selectively provided on the second semiconductor region 22.

[0021] As shown in FIG. 1B , a plurality of third semiconductor regions 23 are provided in the Y direction, for example, between the gate regions 30. For example, the length of the third semiconductor regions 23 in the X direction is longer than the length in the Y direction. The second semiconductor region 22 is located between the spaced-apart third semiconductor regions 23. By providing a plurality of third semiconductor regions 23 in the Y direction, the contact area between the third semiconductor regions 23 and the gate regions 30 can be controlled and the flow of current can be dispersed. As will be described later, when the semiconductor device 1 is in the on state, current flows through the third semiconductor regions 23 near the gate regions 30. The flow of current in the on state can be controlled by the arrangement of the plurality of third semiconductor regions 23 formed in the Y direction. Note that the third semiconductor region 23 may be a region extending in the Y direction and formed continuously.

[0022] A plurality of plugs 40 are arranged so as to contact the second semiconductor region 22 or the third semiconductor region 23, or both. The entire region formed in the Y direction may be collectively referred to as the plug 40, but each of the regions formed may also be referred to as the plug 40.

[0023] The lengths L1, L2, L3 and LG shown in FIG. 1B will be explained in more detail after the description of FIG.

[0024] The cross-sectional structure of the semiconductor device 1 according to the first embodiment will be described below with reference to FIGS. 2A, 2B, and 2C.

[0025] 2A, 2B, and 2C are cross-sectional views taken along lines AA', BB', and CC', respectively, shown in FIG. 1B. The cross-sectional views of FIGS. 2A, 2B, and 2C show the first electrode 11 and the interlayer insulating film 50, which are omitted in FIG. 1B. The cross-sectional views of FIGS. 2B and 2C omit the structure below the first semiconductor region 21.

[0026] First, referring to FIG. 2A , a cross-sectional view taken along line A-A′ of a semiconductor device 1 according to the first embodiment will be described. The semiconductor device 1 according to this embodiment shown in FIG. 2A has a first electrode 11, a second electrode 12, a semiconductor substrate 20, a gate region 30, a plug 40, and an interlayer insulating film 50. The semiconductor substrate 20 has a first semiconductor region 21 of a first conductivity type, a second semiconductor region 22 of a second conductivity type, a third semiconductor region 23 of the first conductivity type, a fourth semiconductor region 24 of the second conductivity type, and a fifth semiconductor region 25 of the second conductivity type. The gate region 30 has a gate insulating film 31 and a gate electrode 32.

[0027] The first electrode 11 and the second electrode are made of a metal containing, for example, AlCu or AlSi. The first electrode 11 is, for example, an emitter electrode of an IGBT. The second electrode 12 is, for example, a collector electrode of the IGBT. A semiconductor substrate 20 is provided between the first electrode 11 and the second electrode 12.

[0028] The semiconductor substrate 20 is made of, for example, a semiconductor containing Si. The first semiconductor region 21 is, for example, an n-type drift layer. The second semiconductor region 22 is, for example, a p-type ― The third semiconductor region 23 is a base region of, for example, n + The fourth semiconductor region 24 is an emitter layer of, for example, p + The fifth semiconductor region 25 is a collector layer of, for example, p + The p-type semiconductor layer is formed by doping Si with B, for example. The n-type semiconductor layer is formed by doping Si with P, for example.

[0029] The gate region 30 is, for example, a gate trench of an IGBT. The gate insulating film 31 contains, for example, silicon oxide such as SiO2. The gate insulating film 31 is, for example, a gate insulating film of an IGBT, and is formed by oxidation. The gate electrode 32 is, for example, a gate electrode of an IGBT, and contains polysilicon.

[0030] The plug 40 is preferably made of a metal containing W (tungsten). The plug 40 may also be covered with a barrier metal 41. The barrier metal 41 is formed between the plug 40 and the semiconductor substrate 20 and between the plug 40 and the interlayer insulating film. The barrier metal 41 has a layer structure containing, for example, Ti and TiN. The barrier metal 41 has higher adhesion to the interlayer insulating film 50 than the plug 40 and suppresses peeling between the barrier metal 41 and the interlayer insulating film 50 when stress is applied to the semiconductor substrate 20 and the interlayer insulating film 50 due to thermal history or the like. Furthermore, when the plug 40 is formed on the surface of the barrier metal 41 by, for example, CVD, the reactivity of the barrier metal 41 with the gas used in CVD can be controlled by selecting the material of the barrier metal 41. For example, when CVD is performed using a gas containing fluorine, the reactivity of fluorine can be reduced by using the barrier metal 41 containing TiN.

[0031] The plug 40 may be covered with a barrier metal 41, and the barrier metal 41 may be in contact with the semiconductor substrate 20. The plug 40 and the semiconductor substrate 20 are electrically connected at the contact portion between the plug 40 and the semiconductor substrate 20. In the description of this specification, the contact area between the plug 40 and the semiconductor substrate 20 is described, but the case where the plug 40 and the semiconductor substrate 20 face each other via the barrier metal 41 is also included in the definition of "contact."

[0032] The plug 40 electrically connects the first electrode 11 and the semiconductor substrate 20. The plug 40 contacts the third semiconductor region 23 in the AA′ cross section and reaches the second semiconductor region 22. A fifth semiconductor region 25 is formed on the bottom surface of the plug 40.

[0033] The gate region 30 is provided under the interlayer insulating film 50 and reaches the first semiconductor region 21 in the negative Z direction. The gate region 30 has a gate electrode 32 covered with a gate insulating film 31. The gate insulating film 31 is provided between the gate electrode 32 and the semiconductor substrate 20, and at least a portion of the gate insulating film 31 contacts the second semiconductor region 22. The gate electrode 32 is electrically insulated from the semiconductor substrate 20 by the gate insulating film 31. By applying a voltage to the gate electrode 32, an inversion layer is formed in the second semiconductor region 22, and the semiconductor device can be turned on.

[0034] The interlayer insulating film 50 is made of silicon oxide such as SiO2. The interlayer insulating film 50 is formed by, for example, CVD. The interlayer insulating film 50 is formed on the semiconductor substrate 20 and is provided so as to cover the gate region 30. The interlayer insulating film 50 electrically insulates the gate electrode 32 and the first electrode 11.

[0035] Figure 2B is an enlarged cross-sectional view taken along line BB' in Figure 1B. The BB' cross section does not pass through plug 40, so plug 40 is not shown in Figure 2B. On the other hand, gate region 30 extends in the Y direction in Figure 1B, so it is shown in Figure 2B in the same way as in Figure 2A.

[0036] 2C is an enlarged cross-sectional view taken along line CC' in FIG. 1B. A plurality of plugs 40 are provided in the Y direction. FIG. 2C also shows a case where a plurality of third semiconductor regions 23 are provided in the Y direction. The arrangement of the plugs 40 in the Y direction can be changed depending on the arrangement of the third semiconductor regions 23 in the Y direction. The plugs 40 and the third semiconductor regions 23 are each provided at a regular interval in the Y direction, for example.

[0037] Some of the plugs 40 may be in contact with the third semiconductor region 23, and others may be located between the plurality of third semiconductor regions 23. At least one plug 40 is provided between the third semiconductor regions 23 spaced apart in the Y direction. For example, as shown in FIG. 2C , the plugs 40 in contact with the third semiconductor region 23 and the plugs 40 located between the plurality of third semiconductor regions 23 are alternately repeated in the Y direction. Note that, as will be described below with reference to FIG. 2D , the plugs 40 in contact with the third semiconductor region 23 and the plugs 40 located between the plurality of third semiconductor regions 23 do not need to be alternately repeated in the Y direction. FIG. 2D is a cross-sectional view taken in the same direction as FIG. 2C , illustrating an example different from the embodiment shown in FIG. 2C .

[0038] 2D , in some of the multiple provided plugs 40, the plugs 40 adjacent to each other in the Y direction may be in contact with the third semiconductor region 23. For example, two or more plugs 40 may be in contact with one region of the multiple provided third semiconductor regions 23.

[0039] 2D , the plugs 40 adjacent to each other in the Y direction may be in contact with different regions spaced apart in the Y direction among the plurality of third semiconductor regions 23. In other words, the third semiconductor region 23, the second semiconductor region 22, and the third semiconductor region 23 may be aligned in the Y direction between the plugs 40 adjacent to each other in the Y direction.

[0040] Alternatively, as shown in FIG. 2D, in at least a part of the plurality of provided plugs 40, adjacent plugs 40 in the Y direction may be located between the third semiconductor regions 23 spaced apart in the Y direction. Among the plurality of provided third semiconductor regions 23, two or more plugs 40 may be provided between adjacent third semiconductor regions 23 in the Y direction.

[0041] Hereinafter, the arrangement of the plugs 40 of the semiconductor device 1 according to the first embodiment will be further described with reference to FIGS. 1B and FIGS. 2A, B, and C.

[0042] First, a description will be given while referring to FIG. 1B. As shown in FIG. 1B, when comparing the interval LG in the X direction of the gate region 30 and the length L1 in the X direction of the plug 40, L1 is shorter. Since L1 is smaller than LG, the plug 40 can be formed between the gate regions 30. Note that L1 (<LG) is not necessarily formed with an arbitrary length within a range smaller than LG, and may be formed sufficiently smaller than LG in consideration of the alignment error in the X direction during the formation of the plug 40.

[0043] Also, the length L1 in the X direction and the length L2 in the Y direction of the plug 40 are different. L1 is the length of the long side of the plug 40 having, for example, a rectangular cross section in the XY plane, and L2 is the length of the short side of the plug 40 having, for example, a rectangular cross section in the XY plane.

[0044] The interval L3 between adjacent plugs 40 in the Y direction may be smaller or larger than L1. The plugs 40 can be provided at a constant interval L3 as shown in FIG. 1B.

[0045] The plug 40 is in contact with the second semiconductor region 22 or the third semiconductor region 23 within the XY plane shown in FIG. 1B. At least a part of the plug 40 may be in contact with both the second semiconductor region 22 and the third semiconductor region 23 within the XY plane.

[0046] Next, a description will be given with reference to FIG. 2A. The plug 40 has a depth D in the Z direction. The depth D is the length in the Z direction from the interface between the plug 40 and the first electrode 11 to the bottom surface of the plug 40. Note that the shape of the bottom surface of the plug 40 shown in FIG. 2A is not limited, and the bottom surface may be rounded.

[0047] The ratio of the depth D to the length L1, D / L1, is referred to as the first aspect ratio. Also, the ratio of the depth D shown in FIG. 2C to the length L2 in the Y direction of the plug 40, D / L2, is referred to as the second aspect ratio.

[0048] The first aspect ratio D / L1 is, for example, within the range of 0 < D / L1 ≤ 2. When the first aspect ratio satisfies 0 < D / L1 ≤ 2, the embedding property when forming the plug 40 can be improved. Desirably, it is within the range of 0 < D / L1 ≤ 1.

[0049] The second aspect ratio D / L2 satisfies D / L1 ≤ D / L2, and for example, 1 ≤ D / L2. By having the second aspect ratio D / L2 satisfy 1 ≤ D / L2, the contact area between the plug 40 and the semiconductor substrate 20 can be increased, which is advantageous for miniaturization. Note that since the first aspect ratio is smaller than the second aspect ratio, even when the second aspect ratio is large, the embedding property of the plug 40 can be kept good.

[0050] Note that, for example, the plug 40 may have a tapered structure in the negative direction of the Z direction. In that case, the definitions of the lengths L1 and L2 may be the maximum length in the X direction of the portion of the plug 40 located between the gate regions 30. For example, in the Z direction, measure the length of the plug 40 in the X direction at the position corresponding to the interface between the semiconductor substrate 20 and the interlayer insulating film 50 as L1.

[0051] Next, while referring to FIG. 2A, the operation of the semiconductor device 1 will be described. As an example, the operation of an IGBT will be described. The first electrode 11 is an emitter electrode, the first semiconductor region 21 is an n ― -type drift region, the second semiconductor region 22 is a p-type base region, and the third semiconductor region 23 is an n +The fourth semiconductor region 24 is a p + The fifth semiconductor region 25 is a p + First, we will explain the operation of turning on the IGBT.

[0052] A negative voltage is applied to the first electrode 11 with respect to the second electrode 12. By applying a positive voltage equal to or greater than a threshold voltage with respect to the potential of the first electrode 11 to the gate electrode 32, an inversion layer (channel) is formed in the second semiconductor region 22 near the gate insulating film 31. That is, an inversion layer having n-type conductivity is formed in the second semiconductor region 22, which is a p-type base region.

[0053] The inversion layer formed in the second semiconductor region 22 has the same conductivity type as the first semiconductor region 21 and the third semiconductor region 23. Therefore, electrons that reach the third semiconductor region 23 from the first electrode 11 (emitter electrode) through the plug 40 flow into the first semiconductor region 21 through the inversion layer formed in the second semiconductor region 22.

[0054] Furthermore, holes are injected into the first semiconductor region 21 (drift layer) from the fourth semiconductor region 24 (collector layer) provided below the first semiconductor region 21. Thus, a current flows from the second electrode 12 (collector electrode) to the first electrode (emitter electrode) with the electrons and holes acting as current carriers, and the IGBT enters an on state.

[0055] Next, when the IGBT is turned off, the potential of the gate electrode 32 is set to, for example, the same potential as the first electrode 11. The inversion layer generated in the second semiconductor region 22 disappears, and the injection of electrons from the third semiconductor region 23 into the first semiconductor region 21 is suppressed. For the IGBT to be completely turned off, it is necessary to discharge the carriers accumulated in the first semiconductor region 21 in the on state. The electrons are discharged to the second electrode 12, and the holes are discharged to the first electrode 11 through the p-type second semiconductor region 22 and the plug 40.

[0056] Holes are discharged, for example, via the following route: Holes accumulated in the first semiconductor region 21 pass through the second semiconductor region 22 and then through the fifth semiconductor region 25, which has the same conductivity type as the second semiconductor region, to be discharged to the plug 40. In other words, the fifth semiconductor region 25 connects the plug 40 and the second semiconductor region 22, and further, by making ohmic contact with the plug 40, serves as a route for discharging holes.

[0057] That is, when the IGBT is in an on state, the plug 40 serves as a path for passing electrons from the first electrode 11 to the third semiconductor region 23, and when the IGBT is turned off, it serves as a path for discharging holes from the second semiconductor region 22 to the first electrode 11. As described above, the plug 40 electrically connects the first electrode 11 and the semiconductor substrate 20, and the semiconductor device 1 operates.

[0058] According to the semiconductor device 1 of this embodiment, the plugs 40 provided in the Y direction each have a length L1 in the X direction and a length L2 in the Y direction that is different from L1, which can suppress defective formation of the plugs 40 and improve the reliability of the semiconductor device. By improving the flatness of the first electrode 11 formed on the plug 40, stress concentration in one part of the electrode and the occurrence of cracks can be suppressed.

[0059] The plug 40 and the semiconductor substrate 20 are generally made of materials with different thermal expansion coefficients. For example, W (tungsten) contained in the plug 40 has a larger thermal expansion coefficient than Si (silicon) contained in the semiconductor substrate. When heat is applied, the plug 40 and the semiconductor substrate 20 expand to different degrees, which can cause distortion and stress. Stress generated between the plug 40 and the semiconductor substrate 20 can cause warping of the wafer. Generally, the wider the plug 40, the thicker the W (tungsten) film must be, which increases stress and raises concerns about wafer warpage. In other words, in the past, increasing the contact area between the plug 40 and the semiconductor substrate 20 could increase the stress applied to the wafer.

[0060] In the following, as an example, the plug 40 is made of W (tungsten). The plug 40 is formed, for example, by filling an opening formed by excavating the semiconductor substrate 20 and the interlayer insulating film 50 in the Z direction with a conductive material. The opening is filled by forming a film containing a conductive material (e.g., W) to a predetermined thickness on the bottom and sidewalls of the opening. For example, to form a plug 40 having a length L2 in the Y direction, a film with a thickness of L2 / 2 is formed on the sidewalls. To fill the opening, a film with a thickness of at least L2 / 2 is formed on the sidewalls of the opening. To properly fill the opening without impairing flatness and suppressing voids, the film thickness is preferably L2 × (3 / 5) or more. More preferably, the film thickness is L2 × (3 / 4) or more.

[0061] Here, the length Tmax is defined. The length Tmax is the film thickness of the W (tungsten) formed on the sidewall of the opening, and is the maximum length at which the magnitude of the stress on the wafer is equal to or less than a predetermined allowable value. The predetermined allowable value for stress is determined so that the amount of warpage of the wafer caused by the stress is sufficiently small. By making the film thickness of the W (tungsten) formed on the sidewall of the opening equal to or less than Tmax, the reliability of the semiconductor device is improved.

[0062] To suppress wafer warpage, the necessary thickness L2 / 2 of the film formed on the sidewall of the opening satisfies L2 / 2≦Tmax. In other words, L2≦2Tmax. The film with a thickness of L2 / 2 formed on the sidewall of the opening has a thickness equal to or less than Tmax, which reduces stress on the wafer. In other words, the length L2 of the plug 40 in the Y direction must be equal to or less than 2Tmax in order to reduce stress on the wafer.

[0063] To better fill the opening, it is desirable that L2≦(5 / 3)Tmax. The film with a thickness of (3 / 5)L2 formed on the sidewall of the opening has a thickness of Tmax or less, which reduces stress on the wafer. It is even more desirable that L2≦(4 / 3)Tmax.

[0064] For example, by forming the plug 40 so that L2≦(4 / 3)Tmax, L1 can be arbitrarily increased as long as it does not exceed LG. This is because the W (tungsten) film is formed thin in the Y direction to suppress wafer warpage. Furthermore, voids can be suppressed and the opening can be filled well. In other words, poor formation of the plug 40 can be suppressed.

[0065] Since L1 may be determined without considering the effect of the W film thickness on wafer warpage, the length of the region where the plug 40 contacts the second semiconductor region 22 or the third semiconductor region 23 can be increased in the X direction to widen the contact area. This reduces the on-resistance and promotes the discharge of carriers from the semiconductor substrate 20 to the plug 40 during switching, thereby reducing switching loss. Reducing switching loss reduces power consumption and makes it possible to provide a semiconductor device with improved switching performance.

[0066] Since L1 may be determined without considering the effect of the W film thickness on wafer warpage, according to this embodiment, a plug 40 with good embeddability can be formed when the range of values ​​of the distance LG in the X direction between the gate regions 30 is wider. The wide range of values ​​of the distance LG will be described later in comparison with the first and second reference examples.

[0067] Furthermore, according to this embodiment, a plurality of third semiconductor regions 23 are provided in the Y direction, and plugs may be formed so as to contact the third semiconductor regions 23, or plugs 40 may be formed so as to contact the second semiconductor region 22 between third semiconductor regions 23 spaced apart in the Y direction. The current density in the XY plane can be controlled by changing either the layout of the third semiconductor regions 23 or the layout of the plugs 40. Increasing the degree of freedom in design and controlling the amount of heat generated by current can improve the reliability of the semiconductor device.

[0068] The third semiconductor region 23 is a region that serves as a path for current when the semiconductor device 1 is in the on state, and the shorter the distance between the multiple plugs 40 in contact with the third semiconductor region 23, in other words, the smaller the degree of dispersion in the XY plane of the multiple plugs 40 in contact with the third semiconductor region 23, the higher the current density in the on state. Conversely, by increasing the degree of dispersion in the XY plane of the multiple plugs 40 in contact with the third semiconductor region 23, the current density can be suppressed and the amount of heat generated can be reduced.

[0069] For example, plugs 40 adjacent to each other in the Y direction may be located between third semiconductor regions 23 spaced apart in the Y direction. That is, by increasing the proportion of plugs 40 in contact with the second semiconductor region 22, it is possible to suppress the current density and the amount of heat generation. Furthermore, by increasing the contact area between the second semiconductor region 22 and the plugs 40, a wider carrier discharge path can be formed, thereby reducing switching loss.

[0070] After suppressing the amount of heat generation, the current density can be increased by, for example, arranging the plugs 40 adjacent in the Y direction so that they are in contact with the third semiconductor region 23 in part. In areas with relatively high heat dissipation, the current density can be designed to be high.

[0071] Furthermore, some of the plugs 40 may be provided so as to straddle the second semiconductor region 22 and the third semiconductor region 23 in the Y direction. By changing the positional relationship between the third semiconductor region 23 and the plugs 40, it is possible to adjust the degree of dispersion in the XY plane of the multiple plugs 40 that contact the third semiconductor region 23. In other words, by adjusting the arrangement of the third semiconductor region 23 and the arrangement of the plugs 40, it is possible to optimize the amount of heat generation and current density according to the electrical characteristics of the semiconductor device.

[0072] The degree of dispersion within the XY plane of the multiple plugs 40 in contact with the third semiconductor region 23 can be changed within the XY plane. For example, the degree of dispersion may be increased toward the end of the active region AR shown in FIG. 1. This can suppress the amount of heat generated at the end of the active region AR and improve reliability.

[0073] According to this embodiment, it is possible to control the current density in the XY plane by changing the layout of the plugs 40, without necessarily changing the layout of the third semiconductor region 23. This improves the degree of freedom in design for controlling the current density. Furthermore, it is possible to reduce the current density by locally changing the positional relationship between the third semiconductor region 23 and the plugs 40 in an area in the XY plane where it is desired to suppress the amount of heat generation. Note that by simultaneously changing the layout of the third semiconductor region 23 and adjusting the layout of the third semiconductor region 23 and the plugs 40, it is possible to further increase the degree of freedom in design.

[0074] Furthermore, compared to controlling the current by changing only the layout of the third semiconductor region 23, it is possible to expand the range of options for the placement of the plugs 40 for a given layout of the third semiconductor region 23. By appropriately selecting the placement of the plugs 40, it is possible to improve the electrical characteristics of the semiconductor device. That is, in addition to the layout of the third semiconductor region 23, it is possible to further control the current by the placement of the plugs 40 in the X and Y directions.

[0075] (Modification of the first embodiment) Next, a modified example of the semiconductor device 1 according to the first embodiment will be described with reference to FIG. 3. FIG. 3 is an enlarged plan view of a modified example of the semiconductor device 1 according to the first embodiment. The difference between FIG. 3 and FIG. 1B is the cross-sectional shape of the plug 40 in the XY plane. FIG. 3 shows a case where the plug 40 has an elliptical shape having a length L1 in the X direction and a length L2 in the Y direction. The length L1 in the X direction is the length of the major axis of the ellipse, and the length L2 in the Y direction is the length of the minor axis of the ellipse. For example, L2 <L1であり、L2≦2Tmaxである。L2≦(5 / 3)Tmaxでもよいし、L2≦(4 / 3)Tmaxでもよい。

[0076] Furthermore, the cross-sectional shape of plug 40 in the XY plane is not limited to the rectangle shown in Fig. 1B or the ellipse shown in Fig. 3. For example, it may be an oval or polygonal shape, or even a polygonal shape with rounded corners.

[0077] More generally, any point within a shape (e.g., a rectangle) representing the cross-sectional shape of plug 40 in the XY plane may be located within a distance of, for example, Tmax from at least one point on the periphery of the shape. The cross-sectional shape of plug 40 in the XY plane has a length of 2Tmax or less in at least one direction. When forming plug 40, the opening can be satisfactorily filled with W (tungsten) having a thickness of Tmax or less.

[0078] For example, in the ellipse shown in Figure 3, the length of the minor axis is L2 ≤ 2Tmax. The distance from the center of the ellipse to any point on the circumference of the ellipse in both directions along the Y axis (minor axis) is Tmax or less. In other words, the center of the ellipse can be well filled with a tungsten film having a thickness of Tmax or less from the sidewall of the opening. The same holds true for any point inside the ellipse, which is the cross-sectional shape of plug 40 shown in Figure 3.

[0079] Furthermore, the cross-sectional shape of the plug 40 in the XY plane may be curved, for example, L-shaped, or may be cross-shaped.

[0080] In other words, the shape of the plug 40 is not limited to an ellipse, and may be any shape that can suppress defective formation of the plug 40. A shape having long and short sides, such as a rectangle, is desirable because it suppresses defective formation of the plug 40 on the short side while allowing the contact length between the plug 40 and the semiconductor substrate 20 on the long side to be large. In this specification, a shape having long and short sides is defined as a "rectangle," including cases where the shape has a long axis and a short axis, such as an ellipse. In other words, the term "long side" is defined not only for rectangles, but also as synonymous with the long axis for shapes such as ellipses. Furthermore, when referring to a "rectangle," it is also intended to include shapes such as ovals with rounded corners.

[0081] 1B, for example, a modification of the first embodiment shown in FIG. 3 can also suppress defective formation of the plug 40 and improve the reliability of the semiconductor device. At the same time, by increasing the contact area between the plug 40 and the second semiconductor region 22, it is possible to reduce switching loss and improve the switching performance of the semiconductor device. The modification of the first embodiment has been described above.

[0082] (1st reference example) Next, a semiconductor device 101 according to a first reference example will be described with reference to Figs. 4 and 5. Differences from the first embodiment will be described in detail. Figs. 4 and 5 show an enlarged plan view and a cross-sectional view of the semiconductor device 101 according to the first reference example. Fig. 4 is an enlarged plan view showing the internal wiring structure, and Fig. 5 is a cross-sectional view showing the DD' cross section shown in Fig. 4.

[0083] First, a plan view of the first reference example will be described with reference to Fig. 4. In the semiconductor device 101, plugs 140 are provided in two rows in the X direction and extend in the Y direction. The plugs 140 are provided between a plurality of gate regions 130 provided in the X direction and extending in the Y direction. The plugs 140 contact the second semiconductor region 122 and the third semiconductor region 123 of the semiconductor substrate 120.

[0084] The gate region 130 has a gate electrode 132 and a gate insulating film 131 that covers the gate electrode 132. The gate electrode 132 and the gate insulating film 131 each extend in the Y direction. The gate electrode 132 is electrically insulated from the semiconductor substrate 120.

[0085] The second semiconductor region 122 and the third semiconductor region 123 are semiconductor regions having different conductivity types. For example, the second semiconductor region 122 is a p-type base region, and the third semiconductor region 123 is an n-type emitter region.

[0086] In the semiconductor device 101 according to the first reference example, the width in the X direction of the plug 140 is referred to as L4, the distance in the X direction between the plugs 140 arranged in two rows in the X direction is referred to as L5, and the distance in the X direction between the gate regions 130 adjacent to each other in the X direction is referred to as LG.

[0087] Next, a DD' cross-sectional view of the semiconductor device 101 according to the first reference example will be described with reference to Fig. 5. The plug 140 extends from the first electrode 111 through the interlayer insulating film 150 to reach the semiconductor substrate 120. In the DD' cross-section shown in Fig. 5, the plug 140 is in contact with the third semiconductor region 123.

[0088] A gate electrode 132 and a gate insulating film 131 covering the gate electrode 132 are buried in the gate region 130. The gate insulating film 131 reaches the first semiconductor region 121 of the semiconductor substrate 120. The gate insulating film 131 is in contact with the second semiconductor region 122.

[0089] 4 and 5, 2L4+L5≦LG, and there are two rows of plugs 140 in the X direction. If 2L4+L5>LG, it is not possible to form two rows of plugs 140 between the gate regions 130. In other words, it is not possible to form openings between the gate regions 130 in which to embed the two rows of plugs 140.

[0090] The openings are formed by excavating the semiconductor substrate 120 and the interlayer insulating film 150 in order to bury the plugs 140. A W (tungsten) film is formed in the openings to form the plugs 140. To form the plugs 140 shown in FIG. 5, it is necessary to form two rows of openings, each having a width of L4 in the X direction, spaced apart by an interval of L5 in the X direction.

[0091] Generally, L4 cannot be made infinitely small. L4 cannot be formed to be less than the length Lmin determined by the precision of excavation of the semiconductor substrate, and L4≧Lmin. When forming an opening for embedding W (tungsten), there is a limit to the processing precision for excavating the semiconductor substrate 120 and the interlayer insulating film 150. In other words, the processing precision in the excavation process may determine the minimum value of L4 that can be realized. In this way, the length Lmin can be defined as the minimum value of L4 determined by the constraints of processing precision. In other words, Lmin can be defined as the minimum diameter of the opening provided in the semiconductor substrate.

[0092] Similarly, L5 is also limited by processing accuracy, and the minimum value of L5 that can be realized can also be determined by the processing accuracy. L5 ≧ Lmin. This is because the processing accuracy of forming the opening by excavation and the processing accuracy of forming the area that remains unexcavated (mesa portion) are, for example, about the same. In the following discussion, we will assume that the minimum values ​​of both L4 and L5 are Lmin.

[0093] Since L4≧Lmin and L5≧Lmin, when LG<3Lmin, due to the limits of processing accuracy when forming the openings, 2L4+L5(≧3Lmin)>LG, and it becomes difficult to form two rows of plugs 140 in the X direction as shown in Figures 4 and 5. That is, according to the semiconductor device 101 of the first reference example, when LG<3Lmin, it becomes difficult to form the plugs 140.

[0094] Also, when LG is large, according to the first reference example, the length of the region where the plug 140 contacts the semiconductor substrate 120 in the X direction may not be able to be made wide. This is because when L4 > 2Tmax, in order to avoid the generation of voids, a thickness of at least Tmax or more is required as the W film thickness, increasing the stress applied to the wafer and promoting the warping of the wafer. To ensure the reliability of the semiconductor device, it is desirable to form it with a length of L4 ≤ 2Tmax. In addition, to ensure flatness, it is desirable to form it within the range of L4 ≤ (4 / 3)Tmax. Hereinafter, for simplicity, the case of L4 ≤ 2Tmax will be described, but the same applies to the cases of L4 ≤ (5 / 3)Tmax and L4 ≤ (4 / 3)Tmax.

[0095] When forming two rows of plugs 140 in the X direction and ensuring the reliability of the semiconductor device, the length of the region where the plug 140 contacts the semiconductor substrate 120 in the X direction can be at most 4Tmax in length. That is, it is not always possible to increase L4 proportionally to the X-direction interval LG of the gate region 130, and it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120 according to the value of LG.

[0096] Specifically, when the range of the value of LG is 4Tmax + Lmin < LG, according to the first reference example, it becomes difficult to increase the contact area between the plug 140 and the semiconductor substrate 20. This is because L5 requires a length of at least Lmin, and even if the value of LG increases, the two rows of formed plugs 140 can each have a maximum width of only 2Tmax.

[0097] When LG increases within the range of LG > 4Tmax + Lmin, in order to suppress the increase in stress and the warping of the wafer, for L4, it should be limited to a length that satisfies L4 ≤ 2Tmax, and the length of the portion where the plug 140 is not formed (the length of L5 or the length in the X direction between the plug 140 and the gate region 130) will be increased. Therefore, it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120. Since it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120, it is difficult to promote the discharge of carriers during turn-off.

[0098] In addition, as will be described later, considering the case of forming three columns of plugs 140 in the X direction, for the inequality 4Tmax + Lmin < LG, the upper limit of LG can be determined. When LG < 5Lmin, it becomes difficult to form three columns of plugs 140 in the X direction. Therefore, the range of LG values for which it is not appropriate to form two or three columns of plugs 140 can be determined as 4Tmax + Lmin < LG < 5Lmin.

[0099] Summarizing the above, according to the semiconductor device 101 according to the first reference example, when LG < 3Lmin, it is difficult to form the plug 140 between the gate regions 130. Also, when 4Tmax + Lmin < LG, it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 120 as LG increases. That is, it can be said that the structure of the first reference example is suitable only for LG within the range of 3Lmin ≤ LG ≤ 4Tmax + Lmin.

[0100] On the other hand, according to the semiconductor device 1 according to the first embodiment, the plug 40 can be formed regardless of the interval LG in the X direction of the gate region 30. In particular, even when (Lmin <) LG < 3Lmin, in the semiconductor device 1, the plug 40 can be formed.

[0101] Also, according to the semiconductor device 1 according to the first embodiment, when LG is large, it is also possible to increase L1 proportionally to LG, and the contact area between the plug 140 and the semiconductor substrate 120 can be increased according to the value of LG. In the first reference example, even in the range of LG values where it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 20, that is, when 4Tmax + Lmin < LG, according to the semiconductor device 1 according to the first embodiment, it is possible to increase the contact area between the plug 40 and the semiconductor substrate 20 proportionally to LG. Therefore, it is possible to promote the discharge of carriers during turn-off and reduce switching losses.

[0102] According to the semiconductor device 1 according to the first embodiment, the reliability and performance of the semiconductor device can be improved for a wider range of LG than in the first reference example, that is, for more diverse arrangements of the gate region 30.

[0103] (Second Reference Example) Subsequently, while referring to FIG. 6, the semiconductor device 102 according to the second reference example will be described.

[0104] FIG. 6 is an enlarged plan view showing the semiconductor device 102 according to the second reference example. The difference from the semiconductor device 101 according to the first reference example is that in the semiconductor device 102 according to the second reference example, the plugs 140 are provided in one row in the X direction and extend in the Y direction. The width of the plugs 140 provided in one row in the X direction is referred to as L6. Similar to the first reference example, the interval in the X direction of the gate region 130 is referred to as LG.

[0105] According to the semiconductor device 102 according to the second reference example, it is possible to form the plug 140 when L6 is smaller than LG. Stated differently using the length Lmin determined from the excavation accuracy, it is possible to form the plug 140 when LG ≧ Lmin.

[0106] In the semiconductor device 101 according to the first reference example shown in FIGS. 4 and 5, it was difficult to form two rows of plugs 140 when LG < 3Lmin. On the other hand, in the semiconductor device 102 according to the second reference example, the plugs 140 can be formed even when LG < 3Lmin. That is, the semiconductor device 102 according to the second reference example can form one row of plugs 140 in the X direction even when LG is smaller compared to the semiconductor device 101 according to the first reference example.

[0107] On the other hand, when L6 > 2Tmax, it is difficult to prevent defective formation of the plugs 140 while suppressing the wafer warpage. That is, in order to ensure the reliability of the semiconductor device, it is desirable that L6 satisfies L6 ≤ 2Tmax.

[0108] In the semiconductor device 102 according to the second reference example, in order not to impair the reliability of the semiconductor device, it is necessary to form the plugs 140 within the range that satisfies L6 ≤ 2Tmax. As LG increases within the range of LG > 2Tmax, it becomes difficult to proportionally increase the contact area between the plugs 140 and the semiconductor substrate 120 in proportion to LG.

[0109] Summarizing the above, according to the semiconductor device 102 according to the second reference example, only for LG within the range of Lmin ≤ LG ≤ 2Tmax, by widening the contact area between the plugs 140 and the semiconductor substrate 120, the discharge of carriers can be promoted, and the performance of the semiconductor device can be improved.

[0110] On the other hand, according to the semiconductor device 1 according to the first embodiment, by increasing L1 in accordance with LG, the contact area between the plugs 40 and the semiconductor substrate 20 can also be increased for LG in the range of 2Tmax < LG, promoting the discharge of carriers and improving the switching performance of the semiconductor device.

[0111] The semiconductor device 102 according to the second reference example has been described above.

[0112] Next, the semiconductor device 101 according to the first reference example and the semiconductor device 102 according to the second reference example will be described while comparing them with the semiconductor device 1 according to the first embodiment. Stated from the conclusion, when LG is within the range of 2Tmax < LG < 3Lmin or 4Tmax + Lmin < LG, neither the structure of the first reference example nor the second reference example is suitable. On the other hand, the semiconductor device 1 according to the first embodiment can increase the contact area between the plug 140 and the semiconductor substrate 20 for any value of LG greater than Lmin.

[0113] For both the semiconductor device 101 according to the first reference example and the semiconductor device 102 according to the second reference example, it becomes difficult to improve the performance when the interval LG in the X direction of the gate region 130 is within a specific range.

[0114] That is, depending on the value of LG, it was necessary to select each time whether to apply the semiconductor device 101 according to the first reference example or the semiconductor device 102 according to the second reference example. Moreover, there was a problem that there was a range of LG in which the plug 140 could not be efficiently formed even when using either the semiconductor device 101 according to the first reference example or the semiconductor device 102 according to the second reference example.

[0115] Here, being able to efficiently form the plug 140 means that it is possible to increase the contact area between the plug 140 and the semiconductor substrate 20 as LG increases. Conversely, when it is difficult to increase the contact area between the plug 140 and the semiconductor substrate 20 with an increase in LG, it can be said that the plug 140 cannot be efficiently formed.

[0116] Note that LG may be determined by the configuration of the semiconductor device. For example, based on characteristics such as the withstand voltage required for the semiconductor device, the interval of the gate region of the IGBT may be determined. Therefore, LG cannot always be arbitrarily selected, and there may be cases where a gate region 30 having a value of LG within the range of 2Tmax < LG < 3Lmin or 4Tmax + Lmin < LG must be formed.

[0117] When the value of LG required for the semiconductor device is within the range of 2Tmax < LG < 3Lmin or 4Tmax + Lmin < LG, neither of the first and second reference examples is appropriate. That is, neither the first nor the second reference example can efficiently form the plug 140.

[0118] Furthermore, for example, focusing on the range of the value of LG for which the first reference example can be judged suitable, 3Lmin ≤ LG ≤ 4Tmax + Lmin, the smaller the difference between 2Tmax and Lmin, the more limited the range of the value of LG that satisfies the inequality. That is, the more similar the lengths of 2Tmax and Lmin are, the narrower the range of LG for which the structure of the first reference example is suitable. The same applies to the range of the value of LG for which the second reference example is suitable, Lmin < LG < 2Tmax.

[0119] That is, for example, as the stress on the wafer needs to be suppressed and the thickness of the tungsten film needs to be reduced, in the structures according to the first and second reference examples, the range of the value of LG that can efficiently form the plug 140 is limited. As the range of the value of LG is limited, the design freedom of the semiconductor device is reduced.

[0120] The above has explained the inequality regarding LG. On the other hand, it may be necessary to consider the inequality regarding L1 together. The inequality regarding L1 can be considered in the case where L1 is set to be smaller than LG by a certain value as a countermeasure against the misalignment error in the X direction when forming the plug 40. That is, in reality, L1 is not necessarily formed to have the same length as LG (it is not always possible to form the plug 40 as long as LG > Lmin), and it may be appropriate to consider the inequality regarding the length L1 at which the plug 40 is formed.

[0121] For example, when Lmin < LG, it is not always possible to form the plug 40 shown in FIG. 1B. This is because when forming the plug 40 having L1 with a length equivalent to LG, an alignment error may occur in the X direction, which may cause the plug 40 and the gate electrode 32 to be electrically connected. Therefore, it is conceivable to form L1 to be smaller than LG by the amount of the alignment error so that the plug 40 and the gate electrode 32 are not electrically connected. In this case, even if Lmin < LG, there is a possibility that L1 < Lmin, which may become impossible to achieve considering the precision of the excavation.

[0122] On the other hand, if Lmin < L1, from the viewpoint of the precision of the excavation, the plug 40 shown in FIG. 1B can be formed. That is, considering the alignment error, Lmin < LG and Lmin < L1 are not always synonymous. Therefore, it is desirable to consider the inequality for LG and the inequality for L1.

[0123] In the semiconductor device 1 according to the first embodiment shown in FIG. 3, the inequality for LG can be rewritten as an inequality for L1. For example, for the inequality 2Tmax < LG < 3Lmin, it can be rewritten as an inequality for L1: 2Tmax < L1 < 3Lmin. When the inequality for LG is rewritten as an inequality for L1, the semiconductor device 1 according to the first embodiment can form the plug 40 even when 2Tmax < L1 < 3Lmin or 4Tmax + Lmin < L1 (< 5Lmin).

[0124] Hereinafter, more generally, a case where n columns (n is a natural number) of plugs 140 are formed in the X direction between the gate regions 130 (not shown) will be described. The first embodiment corresponds to the case of n = 2, and the second embodiment corresponds to the case of n = 1.

[0125] For example, when n = 3, three columns of plugs 140 with a width of L4 are formed in the X direction, and a semiconductor substrate 20 with a width of L5 exists between the plugs 140. Therefore, 3L4 + 2L5 ≤ LG must hold, and since Lmin ≤ L4 and Lmin ≤ L5, in order to form three columns of plugs 140, it is necessary that 5Lmin ≤ LG.

[0126] Also, when n = 3, when 6Tmax + 2Lmin < LG, it becomes difficult to increase the contact area between the plug 140 and the semiconductor substrate 20 in proportion to LG, that is, it becomes difficult to efficiently form the plug 140. In other words, when n = 3, the plug 140 can be efficiently formed only within the range of 5Lmin ≤ LG ≤ 6Tmax + 2Lmin.

[0127] Therefore, it is located between the range of LG values for which the second reference example (n = 2) is appropriate, 3Lmin ≤ LG ≤ 4Tmax + Lmin, and the range of LG values for which the example of n = 3 is appropriate, 5Lmin ≤ LG ≤ 6Tmax + 2Lmin. The range of LG values for which neither structure is appropriate is 4Tmax + Lmin < LG < 5Lmin.

[0128] By the same argument, generally when n columns (n is a natural number) of plugs are formed in the X direction between the gate regions 130, the plug 140 cannot be efficiently formed unless (2n - 1)×Lmin ≤ LG ≤ n×2Tmax + (n - 1)×Lmin.

[0129] As described above, when LG is within the range of 2Tmax < LG < 3Lmin, the plug 140 cannot be efficiently formed by either the second embodiment in the case of n = 1 or the first embodiment in the case of n = 2. Similarly, for a certain natural number n, if LG is within the range of the inequality n×2Tmax + (n - 1)×Lmin < LG < (2n + 1)×Lmin, it is difficult to efficiently form n columns of plugs 140 in the X direction.

[0130] That is, in the method of forming n columns of plugs 140 in the X direction, in addition to the increase in manufacturing cost by changing the number of columns of plugs 140 formed in the X direction according to the value of LG, even if an attempt is made to optimize n within the range of natural numbers, depending on the value of LG, there is a risk that the plugs 140 cannot be formed efficiently.

[0131] Furthermore, as is clear from the inequality (2n - 1)×Lmin < LG < n×2Tmax+(n - 1)×Lmin, not only in the cases of n = 1 and 2, but for any natural number n, for example, as the stress on the wafer needs to be suppressed and the thickness of the tungsten film needs to be reduced, the range of values of LG for which it is appropriate to form n columns of plugs 140 becomes narrower.

[0132] On the other hand, according to the semiconductor device 1 according to the first embodiment, regardless of the value of LG, since L1 can be made large in proportion to LG, the contact area between the plug 40 and the semiconductor substrate 20 can be increased in proportion to LG. That is, plugs 40 can be formed efficiently over a wider range of LG values. Specifically, for a certain natural number n, even when LG is within the range of the inequality n×2Tmax+(n - 1)×Lmin < LG < (2n + 1)×Lmin, it is possible to form the plugs 40 efficiently. Therefore, compared with the method of forming n columns of plugs 140 in the X direction, the degree of freedom in the design of the semiconductor device is increased.

[0133] According to the semiconductor device 1 according to the first embodiment, it is possible to form the plugs 40 efficiently even when the range of the value of LG is wider. For example, even when the value of LG is restricted due to the electrical characteristics of the semiconductor device, the plugs 40 can be formed efficiently. By expanding the range of selection of the value of LG, for example, when controlling the magnitude and distribution of the current flowing through the semiconductor device by the arrangement of the gate region 30, the range of selection related to the optimization of current control can be expanded. By appropriately selecting the value of LG, the electrical characteristics can be improved.

[0134] (Second Embodiment) 7, 8A, and 8B, a semiconductor device 2 according to a second embodiment will be described. The semiconductor device 2 according to the second embodiment is an example of a structure realized by increasing the degree of freedom in designing the third semiconductor region 23 and the plug 40.

[0135] 7, 8A, and 8B are an enlarged plan view and a cross-sectional view showing a semiconductor device 2 according to a second embodiment. FIG. 7 is an enlarged plan view, FIG. 8A shows the E-E' cross section shown in FIG. 7, and FIG. 8B shows the F-F' cross section shown in FIG. 7. Some descriptions of parts of FIG. 7 that are common to FIG. 1B will be omitted. Some descriptions of parts of FIGS. 8A and 8B that are common to FIG. 2A will be omitted.

[0136] 7 has third semiconductor regions 23 that are disposed between a plurality of gate regions 30 that are provided in the X direction and that are offset from one another in the X and Y directions. That is, a plurality of third semiconductor regions 23 are provided in the Y direction, and at least one set of the plurality of third semiconductor regions 23 is disposed with an offset from one another in the X direction. Displacement from one another in the X direction means that at least one of the third semiconductor regions 23 is unevenly distributed between the gate regions 30 in the positive direction of the X direction, and at least one of the third semiconductor regions 23 is unevenly distributed between the gate regions 30 in the negative direction of the X direction.

[0137] Here, the phrase "the third semiconductor regions 23 are unevenly distributed in the positive (negative) direction of the X direction" between the gate regions 30 means that, for each of the multiple third semiconductor regions 23, the center of the third semiconductor region 23 is located in the positive (negative) direction of the X direction with respect to a median line MM' connecting points equidistant from two gate regions 30 adjacent to each other in the X direction. Among the third semiconductor regions 23 unevenly distributed in the positive direction of the X direction, the end in the negative direction of the X direction may be located in the negative direction of the X direction relative to the median line MM', as in the example shown in FIG. 7. Even when the end in the negative direction of the X direction of the third semiconductor region 23 is located in the positive direction of the X direction relative to the median line MM', according to this embodiment, good contact can be achieved by the multiple plugs 40 provided in the Y direction.

[0138] The gate region 30 includes a first gate insulating film 31a and a first gate electrode 32a, and a second gate insulating film 31b and a second gate electrode 32b. The first gate electrode 32a is covered by the first gate insulating film 31a. The second gate electrode 32b is covered by the second gate insulating film 31b. The first gate insulating film 31a and the second gate insulating film 31b are formed spaced apart in the X direction.

[0139] In the third semiconductor region 23, there are regions close to the first gate insulating film 31a and regions close to the second gate insulating film 31b among the first gate insulating film 31a and the second gate insulating film 31b of the gate region 30.

[0140] That is, when comparing the distance in the X direction between the third semiconductor region 23 and the first gate insulating film 31a with the distance in the X direction between the third semiconductor region 23 and the second gate electrode 32b, in the third semiconductor region 23, a region where the former is shorter than the latter and a region where the former is longer than the latter are provided respectively.

[0141] A plurality of plugs 40 are provided in the Y direction so as to be electrically connected to the third semiconductor region 23 arranged shifted from each other in the X direction like this. The length L1 in the X direction and the length L2 in the Y direction of the plug 40 are different. For example, L1 < L2 and L1 ≤ 2Tmax. In order to improve flatness and suppress voids to embed the plug 40 better, it is desirable that L1 ≤ (5 / 3)Tmax or less. More desirably, L1 ≤ (4 / 3)Tmax or less.

[0142] FIG. 8A is a cross-sectional view taken along the line E - E' shown in FIG. 7. The third semiconductor region 23 is unevenly distributed in the vicinity of one gate region 30 in the X direction. In other words, the distance between the third semiconductor region 23 and the first gate insulating film 31a is shorter than the distance between the third semiconductor region 23 and the second gate insulating film 31b.

[0143] The plug 40 is provided to penetrate the interlayer insulating film 50, and electrically connects the first electrode 11 and the semiconductor substrate 20. The plug 40 may be covered with a barrier metal 41. The barrier metal 41 has a layer structure containing, for example, Ti and TiN.

[0144] 8A shows an example in which the plug 40 is formed on the third semiconductor region 23 near the center of the third semiconductor region 23. On the other hand, the plug 40 may penetrate the third semiconductor region 23 in the Z direction and reach the second semiconductor region 22. Furthermore, the plug 40 is not limited to being formed near the center of the third semiconductor region 23 in the X direction, and may be formed at a position closer to or farther from the first gate insulating film 31a.

[0145] 8B is a cross-sectional view taken along the line F-F' in FIG. 7. The third semiconductor region 23 is unevenly distributed in the vicinity of the gate region 30, on the opposite side in the X direction from that in FIG. 8A. The distance between the third semiconductor region 23 and the first gate insulating film 31a is longer than the distance between the third semiconductor region 23 and the second gate insulating film 31b.

[0146] The semiconductor substrate 20 and the first electrode 11 are electrically connected via a plug 40 .

[0147] According to the semiconductor device 2 of this embodiment, by arranging the plug 40 in accordance with the arrangement of the third semiconductor region 23, the electrical connection between the third semiconductor region 23 and the plug 40, and therefore the electrical connection between the semiconductor substrate 20 and the first electrode 11, is improved.

[0148] First, a comparison will be made with a case where electrical connection to the third semiconductor region 23 is attempted using a single plug 40 extending in the Y direction, as in the semiconductor device 102 according to the second reference example shown in Fig. 6. With the single plug 140 shown in Fig. 6, if the third semiconductor region 23 is unevenly distributed in the positive or negative direction of the X direction, there is a risk that the contact area between the plug 140 and the third semiconductor region 23 will be reduced. Furthermore, there is a risk that electrical connection between the plug 140 and the third semiconductor region 23 will not be made in parts.

[0149] 7, when the third semiconductor region 23 has portions that are unevenly distributed in both the positive and negative directions of the X direction, a single plug 140 such as that shown in FIG. 6 may not be able to sufficiently contact the third semiconductor region 23. In other words, when the plug 140 is formed so as to contact the third semiconductor region 23 that is unevenly distributed in one direction, it is difficult for the plug 140 to contact the third semiconductor region 23 that is unevenly distributed in the other direction.

[0150] 7 according to this embodiment, the arrangement of each of the multiple plugs 40 can be adjusted in the X direction, which makes it possible to form the plugs 40 above each of the third semiconductor regions 23 unevenly distributed in the X direction. This makes it possible to ensure reliable contact between the plugs 40 and the third semiconductor regions 23.

[0151] For example, in FIG. 8A, the first semiconductor region 21 is an n-type drift layer, and the second semiconductor region 22 is a p ― The third semiconductor region 23 is an n-type base layer. + Consider the case where the emitter layer has a n-type n-type structure. By applying a positive voltage to the gate electrode 32 relative to the first electrode 11, an n-type inversion layer is generated in the second semiconductor region 22, and the semiconductor device 2 is turned on. FIG. 8A shows a structure in which the third semiconductor region 23 is unevenly distributed near the first gate electrode 32a among the multiple gate electrodes 32. Therefore, current flowing in the on state flows from the first semiconductor region 21 to the third semiconductor region 23, mainly through the inversion layer generated around the first gate insulating film 31a.

[0152] The current that flows into the third semiconductor region 23 flows to the first electrode 11, which is, for example, an emitter electrode, via the plug 40 electrically connected to the third semiconductor region 23. In this embodiment, the plug 40 is arranged close to one of the gate regions 30 (first gate insulating film 31 a and first gate electrode 32 a) in FIG. 8A in accordance with the arrangement of the third semiconductor region 23. This makes it possible to ensure a more reliable electrical connection between the third semiconductor region 23 and the plug 40 than when the plug 40 is arranged close to the gate region 30 (second gate insulating film 31 b and second gate electrode 32 b) in FIG. 8A where the third semiconductor region 23 is not unevenly distributed.

[0153] The same applies to the arrangement of the third semiconductor regions 23 and the plugs 40 shown in FIG. 8B.

[0154] In this way, by providing the plugs 40 in accordance with the arrangement of the third semiconductor regions 23, the semiconductor device 2 according to this embodiment can achieve good electrical connection between the semiconductor substrate 20 and the first electrodes 11 via the plugs 40. In other words, the semiconductor device 2 according to this embodiment can improve the design freedom of the semiconductor device by diversifying the possible structures of the third semiconductor regions 23. For a given layout of the third semiconductor regions 23, the range of options for optimizing current control can be expanded, including the arrangement of the plugs 40 unevenly distributed in the X direction between the gate regions 30. By appropriately selecting the layout of the third semiconductor regions 23 and the plugs 40, it is possible to further improve the electrical characteristics.

[0155] (Third embodiment) 9 and 10 are an enlarged plan view and a cross-sectional view showing a semiconductor device 3 according to the third embodiment. Fig. 10 is a cross-sectional view showing the G-G' cross section shown in Fig. 9. Explanations of parts common to the first embodiment will be omitted as appropriate, and differences will be explained.

[0156] In the semiconductor device 3 according to this embodiment, the gate electrode 32 provided in the gate region 30 is electrically connected to the plug 40. In FIG. 9, a plurality of plugs 40 are provided in the Y direction with respect to the gate region 30 extending in the Y direction. In FIG. 9, the gate pad 13 and the interlayer insulating film 50 shown in FIG. 10 are omitted.

[0157] As shown in FIG. 9, the plug 40 has a length L1 in the X direction and a length L2 in the Y direction. L1 is smaller than the length L7 of the gate electrode 32 in the X direction. Also, for example, L2 < L7, and the gate region 30 is wide in the X direction. The interval in the Y direction between the plurality of plugs 40 formed in the Y direction is L3. For example, L2 < L1.

[0158] The plug 40 is electrically insulated from the semiconductor substrate 20 by the gate insulating film 31.

[0159] FIG. 10 is a cross-sectional view taken along the line G-G′ of FIG. 9. As shown in FIG. 10, the gate pad 13 is electrically connected to the gate electrode 32 via the plug 40. The plug 40 is made of a metal containing, for example, W (tungsten). The gate electrode 32 contains, for example, polysilicon. The gate electrode 32 is, for example, the gate electrode of an IGBT, and the gate pad 13 is, for example, a gate pad electrically connected to the gate electrode 32. By applying a voltage to the gate pad 13, the potential of the gate electrode 32 can be controlled.

[0160] The plug 40 may be coated with a barrier metal 41. The barrier metal 41 has, for example, a layer structure containing Ti and TiN.

[0161] Note that the semiconductor device 3 according to this embodiment may have a first electrode 11 provided on the interlayer insulating film 50 in a region separated from the regions shown in FIGS. 9 and 10. The first electrode 11 is, for example, the emitter electrode of an IGBT. The first electrode 11 is electrically connected to the third semiconductor region 23 of the semiconductor substrate 20 via a conductive member (not shown) provided in the interlayer insulating film 50. The third semiconductor region 23 is, for example, the emitter region of an IGBT.

[0162] Furthermore, the conductive member connecting the first electrode 11 and the semiconductor substrate 20 may be a plug 40 different from the plug 40 shown in FIGS. 9 and 10. In other words, a plug 40 different from the illustrated plug 40 may electrically connect the semiconductor substrate 20 and the first electrode 11 not shown in FIG. 9. The semiconductor device 3 according to the present embodiment may have a structure as shown in FIGS. 1B and 2A in a region not shown in FIG. 9.

[0163] That is, the potentials of the semiconductor substrate 20 and the gate electrode 32 may be respectively controlled via a plurality of plugs 40. That is, the potential of the semiconductor substrate 20 can be controlled via the plug 40 by a structure not shown in FIGS. 9 and 10, and the potentials of the emitter electrode and the gate electrode of the IGBT can be separately controlled via different plugs 40.

[0164] According to the semiconductor device 3 according to the present embodiment, by providing a plurality of plugs 40 spaced apart from each other in the Y direction, the electrical connection between the gate pad 13 and the gate electrode 32 can be improved regardless of the value of L7. For various shapes of the gate electrode 32, it is possible to improve the electrical connection by the plug 40 and surely form an inversion layer on the semiconductor substrate 20.

[0165] Furthermore, by setting the length of the shorter one of L1 and L2 to be, for example, 2Tmax or less, it is possible to suppress warping of the wafer and suppress defective formation of the plug 40. By suppressing defective formation, the reliability of the semiconductor device can be improved.

[0166] According to the semiconductor device 3 according to the present embodiment, a plug 40 having L1 with a magnitude proportional to L7 can be formed. As L7 increases, it is possible to increase the contact area between the gate electrode 32 and the plug 40.

[0167] Note that L7 may be within a range of the inequality n×2Tmax+(n - 1)×Lmin < L7 < (2n + 1)×Lmin for a certain natural number n.

[0168] The wider range of options for the value of L7 allows for a wider range of options for optimizing current control, for example, when controlling the magnitude and distribution of the current flowing through the semiconductor device by the placement of the gate region 30. By selecting the value of L7 appropriately, the electrical characteristics can be improved.

[0169] Furthermore, by electrically connecting the gate electrode 32 and the gate pad 13 via the plug 40, it becomes possible to control the potential of the gate electrode 32. The potential of each of the gate electrodes 32 provided in the X direction can be controlled by a separate plug 40, and a multi-gate structure can be achieved using the multiple plugs 40. By individually controlling the potential of the gate electrodes 32, it is possible to reduce loss during switching and further improve the performance of the semiconductor device.

[0170] In at least one embodiment described above, the multiple plugs 40 provided in the Y direction each have a length L1 in the X direction and a length L2 in the Y direction, with at least one of L1 and L2 being short so as to suppress stress on the wafer. Therefore, by making the other of L1 and L2 long and increasing the contact area between the plug 40 and the semiconductor substrate 20, the performance of the semiconductor device can be improved for a wider range of LG or L7 values. Furthermore, defective formation of the plug 40 can be suppressed, thereby improving the reliability of the semiconductor device.

[0171] Furthermore, it is possible to improve the degree of freedom in design regarding the range of the value of LG or L7, and also to improve the degree of freedom in design regarding the layout of the third semiconductor region 23 and the plug 40. It is possible to widen the range of selection for the value of LG or L7, or the layout of the third semiconductor region 23 and the plug 40. By appropriately selecting the value of LG or L7, or the layout of the third semiconductor region 23 and the plug 40, it is possible to improve the electrical characteristics of the semiconductor device by optimizing current control.

[0172] A method for manufacturing a semiconductor device will be described below.

[0173] A method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

[0174] In the following description, Figures 11, 12, ..., 16 are cross-sectional views corresponding to the A-A' cross section shown in Figure 1B. That is, Figures 11, 12, ..., 16 show cross-sectional views at positions corresponding to the A-A' cross section of Figure 1B, which is a completed drawing, in each manufacturing process.

[0175] In the description of the manufacturing method, the formation of the plug 40 will be described in detail, but the formation of the gate region 30, the semiconductor substrate 20, and the second electrode 12 will be omitted because they are not significantly different from general manufacturing methods.

[0176] FIG. 11 is a cross-sectional view showing a step of providing an interlayer insulating film 50. The semiconductor device 1 has a semiconductor substrate 20, the manufacturing method of which will be omitted, and a gate region 30. The semiconductor substrate 20 contains, for example, Si, and the n-type semiconductor layer is formed by doping, for example, with P, and the p-type semiconductor layer is formed by doping, for example, with B. The gate region 30 has a gate insulating film 31 and a gate electrode 32. The gate insulating film 31 contains, for example, silicon oxide. The gate electrode 32 is, for example, polysilicon.

[0177] 11, an interlayer insulating film 50 is provided on the semiconductor substrate 20 and the gate region 30. The interlayer insulating film 50 is an oxide film containing silicon oxide formed by, for example, CVD (Chemical Vapor Deposition).

[0178] 12, a resist 60 is provided on the interlayer insulating film 50. The resist 60 is selectively formed by, for example, photolithography.

[0179] Next, as shown in FIG. 13, openings 70 are formed by excavating portions where the resist 60 is not provided. A plurality of openings 70 are formed spaced apart from one another in the Y direction. The openings 70 are formed by, for example, RIE (Reactive Ion Etching) or CDE (Chemical Dry Etching). Some of the plurality of openings 70 penetrate the third semiconductor region 23 and reach the second semiconductor region 22, as shown in FIG. 13. Some of the openings 70 may reach the second semiconductor region 22 without contacting the third semiconductor region 23 in a cross section different from the A-A' cross section shown in FIG. 13.

[0180] Subsequently, the resist 60 is stripped, and the conductive film 80 is formed as shown in FIG. 14. However, the barrier metal 41 may be formed before the conductive film 80 is formed. The barrier metal 41 has a layer structure containing, for example, Ti and TiN. The barrier metal 41 is formed by, for example, CVD. The conductive film 80 contains, for example, W (tungsten). The conductive film 80 is formed by, for example, CVD.

[0181] Subsequently, as shown in FIG. 15, the conductive film 80 is partially removed by etching back, and the remaining portion is called a plug 40.

[0182] Finally, as shown in FIG. 16, a first electrode 11 is provided on the plug 40 and the interlayer insulating film 50. The first electrode 11 includes, for example, AlCu or AlSi. The first electrode 11 is formed by, for example, sputtering. In this way, the configuration shown in FIG. 2A is obtained.

[0183] In the manufacturing method described above, in the step of embedding the conductive film 80 in the opening 70 to form the plug 40, as described for example for the semiconductor device 1 according to the first embodiment, by providing a plurality of plugs 40 in the Y direction, it is possible to increase the contact area between the plug 40 and the semiconductor substrate 20 over a wider range of the value range of the spacing (LG shown in FIG. 1B) between the gate regions 30. Furthermore, in the step of embedding the conductive film 80 in the opening 70 to form the plug 40, by having the opening 70 be, for example, rectangular in the XY plane, it is possible to reduce the stress applied to the semiconductor substrate 20 by the plug 40, while suppressing the occurrence of voids and achieving good embedding.

[0184] The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, designs that are appropriately modified by a person skilled in the art from these specific examples are also included within the scope of the embodiments as long as they have the characteristics of the embodiments. The elements, as well as their arrangement, materials, conditions, shapes, sizes, etc., of the above-mentioned specific examples are not limited to those exemplified and can be modified as appropriate.

[0185] Furthermore, the elements of each of the above-described embodiments can be combined to the extent technically possible, and combinations of these are also included within the scope of the embodiments as long as they include the features of the embodiments. In addition, within the scope of the concept of the embodiments, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the embodiments.

[0186] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0187] 11, 111...1st electrode 12...Second electrode 13. Gate pad 20, 120... Semiconductor substrate 21, 121... First semiconductor region 22, 122... Second semiconductor region 23, 123...Third semiconductor region 24...Fourth semiconductor region 25. Fifth Semiconductor Region 30, 130... gate area 31, 131···Gate insulating film 32, 132 Gate electrode 31a...First gate insulating film 31b: Second gate insulating film 32a...first gate electrode 32b: Second gate electrode 40, 140 plug 41, 141... Barrier metal 50, 150... Interlayer insulating film 60···Resist 70...Opening 80 Conductive film 1, 2, 3, 101, 102... Semiconductor device Lmin: Length LG...interval Tmax: Length L1: Length of the plug of semiconductor device 1, 2 or 3 in the X direction L2: Length of the plug of semiconductor device 1, 2 or 3 in the Y direction L3: Spacing between plugs of semiconductor device 1 in the Y direction L4: Length of the plug of the semiconductor device 101 in the X direction L5: Spacing between plugs of semiconductor device 101 in the X direction L6: Length of the plug of the semiconductor device 102 in the X direction L7: Length in the X direction of the gate region of the semiconductor device 3 D Depth

Claims

1. A first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a semiconductor substrate having an interlayer insulating film provided on the semiconductor substrate; a first electrode provided on the interlayer insulating film; a second electrode provided below the semiconductor substrate; a plurality of gate regions extending in a second direction intersecting the first direction from the interlayer insulating film to the semiconductor substrate, the gate regions intersecting the first direction and the second direction; a plurality of plugs positioned between the gate regions in the second direction, spaced apart from one another in the third direction, penetrating the third semiconductor region, contacting the second semiconductor region, and electrically connecting the first electrode and the semiconductor substrate; A semiconductor device having:

2. the plug has a rectangular shape in a plane including the second direction and the third direction; The long side of the rectangular shape of the plug extends along the second direction. The semiconductor device according to claim 1 .

3. The gate region is a gate electrode embedded in the gate region; a gate insulating film covering the gate electrode; and the gate electrode faces the second semiconductor region via the gate insulating film; The semiconductor device according to claim 1 .

4. A first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a semiconductor substrate having an interlayer insulating film provided on the semiconductor substrate; a first electrode provided on the interlayer insulating film; a second electrode provided below the semiconductor substrate; a plurality of buried electrodes extending from the interlayer insulating film to the semiconductor substrate in a first direction that is a thickness direction of the semiconductor substrate, in a second direction that intersects the first direction, and extending in a third direction that intersects the first and second directions, the buried electrodes facing the second semiconductor region via an insulating film; a plurality of plugs positioned between the buried electrodes in the second direction, spaced apart from one another in the third direction, the length of which in the second direction is shorter than the interval between the buried electrodes adjacent to each other in the second direction, and the plugs electrically connecting the first electrodes to the semiconductor substrate; A semiconductor device having:

5. the plug has a rectangular shape in a plane including the second direction and the third direction; The long side of the rectangular shape of the plug extends along the second direction. The semiconductor device according to claim 4 .

6. a plurality of the third semiconductor regions are provided spaced apart in the third direction between the plurality of buried electrodes provided in the second direction; The semiconductor device according to claim 4 .

7. At least one plug contacting the second semiconductor region is provided between the third semiconductor regions spaced apart in the third direction. The semiconductor device according to claim 6.

8. Among the plurality of plugs provided, at least some of the plugs adjacent to each other in the third direction are in contact with the third semiconductor region. The semiconductor device according to claim 7 .

9. Among the plurality of plugs provided, at least some of the plugs adjacent to each other in the third direction are located between the third semiconductor regions spaced apart in the third direction. The semiconductor device according to claim 7 .

10. a portion of the third semiconductor region is unevenly distributed in one direction of the second direction between the buried electrodes, and a portion of the third semiconductor region is unevenly distributed in an opposite direction in the second direction; the plurality of plugs provided in the third direction are arranged to be unevenly distributed in the same direction as the direction in which the third semiconductor region is unevenly distributed in the second direction; The semiconductor device according to claim 6.

11. a depth D of the plug in the first direction and a length L1 of the plug in the second direction satisfy 0<D / L1≦2; The semiconductor device according to claim 1 .

12. The plug contains W, The plug further includes a barrier metal including Ti and TiN. The semiconductor device according to claim 1 .

13. The plug penetrates the third semiconductor region and contacts the second semiconductor region. The semiconductor device according to claim 4 .

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