Semiconductor Devices

Abstract

This semiconductor device (10) comprises: a plurality of sets of gate trenches (S1, S2); a plurality of gate electrodes; a plurality of field plate electrodes; a gate wiring (52); and a source wiring (50). The plurality of field plate electrodes each include two terminals connected to the source wiring (50). An outer peripheral gate wiring part (58) of the gate wiring (52) includes a gate finger (58A2) that extends along a first direction in a plan view, and an inner gate wiring part (60) includes a gate finger (60B) that extends along a second direction in a plan view. A first set of gate trenches (S1_1 to S1_6) extend along the first direction in a plan view and cross the gate finger (60B), and a second set of gate trenches (S2_1 to S2_4) extend in the second direction in a plan view and cross the gate finger (58A2).

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a metal insulator semiconductor field effect transistor (MISFET) having a trench gate structure. In the semiconductor device of Patent Document 1, a gate electrode embedded in each of a plurality of gate trenches is electrically connected to a gate wiring (gate finger) via a gate contact. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-202313 Summary of the Invention [Problem to be solved by the invention]

[0004] In a MISFET having a trench gate structure, the shorter the length of the gate trench, the more the resistance of the electrode (e.g., gate electrode) embedded in the gate trench can be reduced. By using gate fingers as described in Patent Document 1, the length of the gate trench arranged in the chip can be made relatively short. However, an arrangement in which multiple gate trenches each extend in the same direction in a plan view poses the problem that the warping of the semiconductor substrate (wafer) on which the MISFET is formed becomes relatively large during processing. [Means for solving the problem]

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate and including, in a plan view, a periphery region and an active region surrounded by the periphery region, a plurality of sets of gate trenches formed in the semiconductor layer, including a first set and a second set of gate trenches, a plurality of gate electrodes each embedded in a corresponding one of the sets of gate trenches, a plurality of field plate electrodes each embedded in a corresponding one of the sets of gate trenches while being insulated from the gate electrode, an insulating layer formed on the semiconductor layer, a gate wiring formed on the insulating layer and connected to the plurality of gate electrodes, the gate wiring including a periphery gate wiring portion disposed in the periphery region in a plan view and an inner gate wiring portion disposed in the active region in a plan view, and a source wiring formed on the insulating layer and spaced from the gate wiring, each of the plurality of field plate electrodes having two ends connected to the source wiring. The outer peripheral gate wiring portion includes a first gate finger extending along a first direction in a plan view, and the inner gate wiring portion includes a second gate finger extending along a second direction perpendicular to the first direction in a plan view. Each of the first set of gate trenches extends along the first direction in a plan view and intersects with the second gate finger, and each of the second set of gate trenches extends along the second direction in a plan view and intersects with the first gate finger. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, it is possible to reduce the length of the gate trench and reduce the warpage of the semiconductor substrate. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2]FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic plan view of an exemplary semiconductor device according to a first modification. [Figure 5] FIG. 5 is a schematic plan view of an exemplary semiconductor device according to the second modification. [Figure 6] FIG. 6 is a schematic plan view of an exemplary semiconductor device according to a third modification. [Figure 7] FIG. 7 is a schematic plan view of an exemplary semiconductor device according to a fourth modification. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] 1 is a schematic plan view of an exemplary semiconductor device 10 according to one embodiment. Note that the term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal X, Y, and Z axes shown in FIG.

[0011] The semiconductor device 10 is, for example, a MISFET having a trench gate structure. The semiconductor device 10 includes a semiconductor substrate 12, a semiconductor layer 14 formed on the semiconductor substrate 12, multiple pairs of gate trenches S1, S2 formed in the semiconductor layer 14, and an insulating layer 16 formed on the semiconductor layer 14. In this embodiment, the semiconductor substrate 12 may be a Si substrate. The semiconductor substrate 12 includes a bottom surface 12A, which will be described later with reference to FIG. 2, and a top surface 12B opposite to the bottom surface 12A. In FIG. 1, the Z direction is a direction perpendicular to the bottom surface 12A and the top surface 12B of the semiconductor substrate 12.

[0012] In the example of FIG. 1 , the top surface 12B of the semiconductor substrate 12 includes two sides (first sides) 12C and 12E extending along the X direction and two sides (second sides) 12D and 12F extending along the Y direction. Because the top surface 12B of the semiconductor substrate 12 is covered with the semiconductor layer 14 and the insulating layer 16, only the rectangular outer edge (i.e., four sides 12C, 12D, 12E, and 12F) of the semiconductor substrate 12 is shown in FIG. 1 . The area defined by the outer edge of the semiconductor substrate 12 shown in FIG. 1 may correspond to one chip (die). In this disclosure, the X direction is also referred to as the first direction, and the Y direction is also referred to as the second direction. In the example of FIG. 1 , the sides 12C and 12E extending along the X direction have the same length and are shorter than the sides 12D and 12F extending along the Y direction. Sides 12D and 12F extending along the Y direction have the same length and are longer than sides 12C and 12E extending along the X direction. That is, the short-side direction and long-side direction of top surface 12B of semiconductor substrate 12 correspond to the X direction and Y direction, respectively. In another example, sides 12C and 12E may have the same length as sides 12D and 12F, or may have a length greater than sides 12D and 12F.

[0013] The semiconductor layer 14 can be formed of a Si epitaxial layer. In plan view, the semiconductor layer 14 has the same shape as the semiconductor substrate 12. Details of the semiconductor layer 14 will be described later with reference to FIG.

[0014] The insulating layer 16 may include at least one of a silicon oxide (SiO2) layer and a silicon nitride (SiN) layer. The insulating layer 16 is also called an inter-layer dielectric (ILD).

[0015] The multiple sets of gate trenches S1, S2 are indicated by dashed lines in FIG. 1. Each of the multiple sets of gate trenches S1, S2 includes a plurality of gate trenches aligned parallel to each other at equal intervals. The multiple sets of gate trenches S1, S2 include a first set of gate trenches S1 and a second set of gate trenches S2. Each gate trench S1_n of the first set extends along the X direction in a plan view. Each gate trench S2_n of the second set extends along the Y direction in a plan view.

[0016] In the example of FIG. 1 , the first set of gate trenches S1 includes six gate trenches S1_1, ..., S1_6 aligned parallel to one another at equal intervals, and the second set of gate trenches S2 includes four gate trenches S2_1, ..., S2_4 aligned parallel to one another at equal intervals. Furthermore, the multiple sets of gate trenches S1, S2 include four gate trenches S1 of the first set and four gate trenches S2 of the second set. Thus, in one example, the number of gate trenches included in the first set may be greater than the number of gate trenches included in the second set. The number of gate trench sets and the number of gate trenches included in each set can take any value selectable for implementing the semiconductor device 10 of the present disclosure.

[0017] A field plate electrode 18 and a gate electrode 20, which will be described below with reference to FIG. 2, are buried in each of the gate trenches S1_n, S2_n of the plurality of pairs of gate trenches S1, S2.

[0018] 2 is a schematic cross-sectional view of the semiconductor device 10 taken along line F2-F2 in FIG. 1. Here, a cross-section in the YZ plane of one gate trench S1_n of the first set of gate trenches S1 is shown, but the cross-section in the XZ plane of each gate trench S2_n of the second set of gate trenches S2 is similar to that in FIG. 2. Hereinafter, one gate trench S1_n of the first set of gate trenches S1 and related configuration will be described, but it should be noted that such description can be similarly applied to each gate trench and related configuration of the multiple sets of gate trenches S1, S2.

[0019] The semiconductor substrate 12 corresponds to the drain region of the MISFET. The semiconductor layer 14 includes a drift region 22 formed on the semiconductor substrate (drain region) 12, a body region 24 formed on the drift region 22, and a source region 26 formed on the body region 24.

[0020] The drain region formed by the semiconductor substrate 12 is an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 12 is 1×10 18 cm -3 More than 1×10 20 cm -3 The semiconductor substrate 12 may have a thickness of 50 μm or more and 450 μm or less.

[0021] The drift region 22 is an n-type region containing n-type impurities at a concentration lower than that of the semiconductor substrate (drain region) 12. The n-type impurity concentration of the drift region 22 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 22 may have a thickness of 1 μm or more and 25 μm or less.

[0022] The body region 24 is a p-type region containing p-type impurities. The p-type impurity concentration of the body region 24 is 1×10 16 cm -3 More than 1×10 18 cm -3The body region 24 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0023] The source region 26 is an n-type region containing n-type impurities at a higher concentration than the drift region 22. The n-type impurity concentration of the source region 26 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 26 may have a thickness of at least 0.1 μm and at most 1 μm.

[0024] In this disclosure, n-type is also referred to as the first conductivity type, and p-type is also referred to as the second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). The p-type impurity may be, for example, boron (B) or aluminum (Al).

[0025] The semiconductor device 10 may further include a drain electrode 28 formed on the bottom surface 12A of the semiconductor substrate 12. The drain electrode 28 is electrically connected to the semiconductor substrate (drain region) 12. The drain electrode 28 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0026] A gate trench S1_n, which is one of the sets of gate trenches S1, is formed in the semiconductor layer 14. The gate trench S1_n has sidewalls 30 and a bottom wall 32. The gate trench S1_n penetrates the source region 26 and the body region 24 of the semiconductor layer 14 to reach the drift region 22. Therefore, the bottom wall 32 of the gate trench S1_n is adjacent to the drift region 22. The gate trench S1_n can have a depth of not less than 1 μm and not more than 15 μm.

[0027] The field plate electrode 18 and the gate electrode 20 are formed in the gate trench S1_n. The field plate electrode 18 and the gate electrode 20 are separated from each other by a trench insulating layer 34. The trench insulating layer 34 covers the sidewalls 30 and bottom wall 32 of the gate trench S1_n. The gate electrode 20 is disposed in the gate trench S1_n above the field plate electrode 18. Such a structure in which two split electrodes are embedded in the gate trench can be called a split gate structure.

[0028] The field plate electrode 18 is disposed in the gate trench S1_n between the bottom wall 32 of the gate trench S1_n and the bottom surface 20A of the gate electrode 20. The field plate electrode 18 is surrounded by a trench insulating layer 34. By applying a source voltage to the field plate electrode 18, electric field concentration in the gate trench S1_n can be alleviated, thereby improving the breakdown voltage of the semiconductor device 10. Therefore, the field plate electrode 18 can be set to the same potential as the source region 26.

[0029] The gate electrode 20 includes a bottom surface 20A at least a portion of which faces the field plate electrode 18. The gate electrode 20 also includes an upper surface 20B opposite the bottom surface 20A. The upper surface 20B of the gate electrode 20 can be located lower than the upper surface of the semiconductor layer 14.

[0030] In one example, the field plate electrode 18 and the gate electrode 20 are made of conductive polysilicon. The trench insulating layer 34 includes a gate insulating portion 38 that is interposed between the gate electrode 20 and the semiconductor layer 14 and covers the sidewall 30 of the gate trench S1_n. The gate electrode 20 and the semiconductor layer 14 are spaced apart in the Y direction by the gate insulating portion 38. When a predetermined voltage is applied to the gate electrode 20, a channel is formed in the p-type body region 24 adjacent to the gate insulating portion 38. The semiconductor device 10 can control the flow of electrons in the Z direction between the n-type source region 26 and the n-type drift region 22 via this channel.

[0031] The trench insulating layer 34 further includes a lower insulating portion 40 covering the sidewalls 30 and bottom wall 32 of the gate trench S1_n between the field plate electrode 18 and the semiconductor layer 14, and an intermediate insulating portion 42 located between the field plate electrode 18 and the gate electrode 20 in the depth direction of the gate trench S1_n. The lower insulating portion 40 can be formed thicker on the sidewalls 30 of the gate trench S1_n than the gate insulating portion 38. The trench insulating layer 34 can be formed from SiO2, for example.

[0032] The insulating layer 16 is formed on the semiconductor layer 14 and covers the gate electrode 20 embedded in the gate trench S1_n and the trench insulating layer 34. The insulating layer 16 may include a cap insulating layer (not shown) covering the upper surface 20B of the gate electrode 20.

[0033] A contact trench 44 and a contact region 46 adjacent to the bottom wall of the contact trench 44 are formed in the insulating layer 16. The contact trench 44 penetrates the insulating layer 16 and the source region 26 and reaches the body region 24. The contact region 46 is a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 46 is higher than that of the body region 24, at 1×10 19 cm -3 More than 1×10 21 cm -3 A source contact 48 is buried in the contact trench 44. A source wiring 50 is formed on the insulating layer 16 and electrically connected to the contact region 46 via the source contact 48.

[0034] 1, the semiconductor device 10 includes multiple sets of gate trenches S1, S2. Therefore, the semiconductor device 10 can include the same number of field plate electrodes 18 as the number of gate trenches included in the multiple sets of gate trenches S1, S2, and the same number of gate electrodes 20 as the number of gate trenches included in the multiple sets of gate trenches S1, S2. In other words, each field plate electrode 18 is embedded in a corresponding one of the multiple sets of gate trenches S1, S2. Similarly, each gate electrode 20 is embedded in a corresponding one of the multiple sets of gate trenches S1, S2.

[0035] Next, referring again to FIG. 1, the source wiring 50 and gate wiring 52 formed on the insulating layer 16 will be described. The semiconductor device 10 further includes a gate wiring 52 formed on the insulating layer 16, and a source wiring 50 formed on the insulating layer 16 and spaced apart from the gate wiring 52. For convenience and simplification of explanation, an inter-metal dielectric (IMD) that separates the source wiring 50 from the gate wiring 52 is omitted from FIG.

[0036] The semiconductor layer 14 includes a peripheral region 54 and an inner region 56 surrounded by the peripheral region 54 in a planar view. The gate wiring 52 includes a peripheral gate wiring portion 58 disposed in the peripheral region 54 in a planar view, and an inner gate wiring portion 60 disposed in the inner region 56 in a planar view. The boundary between the peripheral region 54 and the inner region 56 is indicated by a two-dot chain line in FIG. 1. The semiconductor layer 14 covers the semiconductor substrate 12, and in one example, the outer edge of the semiconductor layer 14 substantially coincides with the outer edge of the semiconductor substrate 12 in a planar view. Therefore, the outer edge of the peripheral region 54 may also substantially coincide with the outer edge of the semiconductor substrate 12 in a planar view.

[0037] The inner region 56 is a rectangular region that is slightly smaller than the top surface of the semiconductor layer 14. In the example of Fig. 1, the top surface of the semiconductor layer 14 is rectangular, and the short-side direction and long-side direction of the top surface of the semiconductor layer 14 correspond to the X direction and the Y direction, respectively.

[0038] The peripheral region 54 is a rectangular frame-shaped region that surrounds the inner region 56 in a plan view. Therefore, in the example of FIG. 1, the boundary between the peripheral region 54 and the inner region 56 is formed in a rectangular shape. The peripheral region 54 is located between the rectangular outer edge of the semiconductor layer 14 and the inner region 56. The inner region 56 can also be called an active region, and is where the main portion of the MISFET, i.e., the portion that contributes to the operation as a transistor, is mainly formed.

[0039] The peripheral gate wiring portion 58 disposed in the peripheral region 54 can be formed so as to at least partially surround the inner region 56. The peripheral gate wiring portion 58 can extend in the peripheral region 54 along the boundary between the inner region 56 and the peripheral region 54.

[0040] The peripheral gate wiring portion 58 includes a gate finger 58A1 extending along the X direction in a plan view and a gate finger 58B1 extending along the Y direction in a plan view. The gate finger 58A1 is formed closer to the side 12C of the semiconductor substrate 12 in a plan view. The gate finger 58B1 is formed closer to the side 12D of the semiconductor substrate 12 in a plan view. An end of the gate finger 58A1 is connected to an end of the gate finger 58B1.

[0041] The peripheral gate wiring portion 58 further includes a gate finger 58A2 extending along the X direction in a plan view and a gate finger 58B2 extending along the Y direction in a plan view. The gate finger 58A2 is formed closer to the side 12E of the semiconductor substrate 12 in a plan view. The gate finger 58B2 is formed closer to the side 12F of the semiconductor substrate 12 in a plan view. One end of the gate finger 58A2 is connected to the end of the gate finger 58B1 (not connected to the gate finger 58A1). The other end of the gate finger 58A2 is connected to the end of the gate finger 58B2.

[0042] 1, the gate finger 58A1 is shorter than the gate finger 58A2, and as a result, the gate finger 58A1 is spaced apart from the gate finger 58B2. The source wiring 50 runs between the gate finger 58A1 and the gate finger 58B2.

[0043] In this way, the peripheral gate wiring portion 58, which at least partially surrounds the rectangular inner region 56, forms an open loop in the shape of a rectangular frame in plan view. The open portion of the loop of the peripheral gate wiring portion 58 corresponds to the gap between the gate finger 58A1 and the gate finger 58B2, and the peripheral source wiring portion 64 and the inner source wiring portion 66, which will be described later, are connected via this gap.

[0044] The peripheral gate wiring portion 58 may include a gate pad 62. The gate pad 62 may be provided at a position away from the open portion of the loop of the peripheral gate wiring portion 58. In the example of FIG. 1, the open portion of the loop of the peripheral gate wiring portion 58 is located closer to side 12C. Meanwhile, the gate pad 62 is connected to a gate finger 58A2 located closer to side 12E, opposite side 12C. In another example, the gate pad 62 may be connected to another gate finger included in the peripheral gate wiring portion 58.

[0045] The inner gate wiring portion 60 can include a gate finger 60B extending along the Y direction in a plan view and at least one other gate finger intersecting with the gate finger 60B in a plan view. In this embodiment, the gate finger 60B is connected to the gate finger 58A2. The at least one other gate finger also includes a gate finger 60A extending along the X direction in a plan view. The gate finger 60A intersects with the gate finger 60B, for example, at approximately the center of the inner region 56 in a plan view.

[0046] The gate fingers 60B of the inner gate wiring portion 60 extend in the same direction (Y direction) as the gate fingers 58B1, 58B2 of the peripheral gate wiring portion 58. When gate fingers extending in the same direction (Y direction) are present in both the peripheral region 54 and the inner region 56, it becomes possible to arrange the first set of gate trenches S1 adjacent to each other in the X direction, thereby shortening the length of the gate trench S1_n. In the example of FIG. 1, the two first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n of the first set has a length that is approximately ¼ of the dimension of the side 12C.

[0047] The gate fingers 60A of the inner gate wiring portion 60 extend in the same direction (X direction) as the gate fingers 58A1, 58A2 of the peripheral gate wiring portion 58. When gate fingers extending in the same direction (X direction) are present in both the peripheral region 54 and the inner region 56, it becomes possible to arrange multiple second sets of gate trenches S2 adjacent to each other in the Y direction, thereby shortening the length of the gate trench S2_n. In the example of FIG. 1, two second sets of gate trenches S2 are arranged adjacent to each other in the Y direction, and each gate trench S2_n of the second set has a length that is approximately ¼ of the dimension of the side 12D.

[0048] 1, the dimension of side 12D is larger than the dimension of side 12C, and therefore the length of gate trench S2_n is larger than the length of gate trench S1_n. In one example, the number of relatively short gate trenches S1_n can be larger than the number of relatively long gate trenches S2_n in one chip. In another example, the length of gate trench S2_n may be the same as or smaller than the length of gate trench S1_n.

[0049] The source wiring 50 includes a peripheral source wiring portion 64 disposed in the peripheral region 54 and an inner source wiring portion 66 disposed in the inner region 56 . 1, the peripheral source wiring portion 64 is formed continuously in the peripheral region 54 excluding the region where the gate pad 62 is formed, and surrounds the inner region 56 in plan view. The peripheral source wiring portion 64 is connected to the inner source wiring portion 66 in the region between the gate finger 58A1 and the gate finger 58B2 in plan view. Therefore, the peripheral source wiring portion 64 and the inner source wiring portion 66 are at the same potential.

[0050] The inner source wiring portion 66 can be arranged so as to be spaced a predetermined distance from both the outer gate wiring portion 58 and the inner gate wiring portion 60, which can be determined appropriately taking into consideration the withstand voltage, etc. In the example of Fig. 1, the inner source wiring portion 66 is spaced a certain distance from the outer edges of the gate fingers 60A and 60B, which intersect with each other, and therefore has a cross-shaped notch in plan view.

[0051] The multiple sets of gate trenches S1, S2 are arranged so as to at least partially overlap both the source wiring 50 and the gate wiring 52 in a plan view. Each set of gate trenches is arranged so as to intersect with one gate finger in a plan view, where the gate electrode 20 embedded in the gate trench of that set is connected to the gate wiring 52.

[0052] Each of the first set of gate trenches S1_n extending along the X direction in plan view intersects with one of the gate fingers 58B1, 58B2, and 60B extending along the Y direction in plan view. Similarly, each of the second set of gate trenches S2_n extending along the Y direction in plan view intersects with one of the gate fingers 58A1, 58A2, and 60A extending along the X direction in plan view.

[0053] For example, the gate electrode 20 embedded in each of the first set of gate trenches S1_n that intersect with the gate finger 60B is electrically connected to the gate finger 60B in the region where each of the first set of gate trenches S1_n intersects with the gate finger 60B in a plan view.

[0054] Similarly, the gate electrode 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate finger 58A1 or 58A2 is electrically connected to the gate finger 58A1 or 58A2 in the region where each of the second set of gate trenches S2_n intersects with the gate finger 58A1 or 58A2 in a planar view.

[0055] Each of the first set of gate trenches S1_n that intersect with the gate finger 58B1 or 58B2 of the peripheral gate wiring portion 58 is disposed across the inner region 56 and the peripheral region 54. On the other hand, each of the first set of gate trenches S1_n that intersect with the gate finger 60B of the inner gate wiring portion 60 is disposed entirely within the inner region 56.

[0056] Similarly, each of the second set of gate trenches S2_n that intersect with the gate finger 58A1 or 58A2 of the peripheral gate wiring portion 58 is disposed across the inner region 56 and the peripheral region 54. On the other hand, each of the second set of gate trenches S2_n that intersect with the gate finger 60A of the inner gate wiring portion 60 is disposed entirely within the inner region 56.

[0057] A gate finger extending along the Y direction in a plan view can intersect with two or more of the first set of gate trenches S1 in a plan view. In the example of FIG. 1, the gate finger 60B intersects with two of the first set of gate trenches S1 in a plan view.

[0058] Furthermore, the gate finger extending along the X direction in a plan view can intersect with two or more of the second set of gate trenches S2 in a plan view. In the example of Fig. 1, the gate finger 60A intersects with two of the second set of gate trenches S2 in a plan view.

[0059] 1, due to the layout of the source wiring 50 and the gate wiring 52 as described above, each gate trench S1_n of the first set can have a length that is 1 / 3 or less of the dimension of side 12C. Similarly, each gate trench S2_n of the second set can have a length that is 1 / 3 or less of the dimension of side 12D.

[0060] Figure 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in Figure 1, showing an XZ cross section of a first set of two adjacent gate trenches S1, including two gate trenches S1_n formed in the semiconductor layer 14.

[0061] A field plate electrode 18 and a gate electrode 20 are buried in the gate trench S1_n. The gate electrode 20 is disposed above the field plate electrode 18. The field plate electrode 18 includes two ends 18A and 18B connected to the source wiring 50, and the ends 18A and 18B extend along the Z direction from the bottom of the gate trench S1_n to the opening. Therefore, the gate electrode 20 is not present above the ends 18A and 18B.

[0062] Two ends 18A, 18B of the field plate electrode 18 are connected to the source wiring 50 via two field plate contacts 68, respectively. Both of the two ends 18A, 18B of the field plate electrode 18 may be connected to the inner source wiring portion 66. Alternatively, one of the two ends 18A, 18B of the field plate electrode 18 may be connected to the inner source wiring portion 66, and the other of the two ends 18A, 18B may be connected to the outer source wiring portion 64. For example, in the field plate electrode 18 embedded in each of the first set of gate trenches S1_n that intersects with the gate finger 60B of the inner gate wiring portion 60 in a plan view, both of the two ends 18A, 18B are connected to the inner source wiring portion 66. On the other hand, in the field plate electrode 18 embedded in each of the second set of gate trenches S2_n that intersects with the gate finger 58A1 or 58A2 of the peripheral gate wiring portion 58 in a planar view, one of the two ends 18A, 18B is connected to the inner source wiring portion 66, and the other of the two ends 18A, 18B is connected to the peripheral source wiring portion 64.

[0063] 3, both of the two ends 18A, 18B of the right field plate electrode 18 are connected to the inner source wiring portion 66. On the other hand, the ends 18A and 18B of the left field plate electrode 18 are connected to the inner source wiring portion 66 and the peripheral source wiring portion 64, respectively.

[0064] The gate electrode 20 embedded in the gate trench S1_n is connected to the gate wiring 52. More specifically, the gate electrode 20 is connected to the gate wiring 52 via a gate contact 70 that penetrates the insulating layer 16. Unlike the field plate electrode 18, which is connected to the source wiring 50 via two field plate contacts 68, the gate electrode 20 is connected to the gate wiring 52 via one gate contact 70. In the example of FIG. 3, the gate wiring 52 to which the gate electrode 20 is connected is a gate finger extending along the Y direction. Specifically, the gate electrode 20 on the right side of FIG. 3 is connected to gate finger 60B, and the gate electrode 20 on the left side is connected to gate finger 58B2.

[0065] An insulating layer 72 is formed between the source wiring 50 and the gate wiring 52. The insulating layer 72 electrically separates the source wiring 50 from the gate wiring 52. The insulating layer 72 corresponds to an IMD.

[0066] The cross section of the second set of two adjacent gate trenches S2 in the YZ plane is similar to that of Fig. 3 except that the gate trench S2_n has a length different from that of the gate trench S1_n. Note that, although the gate trench S2_n is longer than the gate trench S1_n in the example of Fig. 1, the gate trench S2_n may be shorter than the gate trench S1_n or may have the same length as the gate trench S1_n.

[0067] The operation of the semiconductor device 10 of this embodiment will now be described. According to the semiconductor device 10 of this embodiment, each of the plurality of field plate electrodes 18 includes two ends 18A, 18B that are connected to the source wiring 50. With this configuration, the two ends 18A, 18B of each field plate electrode 18 are connected to the source wiring 50, and therefore the resistance R of the field plate electrode 18 is reduced compared to when only one end is connected. S The length of the gate trench contributing to the above can be substantially reduced to about half.

[0068] Furthermore, according to the semiconductor device 10 of this embodiment, the outer periphery gate wiring portion 58 includes a gate finger 58A1 or 58A2 (first gate finger) extending along the X direction in a plan view, and the inner gate wiring portion 60 includes a gate finger 60B (second gate finger) extending along the Y direction in a plan view. Each gate trench S1_n of the first set extends along the X direction in a plan view and intersects with the gate finger 60B (second gate finger), and each gate trench S2_n of the second set extends along the Y direction in a plan view and intersects with the gate finger 58A1 or 58A2 (first gate finger).

[0069] According to this configuration, each of the gate trenches S1_n extending along the X direction in plan view and the gate trenches S2_n extending along the Y direction in plan view is arranged in the semiconductor layer 14 formed on the semiconductor substrate 12 so as to intersect with a corresponding one of the gate fingers. As a result, warping of the semiconductor substrate 12 during wafer processing can be reduced compared to when only gate trenches extending along the same direction are formed.

[0070] In a MISFET with a split gate structure in which the field plate electrode and gate electrode are embedded in the gate trench, the resistance R of the field plate electrode S The displacement current flowing through the field plate electrode causes the potential V BS Such a potential V BS The increase in the resistance R of the gate electrode reduces the breakdown voltage of the MISFET, which can result in a phenomenon called false firing, in which an avalanche current flows. G The displacement current flowing through the gate electrode V G rises and the threshold voltage V th If the voltage exceeds this limit, the MISFET may accidentally turn on, causing a self-turn-on phenomenon. These phenomena are collectively called the shoot-through phenomenon. Since unintentional shoot-through current flows through a circuit containing a MISFET, increasing switching losses, it is desirable to suppress the shoot-through phenomenon.

[0071] The shoot-through phenomenon occurs when the resistance R of the field plate electrode S and / or the gate electrode resistance R G This can be due to displacement currents flowing through the resistor R S and resistor R G Generally, the longer the gate trench, the lower the resistance R of the field plate electrode. S and the resistance of the gate electrode R G Therefore, in order to suppress the shoot-through phenomenon without changing the MISFET manufacturing process, the resistance R S and resistor R G According to the semiconductor device 10 of the present disclosure, the length of the gate trench can be substantially shortened as described above, thereby suppressing the occurrence of the shoot-through phenomenon.

[0072] The semiconductor device 10 of this embodiment has the following advantages. (1) Each of the plurality of field plate electrodes 18 includes two ends 18A, 18B that are connected to the source wiring 50. According to this configuration, the two ends 18A, 18B of each field plate electrode 18 are connected to the source wiring 50, and therefore the resistance R of the field plate electrode 18 is reduced compared to when only one end is connected. S The length of the gate trench contributing to the above can be substantially reduced to about half.

[0073] (2) The outer peripheral gate wiring portion 58 includes a gate finger 58A1 or 58A2 (first gate finger) extending along the X direction in a plan view, and the inner gate wiring portion 60 includes a gate finger 60B (second gate finger) extending along the Y direction in a plan view. Furthermore, each of the first set of gate trenches S1_n extends along the X direction in a plan view and intersects with the gate finger 60B (second gate finger), and each of the second set of gate trenches S2_n extends along the Y direction in a plan view and intersects with the gate finger 58A1 or 58A2 (first gate finger).

[0074] According to this configuration, both the gate trench S1_n extending along the X direction in plan view and the gate trench S2_n extending along the Y direction in plan view are arranged in the semiconductor layer 14 formed on the semiconductor substrate 12 so as to intersect with a corresponding one of the gate fingers. As a result, warping of the semiconductor substrate 12 during wafer processing can be reduced compared to when only gate trenches extending along the same direction are formed.

[0075] (3) The inner gate wiring portion 60 further includes at least one other gate finger 60A that intersects with the gate finger 60B (second gate finger) in a plan view. With this configuration, since gate fingers extending in the same direction (X direction) are present in both the outer circumferential region 54 and the inner region 56, it is possible to arrange the two second sets of gate trenches S2 adjacent to each other in the Y direction, thereby shortening the length of the gate trench S2_n.

[0076] (4) The peripheral gate wiring portion 58 further includes a gate finger 58B1 or 58B2 (fourth gate finger) extending along the Y direction in plan view. With this configuration, since gate fingers extending along the same direction (Y direction) are present in both the peripheral region 54 and the inner region 56, it is possible to arrange the two first sets of gate trenches S1 adjacent to each other in the X direction, and as a result, it is possible to shorten the length of the gate trench S1_n.

[0077] [Change Example 1] Fig. 4 is a schematic plan view of an exemplary semiconductor device 100 according to Modification 1 of the above embodiment. In Fig. 4, the same components as those in the semiconductor device 10 of Fig. 1 are denoted by the same reference numerals. Further, detailed description of the same components as those in the semiconductor device 10 will be omitted.

[0078] The semiconductor device 100 of the first modification includes a gate wiring 102 formed on an insulating layer 16, and a source wiring 104 formed on the insulating layer 16 and spaced apart from the gate wiring 102. For convenience and simplification of explanation, an IMD that spaces the source wiring 104 from the gate wiring 102 is omitted in FIG.

[0079] The gate wiring 102 includes a peripheral gate wiring portion 106 arranged in the peripheral region 54 in a plan view, and an inner gate wiring portion 108 arranged in the inner region 56 in a plan view. The peripheral gate wiring portion 106 arranged in the peripheral region 54 can be formed so as to at least partially surround the inner region 56. The peripheral gate wiring portion 106 can extend in the peripheral region 54 along the boundary between the inner region 56 and the peripheral region 54.

[0080] The peripheral gate wiring portion 106 includes a gate finger 106A1 extending along the X direction in a plan view and a gate finger 106B1 extending along the Y direction in a plan view. The gate finger 106A1 is formed closer to the side 12C of the semiconductor substrate 12 in a plan view. The gate finger 106B1 is formed closer to the side 12F of the semiconductor substrate 12 in a plan view. An end of the gate finger 106A1 is connected to an end of the gate finger 106B1.

[0081] The peripheral gate wiring portion 106 further includes a gate finger 106A2 extending along the X direction in a plan view and a gate finger 106B2 extending along the Y direction in a plan view. The gate finger 106A2 is formed closer to the side 12E of the semiconductor substrate 12 in a plan view. The gate finger 106B2 is formed closer to the side 12D of the semiconductor substrate 12 in a plan view. One end of the gate finger 106A2 is connected to the end of the gate finger 106B1 (not connected to the gate finger 106A1). The other end of the gate finger 106A2 is connected to the end of the gate finger 106B2.

[0082] 4, the gate finger 106A1 is shorter than the gate finger 106A2, and as a result, the gate finger 106A1 is spaced apart from the gate finger 106B2. The source wiring 104 runs between the gate finger 106A1 and the gate finger 106B2.

[0083] In this way, the peripheral gate wiring 106, which at least partially surrounds the rectangular inner region 56, forms an open loop in the shape of a rectangular frame in plan view. The open portion of the loop of the peripheral gate wiring 106 corresponds to the gap between the gate finger 106A1 and the gate finger 106B2, and the peripheral source wiring 112 and the inner source wiring 114, which will be described later, are connected via this gap.

[0084] The inner gate wiring portion 108 includes a gate finger 108B extending along the Y direction in a plan view and a gate pad 110 connected to the gate finger 108B. The gate pad 110 can be provided at a position away from the open portion of the loop of the aforementioned peripheral gate wiring portion 106. In the example of FIG. 4 , the open portion of the loop of the peripheral gate wiring portion 106 is located closer to side 12C. Meanwhile, the gate pad 110 is connected to a gate finger 106A2 located closer to side 12E, opposite side 12C. The peripheral gate wiring portion 106 is connected to the inner gate wiring portion 108 via the gate pad 110. In another example, the gate pad 110 may be connected to another gate finger included in the peripheral gate wiring portion 106.

[0085] The gate fingers 108B of the inner gate wiring portion 108 extend in the same direction (Y direction) as the gate fingers 106B1 and 106B2 of the peripheral gate wiring portion 106. When gate fingers extending in the same direction (Y direction) are present in both the peripheral region 54 and the inner region 56, it becomes possible to arrange a plurality of first sets of gate trenches S1 adjacent to each other in the X direction, thereby shortening the length of the gate trench S1_n. In the example of FIG. 4, three first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n of the first set has a length that is approximately ⅓ of the dimension of the side 12C.

[0086] Gate finger 108B can have a length equal to or less than half the dimension of side 12D. In this case, even if each of the second set of gate trenches S2_n has a length equal to about half the dimension of side 12D, the second set of gate trenches S2 can be arranged so as not to overlap with gate finger 108B in plan view.

[0087] 4, the dimension of side 12D is greater than the dimension of side 12C, and therefore the length of gate trench S2_n is greater than the length of gate trench S1_n. In one example, the number of relatively short gate trenches S1_n can be greater than the number of relatively long gate trenches S2_n in one chip. In another example, the length of gate trench S2_n may be the same as or shorter than the length of gate trench S1_n.

[0088] The source wiring 104 includes a peripheral source wiring portion 112 disposed in the peripheral region 54 and an inner source wiring portion 114 disposed in the inner region 56 . 4, the peripheral source wiring portion 112 is formed continuously within the peripheral region 54 and surrounds the inner region 56 in a plan view. The peripheral source wiring portion 112 is connected to the inner source wiring portion 114 in a region between the gate finger 106A1 and the gate finger 106B2 in a plan view. Therefore, the peripheral source wiring portion 112 and the inner source wiring portion 114 are at the same potential.

[0089] The inner source wiring portion 114 can be arranged so as to be spaced a predetermined distance from both the outer gate wiring portion 106 and the inner gate wiring portion 108, which can be determined appropriately taking into consideration the withstand voltage, etc. In the example of Fig. 4, the inner source wiring portion 114 is spaced a certain distance from the outer edge of the gate finger 108B, and therefore has a notch extending along the Y direction in plan view.

[0090] The multiple sets of gate trenches S1, S2 are arranged so as to at least partially overlap both the gate wiring 102 and the source wiring 104 in a plan view. Each set of gate trenches is arranged so as to intersect with one gate finger in a plan view, where the gate electrode 20 embedded in the gate trench of that set is connected to the gate wiring 102.

[0091] Each of the first set of gate trenches S1_n extending along the X direction in plan view intersects with one of the gate fingers 106B1, 106B2, and 108B extending along the Y direction in plan view. Similarly, each of the second set of gate trenches S2_n extending along the Y direction in plan view intersects with the gate finger 106A1 extending along the X direction in plan view.

[0092] For example, the gate electrode 20 embedded in each of the first set of gate trenches S1_n that intersect with the gate finger 108B is electrically connected to the gate finger 108B in the region where each of the first set of gate trenches S1_n intersects with the gate finger 108B in a plan view.

[0093] Similarly, the gate electrode 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate finger 106A1 is electrically connected to the gate finger 106A1 in the region where each of the second set of gate trenches S2_n intersects with the gate finger 106A1 in a plan view.

[0094] Each of the first set of gate trenches S1_n that intersects with the gate finger 106B1 or 106B2 of the peripheral gate wiring portion 106 is disposed across the inner region 56 and the peripheral region 54. On the other hand, each of the first set of gate trenches S1_n that intersects with the gate finger 108B of the inner gate wiring portion 108 is disposed entirely within the inner region 56.

[0095] Similarly, each of the second set of gate trenches S2_n that intersects with the gate finger 106A1 of the peripheral gate wiring portion 106 is disposed across the inner region 56 and the peripheral region 54. 4, the first set of gate trenches S1 includes eight gate trenches S1_1, ..., S1_8 aligned parallel to one another at equal intervals, and the second set of gate trenches S2 includes eleven gate trenches S2_1, ..., S2_11 aligned parallel to one another at equal intervals. Furthermore, the multiple sets of gate trenches S1, S2 include three first set of gate trenches S1 and one second set of gate trench S2.

[0096] 4, each of the first set of gate trenches S1_n can have a length that is equal to or less than one-third the dimension of side 12C. Similarly, each of the second set of gate trenches S2_n can have a length that is equal to or less than one-half the dimension of side 12D.

[0097] The explanation for the connection between the field plate electrode 18 and the source wiring 104 (peripheral source wiring portion 112 and inner source wiring portion 114) can be applied to the connection between the field plate electrode 18 and the source wiring 50.

[0098] [Change Example 2] Fig. 5 is a schematic plan view of an exemplary semiconductor device 200 according to Modification 2 of the above embodiment. In Fig. 5, the same components as those in the semiconductor device 10 of Fig. 1 are denoted by the same reference numerals. Further, detailed description of the same components as those in the semiconductor device 10 will be omitted.

[0099] The semiconductor device 200 of the second modification includes a gate wiring 202 formed on the insulating layer 16, and a source wiring 204 formed on the insulating layer 16 and spaced apart from the gate wiring 202. For convenience and simplification of explanation, the IMD that separates the source wiring 204 from the gate wiring 202 is omitted in FIG.

[0100] The gate wiring 202 includes a peripheral gate wiring portion 206 arranged in the peripheral region 54 in a plan view, and an inner gate wiring portion 208 arranged in the inner region 56 in a plan view. The peripheral gate wiring portion 206 arranged in the peripheral region 54 can be formed so as to at least partially surround the inner region 56. The peripheral gate wiring portion 206 can extend in the peripheral region 54 along the boundary between the inner region 56 and the peripheral region 54.

[0101] The peripheral gate wiring portion 206 includes a gate finger 206A1 extending along the X direction in a plan view and a gate finger 206B1 extending along the Y direction in a plan view. The gate finger 206A1 is formed closer to the side 12C of the semiconductor substrate 12 in a plan view. The gate finger 206B1 is formed closer to the side 12F of the semiconductor substrate 12 in a plan view. An end of the gate finger 206A1 is connected to an end of the gate finger 206B1.

[0102] The peripheral gate wiring portion 206 further includes a gate finger 206A2 extending along the X direction in a plan view, a gate finger 206B2 extending along the Y direction in a plan view, and a gate finger 206A3 extending along the X direction in a plan view. The gate finger 206A2 is formed closer to the side 12E of the semiconductor substrate 12 in a plan view. The gate finger 206B2 is formed closer to the side 12D of the semiconductor substrate 12 in a plan view. The gate finger 206A3 is formed closer to the side 12C of the semiconductor substrate 12 in a plan view. One end of the gate finger 206A2 is connected to the end of the gate finger 206B1 (not connected to the gate finger 206A1). The other end of the gate finger 206A2 is connected to the end of the gate finger 206B2. An end of gate finger 206A3 is connected to an end of gate finger 206B2 (not connected to gate finger 206A2).

[0103] 5, the total length of gate finger 206A1 and gate finger 206A3 is shorter than the length of gate finger 206A2, and as a result, gate finger 206A1 is spaced apart from gate finger 206A3. Source wiring 204 runs between gate finger 206A1 and gate finger 206A3.

[0104] In this way, the peripheral gate wiring portion 206, which at least partially surrounds the rectangular inner region 56, forms an open loop in the shape of a rectangular frame in plan view. The open portion of the loop of the peripheral gate wiring portion 206 corresponds to the gap between the gate finger 206A1 and the gate finger 206A3, and the peripheral source wiring portion 212 and the inner source wiring portion 214, which will be described later, are connected via this gap.

[0105] The inner gate wiring portion 208 includes a gate finger 208A extending along the X direction in a plan view, a gate finger 208B extending along the Y direction in a plan view, and a gate pad 210. The gate pad 210 can be provided at a position away from the open portion of the loop of the aforementioned peripheral gate wiring portion 206. In the example of FIG. 5 , the open portion of the loop of the peripheral gate wiring portion 206 is located closer to side 12C. Meanwhile, the gate pad 210 is connected to a gate finger 206A2 located closer to side 12E, opposite side 12C. The gate finger 208A forms a T-shaped junction with the gate finger 208B in a plan view. The gate finger 208B is also connected to the gate pad 210. Therefore, the peripheral gate wiring portion 206 is connected to the gate finger 208B via the gate pad 210. In another example, the gate pad 210 may be connected to another gate finger included in the peripheral gate wiring portion 206.

[0106] The gate fingers 208A of the inner gate wiring portion 208 extend in the same direction (X direction) as the gate fingers 206A1, 206A2, and 206A3 of the peripheral gate wiring portion 206. When gate fingers extending in the same direction (X direction) are present in both the peripheral region 54 and the inner region 56, it becomes possible to arrange the second set of gate trenches S2 adjacent to each other in the Y direction, thereby shortening the length of the gate trench S2_n. In the example of FIG. 5, the two second sets of gate trenches S2 are arranged adjacent to each other in the Y direction, and each gate trench S2_n of the second set has a length that is approximately ⅓ of the dimension of the side 12D.

[0107] The gate fingers 208B of the inner gate wiring portion 208 extend in the same direction (Y direction) as the gate fingers 206B1 and 206B2 of the peripheral gate wiring portion 206. When gate fingers extending in the same direction (Y direction) are present in both the peripheral region 54 and the inner region 56, it becomes possible to arrange the first set of gate trenches S1 adjacent to each other in the X direction, thereby shortening the length of the gate trench S1_n. In the example of FIG. 5, three first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n of the first set has a length that is approximately ⅓ of the dimension of the side 12C.

[0108] 5, the dimension of side 12D is larger than the dimension of side 12C, and therefore the length of gate trench S2_n is larger than the length of gate trench S1_n. In another example, the length of gate trench S2_n may be the same as or smaller than the length of gate trench S1_n.

[0109] The source wiring 204 includes a peripheral source wiring portion 212 disposed in the peripheral region 54 and an inner source wiring portion 214 disposed in the inner region 56 . 5, the peripheral source wiring portion 212 is formed continuously within the peripheral region 54, and surrounds the inner region 56 in plan view. The peripheral source wiring portion 212 is connected to the inner source wiring portion 214 in the region between the gate finger 206A1 and the gate finger 206A3 in plan view. Therefore, the peripheral source wiring portion 212 and the inner source wiring portion 214 are at the same potential.

[0110] The inner source wiring portion 214 can be arranged so as to be spaced a predetermined distance from both the outer gate wiring portion 206 and the inner gate wiring portion 208, which can be determined appropriately taking into consideration the withstand voltage, etc. In the example of Fig. 5, the inner source wiring portion 214 is spaced a certain distance from the outer edges of the gate fingers 208A and 208B, and therefore has a T-shaped notch in plan view.

[0111] The multiple sets of gate trenches S1, S2 are arranged so as to at least partially overlap both the gate wiring 202 and the source wiring 204 in a plan view. Each set of gate trenches is arranged so as to intersect with one gate finger in a plan view, where the gate electrode 20 embedded in the gate trench of that set is connected to the gate wiring 202.

[0112] Each of the first set of gate trenches S1_n extending along the X direction in plan view intersects with one of the gate fingers 206B1, 206B2, and 208B extending along the Y direction in plan view. Similarly, each of the second set of gate trenches S2_n extending along the Y direction in plan view intersects with one of the gate fingers 206A1, 206A3, and 208A extending along the X direction in plan view.

[0113] For example, the gate electrode 20 embedded in each of the first set of gate trenches S1_n that intersect with the gate finger 208B is electrically connected to the gate finger 208B in the region where each of the first set of gate trenches S1_n intersects with the gate finger 208B in a plan view.

[0114] Similarly, the gate electrode 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate finger 206A1 is electrically connected to the gate finger 206A1 in the region where each of the second set of gate trenches S2_n intersects with the gate finger 206A1 in a plan view.

[0115] Each of the first set of gate trenches S1_n that intersects with the gate finger 206B1 or 206B2 of the peripheral gate wiring portion 206 is disposed across the inner region 56 and the peripheral region 54. On the other hand, each of the first set of gate trenches S1_n that intersects with the gate finger 208B of the inner gate wiring portion 208 is disposed entirely within the inner region 56.

[0116] Similarly, each of the second set of gate trenches S2_n that intersects with the gate finger 206A1 or 206A3 of the peripheral gate wiring portion 206 is disposed across the inner region 56 and the peripheral region 54.

[0117] 5, the first set of gate trenches S1 includes six gate trenches S1_1, ..., S1_6 aligned parallel to one another at equal intervals, and the second set of gate trenches S2 includes four gate trenches S2_1, ..., S2_4 aligned parallel to one another at equal intervals. Furthermore, the multiple sets of gate trenches S1, S2 include three first set of gate trenches S1 and four second set of gate trenches S2.

[0118] 5, each gate trench S1_n in the first set can have a length that is equal to or less than 1 / 3 of the dimension of side 12C. Similarly, each gate trench S2_n in the second set can have a length that is equal to or less than 1 / 3 of the dimension of side 12D.

[0119] The explanation for the connection between the field plate electrode 18 and the source wiring 204 (peripheral source wiring portion 212 and inner source wiring portion 214) can be applied to the connection between the field plate electrode 18 and the source wiring 50.

[0120] [Change Example 3] Fig. 6 is a schematic plan view of an exemplary semiconductor device 300 according to Modification 3 of the above embodiment. In Fig. 6, the same components as those in the semiconductor device 10 of Fig. 1 are denoted by the same reference numerals. Further, detailed description of the same components as those in the semiconductor device 10 will be omitted.

[0121] The semiconductor device 300 of the third modification example includes a gate wiring 302 formed on the insulating layer 16, and a source wiring 304 formed on the insulating layer 16 and spaced apart from the gate wiring 302. For convenience and simplification of explanation, the IMD that spaces the source wiring 304 from the gate wiring 302 is omitted in FIG.

[0122] The gate wiring 302 includes a peripheral gate wiring portion 306 arranged in the peripheral region 54 in a plan view, and an inner gate wiring portion 308 arranged in the inner region 56 in a plan view. The peripheral gate wiring portion 306 arranged in the peripheral region 54 can be formed so as to at least partially surround the inner region 56. The peripheral gate wiring portion 306 can extend in the peripheral region 54 along the boundary between the inner region 56 and the peripheral region 54.

[0123] The peripheral gate wiring portion 306 includes a gate finger 306A1 extending along the X direction in a plan view and a gate finger 306B1 extending along the Y direction in a plan view. The gate finger 306A1 is formed closer to the side 12C of the semiconductor substrate 12 in a plan view. The gate finger 306B1 is formed closer to the side 12D of the semiconductor substrate 12 in a plan view. An end of the gate finger 306A1 is connected to an end of the gate finger 306B1.

[0124] The peripheral gate wiring portion 306 further includes a gate finger 306A2 extending along the X direction in a plan view and a gate finger 306B2 extending along the Y direction in a plan view. The gate finger 306A2 is formed closer to the side 12E of the semiconductor substrate 12 in a plan view. The gate finger 306B2 is formed closer to the side 12F of the semiconductor substrate 12 in a plan view. One end of the gate finger 306A2 is connected to the end of the gate finger 306B1 (not connected to the gate finger 306A1). The other end of the gate finger 306A2 is connected to the end of the gate finger 306B2.

[0125] 6, the gate finger 306A1 is shorter than the gate finger 306A2, and as a result, the gate finger 306A1 is spaced apart from the gate finger 306B2. The source wiring 304 runs between the gate finger 306A1 and the gate finger 306B2.

[0126] In this way, the peripheral gate wiring portion 306, which at least partially surrounds the rectangular inner region 56, forms an open loop in the shape of a rectangular frame in plan view. The open portion of the loop of the peripheral gate wiring portion 306 corresponds to the gap between the gate finger 306A1 and the gate finger 306B2, and the peripheral source wiring portion 312 and the inner source wiring portion 314, which will be described later, are connected via this gap.

[0127] The perimeter gate wiring portion 306 may include a gate pad 310. The gate pad 310 may be provided at a position away from the open portion of the loop of the perimeter gate wiring portion 306. In the example of FIG. 6, the open portion of the loop of the perimeter gate wiring portion 306 is located closer to side 12C. Meanwhile, the gate pad 310 is connected to a gate finger 306A2 located closer to side 12E, opposite side 12C. In another example, the gate pad 310 may be connected to another gate finger included in the perimeter gate wiring portion 306.

[0128] The inner gate wiring portion 308 may include a gate finger 308B extending along the Y direction in a plan view and at least one other gate finger intersecting the gate finger 308B in a plan view. In this embodiment, the gate finger 308B is connected to the gate finger 306A2. The at least one other gate finger may include two gate fingers 308A1 and 308A2 extending along the X direction in a plan view. In the example of FIG. 6, the gate finger 306A2, the gate finger 308A1, the gate finger 308A2, and the gate finger 306A1 are aligned parallel to one another at equal intervals.

[0129] The gate fingers 308B of the inner gate wiring portion 308 extend in the same direction (Y direction) as the gate fingers 306B1 and 306B2 of the peripheral gate wiring portion 306. When gate fingers extending in the same direction (Y direction) are present in both the peripheral region 54 and the inner region 56, it becomes possible to arrange the first set of gate trenches S1 adjacent to each other in the X direction, thereby shortening the length of the gate trench S1_n. In the example of FIG. 6, the two first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n of the first set has a length that is approximately ¼ of the dimension of the side 12C.

[0130] The two gate fingers 308A1 and 308A2 of the inner gate wiring portion 308 extend in the same direction (X direction) as the gate fingers 306A1 and 306A2 of the peripheral gate wiring portion 306. When gate fingers extending in the same direction (X direction) are present in both the peripheral region 54 and the inner region 56, it becomes possible to arrange multiple second sets of gate trenches S2 adjacent to each other in the Y direction, thereby shortening the length of the gate trench S2_n. In the example of FIG. 6, two second sets of gate trenches S2 are arranged adjacent to each other in the Y direction. Unlike the semiconductor device 10 shown in FIG. 1, in the semiconductor device 300, the inner gate wiring portion 308 includes two gate fingers 308A1 and 308A2 extending along the X direction. Therefore, six second sets of gate trenches S2 can be arranged, and each gate trench S2_n of the second set has a length of approximately ⅙ of the dimension of the side 12D.

[0131] The source wiring 304 includes a peripheral source wiring portion 312 disposed in the peripheral region 54 and an inner source wiring portion 314 disposed in the inner region 56 . 6, the peripheral source wiring portion 312 is formed continuously in the peripheral region 54 excluding the region where the gate pad 310 is formed, and surrounds the inner region 56 in plan view. The peripheral source wiring portion 312 is connected to the inner source wiring portion 314 in the region between the gate finger 306A1 and the gate finger 306B2 in plan view. Therefore, the peripheral source wiring portion 312 and the inner source wiring portion 314 are at the same potential.

[0132] The inner source wiring portion 314 can be arranged so as to be spaced a predetermined distance, which can be determined appropriately taking into consideration the breakdown voltage, from both the outer gate wiring portion 306 and the inner gate wiring portion 308. In the example of Fig. 6, the inner source wiring portion 314 is spaced a certain distance from the outer edges of the gate finger 308B and the two gate fingers 308A1 and 308A2 that intersect with the gate finger 308B, and therefore has notches that follow the shapes of these fingers in a plan view.

[0133] The multiple sets of gate trenches S1, S2 are arranged so as to at least partially overlap, in plan view, both the gate wiring 302 and the source wiring 304. Each set of gate trenches is arranged so as to intersect with one gate finger in plan view, where the gate electrode 20 embedded in the gate trench of that set is connected to the gate wiring 302.

[0134] Each of the first set of gate trenches S1_n extending along the X direction in plan view intersects with one of the gate fingers 306B1, 306B2, and 308B extending along the Y direction in plan view. Similarly, each of the second set of gate trenches S2_n extending along the Y direction in plan view intersects with one of the gate fingers 306A1, 306A2, 308A1, and 308A2 extending along the X direction in plan view.

[0135] For example, the gate electrode 20 embedded in each of the first set of gate trenches S1_n that intersect with the gate finger 308B is electrically connected to the gate finger 308B in the region where each of the first set of gate trenches S1_n intersects with the gate finger 308B in a plan view.

[0136] Similarly, the gate electrode 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate finger 306A1 is electrically connected to the gate finger 306A1 in the region where each of the second set of gate trenches S2_n intersects with the gate finger 306A1 in a plan view.

[0137] Each of the first set of gate trenches S1_n that intersect with the gate finger 306B1 or 306B2 of the peripheral gate wiring portion 306 is disposed across the inner region 56 and the peripheral region 54. On the other hand, each of the first set of gate trenches S1_n that intersect with the gate finger 308B of the inner gate wiring portion 308 is disposed entirely within the inner region 56.

[0138] Similarly, each of the second set of gate trenches S2_n that intersect with the gate finger 306A1 or 306A2 of the peripheral gate wiring portion 306 is disposed across the inner region 56 and the peripheral region 54. On the other hand, each of the second set of gate trenches S2_n that intersect with the gate finger 308A1 or 308A2 of the inner gate wiring portion 308 is disposed entirely within the inner region 56.

[0139] 6, the first set of gate trenches S1 includes four gate trenches S1_1, ..., S1_4 aligned parallel to one another at equal intervals, and the second set of gate trenches S2 includes four gate trenches S2_1, ..., S2_4 aligned parallel to one another at equal intervals. Furthermore, the multiple sets of gate trenches S1, S2 include six first set of gate trenches S1 and six second set of gate trenches S2.

[0140] 6, each gate trench S1_n in the first set can have a length that is equal to or less than one-third the dimension of side 12C. Similarly, each gate trench S2_n in the second set can have a length that is equal to or less than one-quarter the dimension of side 12D.

[0141] The explanation for the connection between the field plate electrode 18 and the source wiring 304 (peripheral source wiring portion 312 and inner source wiring portion 314) can be applied to the connection between the field plate electrode 18 and the source wiring 50.

[0142] [Change Example 4] Fig. 7 is a schematic plan view of an exemplary semiconductor device 400 according to Modification 4 of the above embodiment. In Fig. 7, the same components as those in the semiconductor device 10 of Fig. 1 are denoted by the same reference numerals. Further, detailed description of the same components as those in the semiconductor device 10 will be omitted.

[0143] In addition to the same components as those of the semiconductor device 10, the semiconductor device 400 further includes a pair of first communicating trenches 402 extending along the Y direction in a plan view and connecting the first set of gate trenches S1 to each other, and a pair of second communicating trenches 404 extending along the X direction in a plan view and connecting the second set of gate trenches S2 to each other.

[0144] The multiple field plate electrodes 18 embedded in the first set of gate trenches S1 are connected to each other within a pair of first communicating trenches 402. The multiple field plate electrodes 18 embedded in the second set of gate trenches S2 are connected to each other within a pair of second communicating trenches 404. Each field plate electrode 18 is connected to the other field plate electrodes 18 at two ends 18A, 18B (see FIG. 3).

[0145] 1, the plurality of field plate electrodes 18 are electrically connected to one another through the source wiring 50. On the other hand, in the semiconductor device 400 according to the fourth modification, the plurality of field plate electrodes 18 can be directly connected to one another within the pair of first communicating trenches 402 or the pair of second communicating trenches 404. This can improve the breakdown voltage of the semiconductor device 400.

[0146] [Other change examples] The above-described embodiment and each modification can be modified and implemented as follows. The inner gate wiring portion may include three or more gate fingers extending along the X direction.

[0147] Each of the plurality of sets of gate trenches may include only one gate trench instead of a plurality of gate trenches aligned parallel to one another at equal intervals. 4, the length of the gate finger 108B may be set to be longer than half the dimension of the side 12D. This makes it possible to increase the number of gate trenches included in the first set of gate trenches S1 while shortening the length of each of the second set of gate trenches S2_n (for example, to approximately the same as that of each of the first set of gate trenches S1_n).

[0148] 5, the length of the gate finger 208B may be set to be longer than half the dimension of the side 12D. This makes it possible to increase the number of gate trenches included in the first set of gate trenches S1 while shortening the length of each of the second set of gate trenches S2_n (for example, to approximately the same as that of each of the first set of gate trenches S1_n).

[0149] A structure may be adopted in which the conductivity types of the regions in the semiconductor layer 14 are reversed. That is, a p-type region may be made into an n-type region, and an n-type region may be made into a p-type region. An additional wiring structure may be formed on the layer containing the source wiring and gate wiring.

[0150] As used in this disclosure, the term "on" includes the meanings "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0151] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y axis direction may be the vertical direction.

[0152] [Note] The technical ideas that can be understood from the above-described embodiments and modified examples are described below. For the purpose of aiding understanding, but not for the purpose of limiting the scope of the invention, the corresponding reference numerals in the embodiments are shown in parentheses for the configurations described in the appendices. The reference numerals are shown as examples to aid understanding, and the components described in the appendices should not be limited to the components indicated by the reference numerals.

[0153] (Appendix 1) A semiconductor substrate (12); a semiconductor layer (14) formed on the semiconductor substrate (12) and including, in a plan view, a peripheral region (54) and an active region (56) surrounded by the peripheral region (54); a plurality of sets of gate trenches (S1, S2) including a first set (S1) and a second set (S2) formed in the semiconductor layer (14); a plurality of gate electrodes (20), each of which is embedded in a corresponding one of the plurality of sets of gate trenches (S1, S2); a plurality of field plate electrodes (18), each of which is embedded in a corresponding one of the plurality of sets of gate trenches (S1, S2) while being insulated from the gate electrode (20); an insulating layer (16) formed on the semiconductor layer (14); a gate wiring (52; 102; 202; 302) formed on the insulating layer (16) and connected to the plurality of gate electrodes (20), the gate wiring including a peripheral gate wiring portion (58; 106; 206; 306) disposed in the peripheral region (54) in a plan view, and an inner gate wiring portion (60; 108; 208; 308) disposed in the active region (56) in a plan view; a source wiring (50; 104; 204; 304) formed on the insulating layer (16) and spaced apart from the gate wiring (52; 102; 202; 302); Equipped with each of the plurality of field plate electrodes (18) includes two ends (18A, 18B) connected to the source wiring (50; 104; 204; 304); the outer peripheral gate wiring portion (58; 106; 206; 306) includes a first gate finger (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) extending along a first direction in a plan view, and the inner gate wiring portion (60; 108; 208; 308) includes a second gate finger (60B; 108B; 208B; 308B) extending along a second direction perpendicular to the first direction in a plan view, each of the first set of gate trenches (S1_n) extends along the first direction in a plan view and intersects with the second gate finger (60B; 108B; 208B; 308B); Each of the second set of gate trenches (S2_n) extends along the second direction in a plan view and intersects with the first gate finger (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2). Semiconductor device.

[0154] (Appendix 2) each of the first set of gate trenches (S1_n) intersects with the second gate finger (60B; 108B; 208B; 308B) between the two ends (18A, 18B) of a field plate electrode (18) embedded in the gate trench in a plan view; Each of the second set of gate trenches (S2_n) intersects with the first gate finger (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) between the two ends (18A, 18B) of the field plate electrode (18) embedded in the gate trench in a plan view. 2. The semiconductor device according to claim 1.

[0155] (Appendix 3) The source wiring (50; 104; 204; 304) a peripheral source wiring portion (64; 112; 212; 312) disposed in the peripheral region (54); an inner source wiring portion (66; 114; 214; 314) disposed in the active region (56); 3. The semiconductor device according to claim 1, further comprising:

[0156] (Appendix 4) Each of the first set of gate trenches (S1_n) is disposed entirely within the active region (56); Each of the second set of gate trenches (S2_n) is disposed across the active region (56) and the peripheral region (54), In the field plate electrode (18) embedded in each of the first set of gate trenches (S1_n), both of the two ends (18A, 18B) are connected to the inner source wiring portion (66; 114; 214; 314), The semiconductor device described in Appendix 3, wherein in the field plate electrode (18) embedded in each of the second set of gate trenches (S2_n), one of the two ends (18A, 18B) is connected to the inner source wiring portion (66; 114; 214; 314), and the other of the two ends (18A, 18B) is connected to the outer source wiring portion (64; 112; 212; 312).

[0157] (Appendix 5) the gate electrodes (20) embedded in the first set of gate trenches (S1_n) are electrically connected to the second gate fingers (60B; 108B; 208B; 308B) in regions where the first set of gate trenches (S1_n) and the second gate fingers (60B; 108B; 208B; 308B) intersect in a plan view; The semiconductor device according to any one of appendices 1 to 4, wherein the gate electrodes (20) embedded in the second set of gate trenches (S2_n) are electrically connected to the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) in a region where the second set of gate trenches (S2_n) intersects with the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) in a planar view.

[0158] (Appendix 6) The semiconductor device according to any one of appendices 1 to 5, wherein the second gate finger (60B; 108B; 208B; 308B) intersects, in a planar view, two or more sets of gate trenches including the first set of gate trenches S1.

[0159] (Appendix 7) The semiconductor device according to any one of appendices 1 to 6, wherein the inner gate wiring portion (60; 308) further includes at least one other gate finger (60A; 308A1, 308A2) that intersects with the second gate finger (60B; 308B) in a planar view.

[0160] (Appendix 8) 8. The semiconductor device according to claim 7, wherein the at least one other gate finger (60A; 308A1, 308A2) includes one gate finger (60A) extending in the first direction in a plan view.

[0161] (Appendix 9) 8. The semiconductor device according to claim 7, wherein the at least one other gate finger (60A; 308A1, 308A2) includes two gate fingers (308A1, 308A2) extending in the first direction in a plan view.

[0162] (Appendix 10) The semiconductor device according to any one of appendices 1 to 9, wherein the inner gate wiring portion (208) further includes a third gate finger (208A) that forms a T-shaped junction with the second gate finger (208B) in a planar view.

[0163] (Appendix 11) The semiconductor device according to any one of appendices 1 to 10, wherein the peripheral gate wiring portion (58; 106; 206; 306) further includes a fourth gate finger (58B1 or 58B2; 106B1 or 106B2; 206B1 or 206B2; 306B1 or 306B2) extending along the second direction in a planar view.

[0164] (Appendix 12) 12. The semiconductor device according to any one of claims 1 to 11, wherein each of the plurality of sets of gate trenches (S1, S2) includes a plurality of gate trenches aligned parallel to each other at equal intervals.

[0165] (Appendix 13) a pair of first communicating trenches (402) extending along the second direction in a plan view and connecting the first set of gate trenches (S1) to each other; a pair of second communicating trenches (404) extending along the first direction in a plan view, which communicate the second set of gate trenches (S2) with each other; further comprising the plurality of field plate electrodes (18) embedded in the first set of gate trenches (S1) are connected to one another within the pair of first communicating trenches (402), the plurality of field plate electrodes (18) embedded in the second set of gate trenches (S2) are connected to one another within the pair of second communicating trenches (404), and each field plate electrode (18) is connected to the other field plate electrodes at the two ends (18A, 18B); 13. The semiconductor device according to any one of claims 1 to 12.

[0166] (Appendix 14) the semiconductor substrate (12) includes a surface (12B) on which the semiconductor layer (14) is formed, the surface (12B) including a first side (12C or 12E) extending along the first direction and a second side (12D or 12F) extending along the second direction; Each of the first set of gate trenches (S1_n) has a length equal to or less than half the dimension of the first side (12C or 12E), Each of the second set of gate trenches (S2_n) has a length equal to or less than half the dimension of the second side (12D or 12F). 14. The semiconductor device according to any one of claims 1 to 13.

[0167] (Appendix 15) 15. The semiconductor device according to claim 14, wherein each of the first set of gate trenches (S1_n) has a length that is equal to or less than 1 / 3 of the dimension of the first side (12C or 12E).

[0168] (Appendix 16) 16. The semiconductor device according to claim 14, wherein each of the second set of gate trenches (S2_n) has a length equal to or less than 1 / 3 of the dimension of the second side (12D or 12F).

[0169] (Appendix 17) The semiconductor device of any one of appendices 14 to 16, wherein the dimension of the second side is larger than the dimension of the first side, and the length of each gate trench of the second set is larger than the length of each gate trench of the first set.

[0170] (Appendix 18) 18. The semiconductor device according to any one of claims 1 to 17, wherein the number of gate trenches included in the first set is greater than the number of gate trenches included in the second set.

[0171] (Appendix 19) The semiconductor device according to any one of appendices 1 to 18, wherein the active region (56) is a rectangular region, the short side direction of the active region (56) corresponds to the first direction, and the long side direction of the active region (56) corresponds to the second direction.

[0172] (Appendix 20) The peripheral region (54) is a rectangular frame-shaped region surrounding the active region (56), 20. The semiconductor device according to claim 19, wherein the peripheral gate wiring portion (58; 106; 206; 306) extends in the peripheral region (54) along a boundary between the active region (56) and the peripheral region (54).

[0173] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0174] 10, 100, 200, 300, 400...Semiconductor equipment 12...Semiconductor substrate 12A...bottom 12B…Top surface 12C, 12E...first side 12D, 12F...Second side 14...Semiconductor layer 16...Insulating layer 18...Field plate electrode 18A,18B...end 20...Gate electrode 22...Drift region 24...Body area 26...Source region 28...Drain electrode 30...Side wall 32...Bottom wall 34...Trench insulating layer 38...Gate insulation 40...Lower insulation part 42...Intermediate insulation section 44...Contact trench 46...Contact area 48...Source Contact 50, 104, 204, 304...Source wiring 52, 102, 202, 302...Gate wiring 54...Outer area 56...Inner area (active area) 58, 106, 206, 306...Outer gate wiring section 60, 108, 208, 308...Inner gate wiring section 58A1, 58A2, 58B1, 58B2, 60A, 60B, 106A1, 106A2, 106B1, 106B2, 108B, 206A1, 206A2, 206A3, 206B1, 206B2, 208A, 208B, 306A1, 306A2, 306B1, 306B2, 308A1, 308A2, 308B...Gate Finger 62, 110, 210, 310...Gate pad 64, 112, 212, 312...Outer source wiring section 66, 114, 214, 314...Inner source wiring section 68...Field plate contact 70...Gate contact 72...insulating layer 402...First connecting trench 404...Second connecting trench S1: First set of gate trenches S2: Second set of gate trenches S1_n, S2_n...Gate trench

Claims

1. a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and including, in a plan view, a peripheral region and an active region surrounded by the peripheral region; a plurality of sets of gate trenches, including a first set and a second set, formed in the semiconductor layer; a plurality of gate electrodes, each of which is embedded in a corresponding one of the plurality of sets of gate trenches; a plurality of field plate electrodes, each of which is embedded in a corresponding one of the plurality of sets of gate trenches while being insulated from the gate electrode; an insulating layer formed on the semiconductor layer; a gate wiring formed on the insulating layer and connected to the plurality of gate electrodes, the gate wiring including a peripheral gate wiring portion disposed in the peripheral region in a plan view and an inner gate wiring portion disposed in the active region in a plan view; a source wiring formed on the insulating layer and spaced apart from the gate wiring; Equipped with each of the plurality of field plate electrodes includes two ends connected to the source line; the outer periphery gate wiring portion includes a first gate finger extending along a first direction in a plan view, and the inner gate wiring portion includes a second gate finger extending along a second direction perpendicular to the first direction in a plan view, each of the first set of gate trenches extends along the first direction in a plan view and intersects with the second gate finger; Each of the second set of gate trenches extends along the second direction in a plan view and intersects with the first gate finger. Semiconductor device.

2. each of the first set of gate trenches intersects with the second gate finger between the two ends of a field plate electrode embedded in the gate trench in a plan view; each of the second set of gate trenches intersects with the first gate finger between the two ends of a field plate electrode embedded in the gate trench in a plan view; The semiconductor device according to claim 1 .

3. The source wiring is a peripheral source wiring portion disposed in the peripheral region; an inner source wiring portion disposed in the active region; The semiconductor device according to claim 1 or 2, comprising:

4. each of the first set of gate trenches is disposed entirely within the active area; Each of the second set of gate trenches is disposed across the active region and the periphery region, In the field plate electrode embedded in each of the first set of gate trenches, both of the two ends are connected to the inner source wiring portion, 4. The semiconductor device according to claim 3, wherein one of the two ends of the field plate electrode embedded in each of the second set of gate trenches is connected to the inner source wiring portion, and the other of the two ends is connected to the outer source wiring portion.

5. the gate electrodes embedded in the first set of gate trenches are electrically connected to the second gate fingers in regions where the first set of gate trenches intersect with the second gate fingers in a plan view; The semiconductor device according to any one of claims 1 to 4, wherein the gate electrodes embedded in each of the second set of gate trenches are electrically connected to the first gate fingers in regions where the gate trenches of the second set intersect with the first gate fingers in a planar view.

6. 6. The semiconductor device according to claim 1, wherein the second gate finger intersects with two or more sets of gate trenches including the first set of gate trenches in a plan view.

7. 7. The semiconductor device according to claim 1, wherein the inner gate wiring portion further includes at least one other gate finger that intersects with the second gate finger in a plan view.

8. The semiconductor device according to claim 7 , wherein the at least one other gate finger includes one gate finger extending in the first direction in a plan view.

9. The semiconductor device according to claim 7 , wherein the at least one other gate finger includes two gate fingers extending in the first direction in a plan view.

10. 10. The semiconductor device according to claim 1, wherein the inner gate wiring portion further includes a third gate finger that forms a T-shaped junction with the second gate finger in a plan view.

11. 11. The semiconductor device according to claim 1, wherein the outer periphery gate wiring portion further includes a fourth gate finger extending along the second direction in plan view.

12. 12. The semiconductor device according to claim 1, wherein each of the plurality of sets of gate trenches includes a plurality of gate trenches aligned parallel to each other at equal intervals.

13. a pair of first communicating trenches extending along the second direction in plan view, the first communicating trenches communicating with each other; a pair of second communicating trenches extending along the first direction in plan view, the second communicating trenches communicating with each other; further comprising the plurality of field plate electrodes embedded in the first set of gate trenches are connected to one another within the pair of first communicating trenches, the plurality of field plate electrodes embedded in the second set of gate trenches are connected to one another within the pair of second communicating trenches, and each field plate electrode is connected to other field plate electrodes at the two ends. The semiconductor device according to any one of claims 1 to 12.

14. the semiconductor substrate includes a surface on which the semiconductor layer is formed, the surface including a first side extending along the first direction and a second side extending along the second direction; Each of the first set of gate trenches has a length equal to or less than half the dimension of the first side; Each of the second set of gate trenches has a length equal to or less than half the dimension of the second side. The semiconductor device according to any one of claims 1 to 13.

15. 15. The semiconductor device of claim 14, wherein each of the first set of gate trenches has a length that is less than or equal to one-third of the dimension of the first side.

Images