Semiconductor devices and electronic devices

Abstract

One purpose of the present invention is to provide a semiconductor device and an electronic device that can minimize anomalies in connections made between different chips.　The semiconductor device has an insulating layer, and comprises a first chip having a plurality of wiring layers having wiring formed inside the insulating layer, and at least one second chip having a plurality of electroconductive parts mounted on the first chip. The first chip has a plurality of pad layers, a connection structure in which the pad layers and the electrically conductive parts are electrically connected is formed on the first chip, and the plurality of pad layers are formed on at least a plurality of different wiring layers.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and an electronic device. [Background technology]

[0002] Known semiconductor devices include those having a structure in which a semiconductor chip is mounted on a substrate that constitutes the semiconductor chip, and another chip is placed directly on the substrate, as shown in Patent Document 1. The other chip can be, for example, a chip equipped with a driving IC for driving a semiconductor element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-163368 Summary of the Invention [Problem to be solved by the invention]

[0004] When another chip is placed on a substrate that constitutes a semiconductor chip, the other chip is electrically connected to the semiconductor chip by a method such as pressure bonding the other chip onto the semiconductor chip. In this case, it is required to be able to suppress poor electrical connection between the semiconductor chip and the other chip even if there is variation in the pressure applied from the other chip to the semiconductor chip during pressure bonding. Pressure variation is likely to occur when there is variation in the thickness of the substrate that constitutes the other chip. Therefore, it is required to suppress poor electrical connection between the semiconductor chip and the other chip even if there is variation in the thickness of the substrate that constitutes the other chip.

[0005] The present disclosure has been made in consideration of the above-mentioned points, and one of its objectives is to provide a semiconductor device and an electronic device that can suppress poor connections between different chips, i.e., another chip and a semiconductor chip, when another chip is crimped onto a semiconductor chip, even if the other chip has thickness variations. [Means for solving the problem]

[0006] The present disclosure provides, for example, (1) a first chip having an insulating layer and a plurality of wiring layers each having wiring formed inside the insulating layer; at least one second chip mounted on the first chip and having a plurality of conductive portions; the first chip has a plurality of pad layers; a connection structure is formed that electrically connects the pad layer and the conductive portion, The pad layers are formed on at least a plurality of different wiring layers. Crate , a resin film containing conductive particles is provided between the first chip and the second chip; the conductive portion is a bump, The connection structure has a structure in which the pad layer and the bump are connected via conductive particles. It is a semiconductor device.

[0007] The present disclosure relates to the semiconductor device described in (1) above. Device The electronic device may be an electronic device using the above. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of an example of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view schematically showing the state of a vertical cross section taken along line AA in FIG. [Figure 3] 3A is a bottom view schematically illustrating a second chip in an example of the semiconductor device according to the first embodiment, and FIG. 3B is a cross-sectional view schematically illustrating the second chip in an example of the semiconductor device according to the first embodiment. [Figure 4] 4A to 4D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5A and 5B are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view schematically illustrating a schematic configuration of an example of the semiconductor device according to the first embodiment. [Figure 8] 8A and 8B are cross-sectional views for explaining an example of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view for explaining an example of a semiconductor device according to Modification 1 of the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view illustrating an example of a semiconductor device according to the second modification of the first embodiment. [Figure 11] 11A and 11B are plan views for explaining an example of the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a plan view for explaining an example of the semiconductor device according to the third embodiment. [Figure 13] 13A and 13B are a bottom view and a cross-sectional view, respectively, of a second chip in an example of the semiconductor device according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view for explaining an example of a semiconductor device according to the fourth embodiment. [Figure 15] FIG. 15 is a diagram for explaining an example of a polishing step of the second tip. [Figure 16] 16A and 16B are diagrams illustrating examples of electronic devices using semiconductor devices. [Figure 17] FIG. 17 is a diagram illustrating an example of an electronic device using a semiconductor device. [Figure 18] FIG. 18 is a diagram illustrating an example of an electronic device using a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment of the present disclosure will be described below with reference to the drawings. The description will be given in the following order: In this specification and the drawings, components having substantially the same functional configuration are designated by the same reference numerals, and redundant description will be omitted.

[0010] The explanation will be given in the following order. 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth Embodiment 5. Application Examples 6. Examples of other devices

[0011] The following description is a preferred example of the present disclosure, and the content of the present disclosure is not limited to these embodiments. Furthermore, in the following description, directions such as front-to-back, left-to-right, and up-down are indicated for the sake of convenience, but the content of the present disclosure is not limited to these directions. In the examples of Figures 1, 2, 3, etc., the Z axis direction is the up-down direction (the upper side is the +Z direction, and the lower side is the -Z direction), the X axis direction is the front-to-back direction (the front side is the +X direction, and the rear side is the -X direction), and the Y axis direction is the left-to-right direction (the right side is the +Y direction, and the left side is the -Y direction), and the description will be based on this. The same applies to Figures 4 to 15. Unless otherwise specified, the relative size ratios of the sizes and thicknesses of each layer shown in Figure 1 and other figures are for convenience and do not limit the actual size ratios. The same definitions and size ratios regarding these directions apply to Figures 2 to 15.

[0012] The semiconductor device according to the present disclosure is not particularly limited, and examples thereof include a semiconductor display device equipped with a light-emitting element. The light-emitting element used in the semiconductor display device is not particularly limited, and examples thereof include an OLED (Organic Light Emitting Diode) (organic EL light-emitting element) and an LED (Light Emitting Diode) (semiconductor light-emitting element). Furthermore, among OLEDs and LEDs, so-called micro OLEDs and micro LEDs, which are more miniaturized, may be adopted as the light-emitting element.

[0013] The following first to fourth embodiments will be described taking as an example a case where the semiconductor device is used as a display device, in particular a case where the semiconductor device is a display device using an OLED as a light-emitting element.

[0014] [1 First embodiment] [1-1 Configuration of semiconductor device] 1 and 2, a semiconductor device 1 according to the first embodiment has a first chip 10 and a second chip 20. Figures 1 and 2 are a plan view and a cross-sectional view, respectively, for explaining an example of the semiconductor device 1 according to the first embodiment.

[0015] (display area and outer area) As shown in FIG. 1, the semiconductor device 1 includes a display area 100A and an outer area 100B on the display surface D side. The display area 100A is defined as an area where a display unit (described later) is disposed, and a display area 100C is defined within or over the entire display area 100A, for emitting light generated from the display area 11 to the outside. In the example of FIG. 1, the display area 100A is formed as a rectangular area on the first chip 10 in a plan view of the semiconductor device 1, and the display area 100C is the area surrounded by a dashed line. The outer area 100B is the area outside the display area 100A on the first chip. The display area 100A and the outer area 100B are adjacent to each other. The display surface D refers to the surface of the semiconductor device 1 through which light generated by the light-emitting elements is extracted to the outside.

[0016] In the following description, the surface facing the display surface D of the semiconductor device 1 (the surface on the +Z direction side) will be referred to as the first surface (top surface), and the surface on the back side of the semiconductor device 1 (the surface on the -Z direction side) will be referred to as the second surface (bottom surface).

[0017] (First chip) The first chip 10 is a semiconductor chip. In the example of Fig. 1 and Fig. 2, the semiconductor chip that becomes the first chip 10 has a drive substrate 14 and a display unit 11 formed on the drive substrate 14. The first chip 10 has a plurality of wiring layers 12 and an insulating layer 13 on the drive substrate 14.

[0018] (Display) As described above, the display unit 11 is formed in a portion corresponding to the display area 100A of the first chip 10. The display unit 11 in the example of FIG. 1 has a large number of pixels, and has a structure (not shown) in which a plurality of light-emitting elements are arranged on the drive substrate 14 for each pixel. The light-emitting elements are arranged according to the pixel pattern. In this example, organic EL light-emitting elements are used as the light-emitting elements, as described above. Note that the display unit 11 may be provided with a counter substrate 21 such as a glass substrate so as to cover the light-emitting elements. For ease of explanation, FIG. 1 omits illustration of each component, such as the light-emitting elements arranged between the drive substrate 14 and the counter substrate 21. For ease of explanation, the display unit 11 is also omitted from FIGS. 2 to 14.

[0019] (Drive board) In the first chip 10, as shown in FIG. 2, the drive substrate 14 has a substrate 15, a semiconductor element 16 provided on the first surface side of the substrate 15, and a multilayer wiring section 17.

[0020] (substrate) Substrate 15 may be made of, for example, glass or resin with low moisture and oxygen permeability, or may be made of a semiconductor that facilitates the formation of transistors and the like. Specifically, substrate 15 may be a glass substrate, a semiconductor substrate, a resin substrate, or the like. Glass substrates include, for example, high strain point glass, soda glass, borosilicate glass, forsterite, lead glass, or quartz glass. Semiconductor substrates include, for example, amorphous silicon, polycrystalline silicon, or single crystal silicon. Resin substrates include, for example, at least one selected from the group consisting of polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate. In the example of FIG. 2, semiconductor elements are formed on substrate 15. From the viewpoint of ease of forming such semiconductor elements, a silicon substrate is preferably used as substrate 15.

[0021] (semiconductor element) As shown in the example of FIG. 2, a semiconductor element 16 is provided on the first surface side of the substrate 15. The semiconductor element 16 may be selected appropriately depending on the function of the semiconductor device 1, and an example thereof is a transistor such as a CMOS (Complementary Metal Oxide Semiconductor). The semiconductor element 16 shown in FIG. 2 is a transistor and has a gate 16A, a source 16B, and a drain 16C. In this example, a sidewall oxide film 19 made of an insulating material is formed on the side surface of the gate 16A. Furthermore, each semiconductor element 16 is isolated by an element isolation layer 18. An example of the material of the element isolation layer 18 is SiO2.

[0022] (Multilayer wiring part) The multilayer wiring section 17 is formed on the first surface side of the substrate 15. The multilayer wiring section 17 has an insulating layer 13 and multiple wiring layers 12. In the example of FIG. 2, the multilayer wiring section 17 is formed on the first surface side of the substrate 15 so as to cover the semiconductor element 16.

[0023] (wiring layer) The wiring layer 12 has wiring 120. In the wiring layer 12, the wiring 120 is formed in a pattern corresponding to the design of the semiconductor device 1 in a plan view of the multilayer wiring section 17. The material of the wiring 120 is not particularly limited, but examples thereof include metal materials such as copper, gold, silver, and aluminum. In a plan view of the multilayer wiring section 17, the thickness direction (Z-axis direction) of the multilayer wiring section 17 is taken as the line of sight.

[0024] The wiring layers 12 are provided in a plurality of layers spaced apart in the vertical direction (Z-axis direction). There is no particular limitation on the number of wiring layers 12, but in the example of FIG. 2, five wiring layers 12 are stacked. An insulating layer 13 is provided between adjacent wiring layers 12. The plurality of wiring layers 12 are provided inside the insulating layer 13. Note that the inside of the insulating layer 13 as referred to here includes the case where the wiring layers 12 are buried in the insulating layer 13, as well as the case where at least a part of the wiring layers 12 is exposed from an opening (e.g., pad opening 26) provided in the insulating layer 13.

[0025] Vertically adjacent wiring layers 12 are electrically connected to each other by vias 24 formed at predetermined positions. The spacing between adjacent wiring layers 12 is determined depending on various conditions, such as the position of the pad layer 22, the wiring pattern, and the wiring resistance, which will be described later. The vias 24 may have a general structure, and have a structure in which a layer of conductive material is formed on the inner wall surface of a hole formed at a predetermined position in the insulating layer 13 so as to connect the wiring layers 12. The conductive material forming the vias 24 may be the same as that of the wiring 120. In FIG. 2, the vias 24 are solid, but this is merely an example and does not exclude the vias 24 from having a hollow shape.

[0026] 2, the lowest wiring layer 12, i.e., the wiring layer 12 closest to the substrate 15, is electrically connected to the semiconductor element 16 via a contact wiring 23. The material of the contact wiring 23 is not particularly limited, but a metal material such as tungsten can be suitably used. An insulating layer 13 is also interposed between the wiring layer 12 closest to the substrate 15 and the substrate 15, and a contact hole is formed on the semiconductor element 16 in this insulating layer 13, with the contact wiring 23 further embedded in the contact hole.

[0027] (insulating layer) An insulating layer 13 is formed in the multilayer wiring section 17. The insulating layer 13 fills the gap between adjacent wiring layers 12. The insulating layer 13 also fills the gap between the wiring layer 12 closest to the substrate 15 and the substrate 15. The insulating layer 13 also covers the wiring layer 12 farthest from the substrate 15.

[0028] The material of the insulating layer 13 is not particularly limited, but from the viewpoint of high-speed signal transmission, a material with a low dielectric constant (low relative dielectric constant material) (so-called low-k material) is suitable.

[0029] The insulating layer 13 may have a structure in which multiple layers are stacked together. For example, as shown in FIGS. 4D, 5A, 5B, etc., which will be described in the manufacturing method described later, the insulating layer 13 may have a layered structure including a layer 113 filling the gap between the wiring layer 12 closest to the substrate 15 and the substrate 15, a layer 113 filling the gap between adjacent wiring layers 12, and a layer 113 covering the wiring layer 12 farthest from the substrate 15. In this layered structure, adjacent layers are integrated in the areas where no wiring layer is formed. That is, in this case, the insulating layer 13 has a structure in which multiple layers 113 are stacked together. When the insulating layer 13 has a structure in which multiple layers 113 are stacked together, the number of layers is not particularly limited. 4D, 5A, and 5B, all layers 113 are formed of the same material, and adjacent layers 113 are in contact with each other and integrated in the areas where wiring layer 12 is not formed. In FIGS. 4D and 5A, the boundaries between adjacent layers 113 are indicated by dashed lines.

[0030] (Pad layer) The first chip 10 has a pad layer 22. The pad layer 22 can be used as a connection terminal for electrically connecting a chip other than the first chip 10 to the first chip 10. The first chip 10 is provided with a plurality of pad layers 22. In the semiconductor device 1 according to the first embodiment, at least two different wiring layers 12 of the first chip 10 have pad layers 22. In the example of FIG. 2, the first wiring layer 12A1 and the second wiring layer 12A2 have pad layers 22. The nth wiring layer 12 from the top is designated as the nth wiring layer 12An (n is an integer of 2 or more). Therefore, the wiring layers 12 are arranged in order from the topmost wiring layer 12, namely, the first wiring layer 12A1, the second wiring layer 12A2, and the third wiring layer 12A3, with the insulating layer 13 interposed therebetween. In this specification, when the first wiring layer 12A1, the second wiring layer 12A2, . . . , and the n-th wiring layer 12An are not particularly distinguished from each other, they are simply referred to as wiring layers 12.

[0031] In the example of FIG. 2, there is no wiring layer 12 without a pad layer 22 between the multiple wiring layers 12 (the first wiring layer 12A1 and the second wiring layer 12A2) with pad layers 22 provided thereon. However, FIG. 2 is just an example, and the semiconductor device 1 may have one or more wiring layers 12 without a pad layer 22, which will be described in the explanation of Modification 2. Note that with regard to the pad layer 22, the pad layer 22 in the first wiring layer 12A1 may be referred to as the first pad layer 22A1, and the pad layer 22 in the second wiring layer 12A2 may be referred to as the second pad layer 22A2. Furthermore, when there is no need to particularly distinguish between the first pad layer 22A1, the second pad layer 22A2, etc., they will simply be referred to as pad layers 22.

[0032] The pad layer 22, both the first pad layer 22A1 and the second pad layer 22A2, is used as a connection terminal electrically connected to a conductive portion (bump 25 in the example of FIG. 2) of the second chip 20, which will be described later. An opening (pad opening 26) is formed above a predetermined region of the pad layer 22. An upper space is opened from a predetermined region on the first surface side of the first pad layer 22A1, and the pad opening 26 is formed in the opened portion. Similarly to the first pad layer 22A1, the second pad layer 22A2 also has a space opened from a predetermined region on the first surface side to the upper side, and the pad opening 26 is formed in the opened portion.

[0033] The number and positions of the pad layers 22 (positions in a plan view of the semiconductor device 1) are not particularly limited, but are provided under the conditions of the number and positions according to the number and positions of the conductive parts provided on the second chip 20, which will be described later. The material of the pad layers 22 is not particularly limited as long as it is conductive, and the same material as the wiring 120 may be used, and similarly to the wiring 120, a metal material can be preferably used.

[0034] (difference in pad layer position) In the semiconductor device 1, the positions of the pad layers 22 provided on different wiring layers 12 are different from each other. In this case, as shown in FIG. 7 , the difference M in the vertical (Z-axis) position between the uppermost pad layer 22 and the lowermost pad layer 22 is preferably equal to or less than half the average particle diameter of the conductive particles 31 described below. As described below, the average particle diameter of the conductive particles 31 is often within a range of approximately 3 μm to approximately 10 μm. FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device 1 according to the first embodiment. In the example of FIG. 7 , among the wiring layers 12 having pad layers 22, the first pad layer 22A1 located closest to the first surface and the second pad layer 22A2 located closest to the second surface are located differently from each other. Furthermore, the difference M in the positions of the first pad layer 22A1 and the second pad layer 22A2 is preferably equal to or less than half the average particle diameter of the conductive particles 31. In this case, when the second chip 20, the anisotropic conductive film 30 described below, and the first chip 10 are pressure-bonded together, the conductive particles 31 sandwiched between the bumps 25 and the first pad layer 22A1 and the conductive particles 31 sandwiched between the bumps 25 and the second pad layer 22A2 can both be appropriately deformed by the pressing force applied between the bumps 25 and the pad layer 22. In the example of Fig. 2, the conductive particles 31 sandwiched between the first pad layer 22A1 and the bumps 25 and the conductive particles 31 sandwiched between the second pad layer 22A2 and the bumps 25 can both be crushed (deformed) to about half or more of their size before pressure-bonding.

[0035] The positions of the pad layers 22 refer to the positions along the thickness direction (Z-axis direction) of the multilayer wiring section 17. The difference M in the positions of the multiple pad layers 22 refers to the distance between the multiple pad layers 22 along the up-down direction (Z-axis direction).

[0036] (Second chip) In the semiconductor device 1, at least one second chip 20 is mounted on (on the first surface side of) the first chip 10. In the example of FIG. 1, one second chip 20 is mounted on a semiconductor chip serving as the first chip 10. The second chip 20 is also disposed in the outer region 100B. Therefore, the size of the second chip 20 is smaller than the size of the first chip 10.

[0037] The second chip 20 is an IC chip having electronic components and integrated circuits according to functions mounted on a substrate (not shown), and is different from the first chip 10. Examples of IC chips include display driver integrated circuits (DDICs), memories, sensors, and image processing integrated circuits (ICs).

[0038] (2nd chip thickness) The thickness of the second chip 20 may be uniform or non-uniform. In the example of FIG. 3B, the thickness of the second chip 20 is non-uniform (varies). In this case, the thickness distribution of the second chip 20 is not particularly limited. The thickness distribution of the second chip 20 may be determined according to the distribution of the density of the bumps 25, which will be described later. In the example of FIG. 3B, the thickness T1 of the second chip 20 near two end portions 27 spaced apart in the longitudinal direction of the second chip 20 (the left-right direction (Y-axis direction) in FIG. 3B) is smaller than the thickness T2 of the second chip 20 at the central portion 28 of the second chip 20. Note that the thickness of the second chip 20 refers to the thickness of the second chip 20 excluding the bumps 25. The vicinity of the end portions 27 refers to the portion from the end face of the second chip 20 to a predetermined position toward the central portion 28. Central portion 28 refers to the portion extending from the center of second chip 20 to a predetermined position toward end portion 27. Fig. 3B is a cross-sectional view showing an example of second chip 20, and corresponds to the cross-sectional view of second chip 20 shown in Fig. 3A. Fig. 3A is a bottom view showing an example of second chip 20.

[0039] The thickness distribution of the second chip 20 as shown in the example of Figure 3B tends to be realized when, in the manufacturing process of the semiconductor device 1, a process (polishing process) is carried out in which the first surface side of the second chip 20 (the surface side on which the bumps 25 are not provided) is polished after the bumps 25 are provided on the second chip 20.

[0040] In the polishing process, as shown in FIG. 15 , a backgrind tape (BG tape 32) is provided as a protective tape on the second surface of the second chip 20 so as to cover a bump group 125 consisting of a plurality of bumps 25. The BG tape 32 is then fixed on the suction unit 36 ​​of a suction device, and the first surface of the second chip 20 is polished by a polishing unit 37 of the polishing device. FIG. 15 is a diagram illustrating an example of the polishing process for the second chip 20. During the polishing process, more of the second chip 20 is polished in areas where the bumps 25 are densely packed than in areas where the bumps 25 are sparsely packed. Thus, the thickness of the second chip 20 tends to vary depending on the distribution of the density of the bumps 25. The suction device and polishing device may be, for example, those commonly used in the polishing process for semiconductor chips. The bump group 125 refers to a set of multiple bumps 25 arranged in a region defined as a region where the bumps 25 are relatively densely packed.

[0041] (Conductive part) The second chip 20 has a second surface facing the first surface of the first chip 10, and has a plurality of conductive portions on the surface facing the first chip 10.

[0042] The conductive portion is electrically connected to the integrated circuit mounted on the second chip 20. In the semiconductor device 1, a connection structure 33 is formed that electrically connects the conductive portion and the pad layer 22 of the first chip 10.

[0043] The conductive portion may be formed in a layer shape on the back surface (second surface) of the second chip 20, or may be formed in a protrusion shape. In the example of FIG. 2, the conductive portion is a conductive protrusion (bump 25) protruding from the back surface (second surface) of the second chip 20. In the description of the first embodiment, a case where the conductive portion is a bump 25 is used as an example. Note that the description using the case where the conductive portion is a bump 25 as an example also applies to the second to fourth embodiments described later.

[0044] (bump) The bumps 25 as conductive portions are configured to be electrically connected to the desired pad layer 22 of the first chip 10. The type of bump 25 is not particularly limited, and examples thereof include pillar bumps and stud bumps. Examples of materials for the bumps 25 include gold, silver, copper, tin, and alloys thereof. The cross-sectional shape of the bumps 25 is rectangular in the example shown in FIG. 3A (described later), but is not limited thereto and may be circular or other shapes. From the viewpoint of facilitating connection of the bumps 25 to the pad layer 22, it is preferable that the cross-sectional size of the bumps 25 be smaller than that of the pad layer 22. The number of bumps 25 is determined depending on the type of integrated circuit and electronic components mounted on the second chip 20. In the examples shown in FIGS. 2 and 3, a plurality of bumps 25 are provided. The size of each bump 25 is not particularly limited, but in the example shown in FIG. 2, the size of each bump 25 is generally uniform.

[0045] (bump density) The density distribution of the bumps 25 on the second chip 20 (the distribution of the density of the bumps 25) may be determined according to the design of the circuit of the second chip 20. In the example of FIGS. 3A and 3B, the second chip 20 is formed in a long, narrow rectangular shape in a plan view of the second chip 20, and the density of the bumps 25 near two end portions 27 spaced apart in the longitudinal direction of the second chip 20 is greater than the density of the bumps 25 in the central portion 28 of the second chip 20. The density of the bumps 25 refers to the number of bumps 25 formed per unit area. In the example of FIG. 3A, the region defining the unit area (unit region RU) is indicated by the region surrounded by a dashed line. In this example, the number of bumps 25 formed in the unit region RU defined near the end portions 27 is greater than the number of bumps 25 formed in the unit region RU defined in the central portion 28.

[0046] 3B, the thickness T1 of the second chip 20 in the vicinity of the end portion 27 of the second chip 20 is smaller than the thickness T2 of the second chip 20 in the central portion 28 of the second chip 20. Therefore, the plurality of bumps 25 are formed on the second chip 20 such that the density of the bumps 25 formed in the portion where the thickness of the second chip 20 is relatively large (the central portion 28) is lower than the density of the bumps 25 formed in the portion where the thickness of the second chip 20 is relatively small (the end portion 27).

[0047] (Connection structure) In the semiconductor device 1, as described above, a connection structure 33 is formed that electrically connects the pad layer 22 and the conductive portion. The second chip 20 and the first chip 10 are electrically connected via the connection structure 33. When the conductive portion is a bump 25, the connection structure 33 is a structure that electrically connects the pad layer 22 and the bump 25, as shown in FIG. 2. The pad layer 22 and the bump 25 may be directly connected, or may be electrically connected via conductive particles 31, which will be described later. The connection structure 33 may also have a structure that includes both a portion where the pad layer 22 and the bump 25 are directly connected, and a portion where the pad layer 22 and the bump 25 are electrically connected via conductive particles 31. In FIG. 2, the connection structure 33 is depicted as the portion surrounded by a dashed line.

[0048] In the example shown in Figure 2, the structure in which the pad layer 22 and the bump 25 are electrically connected by sandwiching the conductive particles 31 is realized by providing a resin film containing the conductive particles 31 between the first chip 10 and the second chip 20.

[0049] (anisotropic conductive film) As shown in the example of FIG. 2, an anisotropic conductive film (ACF) (ACF) 30 is preferably used as the resin film containing conductive particles 31. The anisotropic conductive film 30 contains conductive particles 31 dispersed throughout the anisotropic conductive film 30. The connection structure 33 can be formed using the anisotropic conductive film 30 as described below. The anisotropic conductive film 30 is placed on the first surface of the first chip 10, and the second chip 20 is placed on the anisotropic conductive film 30. At this time, the second chip 20 and the first chip 10 are aligned so that the tips of the bumps 25 of the second chip 20 are directed toward the pad layer 22 of the first chip 10. Then, the second chip 20, the anisotropic conductive film 30, and the first chip 10 are pressure-bonded together (hereinafter referred to as the pressure-bonding process). During this compression bonding step, a portion of the anisotropic conductive film 30 enters the pad opening 26 above the pad layer 22. The conductive particles 31 contained in the anisotropic conductive film 30 are sandwiched between the bump 25 and the pad layer 22, and the bump 25 and the pad layer 22 are electrically connected via the conductive particles 31. From the viewpoint of effectively exhibiting the conductivity of the conductive particles 31, it is preferable that the conductive particles 31 be crushed (deformed) while sandwiched between the bump 25 and the pad layer 22 during the compression bonding step.

[0050] In the semiconductor device 1, the degree of deformation (deformation degree) of the conductive particles 31 may vary depending on the distance between the bump 25 and the pad layer 22. In the example of FIG. 2, the distance between the bump 25 and the second pad layer 22A2 is greater than the distance between the bump 25 and the first pad layer 22A1. In this case, the degree of deformation of the conductive particles 31 located between the bump 25 and the first pad layer 22A1 is greater than the degree of deformation of the conductive particles 31 located between the bump 25 and the second pad layer 22A2. In the example of FIG. 2, the conductive particles 31 located between the bump 25 and the first pad layer 22A1 are deformed to an almost completely crushed state. It is preferable that the conductive particles 31 located between the bump 25 and the second pad layer 22A2 are also crushed to an extent that the conductive effect of the conductive particles 31 is more reliably exhibited. From this point of view, it is preferable that the state of the conductive particles 31 after being sandwiched between the bump 25 and the pad layer 22 is such that they are crushed between the bump 25 and the pad layer 22 to the extent that the average particle diameter of the conductive particles 31 is less than half of the state of the conductive particles 31 before being sandwiched between the bump 25 and the pad layer 22.

[0051] (Deformation degree of conductive particles) The degree of deformation of the conductive particles 31 indicates the rate of change ((W1-W2) / W1) of the average particle diameter (W2) of the conductive particles 31 along the bonding direction after the bonding process relative to the average particle diameter (W1) of the conductive particles 31 along the bonding direction (-Z direction in the example of Figure 7) before the bonding process, for the conductive particles 31 sandwiched between the bump 25 and the pad layer 22, as shown in Figure 7.

[0052] (Average particle size of conductive particles) The average particle diameter of the conductive particles 31 is preferably smaller than the opening diameter of the pad opening 26. This makes it easier for the conductive particles 31 to enter the pad opening 26 when a portion of the anisotropic conductive film 30 enters the pad opening 26 above the pad layer 22. Specifically, as described above, the average particle diameter of the conductive particles 31 is often within the range of approximately 3 μm to approximately 10 μm. The average particle diameter (W1) of the conductive particles 31 along the compression direction before the compression step is preferably the arithmetic mean value of the sizes (particle diameters) along the compression direction of 10 conductive particles 31 arbitrarily selected in a portion of the anisotropic conductive film 30 that is expected to be sandwiched between the bump 25 and the pad layer 22. However, the average particle diameter (W1) of the conductive particles 31 may also be the arithmetic mean value of the sizes (particle diameters) along the compression direction of 10 conductive particles 31 arbitrarily selected throughout the entire anisotropic conductive film 30. The average particle diameter (W2) of the conductive particles 31 along the bonding direction after the bonding process shall represent the arithmetic mean value of the size (particle diameter) along the bonding direction of 10 conductive particles 31 (if less than 10, the total number of conductive particles 31 sandwiched between the bump 25 and the pad layer 22) arbitrarily selected from the conductive particles 31 sandwiched between the bump 25 and the pad layer 22.

[0053] (Positional relationship between bump and pad layer) The bumps 25 and the pad layer 22 are formed facing each other. When the thickness of the second chip 20 is non-uniform, as shown in the example of FIG. 3B, it is preferable that the bumps 25 formed in the thicker portion of the second chip 20 and the bumps 25 formed in the thinner portion of the second chip 20 are connected to the pad layers 22 formed on different wiring layers 12, as shown in FIGS. 8A and 8B. FIGS. 8A and 8B are diagrams illustrating an example in which the thickness of the second chip 20 is non-uniform. FIG. 8A shows the state of the first chip 10 and the second chip 20 during the pressure-bonding process, and FIG. 8B shows an example of the semiconductor device 1 after the pressure-bonding process. In FIG. 8A, the arrow P indicates the pressure-bonding direction when the second chip 20 is pressure-bonded to the first chip 10.

[0054] 8A and 8B, the position of the pad layer 22 connected to the bumps 25 formed in the relatively thinner portions of the second chip 20 is located higher (closer to the first surface) than the position of the pad layer 22 connected to the bumps 25 formed in the relatively thicker portions of the second chip 20. That is, in these examples, the bumps 25 formed in the thinner portions of the second chip 20 are connected to the first pad layer 22A1 of the pad layer 22 located above the first chip 10, and the bumps 25 formed in the thicker portions of the second chip 20 are connected to the second pad layer 22A2 located below the first pad layer 22A1.

[0055] (External connection terminal) 1, the first chip 10 may be provided with external connection terminals 35 for connecting to other devices different from the semiconductor device 1. However, this does not prohibit the semiconductor device 1 from being provided with the external connection terminals 35.

[0056] [1-2 Manufacturing method] Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 4 to 6. Here, the description will continue using the semiconductor device 1 shown in FIG. 2 as an example. For the sake of convenience, description and explanation of the steps related to the formation of the display unit 11 will be omitted. The display unit 11 will be omitted from FIGS. 4 to 6. The same applies to FIGS. 7 to 15.

[0057] A substrate 15 is prepared (FIG. 4A), an element isolation layer 18 is embedded on the first surface side of the substrate 15, and then a semiconductor element 16 is formed (FIGS. 4B and 4C). The steps of forming the element isolation layer 18 and the semiconductor element 16 may be performed by appropriately using, for example, a general method for forming a semiconductor element.

[0058] As shown in FIG. 4D , a layer 113 is provided on the first surface of the substrate 15 to form the insulating layer 13 so as to cover the semiconductor element 16. The layer 113 is formed from a material that forms the insulating layer 13. Then, a step of forming contact wiring 23 and a step of forming the wiring layer 12 are performed. Furthermore, a step of forming the layer 113 so as to cover the wiring layer 12, a step of forming vias 24, and a step of forming the wiring layer 12 are performed. By sequentially performing the steps of forming the layer 113, forming the vias 24, and forming the wiring layer 12, a state is formed in which the wiring layers 12 are stacked with the layers 113 interposed between them, as shown in FIG. 4D . FIG. 4D shows a state in which three layers 113 and three layers of wiring layers 12 have been formed, starting from the position closest to the substrate 15.

[0059] Furthermore, the steps of forming layer 113, forming via 24, and forming wiring layer 12 are repeatedly performed. By performing the steps of forming layer 113 and wiring layer 12 and the step of forming via 24 in this manner, the wiring layer 12 is formed up to the position farthest from substrate 15 (the uppermost position (the position on the first surface side)). In the example of FIG. 5A, a state in which six layers 113 and five wiring layers 12 are formed is formed. At this time, insulating layer 13 is formed by a plurality of layers 113, and a multilayer wiring section 17 is formed by insulating layer 13 and a plurality of wiring layers 12. After the multilayer wiring section 17 is formed, a pad opening 26 is formed above the position of pad layer 22, as shown in FIG. 5B. In this way, the first chip 10 is formed. Note that the steps of forming contact wiring 23, forming layer 113, forming wiring layer 12, forming via 24, and forming pad opening 26 may all be performed by using, for example, a method used in a general semiconductor chip formation method.

[0060] As shown in FIG. 6, an anisotropic conductive film 30 is provided on the first chip 10 so as to cover its first surface side (the surface side on which the pad openings 26 are formed in FIG. 6). Furthermore, the second chip 20 is placed on the first surface side of the anisotropic conductive film 30. At this time, the second chip 20 is positioned so that the bumps 25 of the second chip 20 and the pad layer 22 of the first chip 10 face each other with the anisotropic conductive film 30 sandwiched between them. Then, a pressure-bonding process is carried out. The pressure-bonding process can be carried out, for example, by applying a pressure from the second chip 20 to the first chip 10 in the direction of arrow P (pressure-bonding direction). In the pressure-bonding process, the second chip 20 and the first chip 10 are pressure-bonded with the anisotropic conductive film 30 sandwiched between them. In this way, the semiconductor device 1 is obtained.

[0061] [1-3 Actions and Effects] In conventional semiconductor devices, when a connection structure is formed in which a conductive portion is electrically connected to the pad layer of a first chip by pressing a second chip onto the first chip, there is a need to prevent poor electrical connection between the pad layer and the conductive portion.

[0062] In particular, in the manufacturing process of a semiconductor device, a polishing process of the second chip may be performed. The polishing process may result in uneven thickness of the second chip. If the thickness of the second chip is uneven, the pressure applied from the second chip to the first chip during the pressure-bonding process may vary. In this case, the resulting semiconductor device may have uneven connection strength with the first chip depending on the position within the second chip.

[0063] Therefore, there is a need for technology that can make connection structures that electrically connect the conductive portions of the second chip and the pad layers of the first chip less likely to cause poor connections, even if variations in the pressure applied from the second chip to the first chip occur due to various factors such as uneven thickness of the second chip.

[0064] In the semiconductor device 1 according to the first embodiment, as shown in FIG. 7 , a connection structure 33 is formed that electrically connects the conductive portions (bumps 25) of the second chip 20 and the pad layer 22 of the first chip 10, and the pad layer 22 is formed in a plurality of different wiring layers 12. Therefore, in the first embodiment, there are a plurality of positions of the pad layer 22. According to the first embodiment, for example, when there are portions where the second chip 20 applies a pressing force F1 to the first chip 10 and portions where the pressing force F2 is applied from the second chip 20, the position of the pad layer 22 in the portion of the first chip 10 where the pressing force F1 larger than the pressing force F2 is applied can be set lower (to the −Z side) than the pad layer 22 in the portion where the pressing force F2 is applied. Therefore, even when there are portions where the second chip 20 applies a pressing force F1 to the first chip 10 and portions where the pressing force F2 is applied from the second chip 20 to the first chip 10, a connection failure can be prevented in the connection structure that electrically connects the conductive portions of the second chip 20 and the pad layer 22 of the first chip 10. Therefore, according to the semiconductor device 1 of the first embodiment, it is possible to prevent connection failures between different chips, that is, the first chip 10 and the second chip 20.

[0065] 8A and 8B, in the semiconductor device 1 according to the first embodiment, when the thickness of the second chip 20 is non-uniform, the position of the pad layer 22 of the first chip 10 can be adjusted according to the thickness of the second chip 20. That is, as shown in FIG. 8B, the position of the pad layer 22 connected to the bumps 25 formed in the portion of the second chip 20 where the thickness is relatively small can be positioned higher than the position of the pad layer 22 connected to the bumps 25 formed in the portion of the second chip 20 where the thickness is relatively large. Therefore, even if the pressing force applied from the second chip to the first chip varies due to the non-uniform thickness of the second chip 20, the connection strength to the first chip 10 can be made roughly uniform regardless of the position within the second chip 20. Thus, according to the semiconductor device 1 of the first embodiment, even if the thickness of the second chip 20 is uneven, poor connection is less likely to occur in the connection structure 33 that electrically connects the bumps 25 of the second chip 20 and the pad layer 22 of the first chip 10.

[0066] Next, a modification of the semiconductor device 1 according to the first embodiment will be described.

[0067] [1-4 Variations] (Variation 1) The first embodiment has been described above using the example of Fig. 2 in which two different wiring layers 12 of the first chip 10 have pad layers 22. The first embodiment is not limited to this example, and as shown in Fig. 9, three or more different wiring layers 12 may have pad layers 22 (this form is called Modification 1). Fig. 9 is a diagram for explaining one example of a semiconductor device 1 according to Modification 1 of the first embodiment.

[0068] 9, from the first surface side to the second surface side, the first wiring layer 12A1, the second wiring layer 12A2, and the third wiring layer 12A3 have pad layers 22 (first pad layer 22A1, second pad layer 22A2, and third pad layer 22A3) in this order. The pad layers 22 provided on these three wiring layers 12 are electrically connected to the bumps 25 of the second chip 20.

[0069] According to the semiconductor device 1 of variant example 1, even if the variation in the pressing force applied from the second chip 20 to the first chip 10 increases, poor connection is less likely to occur in the connection structure 33 that electrically connects the bumps 25 of the second chip 20 and the pad layer 22 of the first chip 10.

[0070] (Variation 2) The above description of the semiconductor device 1 according to the first embodiment has been given in the case where, among the wiring layers 12 of the first chip 10, a wiring layer 12 without a pad layer 22 is not interposed between different wiring layers 12 having pad layers 22. The first embodiment is not limited to this. In the first embodiment, as shown in FIG. 10 , a wiring layer 12 without a pad layer 22 may be interposed between different wiring layers 12 having pad layers 22 (this form is referred to as Modification 2). FIG. 10 is a diagram for explaining an example of the semiconductor device 1 according to Modification 2 of the first embodiment. Note that, for convenience of explanation, the anisotropic conductive film 30 and the second chip 20 are omitted from FIG. 10 .

[0071] In the semiconductor device 1 shown in the example of FIG. 10, from the first surface side toward the second surface side, the first wiring layer 12A1 and the third wiring layer 12A3 have pad layers 22 in this order. The pad layers 22 provided on each of these wiring layers 12 are electrically connected to bumps 25 of the second chip 20. The pad layer 22 is not formed on the second wiring layer 12A2 interposed between the first wiring layer 12A1 and the third wiring layer 12A3. Note that the example of FIG. 10 is just one example, and two or more wiring layers 12 without pad layers 22 may be formed between different wiring layers 12 having pad layers 22.

[0072] According to the semiconductor device 1 of the second modification, the same effects as those of the first modification can be obtained.

[0073] Next, a semiconductor device according to a second embodiment will be described.

[0074] [2 Second embodiment] [2-1 Configuration of semiconductor device] The semiconductor device 1 according to the second embodiment has a plurality of second chips 20 mounted on a first chip 10. As for other configurations, the semiconductor device 1 according to the second embodiment may be formed in the same manner as the semiconductor device 1 according to the first embodiment. Therefore, a description of other configurations will be omitted.

[0075] (Second chip) In the semiconductor device 1 according to the second embodiment, the mounting positions of the multiple second chips 20 on the first chip 10 are not particularly limited, but it is preferable that they are arranged in the outer region 100B described in the first embodiment.

[0076] The number of second chips 20 is not particularly limited. For example, as shown in FIG. 11A, two second chips 20A and 20B may be mounted on the first chip 10. Alternatively, as shown in FIG. 11B, three second chips 20A, 20B, and 20C may be mounted on the first chip 10. In the examples of FIGS. 11A and 11B, the second chip 20 is provided on the display surface D side. FIGS. 11A and 11B are plan views for explaining an example of a semiconductor device 1 according to the second embodiment. For convenience of explanation, the external connection terminals 35 and the display unit 11 are omitted in FIGS. 11A and 11B. In this specification, when the second chips 20A, 20B, and 20C are not particularly distinguished from each other, they are referred to as the second chips 20.

[0077] The shape of each of the multiple second chips 20 is not particularly limited. The multiple second chips 20 may have the same shape or different shapes. The functions of the multiple second chips 20 may be the same or different. The bumps 25 provided on the multiple second chips 20 may have the same shape or different shapes. In the example of FIG. 11A , the shape of the bumps 25 provided on the second chip 20A and the shape of the bumps 25 provided on the second chip 20B may be the same or different. The same applies to the size and material of the bumps 25. Furthermore, if the thickness of each of the multiple second chips 20 is non-uniform, the state of thickness variation may differ among the multiple second chips 20.

[0078] (Connection structure) In the semiconductor device 1 according to the second embodiment, a connection structure 33 is formed corresponding to each of the second chips. For example, in the example of Fig. 11A, the bumps 25 of the second chip 20A are connected to the pad layer 22 formed on the portion of the first chip 10 corresponding to the second chip 20A. The bumps 25 of the second chip 20B are connected to the pad layer 22 formed on the portion of the first chip 10 corresponding to the second chip 20B. That is, in the semiconductor device 1, a connection structure 33 is formed between the second chip 20A and the first chip 10, and a connection structure 33 is formed between the second chip 20B and the first chip 10.

[0079] The pad layer 22 of the first chip 10 is determined according to the second chip 20 having bumps 25 connected to the pad layer 22. Therefore, when comparing connection structures 33 corresponding to different second chips 20, the sizes of the pad layers 22 forming the connection structures 33 may be different from each other. For example, in the example of FIG. 11A , when comparing the size of the pad layer 22 of the first chip 10 in the connection structure 33 corresponding to the second chip 20A with the size of the pad layer 22 of the first chip 10 in the connection structure 33 corresponding to the second chip 20B, the sizes of the pad layers 22 may be different from each other. The same applies to the shape and material of the pad layer 22.

[0080] Furthermore, when comparing connection structures 33 corresponding to different second chips 20, the combinations of the multiple wiring layers 12 having the pad layers 22 forming the connection structures 33 may be different from each other. Specifically, for example, in the example of FIG. 11A , the portion of the first chip 10 where the pad layers 22 forming the connection structure 33 corresponding to the second chip 20A are arranged may have the structure shown in FIG. 2 described in the first embodiment, and the portion where the pad layers 22 forming the connection structure 33 corresponding to the second chip 20B are arranged may have the structure shown in FIG. 10 described in the first embodiment. In this case, the pad layers 22 in the connection structure 33 corresponding to the second chip 20A are formed on the first wiring layer 12A1 and the second wiring layer 12A2. The combination of the multiple wiring layers 12 having the pad layers 22 forming the connection structure 33 corresponding to the second chip 20A is the first wiring layer 12A1 and the second wiring layer 12A2. Furthermore, pad layer 22 in connection structure 33 corresponding to second chip 20B is formed on first wiring layer 12A1 and third wiring layer 12A3. The combination of multiple wiring layers 12 having pad layer 22 forming connection structure 33 corresponding to second chip 20B is first wiring layer 12A1 and third wiring layer 12A3, which is different from the combination of first wiring layer 12A1 and second wiring layer 12A2.

[0081] [2-2 Actions and Effects] In the semiconductor device 1 of the second embodiment, even if there is variation in the pressing force applied from the second chip 20 to the first chip 10 when each of the multiple second chips 20 is pressure-bonded to the first chip 10, poor connection is less likely to occur in the connection structure 33 that electrically connects the bumps 25 of the second chip 20 to the pad layer 22 of the first chip 10.

[0082] [3 Third embodiment] [3-1 Configuration of semiconductor device] In the semiconductor device 1 according to the third embodiment, at least one of the sizes of the plurality of pad layers 22 provided on the first chip 10 and the sizes of the plurality of bumps 25 provided on the second chip 20 is non-uniform. As for other configurations, the semiconductor device 1 according to the third embodiment may be formed in the same manner as the semiconductor device 1 according to the first or second embodiment. Therefore, a description of the other configurations will be omitted.

[0083] (Pad layer) In the semiconductor device 1 according to the third embodiment, the sizes of the pad layers 22 of the first chip 10 may vary as shown in FIG. 12 when comparing the sizes of the pad layers 22 formed on different wiring layers 12. The sizes of the pad layers 22 may also vary corresponding to the difference in the size of the bumps on the second chip 20. In the example of FIG. 12, the sizes of the pad layers 22 vary corresponding to the difference in the wiring layers 12 on which the pad layers 22 are formed and the difference in the size of the bumps 25 on the second chip 20. That is, the size of the third pad layer 22A3 is larger than the sizes of the first pad layer 22A1 and the second pad layer 22A2. FIG. 12 is a bottom view illustrating an example of the second chip 20 in the semiconductor device 1 according to the third embodiment.

[0084] (bump) In the semiconductor device 1 according to the third embodiment, the sizes of the plurality of bumps 25 formed on the second chip 20 may vary as shown in FIG.

[0085] 12, similarly to the semiconductor device 1 according to the first modification of the first embodiment, the first wiring layer 12A1, the second wiring layer 12A2, and the third wiring layer 12A3 have pad layers 22 (first pad layer 22A1, second pad layer 22A2, and third pad layer 22A3, respectively) arranged in this order from the first surface side to the second surface side. The pad layers 22 provided on these three wiring layers 12 are electrically connected to the bumps 25 of the second chip 20.

[0086] The size of the bumps 25 connected to the third pad layer 22A3 is larger than the sizes of the bumps 25 connected to the first pad layer 22A1 and the second pad layer 22A2.

[0087] (2nd chip thickness and bump size) When the thickness of the second chip 20 is non-uniform, the size of the bumps 25 of the second chip 20 may vary depending on the thickness of the second chip 20, as shown in FIGS. 13A and 13B. In the example of FIG. 13A, the thickness of the second chip 20 near the end portions 27 of the second chip 20 is smaller than the thickness of the second chip 20 near the central portion 28 of the second chip 20. The size of the bumps 25 formed near the end portions 27 of the second chip 20 is larger than the size of the bumps 25 formed near the central portion 28 of the second chip 20. In this case, the proportion of the area occupied by the bumps 25 in the unit region RU defined near the end portions 27 is higher than the proportion in the unit region RU defined in the central portion 28.

[0088] The sizes of the plurality of pad layers 22 of the first chip 10 may also vary in accordance with the variation in size of the bumps 25 corresponding to the difference in thickness of the second chip 20.

[0089] [3-2 Actions and Effects] In the semiconductor device 1 according to the third embodiment, the same effects as those of the semiconductor device 1 according to the first embodiment can be obtained.

[0090] [4 Fourth embodiment] [4-1 Configuration of semiconductor device] The semiconductor device 1 according to the fourth embodiment has the configuration of any one of the first to third embodiments described above. Furthermore, in the semiconductor device 1 according to the fourth embodiment, as shown in FIG. 14 , at least some of the pad layers 22 are arranged vertically with an insulating layer 13 interposed therebetween, and the vertically arranged pad layers 22 form a pad structure 34 in which the pad layers 22 are electrically connected to each other. In FIG. 14 , the pad structure 34 is shown as a portion surrounded by a dashed line. FIG. 14 is a cross-sectional view for explaining an example of the semiconductor device according to the fourth embodiment. Note that in the description of the fourth embodiment, description of the same configuration as the semiconductor device 1 according to the first or second embodiment will be omitted. Note that for convenience of explanation, the anisotropic conductive film 30 and the second chip 20 will be omitted in FIG. 14 , as described above with reference to FIG. 10 .

[0091] (Pad structure) In the semiconductor device 1 according to the fourth embodiment, for at least a part of the pad layer 22 connected to the bumps 25 of the second chip 20 to be connected, another pad layer 22 is formed below the pad layer 22 so as to be aligned in the vertical direction. Therefore, in the first chip 10, a pad layer 22 that does not face the bumps 25 of the second chip 20 is formed below the pad layer 22 that faces the bumps 25 of the second chip 20.

[0092] 14, a first pad layer 22A1 formed on the first wiring layer 12A1 and a second pad layer 22A2 formed on the second wiring layer 12A2 are formed as pad layers 22 facing the bumps 25 of the second chip 20. Below the first pad layer 22A1, a pad layer 22B1 formed on the second wiring layer 12A2 and a pad layer 22C1 formed on the third wiring layer 12A3 are formed as pad layers 22 not facing the bumps 25, and are aligned vertically. The first pad layer 22A1, pad layer 22B1, and pad layer 22C1 are electrically connected to each other by vias 24. In this case, the first pad layer 22A1, pad layer 22B1, and pad layer 22C1 electrically connected to each other by vias 24 form a pad structure 34.

[0093] Additionally, below the second pad layer 22A2 formed on the second wiring layer 12A2, a pad layer 22B2 formed on the third wiring layer 12A3 as a pad layer 22 that does not face the bump 25 is formed so as to be aligned in the vertical direction. The second pad layer 22A2 and the pad layer 22B2 are electrically connected to each other by vias 24. In this case, the second pad layer 22A2 and the pad layer 22B2 electrically connected to each other by vias 24 form a pad structure 34.

[0094] [4-2 Actions and Effects] The semiconductor device 1 according to the fourth embodiment can achieve the same effects as the semiconductor device according to the first embodiment. Moreover, in the pad structure 34, the pad layers 22 have a hierarchical structure, and the function of the pad layers 22 connected to the bumps 25 can be exhibited by the entire pad structure 34, and the characteristics of the pad layers 22 as connection terminals can be stabilized.

[0095] [5 Application Examples] (electronic equipment) The semiconductor device according to the present disclosure may be provided in various electronic devices. For example, the semiconductor device 1 according to the above-described embodiment (any one of the first to fourth embodiments) may be provided in various electronic devices. The semiconductor device 1 according to the above-described embodiment is preferably provided in devices that require high resolution and are used in close proximity to the eyes for magnification, such as electronic viewfinders for video cameras and single-lens reflex cameras, or head-mounted displays.

[0096] (Example 1) Fig. 16A is a front view showing an example of the appearance of digital still camera 310. Fig. 16B is a rear view showing an example of the appearance of digital still camera 310. This digital still camera 310 is an interchangeable lens single-lens reflex type, and has an interchangeable taking lens unit (interchangeable lens) 312 located approximately in the center of the front of camera main body 311, and a grip part 313 on the left side of the front for the photographer to hold.

[0097] A monitor 314 is provided at a position shifted to the left from the center of the back of the camera body 311. An electronic viewfinder (eyepiece window) 315 is provided above the monitor 314. By looking through the electronic viewfinder 315, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 312 and determine the composition. Any of the semiconductor devices 1 according to the above-described embodiment and modifications can be used as the electronic viewfinder 315.

[0098] (Example 2) 17 is a perspective view showing an example of the appearance of a head-mounted display 320. The head-mounted display 320 has, for example, ear hooks 322 on both sides of a glasses-shaped display unit 321 for wearing on the user's head. As the display unit 321, any of the semiconductor devices 1 according to the above-described embodiment and modifications can be used.

[0099] (Example 3) 18 is a perspective view showing an example of the appearance of a television device 330. This television device 330 has, for example, an image display screen unit 331 including a front panel 332 and a filter glass 333, and this image display screen unit 331 is configured by any one of the semiconductor devices 1 according to the above-described embodiment and modifications.

[0100] [6 Examples of other devices] The semiconductor device according to the present disclosure has been described in detail in the above first to fourth embodiments and modifications, taking as an example a case where the semiconductor device is used as a display device. The semiconductor device according to the present disclosure is not limited to a display device and may be used as other devices. Examples of other devices include a logic device and an imaging device. Even when the semiconductor device according to the present disclosure is used as a logic device or an imaging device, the configurations shown in the above first to fourth embodiments and modifications can be adopted.

[0101] However, if the semiconductor device 1 is a device other than a display device, the display unit 11 of the first chip 10 is changed to a part corresponding to the semiconductor device. For example, if the semiconductor device is an imaging device, the first chip 10 has an imaging unit formed thereon instead of the display unit 11. The imaging unit can be formed by mounting an image sensor or the like on the first chip 10. An example of the image sensor is a CMOS image sensor. For example, a CMOS image sensor has a configuration in which a large number of imaging elements are arranged in a sensor region defined on a substrate, and the imaging elements are electrically connected to a drive substrate. Note that, similar to the description of the case in which the semiconductor device is a display device, a chip or the like equipped with a circuit (such as a driver IC) for driving and controlling these imaging elements is mounted as the second chip 20. For other configurations (such as the position of the pad layer 22), the details described in the first to fourth embodiments can be applied.

[0102] The above has specifically described embodiments of the present disclosure, their variations, and examples of manufacturing methods thereof, but the present disclosure is not limited to the above-described embodiments, variations, and examples of manufacturing methods, and various modifications based on the technical ideas of the present disclosure are possible.

[0103] For example, the configurations, methods, steps, shapes, materials, and numerical values, etc., given in the above-described embodiments, their variations, and examples of their manufacturing methods are merely examples, and different configurations, methods, steps, shapes, materials, and numerical values, etc., may be used as necessary.

[0104] Furthermore, the configurations, methods, steps, shapes, materials, numerical values, etc. listed in the above-described embodiments, their variations, and examples of their manufacturing methods can be combined with each other as long as they do not deviate from the spirit of this disclosure.

[0105] Unless otherwise specified, the materials exemplified in the above-described embodiments can be used singly or in combination of two or more.

[0106] It should be noted that the contents of the present disclosure should not be construed as being limited to the effects exemplified in the present disclosure.

[0107] The present disclosure may also have the following configurations. (1) a first chip having an insulating layer and a plurality of wiring layers each having a wiring formed inside the insulating layer; at least one second chip mounted on the first chip and having a plurality of conductive portions; the first chip has a plurality of pad layers; a connection structure is formed that electrically connects the pad layer and the conductive portion, the plurality of pad layers are formed on at least the plurality of different wiring layers; Semiconductor device. (2) a resin film containing conductive particles is provided between the first chip and the second chip; the conductive portion is a bump, the connection structure has a structure in which the pad layer and the bump are connected via the conductive particles; The semiconductor device according to (1) above. (3) a difference in vertical position between the uppermost pad layer and the lowermost pad layer is equal to or less than half of the conductive particles; The semiconductor device according to (2) above. (4) The wiring layers each having the pad layer are not interposed with any other wiring layer each having no pad layer. The semiconductor device according to any one of (1) to (3) above. (5) the wiring layers each having the pad layer interposed therebetween are the wiring layers each having the pad layer; The semiconductor device according to any one of (1) to (3) above. (6) At least some of the pad layers are arranged in a vertical direction with the insulating layer interposed therebetween, and the vertically arranged pad layers form a pad structure in which the pad layers are electrically connected to each other. The semiconductor device according to any one of (1) to (5) above. (7) The pad layers formed on different wiring layers have different sizes. The semiconductor device according to any one of (1) to (6) above. (8) A plurality of the second chips are mounted on the first chip. The semiconductor device according to any one of (1) to (7) above. (9) the connection structures are formed corresponding to the respective second chips, When the connection structures corresponding to different second chips are compared, the sizes of the pad layers forming the connection structures are different from each other. The semiconductor device according to (8) above. (10) the connection structures are formed corresponding to the respective second chips, When the connection structures corresponding to different second chips are compared, the combinations of the plurality of wiring layers having the pad layers forming the connection structures are different from each other. The semiconductor device according to (8) or (9) above. (11) The thickness of the second chip is non-uniform. The semiconductor device according to any one of (1) to (10) above. (12) The conductive portions are formed in the second chip such that the density of the conductive portions formed in the portions of the second chip where the thickness is relatively large is lower than the density of the conductive portions formed in the portions of the second chip where the thickness is relatively small. The semiconductor device according to (11) above. (13) the conductive portion formed in the portion of the second chip where the thickness is relatively large and the conductive portion formed in the portion of the second chip where the thickness is relatively small are connected to the pad layers formed in the wiring layers different from each other; The semiconductor device according to (11) or (12) above. (14) a position of the pad layer connected to the conductive portion formed in the portion of the second chip where the thickness is relatively small is located above a position of the pad layer connected to the conductive portion formed in the portion of the second chip where the thickness is relatively large; The semiconductor device according to (11) or (12) above. (15) the first chip includes a silicon substrate and has the insulating layer and the wiring layer on the silicon substrate; The semiconductor device according to any one of (1) to (14) above. (16) Used as a display device, The semiconductor device according to any one of (1) to (15) above. (17) Using the semiconductor device according to any one of (1) to (16) above, electronic equipment. [Explanation of symbols]

[0108] 1: Semiconductor device 10: First chip 11:Display section 12: Wiring layer 13: Insulating layer 14: Drive board 15: Circuit board 16: Semiconductor elements 17:Multilayer wiring section 18: Element isolation layer 19: Sidewall oxide film 20: Second chip 22: Pad layer 23: Contact wiring 24: Beer 25: Bump 26: Pad opening 27: Edge 28: Central part 30: Anisotropic conductive film 31: Conductive particles 32: BG tape 33: Connection structure 34: Pad structure 35: External connection terminal 36: Suction part 37: Polishing section 113: layer 120: Wiring 125: Bumps RU: unit area

Claims

1. a first chip having an insulating layer and a plurality of wiring layers each having wiring formed inside the insulating layer; at least one second chip mounted on the first chip and having a plurality of conductive portions; the first chip has a plurality of pad layers; a connection structure is formed that electrically connects the pad layer and the conductive portion, the plurality of pad layers are formed on at least the plurality of different wiring layers, a resin film containing conductive particles is provided between the first chip and the second chip; the conductive portion is a bump, the connection structure has a structure in which the pad layer and the bump are connected via the conductive particles; Semiconductor device.

2. a difference in vertical position between the uppermost pad layer and the lowermost pad layer is equal to or less than half of the conductive particles; The semiconductor device according to claim 1 .

3. The wiring layers each having the pad layer are not interposed with any other wiring layer each having no pad layer. The semiconductor device according to claim 1 .

4. the wiring layers each having the pad layer interposed therebetween are the wiring layers each having the pad layer; The semiconductor device according to claim 1 .

5. At least some of the pad layers are arranged in a vertical direction with the insulating layer interposed therebetween, and the vertically arranged pad layers form a pad structure in which the pad layers are electrically connected to each other. The semiconductor device according to claim 1 .

6. The pad layers formed on different wiring layers have different sizes. The semiconductor device according to claim 1 .

7. A plurality of the second chips are mounted on the first chip. The semiconductor device according to claim 1 .

8. the connection structures are formed corresponding to the respective second chips, When the connection structures corresponding to different second chips are compared, the sizes of the pad layers forming the connection structures are different from each other. The semiconductor device according to claim 7 .

9. the connection structures are formed corresponding to the respective second chips, When the connection structures corresponding to different second chips are compared, the combinations of the plurality of wiring layers having the pad layers forming the connection structures are different from each other. The semiconductor device according to claim 7 .

10. the thickness of the second chip is non-uniform; The semiconductor device according to claim 1 .

11. the second chip has the conductive portions formed thereon such that the density of the conductive portions formed in the portions of the second chip where the thickness is relatively large is lower than the density of the conductive portions formed in the portions of the second chip where the thickness is relatively small; The semiconductor device according to claim 10.

12. the conductive portion formed in the portion of the second chip where the thickness is relatively large and the conductive portion formed in the portion of the second chip where the thickness is relatively small are connected to the pad layers formed in the wiring layers different from each other; The semiconductor device according to claim 10.

13. a position of the pad layer connected to the conductive portion formed in the portion of the second chip where the thickness is relatively small is located higher than a position of the pad layer connected to the conductive portion formed in the portion of the second chip where the thickness is relatively large; The semiconductor device according to claim 10.

14. the first chip includes a silicon substrate, and has the insulating layer and the wiring layer on the silicon substrate; The semiconductor device according to claim 1 .

15. Used as a display device, The semiconductor device according to claim 1 .

16. A semiconductor device according to claim 1 is used. electronic equipment.

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