Silicon carbide semiconductor device

Abstract

To improve the performance of a SiC power MISFET having, as a channel region, the side surface of a trench formed in the upper surface of a silicon carbide semiconductor substrate.SOLUTION: A silicon carbide semiconductor device includes a trench 9 formed on the upper surface of a silicon carbide semiconductor substrate, a gate electrode 2 in the trench 9, an n-type drift layer 4, a p-type guard region 8, an n-type semiconductor region 6c to which a source potential is applied, which are formed in this order from the lower surface to the upper surface in the silicon carbide semiconductor substrate, a p-type body layer 5 and an n-type current diffusion region 7 having an impurity concentration lower than that of the guard region 8, and an n-type JFET region 13 formed in the silicon carbide semiconductor substrate at a distance from the trench 9 and connecting the current diffusion region 7 and the drift layer 4, and the semiconductor region 6c is separated from the drift layer 4, the current diffusion region 7, and the JFET region 13, and the semiconductor region 6c, the body layer 5, and the current diffusion region 7 adjacent to the first side surface of the trench 9 in a plan view overlap each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device, which is a power semiconductor device, and particularly to one having a trench structure. [Background technology]

[0002] In the power metal insulator semiconductor field effect transistor (MISFET), which is one type of power semiconductor device, power MISFETs using silicon (Si) substrates (hereinafter referred to as Si power MISFETs) have traditionally been mainstream.

[0003] However, power MISFETs (hereinafter referred to as SiC power MISFETs) using silicon carbide (SiC) substrates (hereinafter referred to as SiC substrates) are capable of achieving higher breakdown voltages and lower losses compared to Si power MISFETs. For this reason, SiC power MISFETs are attracting particular attention in the field of power-saving or environmentally friendly inverter technology.

[0004] Compared to Si power MISFETs, SiC power MISFETs can achieve lower on-resistance at the same breakdown voltage. This is because silicon carbide (SiC) has a dielectric breakdown field strength approximately seven times greater than that of silicon (Si), allowing the epitaxial layer that serves as the drift layer to be made thinner.

[0005] Patent Document 1 (JP 2012-44167 A) describes a MOSFET in which a source region is formed in contact with the bottom of a trench in which a gate electrode is buried, and a channel through which current flows from top to bottom is formed near the side surface of the trench. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-44167 Summary of the Invention [Problem to be solved by the invention]

[0007] In a FIN-type trench-gate MOSFET in which gate electrodes are embedded in multiple trenches formed on the upper surface of a semiconductor substrate, a channel is formed along the side surface of the trench, and current flows laterally through the channel. In this case, the channel width (gate width) can only be expanded within a narrow range, making it difficult to improve the performance of silicon carbide semiconductor devices. Furthermore, such MOSFETs have problems such as a tendency for the electric field to concentrate near the upper corners of the trench and for the channel length to vary. Furthermore, the need to form deep trenches also leads to problems such as a tendency for the electric field to increase and low short-circuit resistance.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A brief summary of a representative embodiment of the present invention will be given below.

[0010] a gate electrode formed in the trench via an insulating film; and a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type different from the first conductivity type, the second semiconductor region being in contact with a first side surface of the trench and receiving a source potential, the gate electrode being formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. The gate electrode is formed in the trench via an insulating film. the fourth semiconductor region of the second conductivity type in contact with the first side surface and having a lower impurity concentration than the second semiconductor region, the fifth semiconductor region of the first conductivity type in contact with the first side surface of the trench, and a sixth semiconductor region of the first conductivity type formed in the silicon carbide semiconductor substrate at a distance from the trench and connecting the fifth semiconductor region and the first semiconductor region, the third semiconductor region being spaced apart from the first semiconductor region, the fifth semiconductor region, and the sixth semiconductor region, the gate electrode, and the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region adjacent to the first side surface of the trench and overlapping each other in a planar view constitute a field effect transistor, and a channel of the field effect transistor is generated between the third semiconductor region and the fifth semiconductor region in the fourth semiconductor region in contact with the first side surface of the trench. [Effects of the Invention]

[0011] The effects obtained by the representative inventions disclosed in this application will be briefly explained as follows.

[0012] According to the present invention, the performance of a silicon carbide semiconductor device can be improved. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment; [Figure 2] 1 is a plan view showing a silicon carbide semiconductor device according to an embodiment; [Figure 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. [Figure 4] FIG. 3 is a cross-sectional view taken along line BB in FIG. 2. [Figure 5] 3 is a plan view showing the silicon carbide semiconductor device taken along line CC in FIG. 2. FIG. [Figure 6] 1A and 1B are a plan view and a cross-sectional view showing a plurality of unit cells of a silicon carbide semiconductor device according to an embodiment of the present invention; [Figure 7] FIG. 1 is a plan view showing a silicon carbide semiconductor device according to a first modified example of the embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line AA in FIG. 7. [Figure 9] FIG. 8 is a cross-sectional view taken along line DD in FIG. [Figure 10] 9 is a plan view showing the silicon carbide semiconductor device taken along line CC in FIG. 8. FIG. [Figure 11] FIG. 10 is a plan view showing a silicon carbide semiconductor device according to a second modification of the embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line AA in FIG. [Figure 13] FIG. 12 is a cross-sectional view taken along line DD in FIG. [Figure 14] 13 is a plan view showing the silicon carbide semiconductor device taken along line CC in FIG. 12. FIG. [Figure 15] 11A and 11B are a plan view and a cross-sectional view showing a plurality of unit cells of a silicon carbide semiconductor device according to a third modification of the embodiment. [Figure 16] 13A and 13B are a plan view and a cross-sectional view showing a plurality of unit cells of a silicon carbide semiconductor device according to a fourth modification of the embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing a plurality of unit cells of a silicon carbide semiconductor device according to a fifth modification of the embodiment. [Figure 18] FIG. 11 is a cross-sectional view showing a plurality of unit cells of a silicon carbide semiconductor device according to a third modification of the embodiment. [Figure 19] FIG. 11 is a plan view showing a plurality of unit cells of a silicon carbide semiconductor device according to a third modification of the embodiment. [Figure 20] FIG. 13 is a cross-sectional view showing a plurality of unit cells of a silicon carbide semiconductor device according to a sixth modification of the embodiment. [Figure 21] FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to a first comparative example. [Figure 22] FIG. 10 is a cross-sectional view showing a silicon carbide semiconductor device according to Comparative Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. Furthermore, in the following embodiments, explanations of identical or similar parts will not be repeated unless specifically required. Furthermore, in the drawings for explaining the embodiments, hatching may be used even in plan views or perspective views to make the configuration easier to understand. Furthermore, in the drawings for explaining the embodiments, hatching may be omitted in cross-sectional views to make the configuration easier to understand.

[0015] Also," - " and " + " is a symbol that indicates the relative impurity concentration of n-type or p-type conductivity. For example, "n -- "," "n - "," "n," "n + "," "n ++ The concentration of n-type impurities increases in this order.

[0016] (Embodiment) Hereinafter, a silicon carbide semiconductor device will be described with reference to the drawings, using as an example a SiC power MISFET (Metal Insulator Semiconductor Field Effect Transistor), i.e., a trench-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which has a semiconductor layer in contact with the side surface of a trench (groove, recess) as a channel region.

[0017] <Structure of Silicon Carbide Semiconductor Device> The structure of a silicon carbide semiconductor device according to this embodiment will be described with reference to FIGS. 1 to 6. FIG. 1 shows a simplified cross-sectional view of the silicon carbide semiconductor device according to this embodiment, and FIGS. 2 to 6 show a more specific configuration of the silicon carbide semiconductor device. In FIG. 2, the structure on the semiconductor substrate is shown only by a contact plug connected to a source potential, with dashed lines, and other structures on the semiconductor substrate, such as an insulating film (interlayer insulating film) and a gate electrode, are not shown. In addition, in each cross-sectional view, the outlines of multiple trenches that are not included in the cross section and exist in the depth direction (Y direction) of the figure are shown by dashed lines. In addition, in FIG. 2, the gate electrodes in the trenches and the insulating film covering the bottom surfaces of the trenches are not shown, and the structure in the semiconductor substrate below them is shown transparently. This is also true for other plan views.

[0018] As shown in Fig. 2, the silicon carbide semiconductor device of this embodiment has an n-type silicon carbide (SiC) epitaxial substrate (silicon carbide semiconductor substrate, hereinafter referred to as semiconductor substrate) having an upper surface (first main surface) and an opposite lower surface (back surface, second main surface). + A silicon carbide substrate and an n-type silicon carbide film formed on the silicon carbide substrate by epitaxial growth. - The epitaxial layer is a semiconductor layer containing SiC. In each drawing of the present application, the n-type epitaxial layer is mainly composed of - The drift layer 4 is a semiconductor region of n-type. +1 shows a drain region 12 formed of a silicon carbide substrate of a type semiconductor region. That is, the portion shown as the drain region 12 in each drawing is a silicon carbide substrate.

[0019] That is, a drain region 12 is formed in the semiconductor substrate at a predetermined depth from the bottom surface, and a drift layer 4 is formed in the semiconductor substrate above (on the upper surface side of) the drain region 12 in contact with the drain region 12. The n-type impurity concentration of the drain region 12 is higher than the n-type impurity concentration of the drift layer 4. The drift layer 4, body layer 5, source region 6a, semiconductor regions 6b and 6c, current diffusion region 7, guard region 8, and JFET region 13 are formed in the epitaxial layer.

[0020] A drain electrode 3 is formed in contact with the lower surface of the drain region 12, i.e., the lower surface of the semiconductor substrate. That is, the lower surface of the semiconductor substrate is covered with the drain electrode 3, and the drain electrode 3 is electrically connected to the drain region 12. The drain electrode 3 is made of a laminated conductor film containing, for example, gold (Au).

[0021] A trench 9 is formed in the upper surface of the semiconductor substrate, reaching partway down into the semiconductor substrate. The trenches 9 extend, for example, in the X direction along the upper surface of the semiconductor substrate, and are arranged in a plurality of rows in the Y direction, which is perpendicular to the X direction in a plan view. The Z direction is the thickness direction of the semiconductor substrate and is a direction (vertical direction, depth direction) perpendicular to both the X direction and the Y direction. The planar shape, cross-sectional shape in the XZ plane, and cross-sectional shape in the YZ plane of the trench 9 are, for example, rectangular. That is, the trench 9 has two side surfaces extending along the X direction. Here, one of the two side surfaces of the trench 9 extending along the X direction is referred to as a first side surface.

[0022] A gate electrode 2 is buried in each trench 9 via an insulating film 11 (see FIG. 4). The gate electrodes 2 in each trench 9 are connected to each other by the gate electrode 2 extending in the Y direction on the upper surface of the semiconductor substrate. That is, in a cross section along the Y direction, the gate electrode 2 has a comb-like structure. That is, multiple trench gate electrodes lined up in the Y direction are connected in parallel to each other by the gate electrodes 2 above them. The lower surface, side surface, and upper surface of the gate electrode 2 extending in the Y direction on the semiconductor substrate are covered with an insulating film 11. That is, the insulating film 11 includes a gate insulating film formed below the gate electrode 2 extending in the Y direction and an interlayer insulating film formed above the gate insulating film. In a plan view, the semiconductor region 6c, the body layer 5, and the current spreading region 7 that contact the first side surface of the trench 9 overlap each other.

[0023] Formed in the semiconductor substrate, in this order from the bottom surface to the top surface, are a drain region 12, a drift layer 4, a guard region 8, a semiconductor region 6c in contact with the first side surface of the trench 9, a body layer 5 in contact with the first side surface of the trench 9, and a current diffusion region 7 in contact with the top surface of the semiconductor substrate and the first side surface of the trench 9. Also formed in the semiconductor substrate is a JFET (Junction Field Effect Transistor) region 13 spaced apart from the trench 9 and in contact with the side surfaces of the body layer 5 and the guard region 8, the bottom surface of the current diffusion region 7, and the top surface of the drift layer 4. The JFET region is an n-type semiconductor region sandwiched between p-type semiconductor layers, and has a lower n-type impurity concentration than the drain region 12, the current diffusion region 7, the source region 6a, and the semiconductor region 6c. The n-type impurity concentration of the JFET region may be higher than the n-type impurity concentration of the drift layer 4 or may be the same as the n-type impurity concentration of the drift layer 4. The semiconductor region 6c has an n-type impurity concentration of 0.05%. + The guard region 8 is a p + the body layer 5 is a p-type semiconductor region, and the current spreading region 7 is an n-type semiconductor region. + The JFET region 13 is an n-type semiconductor region.

[0024] Moreover, directly above the semiconductor region 6c, a semiconductor region 6b and a source region 6a are formed in this order toward the upper surface of the semiconductor substrate. ++ The source region 6a, which is a type semiconductor region, is in contact with the upper surface of the semiconductor substrate and is formed to a predetermined depth from the upper surface. - The n-type impurity concentration of the semiconductor region 6b, which is a type semiconductor region, is lower than the n-type impurity concentration of the JFET region 13. The source region 6a and the semiconductor region 6b are both in contact with the side surface of the body layer 5 and are separated from the trench 9. The insulating film 11 described above is formed on the upper surface of the semiconductor substrate, and a through-hole (contact hole, connection hole) is formed in the insulating film 11 directly above the source region 6a. A contact plug (conductive connection portion, source contact region) 1 electrically connected to the source electrode is buried in the through-hole. The contact plug 1 is, for example, integrated with a source electrode (not shown) formed on the upper surface of the semiconductor substrate and on the insulating film 11. The lower surface of the source region 6a is in contact with the upper surface of the semiconductor region 6b, and the lower surface of the semiconductor region 6b is in contact with the upper surface of the semiconductor region 6c. The source region 6a, the semiconductor region 6b, and the semiconductor region 6c are all separated from the current spreading region 7, the JFET region 13, the drift layer 4, and the drain region 12. A source potential is applied to the semiconductor region 6c from the source electrode via the contact plug 1, the source region 6a, and the semiconductor region 6b. In other words, the contact plug 1 is a connection portion (source contact region) between the upper surface of the semiconductor substrate and the source electrode.

[0025] The current diffusion region 7 is a low-resistance region that diffuses electrons across the entire width of the JFET region 13 in the X direction when electrons flow from the current diffusion region 7 to the JFET region 13, thereby allowing current to flow in a wide region. In other words, by forming the current diffusion region 7 with a higher n-type impurity concentration than the JFET region, it is possible to prevent current from flowing locally.

[0026] The bottom of the trench 9 terminates halfway into the semiconductor region 6c. Here, the trench 9 does not reach the guard region 8. In other words, the bottom surface of the trench 9 and the top surface of the guard region 8 are spaced apart from each other. One end of the bottom of the trench 9 in the first direction (X direction), i.e., the lower corner, is covered by the semiconductor region 6c. The other end (lower corner) of the bottom of the trench 9 in the first direction is spaced apart from the semiconductor region 6c and is covered by a part of the body layer 5 adjacent to the semiconductor region 6c in the first direction. As described above, a part of the body layer 5 is adjacent to the semiconductor region 6c, but a part of the guard region 8 may also be adjacent to the semiconductor region 6c. In that case, the end (lower corner) of the bottom of the trench 9 on the JFET region 13 side in the first direction is covered by the guard region 8. The bottom surface of the trench 9 may reach a partway into the guard region 8 below the semiconductor region 6c. In that case, the entire bottom of the trench 9 is covered by the guard region 8. The guard region 8 has a higher p-type impurity concentration than the body layer 5. The body layer 5 and the guard region 8 are in contact with each other.

[0027] Furthermore, one end of the upper end of trench 9 in the first direction is covered by the current diffusion region 7, and the other end is spaced apart from the current diffusion region 7 and covered by the body layer 5. One end of the first side surface of trench 9 in the first direction is spaced apart from the current diffusion region 7, and the other end is spaced apart from the semiconductor region 6c.

[0028] The source region 6a, semiconductor region 6b, and semiconductor region 6c constituting the source, the drain region 12 constituting the drain, the drift layer 4, the JFET region 13, and the current diffusion region 7, and the gate electrode 2 constitute a trench MOSFET (a MOS field-effect transistor with a trench gate). When the MOSFET of this embodiment is in an on-state, a channel is formed vertically between the current diffusion region 7 and the semiconductor region 6c directly below it in the body layer 5 adjacent to the side surface of the trench 9. Therefore, current flows through the channel (anti-transfer) in the body layer 5 from the current diffusion region 7 toward the semiconductor region 6c, as shown by the arrow in FIG. 1 .

[0029] 2 to 6, a specific structure of the silicon carbide semiconductor device of this embodiment will be described. The silicon carbide semiconductor device differs from the MOSFET shown in FIG. 1 only in that a potential fixing region (body contact region) 14 for body contact is formed. The potential fixing region 14 serves to supply a source potential to the body layer 5 and the guard region 8 and fix the potentials of the body layer 5 and the guard region 8. ++ It is a type semiconductor region.

[0030] As shown in FIGS. 2 and 3 , the potential clamping region 14 contacts the source region 6 a in the X direction and is separated from the current diffusion region 7 via the body layer 5. The potential clamping region 14 contacts the body layer 5 and a first side surface of the trench 9. The source region 6 a, the potential clamping region 14, the semiconductor regions 6 b and 6 c, the body layer 5, the current diffusion region 7, the JFET region 13, and the guard region 8 extend in the Y direction. A plurality of trenches 9 are arranged in the Y direction, which is the short side direction of the trenches 9. A plate-shaped semiconductor substrate (semiconductor layer) is formed between adjacent trenches 9 in the Y direction. This semiconductor layer (protruding portion) extends in the X direction and has a relatively thin thickness in the Y direction and is called a fin. For this reason, the MOSFET of this embodiment is also called a fin trench MOSFET.

[0031] Here, the region in which the trenches 9 are aligned in the Y direction is referred to as the trench-arrangement region. The source region 6a and the semiconductor region 6b are located on opposite sides of the JFET region 13 in the X direction, with the trench-arrangement region sandwiched between them. Furthermore, the end of the current spreading region 7 in the X direction and the end of the semiconductor region 6c in the X direction overlap with the trench-arrangement region in a plan view, with the other portion of the current spreading region 7 extending from the trench-arrangement region in one direction in the X direction and the other portion of the semiconductor region 6c extending from the trench-arrangement region in the other direction in the X direction. In other words, in a plan view, the current spreading region 7 and the semiconductor region 6c extend in opposite directions, with the trench-arrangement region in between.

[0032] 2, the contact plug 1 extends in the Y direction. In plan view, the contact plug 1 overlaps both the source region 6a and the potential fixing region 14, which are adjacent to each other in the X direction. The bottom surface of the contact plug 1 is connected to both the source region 6a and the potential fixing region 14. A plurality of trenches 9 are formed side by side in a direction parallel to the long sides of the contact plug 1 (Y direction).

[0033] The potential clamping region 14 is formed between the semiconductor region 6c and the first main surface of the semiconductor substrate. One end of the upper end of the trench 9 in the X direction is covered by the current diffusion region 7, and the other end is spaced apart from the current diffusion region 7 and covered by the potential clamping region 14. Impurities constituting the potential clamping region 14 tend to diffuse downward. Therefore, to prevent the semiconductor region 6c from being divided by the potential clamping region 14, the potential clamping region 14 is formed shallow. In other words, the potential clamping region 14 is spaced apart from the upper surface of the semiconductor region 6c.

[0034] 4, a gate electrode 2 is buried in each trench 9 via an insulating film 11. The bottom of the gate electrode 2 is located below the upper surface of the semiconductor region 6c, and the gate electrode 2 is adjacent to the semiconductor region 6c, the body layer 5, and the current spreading region 7 in the Y direction via the insulating film 11.

[0035] 5 shows a plan view of the semiconductor substrate taken along line CC in FIGS. 3 and 4. However, hatching is omitted in FIG. 5. As shown in FIG. 5, island-shaped openings are provided discretely in the Y direction in the semiconductor region 6c, and a body layer 5 is formed in each opening. The body layer 5 is connected at its bottom to the guard region 8. Therefore, a source potential is applied from the potential fixing region 14 to the guard region 8 via the body layer 5.

[0036] 2 to 5 show one unit cell including a drift layer 4, a guard region 8, a source region 6a, semiconductor regions 6b and 6c, a current spreading region 7, a JFET region 13, and a potential clamping region 14. Note that the unit cell in plan view may extend further in the Y direction than the range shown in FIGS. 2 and 5. FIG. 6 shows a structure in which multiple unit cells are arranged in the X direction, and the cell arrangement will be described below. In FIG. 6, a plan view is shown on the upper side, and a cross-sectional view of a portion corresponding to line AA in the plan view is shown on the lower side.

[0037] As shown in FIG. 6, unit cells UC of the MOSFET are arranged in the X direction with their layouts inverted. That is, a plurality of unit cells UC are arranged in the X direction, and unit cells adjacent to each other in the X direction have a plane layout that is line-symmetrical with respect to the boundary line between them. In other words, the structures of unit cells adjacent to each other in the X direction are line-symmetrical in plan view. In this case, unit cells adjacent to each other in the Y direction with the JFET region 13 at the center share one JFET region 13. In other words, in the cross section shown in FIG. 6, one unit cell has 0.5 JFET regions 13 per trench arrangement region. The contact plugs 1 extend in the Y direction along the upper surface of the semiconductor substrate, and a plurality of trenches are arranged in the lateral direction (X direction). A plurality of trenches are discretely arranged in a direction parallel to the long sides of the contact plugs 1 on the upper surface of the semiconductor substrate between the contact plugs 1 adjacent to each other in the lateral direction.

[0038] Here, the JFET region 13 is a region sandwiched between the p-type body layer 5 and the guard region 8. When the MOSFET is in an off state, the JFET region 13 is a region where depletion layers extend from the opposing side surfaces of adjacent p-type semiconductor regions and these depletion layers contact each other.

[0039] When the MOSFET is in the off state, no channel is formed, and no current flows. However, to suppress the minute current between the source and drain during the off state and improve the breakdown voltage, guard regions 8 are provided below trenches 9 and JFET regions 13 are provided next to guard regions 8. By providing guard regions 8, the depletion layer closes within the JFET regions 13 between adjacent guard regions 8 during the MOSFET's off state, blocking the current path between the source and drain. In other words, guard regions 8 connect the depletion layers that form around them between adjacent guard regions 8, thereby suppressing minute currents and improving the breakdown voltage. Therefore, even if the impurity concentration of drift layer 4 is increased to reduce the device's resistance, the breakdown voltage during the off state can be maintained.

[0040] <Effects of this embodiment> 21 shows a cross-sectional view of a trench-gate MOSFET, which is a silicon carbide semiconductor device of Comparative Example 1. As shown in FIG. 21, the MOSFET of Comparative Example 1 has a drain region 12, a drift layer 4, a body layer 5, and a current diffusion region 7, which are formed in this order from the bottom surface side to the top surface side of a semiconductor substrate. A first side surface of trench 9 is adjacent to drift layer 4, body layer 5, and current diffusion region 7, and drift layer 4, body layer 5, and current diffusion region 7 are sandwiched between guard regions 8 spaced apart from trench 9. A gate electrode 2 is buried in trench 9, and a source potential is applied to guard region 8 and current diffusion region 7 from contact plug 1.

[0041] In Comparative Example 1, a channel is formed in the body layer 5 adjacent to the first side surface of the trench 9, and current flows from bottom to top in the channel. In this case, the drift layer 4 sandwiched between the p-type semiconductor regions is considered to function as a JFET region where the depletion layer closes in the off state. However, the region below the bottom of the trench 9 does not have enough length (thickness) to function as a JFET region, and there is a risk that the effects of suppressing minute currents and improving breakdown voltage may not be sufficiently obtained.

[0042] Furthermore, in Comparative Example 1, only the drift layer 4, which is an n-type semiconductor region, exists between the trench 9 and the drain region 12. Therefore, the trench 9 is close to the drain potential, and an electric field concentrates, making it easy for breakdown to occur. However, even if an attempt is made to separate the trench 9 and the drain region 12 by forming the trench 9 shallow, it is difficult to obtain the desired channel length if the trench 9 is too shallow.

[0043] Furthermore, in Comparative Example 1, a channel (parasitic channel) is likely to be formed on the second side surface of trench 9, which is perpendicular to the first side surface. The channel formed on the second side surface has different characteristics from the channel formed on the first side surface due to factors such as the surface orientation of the semiconductor substrate. Therefore, when current flows through both of these channels, the presence of channels with different characteristics causes variations in the characteristics (e.g., threshold voltage) of the MOSFET.

[0044] In contrast, as shown in Comparative Example 2 in Figure 22, it is conceivable to arrange the JFET region 13 beside the trench and ensure its sufficient length, thereby suppressing minute currents and improving breakdown voltage. The structure of the silicon carbide semiconductor device of Comparative Example 2 differs from that of the present embodiment in that the semiconductor region 6c is formed on the upper end side of the trench 9 rather than on the bottom side and is directly connected to the source region 6a. In this case, when the MOSFET is in the on state, a channel is formed in the body layer 5 between the current spreading region 7 and the semiconductor region 6c, along the first side surface of the trench 9, and current flows laterally from the current spreading region 7 side to the semiconductor region 6c side.

[0045] Here, the guard region 8 is interposed between the trench 9 and the drain region 12, so that the electric field concentration at the bottom of the trench 9 due to the drain potential can be alleviated, and dielectric breakdown can be prevented.

[0046] However, while there are two possible methods for widening the channel width in Comparative Example 2: miniaturizing the fins, and deepening the trench 9, current spreading region 7, and semiconductor region 6c, both of these methods are difficult. Therefore, in the MOSFET of Comparative Example 2, the channel width can only be widened within a narrow range, making it difficult to improve the performance of the silicon carbide semiconductor device.

[0047] Furthermore, in Comparative Example 2, a channel (parasitic channel) is also formed near the upper corner of the first side surface of the trench. Because this channel is prone to electric field concentration and has the characteristic of a low threshold voltage, the flow of current through such a channel causes a deterioration in the resistance-threshold voltage trade-off of the MOSFET.

[0048] Furthermore, the MOSFET channel length of Comparative Example 2 is determined by the distance between the current spreading region 7 and the semiconductor region 6c. The current spreading region 7 and the semiconductor region 6c, which are formed by photolithography and ion implantation, are prone to variations in their distance due to factors such as the dimensional spread of the resist mask or misalignment during photolithography. This distance variation is up to approximately ±200 nm. This poses a problem of variations in MOSFET characteristics across the wafer.

[0049] Furthermore, when an abnormally large current flows due to, for example, a short-circuit fault, if the source region 6a and the semiconductor region 6c, which have high impurity concentrations, are in contact with each other, as in Comparative Example 2, there is a risk that short-circuit resistance cannot be ensured because a low-concentration region for dropping the voltage is not inserted.

[0050] In contrast, in this embodiment, the semiconductor region 6c is formed so as to contact the first side surface of the trench 9 directly below the current diffusion region 7. As a result, when the MOSFET is on, a channel is generated vertically in the body layer 5 between the semiconductor region 6c and the current diffusion region 7, and current flows downward from the current diffusion region 7 to the semiconductor region 6c. Therefore, the channel width of the MOSFET can be adjusted by the length of the trench 9 in the first direction (X direction). Therefore, the channel width can be adjusted over a wide range without changing the difficulty of the manufacturing process.

[0051] Furthermore, since a channel is generated between the semiconductor region 6c and the current spreading region 7, which are in contact with the first side surface of the trench 9, no channel exists that passes through the upper ends of the sides of the trench 9. This prevents current from flowing through a channel that has low threshold voltage characteristics. This prevents the resistance-threshold voltage tradeoff of the MOSFET from deteriorating, and allows the threshold voltage to be kept constant.

[0052] The channel length is determined by the distance between the current spreading region 7 and the semiconductor region 6c. The depth variation of the semiconductor region due to ion implantation is easier to control than the lateral variation of the semiconductor region due to misalignment in photolithography. This reduces the variation in channel length across the wafer.

[0053] Furthermore, compared to Comparative Example 1, in this embodiment, the trench 9 only needs to be deep enough so that its side surface contacts the semiconductor region 6c, making it possible to make the trench shallower. As described above, since there is little variation in the spacing between the current spreading region 7 and the semiconductor region 6c formed by photolithography and ion implantation, it is easy to set the depth of the trench 9 shallow. Therefore, the trench 9 can be formed shallow while maintaining high performance. Therefore, the trench 9 is farther away from the drain potential of the drain region 12, reducing the electric field. Furthermore, the guard region 8 formed between the trench 9 and the drain region 12 also reduces the electric field.

[0054] Furthermore, an n-type semiconductor region 6b with a lower impurity concentration than the source region 6a and the semiconductor region 6c is interposed as a source potential supply path between the heavily doped source region 6a and the semiconductor region 6c. By inserting the lightly doped semiconductor region 6b, the voltage of the semiconductor region 6c can be reduced when an abnormally large current flows. This reduces the saturation current of the gate and improves short-circuit resistance.

[0055] Moreover, here, the JFET region 13 is disposed beside the trench 9 to ensure a sufficient length of the JFET region 13, which provides the effects of suppressing minute currents and improving breakdown voltage.

[0056] Furthermore, here, the current spreading region 7 does not reach one end of the first side surface of the trench 9 in the X direction. This prevents a channel from being generated on the side surface of the second side surface that is perpendicular to the first side surface and that is closer to the source region 6a. This prevents a channel with different characteristics from the channel along the first side surface from being generated along the second side surface, thereby suppressing variations in the MOSFET characteristics.

[0057] Furthermore, here, the semiconductor region 6c does not reach the other end of the first side surface of the trench 9 in the X direction. This prevents a channel from being generated on the side surface of the JFET region 13, which is perpendicular to the first side surface. This prevents a channel with different characteristics from the channel along the first side surface from being generated along the second side surface, thereby suppressing variations in MOSFET characteristics. In other words, current flows only along the side surface (first side surface) in the short direction of the trench 9, preventing current from flowing along other trench side surfaces with different plane orientations.

[0058] As described above, in this embodiment, the performance of the silicon carbide semiconductor device can be improved.

[0059] <Variation 1> As a first modification of the present embodiment, a structure in which source regions and potential fixing regions are alternately arranged in the extending direction of a source contact plug will be described with reference to Figs. 7 to 10. Figs. 8 and 9 are cross-sectional views taken along lines AA and DD in Fig. 7, respectively. Fig. 10 is a plan view of the semiconductor substrate cut along line CC in Figs. 8 and 9.

[0060] 7 and 10, the source regions 6a and the potential clamping regions 14 are arranged alternately in the Y direction. As shown in FIG. 8, the potential clamping regions 14 are spaced apart from the trenches 9 and reach the upper surfaces of the guard regions 8. That is, the potential clamping regions 14 are formed between the guard regions 8 and the upper surface of the semiconductor substrate, and are in contact with the body layers 5 and the guard regions 8. A source potential is applied to the body layers 5 and the guard regions 8 via the potential clamping regions 14 electrically connected thereto.

[0061] Between adjacent potential fixing regions 14 in the Y direction, the source region 6a is electrically connected to the semiconductor region 6c via the underlying semiconductor region 6b. As shown in Fig. 10, a part of the semiconductor region 6b is located between the trenches 9 aligned in the Y direction, and another part is located between the potential fixing regions 14 aligned in the Y direction. The source regions 6a and the potential fixing regions 14 formed on the upper surface of the semiconductor substrate are alternately aligned directly below the contact plugs (source contact plugs) 1 extending in the Y direction, and are connected to the bottom surfaces of the contact plugs 1.

[0062] In this modification, even if the potential fixing region 14 diffuses downward, the semiconductor region 6c is not divided by the potential fixing region 14. Therefore, the potential fixing region 14 can be formed deeper than in the structures shown in Figures 1 to 6. This makes it easier to fix the potential of the guard region 8.

[0063] <Variation 2> As a second modification of this embodiment, p +The structure for forming the electric field buffer layer of the mold will be described with reference to Fig. 11 to Fig. 14. Fig. 12 and Fig. 13 are cross-sectional views taken along lines AA and DD in Fig. 11, respectively. Fig. 14 is a plan view of the semiconductor substrate cut along line CC in Fig. 12 and Fig. 13.

[0064] As shown in FIGS. 11 to 13, the structure of this modification has a p + The difference is that a p type electric field relaxation layer 10 is formed. + The electric field relaxation layer 10 is formed between the upper surface of the current diffusion region 7 and the upper surface of the semiconductor substrate. + The p-type impurity concentration of the field relaxation layer 10 is higher than the p-type impurity concentration of the body layer 5. In plan view, the field relaxation layer 10 extends in the Y direction, similar to the current diffusion region 7, and a portion of it is located between the trenches 9 adjacent to each other in the Y direction. That is, the field relaxation layer 10 contacts a first side surface of the trench 9 above the current diffusion region 7. The field relaxation layer 10 contacts the potential clamping regions 14 adjacent to each other in the X direction, and a source potential is applied to the field relaxation layer 10 via the electrically connected potential clamping regions 14.

[0065] The current diffusion region 7 above the JFET region 13 is a location where the electric field is likely to become strong. Therefore, by providing the electric field relaxation layer 10 as in this modification, the electric field of the insulating film 11 above the current diffusion region 7 can be weakened. This prevents dielectric breakdown from occurring between the current diffusion region 7 and the gate electrode 2 above it. In addition, because a source potential is applied to the electric field relaxation layer 10, the gate-drain capacitance between the top of the JFET region 13 and the gate electrode 2 above it is converted into gate-source capacitance. As a result, the switching characteristics of the MOSFET are improved.

[0066] Furthermore, compared to Modification 1, the current spreading region 7 is separated from the upper surface of the semiconductor substrate toward the lower surface, which can suppress the occurrence of a parasitic channel on the second side surface (the side surface on the potential fixing region 14 side) of the trench 9. This can suppress variations in the characteristics of the MOSFET.

[0067] Furthermore, the length of the effective JFET region is longer here than in Modification 1. That is, while a JFET is an n-type semiconductor region sandwiched between p-type semiconductor regions, by forming the potential clamping region 14, the current spreading region 7 is sandwiched between the potential clamping region 14 and the body layer 5. Therefore, the current spreading region 7 functions as a JFET region, and the length of the effective JFET region is longer. This improves the short-circuit resistance.

[0068] <Variation 3> As a third modification of the present embodiment, a structure in which adjacent unit cells are arranged without being inverted will be described with reference to Fig. 15. In Fig. 15, a plan view is shown at the top, and a cross-sectional view of a portion corresponding to line AA in the plan view is shown at the bottom.

[0069] 15 , in this modification, unit cells UC adjacent to each other in the X direction are arranged side by side without inverting their structures, including their planar layouts. Here, a portion of the JFET region 13 contacts the upper surface of the semiconductor substrate next to an end of the current diffusion region 7. In addition, a portion of the potential clamping region 14 extending in the Y direction from the upper surface of the semiconductor substrate to the upper surface of the guard region 8 is located between the current diffusion region 7 in a given unit cell UC and the source region 6 a in another unit cell UC adjacent to it in the X direction. In other words, of the side surfaces of the trench 9 in the X direction, the side surface opposite to the trench 9 contacts the potential clamping region 14.

[0070] As a result, of the unit cells UC adjacent to each other in the X direction, the current diffusion region 7 and JFET region 13 constituting one unit cell UC are separated from the source region 6a and semiconductor regions 6b and 6c constituting the other unit cell UC by a potential fixing region 14 extending in the Y direction.

[0071] Furthermore, the guard region 8 located on the opposite side of the JFET region 13 from the trench 9 in the X direction is formed in a convex shape so as to dig into the center of the JFET region 13 more than the side surface of the JFET region 13. In other words, the end of the guard region 8 located on the JFET region 13 side, located on the opposite side of the JFET region 13 from the trench 9 in the X direction, terminates closer to the center of the JFET region 13 than the side surface of the JFET region 13. As a result, the width of the JFET region 13 sandwiched between the two guard regions 8 in the X direction is narrower than the width of the JFET region 13 sandwiched between the body layer 5 and the potential clamping region 14.

[0072] In this modification, the structures of adjacent unit cells UC are not inverted, so one JFET region 13 is formed for one unit cell. In other words, the density of the JFET region 13 can be increased by approximately two times compared to the structure described using FIG. 6. This allows the resistance of the JFET region 13 to be reduced.

[0073] Furthermore, because the resistance of the JFET region 13 can be reduced, it is also possible to reduce the distance between the guard regions 8 that sandwich the JFET region 13 in the X direction. This facilitates the closure of the depletion layer in the JFET region 13 between adjacent guard regions 8 during MOSFET off-state operation. This prevents an increase in the resistance of the JFET region 13, while also suppressing minute currents and improving breakdown voltage. Furthermore, because the width of the JFET region 13 can be easily adjusted along its path (the current path of the JFET region 13), the trade-off between the resistance and threshold voltage of the MOSFET can be improved.

[0074] Here, the phases of the arrangement of the potential fixing regions 14 and the source regions 6a in the unit cells UC adjacent to each other in the X direction are changed, but the arrangements of these regions may be the same in the adjacent unit cells UC.

[0075] <Variation 4> As a fourth modification of this embodiment, a structure in which adjacent unit cells are arranged without being inverted and the JFET region is formed at an angle will be described with reference to Fig. 16. In Fig. 16, a plan view is shown on the upper side, and a cross-sectional view of a portion corresponding to line AA in the plan view is shown on the lower side.

[0076] 16, in this modification, similar to the third modification, adjacent unit cells UC in the X direction are arranged side by side without inverting the structure including the planar layout. In addition, the JFET region 13 is formed at an oblique angle with respect to the upper and lower surfaces of the semiconductor substrate. Furthermore, of the unit cells UC adjacent to each other in the X direction, the current spreading region 7 and JFET region 13 constituting one unit cell UC are separated from the source region 6a and semiconductor regions 6b and 6c constituting the other unit cell UC by the body layer 5. The width in the X direction of the obliquely formed JFET region 13 is substantially constant at any height.

[0077] The JFET region 13 in this modification is formed by, for example, oblique ion implantation. The JFET region 13 has an angle such that the distance from the trench 9 in the X direction gradually increases from the upper surface side to the lower surface side of the semiconductor substrate. Therefore, the arrangement period (cell pitch) of the unit cells UC can be reduced for the following reasons. That is, in this case, the JFET region 13 near the lower surface of the high-voltage semiconductor substrate is spaced apart from the trench 9. Although the electric field tends to concentrate at the lower corners of the trench 9, by forming the JFET region 13 at an angle, the lower corners of the trench 9 and the JFET region 13 can be separated. This ensures a sufficient breakdown voltage between the trench 9 and the JFET region 13. Therefore, the distance between the trench 9 and the upper end of the JFET region 13 can be reduced. As a result, the current diffusion region 7 in the unit cell UC can be separated from the contact plug 1 in the adjacent unit cell UC via the body layer 5. This reduces the distance between the contact plug 1 and the JFET region 13 in a plan view. As a result, the arrangement period (cell pitch) of the unit cells UC can be reduced. Note that the upper end of the JFET region 13 is spaced apart from the trench 9 to prevent a short circuit between the trench 9 and the JFET region 13.

[0078] In addition, since the JFET region 13 is formed at an angle, the length (current path) of the JFET region 13 can be extended compared to when the JFET region 13 is formed perpendicular to the upper surface of the semiconductor substrate, thereby improving the short-circuit resistance of the MOSFET.

[0079] <Variation 5> As a fifth modification of the present embodiment, a structure in which a plurality of JFET regions are arranged in the Y direction will be described with reference to Figs. 17 to 19. Figs. 17 and 18 are cross-sectional views showing a silicon carbide semiconductor device of this modification. Fig. 19 is a plan view showing a silicon carbide semiconductor device of this modification. Fig. 17 is a cross-sectional view taken along line AA in Fig. 19, and Fig. 18 is a cross-sectional view taken along line EE in Fig. 19. Figs. 17 to 19 show two unit cells arranged side by side.

[0080] As shown in FIGS. 17 to 19, in this modification, a plurality of JFET regions 13 extending in the X direction are arranged side by side in the Y direction in each unit cell. That is, the JFET regions 13 in this modification are FIN-type JFET regions. Here, adjacent unit cells UC have structures that are inverted at their boundaries. The phases of the potential clamping regions 14 and source regions 6a in unit cells UC adjacent to each other in the X direction are not identical, but may be the same. A body layer 5 is formed between the JFET regions 13 adjacent to each other in the Y direction. The other structures are the same as those described with reference to FIG. 5.

[0081] The narrower the width of the JFET region, the better the short-circuit resistance, but the increased on-resistance must be compensated for by increasing the number of JFET regions. By forming multiple FIN-type JFET regions with a small width in the Y direction, as in this modification, the effective number of JFET regions 13 can be increased.

[0082] Here, the width of the JFET region is 1 μm, and the cell pitch excluding the JFET region formation area is 6 μm. In a structure in which the JFET region extends in the Y direction, the density of the JFET region is (length of the JFET region per unit cell) / (unit cell area) = 1 μm / (1 + 6) μm = 0.14 μm / μm 2 is.

[0083] In this modification, when the length of the formation portion of the JFET region 13 is L and the arrangement period of the JFET region is P, for example, when L=5 μm and P=2 μm, L / P(L+6)=5 μm / 2 μm×11 μm=0.23 μm / μm 2 This allows the density of the JFET region to be increased by approximately 1.5 times, thereby reducing the resistance of the JFET region 13.

[0084] <Variation 6> As a sixth modification of the present embodiment, a structure in which a Schottky barrier diode is formed directly above a JFET region will be described with reference to Fig. 20. Fig. 20 is a cross-sectional view showing a silicon carbide semiconductor device in this modification, illustrating two adjacent unit cells.

[0085] 20, adjacent unit cells UC have structures that are inverted at their boundaries. In this modification, a plurality of JFET regions 13 extending in the X direction are arranged in the Y direction within each unit cell. The phases of the potential clamping regions 14 and source regions 6a of adjacent unit cells UC in the X direction are not identical, but may be the same.

[0086] Here, the JFET region 13 has a first portion adjacent to the body layer 5 in the X direction and having a relatively large width in the X direction, and a second portion adjacent to the guard region 8 in the X direction and having a smaller width in the X direction than the first portion. An n-type semiconductor region 16 is formed in contact with the upper surface of the semiconductor substrate directly above the first portion and in a portion of the semiconductor substrate sandwiched between two current spreading regions 7 in the X direction. That is, the semiconductor region 16 is formed between the upper surface of the semiconductor substrate and the upper surface of the JFET region 13, and is connected to the upper surface of the JFET region 13. The n-type impurity concentration of the semiconductor region 16 is lower than the n-type impurity concentration of the JFET region 13.

[0087] In the insulating film 11 on the upper surface of the semiconductor substrate, through-holes (connection holes) are formed directly above the JFET region 13 and the semiconductor region 16, penetrating the insulating film 11, and contact plugs 17 are buried in the through-holes. The bottom surface of the contact plugs 17 is connected to the semiconductor region 16. The connection between the contact plugs 17 and the semiconductor region 16 forms a Schottky junction, forming a Schottky barrier diode. The rest of the structure is the same as the structure described with reference to FIG. 5.

[0088] In this modification, the provision of a Schottky barrier diode can suppress the current degradation that is unique to SiC power devices. That is, the junction between the p-type semiconductor region consisting of the potential clamping region 14 and the guard region 8 and the n-type semiconductor region consisting of the drain region 12 and the drift layer 4 forms a PN diode. This PN diode is a bipolar element through which holes and electrons flow. In SiC power devices, there is a problem in that the characteristics deteriorate when holes flow through this PN diode.

[0089] In this modification, holes flow into the Schottky barrier diode, so mainly electrons flow into the PN diode. This prevents holes from flowing into the PN diode, suppressing degradation during conduction. It also reduces diode loss and switching loss.

[0090] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0091] For example, the materials, conductivity types, and manufacturing conditions of each part are not limited to those described in the above-described embodiments, and it goes without saying that many variations are possible. Here, for convenience of explanation, the conductivity types of the semiconductor substrate and semiconductor film have been fixed, but they are not limited to the conductivity types described in the above-described embodiments. That is, although an n-type SiC power MISFET has been described in the first embodiment and each modification, a p-type SiC power MISFET in which the conductivity types of each semiconductor region are reversed can also achieve the same effects as those of the above-described embodiments and each modification.

[0092] Furthermore, the first embodiment and the second to fifth modifications can be combined with each other as long as no contradiction occurs, such as a difference in the orientation of the unit cells. [Explanation of symbols]

[0093] 1, 17 Contact plug 2 gate electrode 3 Drain electrode 4 Drift layer 5 Body Layer 6a Source Region 6b, 6c, 16 Semiconductor area 7 Current spreading region 8 Guard Area 9. Trench 10 Electric field relaxation layer 11. Insulating film 12 Drain region 13 JFET area 14 Potential fixing region UC unit cell

Claims

1. a silicon carbide semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a source electrode formed on the first major surface; a plurality of source contact regions that are connected between the first main surface and the source electrode and extend along the first main surface; a plurality of trenches formed in the first main surface between the source contact regions adjacent to each other in a short-side direction of the source contact regions, the trenches being aligned in a direction parallel to the long sides of the source contact regions; a gate electrode formed in the trench via an insulating film; Within the silicon carbide semiconductor substrate, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type different from the first conductivity type, a third semiconductor region of the first conductivity type in contact with a first side surface of the trench and to which a source potential is applied, a fourth semiconductor region of the second conductivity type in contact with the first side surface of the trench and having an impurity concentration lower than that of the second semiconductor region, and a fifth semiconductor region of the first conductivity type in contact with the first side surface of the trench, are formed in this order from the second main surface side toward the first main surface; a sixth semiconductor region of the first conductivity type formed in the silicon carbide semiconductor substrate at a distance from the trench and connecting the fifth semiconductor region and the first semiconductor region; and the third semiconductor region is spaced apart from the first semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; the gate electrode, and the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region that are adjacent to the first side surface of the trench and overlap one another in a plan view, form a field effect transistor; a channel of the field effect transistor occurring between the third semiconductor region and the fifth semiconductor region in the fourth semiconductor region contacting the first side surface of the trench;

2. 2. The silicon carbide semiconductor device according to claim 1, a seventh semiconductor region of the first conductivity type and an eighth semiconductor region of the first conductivity type formed in this order on the first main surface side with respect to the third semiconductor region; and the source contact region is connected to the eighth semiconductor region at the first major surface; the seventh semiconductor region has an impurity concentration lower than the impurity concentrations of the third semiconductor region and the eighth semiconductor region; the seventh semiconductor region and the eighth semiconductor region are spaced apart from the trench; a source potential is applied to the third semiconductor region via the source contact region, the eighth semiconductor region, and the seventh semiconductor region;

3. 2. The silicon carbide semiconductor device according to claim 1, A silicon carbide semiconductor device, wherein the fifth semiconductor region is spaced apart from one end of the trench in a first direction along the first main surface and the first side surface of the trench.

4. 2. The silicon carbide semiconductor device according to claim 1, The silicon carbide semiconductor device, wherein the third semiconductor region is spaced apart from one end of the trench in a first direction along the first main surface and the first side surface of the trench.

5. 3. The silicon carbide semiconductor device according to claim 2, a ninth semiconductor region of the second conductivity type formed between the first main surface and the third semiconductor region and spaced apart from the fifth semiconductor region, the ninth semiconductor region having a higher impurity concentration than the fourth semiconductor region; the ninth semiconductor region is in contact with the fourth semiconductor region and is electrically connected to the source contact region and the second semiconductor region.

6. 3. The silicon carbide semiconductor device according to claim 2, a ninth semiconductor region of the second conductivity type formed between the first main surface and the second semiconductor region, spaced apart from the fifth semiconductor region and the trench, and having a higher impurity concentration than the fourth semiconductor region; the ninth semiconductor region is in contact with the fourth semiconductor region and the second semiconductor region, and is connected to the source contact region.

7. 3. The silicon carbide semiconductor device according to claim 2, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, the sixth semiconductor region, the seventh semiconductor region, and the eighth semiconductor region constitute a unit cell, a plurality of the unit cells are arranged in a first direction along the first main surface and the first side surface of the trench; In the first direction, the seventh semiconductor region and the eighth semiconductor region are located on opposite sides of the trench from the sixth semiconductor region, the unit cells adjacent to each other in the first direction have a structure that is line-symmetrical about a boundary line between the unit cells in a plan view.

8. 3. The silicon carbide semiconductor device according to claim 2, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, the sixth semiconductor region, the seventh semiconductor region, and the eighth semiconductor region constitute a unit cell, a plurality of the unit cells are arranged in a first direction along the first main surface and the first side surface of the trench without inverting their planar layout; In the first direction, the seventh semiconductor region and the eighth semiconductor region are located on opposite sides of the trench from the sixth semiconductor region, of the unit cells adjacent to each other in the first direction, the fifth semiconductor region and the sixth semiconductor region constituting one of the unit cells and the third semiconductor region constituting the other of the unit cells are separated from each other by the tenth semiconductor region of the second conductivity type formed in the silicon carbide semiconductor substrate.

9. 2. The silicon carbide semiconductor device according to claim 1, a second conductivity type eleventh semiconductor region formed in the silicon carbide semiconductor substrate between the fifth semiconductor region and the first main surface;

10. 9. The silicon carbide semiconductor device according to claim 8, the sixth semiconductor region has an angle such that a distance from the trench in the first direction gradually increases from the first main surface side toward the second main surface side.

11. 2. The silicon carbide semiconductor device according to claim 1, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region constitute a unit cell, a plurality of the unit cells are arranged in a first direction along the first main surface and the first side surface of the trench; Within the unit cell, a plurality of the sixth semiconductor regions are arranged side by side in a second direction perpendicular to the first direction in a plan view, At least one of the fourth semiconductor region and the second semiconductor region is formed between the sixth semiconductor regions adjacent to each other in the second direction.

12. 2. The silicon carbide semiconductor device according to claim 1, a twelfth semiconductor region of the first conductivity type formed between the sixth semiconductor region and the first main surface in the silicon carbide semiconductor substrate and connected to the sixth semiconductor region, the twelfth semiconductor region having a lower impurity concentration than the fifth semiconductor region; a connection portion formed on the first main surface and forming a Schottky junction with the twelfth semiconductor region; and the twelfth semiconductor region and the Schottky junction connection portion form a Schottky barrier diode.

13. 2. The silicon carbide semiconductor device according to claim 1, The second semiconductor region is spaced apart from the trench.

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