Semiconductor Devices

Abstract

To provide a semiconductor device which can increase breakdown resistance and make recovery characteristics better and in which a recovery loss is unlikely to increase.SOLUTION: A semiconductor device 100 comprises a semiconductor substrate 110, an insulation layer 120 including an opening 122, and a surface electrode 130. The semiconductor substrate 110 comprises a drift region 112, a p-type impurity region 113, and a peripheral impurity region 114. The p-type impurity region 114 includes a high-concentration region 115 formed in a portion overlapping the peripheral impurity region 114. A recombination center is formed in the semiconductor substrate 110. An inner peripheral end of the peripheral impurity region 114 on a surface of the semiconductor substrate 110 is located on the inner periphery side of an end part of the opening 122. A length from the inner peripheral end of the peripheral impurity region 114 to the end part of the opening 122 is greater than or equal to 0.01 μm and less than 30 μm.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, semiconductor devices (diodes) have been known that include a surface electrode connected to a semiconductor substrate via an opening in an insulating layer (see, for example, Patent Document 1).

[0003] FIG. 7 is a cross-sectional view showing a conventional semiconductor device 900. Reference numeral 917 denotes a guard ring. The semiconductor device described in Patent Document 1 (hereinafter referred to as the conventional semiconductor device 900) includes a semiconductor substrate 910, an insulating layer 920, a front surface electrode 930, a back surface electrode 940, and a surface protective film 950, as shown in FIG. 7. The insulating layer 920 is formed on the surface of the semiconductor substrate 910 and has an opening 922 that exposes the surface of the semiconductor substrate 910. The front surface electrode 930 is connected to the semiconductor substrate 910 at the opening 922.

[0004] The semiconductor substrate 910 is n + A low-resistance semiconductor layer 911, an n-type drift region 912, and a p-type semiconductor layer formed in the surface layer of the drift region 912. - and a p-type peripheral impurity region 914 formed on the periphery of the p-type impurity region 913 in the surface layer portion of the drift region 912 and having an impurity concentration higher than that of the p-type impurity region 913.

[0005] According to the conventional semiconductor device 900, since it has the peripheral impurity region 914, the gradient of the impurity concentration at the outer peripheral edge of the p-type impurity region 913 can be reduced, thereby suppressing breakdown at the outer peripheral edge of the p-type impurity region 913. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 10-335679 Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, efforts have been made to realize an oxygen-free society, which has led to a demand for low-loss electrical equipment, and in the field of semiconductor devices, there is a demand for high-efficiency, low-loss semiconductor devices for use in such electrical equipment.

[0008] However, in the conventional semiconductor device 900, when switching is turned on and off, holes remaining in the peripheral region A2 flow into the surface electrode 930 via the peripheral impurity region 914. This causes a sudden increase in current density near the intersection of the current flowing into the surface electrode 930 via the p-type impurity region 913 (current due to holes remaining in the element formation region A1) and the current flowing into the surface electrode 930 via the peripheral impurity region 914. This causes a sudden rise in temperature near the intersection, making it difficult to increase the breakdown voltage. In addition, the sudden increase in reverse recovery current makes it difficult to improve recovery characteristics, resulting in an increase in recovery loss.

[0009] The present invention has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that can increase the breakdown voltage, improve recovery characteristics, and is less likely to experience an increase in recovery loss. [Means for solving the problem]

[0010] a first semiconductor device according to the present invention comprising: a semiconductor substrate; an insulating layer formed on a surface of the semiconductor substrate and having an opening exposing the surface of the semiconductor substrate; and a surface electrode connected to the semiconductor substrate at the opening; wherein the semiconductor substrate has a first conductivity type drift region; a second conductivity type impurity region formed in a surface layer portion of the drift region; and a second conductivity type peripheral impurity region formed in a peripheral portion of the second conductivity type impurity region in the surface layer portion of the drift region, the second conductivity type peripheral impurity region having a higher impurity concentration than the impurity concentration in the second conductivity type impurity region, the second conductivity type impurity region being formed in at least a portion overlapping with the peripheral impurity region and having a high impurity concentration higher than the other regions of the second conductivity type impurity region; a recombination center formed within the semiconductor substrate; an inner peripheral edge of the peripheral impurity region on the surface of the semiconductor substrate being located on the inner peripheral side of an edge of the opening; and a length from the inner peripheral edge of the peripheral impurity region to the edge of the opening being 0.01 μm or more and less than 30 μm.

[0011] A second semiconductor device of the present invention comprises a semiconductor substrate, an insulating layer formed on a surface of the semiconductor substrate and having an opening exposing the surface of the semiconductor substrate, and a surface electrode connected to the semiconductor substrate at the opening, wherein the semiconductor substrate has a first conductivity type drift region, a second conductivity type impurity region formed in a surface layer portion of the drift region, and a second conductivity type peripheral impurity region formed in a peripheral portion of the second conductivity type impurity region in the surface layer portion of the drift region, the second conductivity type peripheral impurity region having a portion overlapping with the second conductivity type impurity region and having an impurity concentration higher than that of the second conductivity type impurity region, the second conductivity type impurity region having a high concentration region formed at least in a portion overlapping with the peripheral impurity region and having an impurity concentration higher than that of other regions of the second conductivity type impurity region, a recombination center is formed within the semiconductor substrate, an inner peripheral edge of the peripheral impurity region on the surface of the semiconductor substrate is located at the same position as an edge of the opening or on the outer peripheral side thereof, and the impurity concentration of the high concentration region is 1.0×10 16 cm -3 ~1.0×10 20 cm -3is characterized in that it is within the range of [Effects of the Invention]

[0012] According to the first semiconductor device of the present invention, recombination centers are formed within the semiconductor substrate, and the length from the inner edge of the peripheral impurity region to the edge of the opening is 0.01 μm or more and less than 30 μm. Therefore, when switching on and off, holes and other impurities generated in the semiconductor substrate, including the peripheral region, are collected by the recombination centers, thereby reducing the amount of current reaching the surface electrode (reducing the number of holes reaching the surface electrode). This reduces both the current flowing into the surface electrode via the second conductivity-type impurity region and the current flowing into the surface electrode via the peripheral impurity region, reducing the current density near the junction and suppressing temperature rise. As a result, breakdown voltage can be increased. Furthermore, reducing the current density in the element formation region allows the length from the inner edge of the peripheral impurity region to the edge of the opening to be shortened. This prevents a sudden increase in recovery current, improving recovery characteristics and suppressing an increase in recovery loss.

[0013] According to the second semiconductor device of the present invention, a recombination center is formed in the semiconductor substrate, and the inner peripheral edge of the peripheral impurity region is located at the same position as the edge of the opening or on the outer peripheral side thereof, and the impurity concentration of the high concentration region is 1.0×10 16 cm -3 ~1.0×10 20 cm -3Because the area is within this range, holes and other impurities generated in the semiconductor substrate, including the peripheral region, are collected by the recombination centers during switching on and off, thereby reducing the amount of current reaching the surface electrode. This reduces the current density near the area where the current density of the current flowing from the element formation region to the surface electrode via the second-conductivity-type impurity region overlaps with the current density of the current flowing from the peripheral impurity region to the second-conductivity-type impurity region and then to the surface electrode, thereby suppressing temperature rise. As a result, the breakdown voltage can be increased. Furthermore, because the current density in the element formation region can be reduced, the breakdown voltage can be maintained even without contact between the peripheral impurity region and the surface electrode. Furthermore, because the peripheral impurity region and the surface electrode do not contact each other, a sudden increase in recovery current can be prevented, improving recovery characteristics and suppressing an increase in recovery loss.

[0014] According to the first and second semiconductor devices of the present invention, the second conductivity type impurity region is formed at least in a portion overlapping with the peripheral impurity region and has a high concentration region having a higher impurity concentration than other regions of the second conductivity type impurity region, thereby preventing holes in the peripheral region from flowing to the surface of the element formation region due to the difference in impurity concentration between the second conductivity type impurity region and the peripheral impurity region, thereby preventing an increase in current density on the surface of the element formation region and resulting in a semiconductor device with further improved breakdown resistance. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. [Figure 2] 1 is an enlarged cross-sectional view of a main part of a semiconductor device 100 according to a first embodiment. [Figure 3] 10 is a graph showing recovery voltage waveforms and recovery currents of the "conventional structure" and the "invention structure." [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device 101 according to a second embodiment. [Figure 5]10 is an enlarged cross-sectional view of a main part of a semiconductor device 101 according to a second embodiment. FIG. [Figure 6] FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modified example. [Figure 7] FIG. 1 is a cross-sectional view showing a conventional semiconductor device 900. DETAILED DESCRIPTION OF THE INVENTION

[0016] The semiconductor device of the present invention will be described below based on the embodiments shown in the drawings. Note that the embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0017] [Embodiment 1] 1. Configuration of the semiconductor device 100 according to the first embodiment FIG. 1 is a cross-sectional view showing a semiconductor device 100 according to a first embodiment. In FIG. 1, "x" indicates a recombination center. FIG. 2 is an enlarged cross-sectional view of a main portion of the semiconductor device 100 according to the first embodiment. As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 110, an insulating layer 120 formed on the surface of the semiconductor substrate 110 and having an opening 122 that exposes the surface of the semiconductor substrate 110, a front surface electrode 130 connected to the semiconductor substrate 110 in the opening 122, a back surface electrode 140 formed on the back surface of the semiconductor substrate 110, an EQR electrode (Equi-Potential Ring electrode) 132 formed near the outermost periphery of the surface of the semiconductor substrate 110, and a protective insulating film 150 having an opening in its center.

[0018] The semiconductor device 100 according to the first embodiment is configured with an element forming region A1 and an outer peripheral region A2. In the first embodiment, the element forming region A1 is located on the inner side of an inner peripheral edge B of a peripheral impurity region 114, which will be described later, and the outer peripheral region A2 is located on the outer side of the inner peripheral edge B of the peripheral impurity region 114.

[0019] The semiconductor substrate 110 is n +a low-resistance semiconductor region 111, an n-type drift region 112, a p-type impurity region 113 formed in the surface layer of the drift region 112, and a p-type impurity region 114 formed in the peripheral portion of the p-type impurity region 113 in the surface layer of the drift region 112, having a portion overlapping with the p-type impurity region 113 and having an impurity concentration higher than the impurity concentration of the p-type impurity region 113. + The n-type peripheral impurity region 114 and the n-type peripheral impurity region 114 formed on the outermost periphery of the semiconductor substrate 110 + and a channel stop region 116.

[0020] Recombination centers are formed within the semiconductor substrate 110. The recombination centers may be formed by irradiating the semiconductor substrate 110 with an electron beam (and then annealing), or by applying a heavy metal (e.g., platinum or gold) to the semiconductor substrate and then heating it to diffuse it.

[0021] The impurity concentration of the drift region 112 is 1.0×10 13 cm -3 ~1.0×10 15 cm -3 The channel stop region 116 is connected to the EQR electrode 132 located on the outermost periphery of the semiconductor substrate 110. The impurity concentration of the channel stop region 116 is higher than the impurity concentration of the drift region 112.

[0022] The p-type impurity region 113 has a region overlapping with the peripheral impurity region 114, and a high-concentration region 115 is formed in the region overlapping with the peripheral impurity region 114. In the first embodiment, the high-concentration region 115 is formed only in the region where the p-type impurity region 113 and the peripheral impurity region 114 overlap, but it may be formed not only in the overlapping region but also on the inner periphery of the overlapping region. The impurity concentration of the high-concentration region 115 is higher than the impurity concentration in other regions of the p-type impurity region 113 and higher than the impurity concentration of the peripheral impurity region 114. The impurity concentration of the high-concentration region 115 is 1.0×10 16 cm -3 ~1.0×10 20 cm -3 and more preferably in the range of 2.0×1017 cm -3 ~1.0×10 20 cm -3 is within the range.

[0023] 1 and 2, the p-type impurity region 113 is formed inside the opening 122, and an end of the p-type impurity region 113 is located on the inner periphery side of the end of the opening 122. In the region between the outer periphery side end of the p-type impurity region 113 (the outer periphery side end of the high concentration region 115) and the end B of the opening 122, the peripheral impurity region 114 and the surface electrode 130 are in contact with each other. The impurity concentration of the p-type impurity region 113 is lower than the impurity concentration of the high concentration region 115, and is, for example, 5.0×10 15 cm -3 ~4.4×10 16 cm -3 is within the range.

[0024] The depth of the peripheral impurity region 114 is deeper than the depth of the p-type impurity region 113. An inner peripheral edge B of the peripheral impurity region 114 on the surface of the semiconductor substrate 110 is located on the inner peripheral side of the edge A of the opening 122, and a length L1 from the inner peripheral edge B of the peripheral impurity region 114 to the edge A of the opening 122 is 0.01 μm or more and less than 30 μm. The impurity concentration of the peripheral impurity region 114 is lower than that of the high concentration region 115. Therefore, the impurity concentrations increase in the order of the p-type impurity region 113, the peripheral impurity region 114, and the high concentration region 115.

[0025] 2. State of carriers when switching on and off in the semiconductor device 100 according to the first embodiment Before describing the state of carriers when switching on and off in the semiconductor device 100 according to the first embodiment, the state of carriers when switching on and off in the conventional semiconductor device 900 will be described.

[0026] In the conventional semiconductor device 900, when a voltage is applied between the front surface electrode 930 and the back surface electrode 940 during switching on, holes as carriers move within the semiconductor base 910 from the front surface electrode 930 toward the back surface electrode 940. Then, when the voltage is no longer applied between the front surface electrode 930 and the back surface electrode 940 and switching transitions to the off state, the holes within the semiconductor base 910 move toward the front surface electrode 930 and are collected by the front surface electrode 930.

[0027] In the peripheral region A2, the remaining holes also move toward the surface electrode 930. However, because the insulating layer 920 is formed on the surface of the semiconductor substrate 910 in the peripheral region A2, the holes move toward the element formation region A1 and are collected by the surface electrode 930 through the peripheral impurity region 914. This increases the current density near the peripheral impurity region 914 and the p-type impurity region 913, making it difficult to increase the breakdown resistance. Furthermore, it takes time for the holes to reach the surface electrode 930, which lengthens the reverse recovery time.

[0028] In contrast, in the peripheral region of the semiconductor device 100 according to the first embodiment, (1) recombination centers are formed in the semiconductor substrate 110, so holes are collected by the recombination centers, and the number of holes moving toward the element formation region is reduced. Also, (2) the inner edge B of the peripheral impurity region 114 on the surface of the semiconductor substrate 110 is located on the inner side of the edge A of the opening 122. Therefore, holes not only move to the surface electrode 130 via the peripheral impurity region 114 as in the conventional case, but also move to the surface electrode 130 via the p-type impurity region 113. Therefore, holes can be efficiently collected. Also, (3) the high-concentration region 115 of the p-type impurity region 113 is formed in the region where the p-type impurity region 113 and the peripheral impurity region 114 are in contact with each other. This prevents the current density of the current flowing in the peripheral impurity region 114 from becoming larger than the current density of the current flowing in the p-type impurity region 113. This alleviates the difference in impurity concentration between the p-type impurity region 113 and the peripheral impurity region 114, thereby preventing an increase in current density. Furthermore, since the length S1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 is 0.01 μm or more and less than 30 μm, a soft recovery waveform is obtained, as shown in the waveform of the "invention structure" in Figure 3. As a result, the recovery voltage can be suppressed and the reverse recovery current can be reduced.

[0029] 3. Effects of the semiconductor device 100 according to the first embodiment According to the semiconductor device 100 of the first embodiment, recombination centers are formed within the semiconductor substrate 110, and the length L1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 is 0.01 μm or more and less than 30 μm. Therefore, holes and other impurities generated in the semiconductor substrate 110, including the peripheral region A2, are collected by the recombination centers during on / off switching, thereby reducing the amount of current reaching the surface electrode 130 (reducing the number of holes reaching the surface electrode 130). This reduces both the current flowing into the surface electrode 130 via the p-type impurity region 113 and the current flowing into the surface electrode 130 via the peripheral impurity region 114, thereby reducing the current density near where the currents converge and suppressing temperature rise. As a result, the breakdown voltage can be increased. Furthermore, because the current density in the element formation region A1 can be reduced, the length L1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 can be reduced. Therefore, a sudden increase in recovery current can be prevented, which improves the recovery characteristics and suppresses an increase in recovery loss.

[0030] In the first embodiment, the length L1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 is set to 0.01 μm or more because, if the length L1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 is less than 0.01 μm, the contact area between the peripheral impurity region 114 and the surface electrode 130 is small, and fewer holes move from the peripheral impurity region 114 to the surface electrode 130, making it difficult to efficiently collect holes. The length L1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 is set to less than 30 μm because, if the length L1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 is 30 μm or more, the contact area between the peripheral impurity region 114 and the surface electrode 130 becomes large, causing a sudden increase in recovery current and resulting in large recovery loss (see the waveform for the “conventional structure” in FIG. 3 ).

[0031] FIG. 3 is a graph showing the recovery voltage and recovery current of the "conventional structure" and the "invention structure." FIG. 3(a) shows the recovery voltage waveforms of the "conventional structure" and the "invention structure," and FIG. 3(b) shows the recovery current waveforms of the "conventional structure" and the "invention structure." In FIG. 3, the "conventional structure" (dashed line in FIG. 3) is a semiconductor device having a configuration similar to that of the semiconductor device 100 according to the first embodiment, except that the length L1 from the inner circumferential edge of the peripheral impurity region 114 to the edge of the opening 122 is 60 μm. Furthermore, the "invention structure" (solid line in FIG. 3) is a semiconductor device having a configuration similar to that of the semiconductor device 100 according to the first embodiment. As shown in Figure 3(a), the recovery voltage waveform of the "inventive structure" during on / off switching has a smaller peak after rising than the peak of the waveform of the "conventional structure," and the amplitude of the ringing immediately after the peak is also smaller. Also, as shown in Figure 3(b), the recovery current waveform of the "inventive structure" during on / off switching has a larger reverse recovery current and a shorter reverse recovery time than the waveform of the "conventional structure."

[0032] If the p-type impurity region 113 were entirely a high-concentration region, the current density in the p-type impurity region could be reduced during on / off switching, but current would tend to flow rapidly to the surface electrode 130, resulting in hard recovery and making it difficult to obtain a good recovery waveform. In contrast, in the semiconductor device 100 according to the first embodiment, the high-concentration region 115 is formed only in the region where the p-type impurity region 113 and the peripheral impurity region 114 overlap, which makes it easier for current to flow relatively slowly to the surface electrode 130, resulting in soft recovery and making it possible to obtain a good recovery waveform.

[0033] Furthermore, according to the semiconductor device 100 of the first embodiment, the impurity concentration of the drift region 112 is 1.0×10 13 cm -3 ~1.0×10 15 cm -3Since the temperature is within this range, the current density (amount of holes) of the recovery current can be made relatively small when switching on and off, and furthermore, recombination centers are formed within the semiconductor substrate 110, which enable holes to be collected, thereby further reducing the current density of the recovery current near the surface of the semiconductor substrate 110. As a result, the breakdown resistance can be further increased.

[0034] [Embodiment 2] FIG. 4 is a cross-sectional view of the semiconductor device 101 according to the second embodiment. FIG. 5 is an enlarged cross-sectional view of a main part of the semiconductor device 101 according to the second embodiment. The semiconductor device 101 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the position of the inner circumferential end of the peripheral impurity region on the surface of the semiconductor substrate is different from that of the semiconductor device 100 according to the first embodiment (see FIGS. 4 and 5). That is, in the semiconductor device 101 according to the second embodiment, the inner circumferential end B of the peripheral impurity region 114 on the surface of the semiconductor substrate 110 is located on the outer circumferential side of the end A of the opening 122. Therefore, the peripheral impurity region 114 is not in contact with the surface electrode 130.

[0035] The p-type impurity region 113 extends to the outer periphery of the opening 122 and has a region overlapping with the peripheral impurity region 114. As in the first embodiment, the high-concentration region 115 is formed only in the region where the p-type impurity region 113 and the peripheral impurity region 114 overlap (strictly speaking, only in the vicinity of the overlapping region). Therefore, the high-concentration region 115 is not in contact with the surface electrode 130, and is connected to the surface electrode 130 via the other portion of the p-type impurity region 113.

[0036] The impurity concentration in the high concentration region is 1.0×10 16 cm -3 ~1.0×10 20 cm -3 More preferably, it is in the range of 2.0×10 17 cm -3 ~1.0×10 20 cm -3This is higher than the impurity concentration of the p-type impurity region 113 and higher than the impurity concentration of the peripheral impurity region 114. Therefore, in the second embodiment as well, the impurity concentrations increase in the order of the p-type impurity region 113, the peripheral impurity region 114, and the high-concentration region 115.

[0037] As described above, in the semiconductor device 101 according to the second embodiment, the position of the inner circumferential edge of the peripheral impurity region on the surface of the semiconductor substrate is different from that of the semiconductor device 100 according to the first embodiment. However, a recombination center is formed in the semiconductor substrate 110, and the inner circumferential edge of the peripheral impurity region 114 is located on the outer circumferential side of the edge of the opening 122. The impurity concentration of the high concentration region 115 is 1.0×10 16 cm -3 ~1.0×10 20 cm -3 cm -3 Because the distance θ is within this range, holes and other impurities generated in the semiconductor substrate 110, including the peripheral region A2, are collected by recombination centers during switching on and off, thereby reducing the amount of current reaching the surface electrode 130. This reduces the current density near the area where the current density of the current flowing from the element formation region A1 to the surface electrode 130 via the p-type impurity region 113 overlaps with the current density of the current flowing from the peripheral impurity region 114 to the p-type impurity region 113 and then to the surface electrode 130, thereby suppressing temperature rise. This results in an increased breakdown voltage. Furthermore, because the current density in the element formation region A1 can be reduced, the breakdown voltage can be maintained even if the peripheral impurity region 114 and the surface electrode 130 do not contact each other. Furthermore, because the peripheral impurity region 114 and the surface electrode 130 do not contact each other, a sudden increase in recovery current can be suppressed, improving recovery characteristics and suppressing an increase in recovery loss.

[0038] Furthermore, in the semiconductor device 101 according to the second embodiment, the p-type impurity region 113 extends to the outer periphery of the opening 122, so that holes flow from the peripheral impurity region 114 (high concentration region 115) to the front surface electrode 130 via the relatively low concentration p-type impurity region 113. This makes it possible to improve the recovery characteristics and suppress an increase in recovery loss.

[0039] The semiconductor device 101 of embodiment 2 has the same configuration as the semiconductor device 100 of embodiment 1 except for the position of the inner end of the peripheral impurity region on the surface of the semiconductor substrate, and therefore has the corresponding effects of the semiconductor device 100 of embodiment 1.

[0040] Although the present invention has been described above based on the above embodiment, the present invention is not limited to the above embodiment and can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0041] (1) The positions, connections, numbers, etc. described in the above embodiments (including each modified example; the same applies below) are examples and can be changed within the scope that does not impair the effects of the present invention.

[0042] (2) In the second embodiment, the inner peripheral edge of the peripheral impurity region 114 on the surface of the semiconductor substrate 110 is located on the outer peripheral side of the edge of the opening 122. However, the present invention is not limited to this. The inner peripheral edge of the peripheral impurity region 114 on the surface of the semiconductor substrate 110 may be located at the same position as the edge of the opening 122 in the horizontal direction.

[0043] (3) In the above embodiments, a diode is used as the semiconductor device, but the present invention is not limited to this. The semiconductor device may be a MOSFET or any other suitable semiconductor device.

[0044] (4) In the above embodiments, the high-concentration region is formed only in the region where the p-type impurity region and the peripheral impurity region overlap, but the present invention is not limited to this. The high-concentration region may also be formed in the second-conductivity-type impurity region in a region other than the overlapping region. However, making the entire second-conductivity-type impurity region a high-concentration region is not preferable in terms of recovery characteristics, and it is preferable to have a region other than the high-concentration region.

[0045] (5) In each of the above embodiments, the impurity concentration in the drift region is set to 1.0×10 13 cm -3 ~1.0×10 15 cm -3 However, the present invention is not limited to this range, and the present invention can be applied to impurity concentrations other than this range.

[0046] (6) In each of the above embodiments, a p-type guard ring region may be formed on the outer periphery of the peripheral impurity region 114. The number of p-type guard ring regions may be multiple. In addition, the depth of the guard ring is preferably the same as the depth of the peripheral impurity region 114.

[0047] (7) In each of the above embodiments, the outer peripheral edge of the p-type impurity region 113 is located inside the inner peripheral edge A of the insulating layer 120, but the present invention is not limited to this. The outer peripheral edge of the p-type impurity region 113 may be located outside the inner peripheral edge A of the insulating layer 120 (see FIG. 6). [Explanation of symbols]

[0048] 100,101,900... semiconductor device, 110,910... semiconductor substrate, 111,911... low-resistance semiconductor region, 112,912... drift region, 113,913... p-type impurity region, 114,914... peripheral impurity region, 115,915... high-concentration region, 116,916... channel stop region, 120,920... insulating layer, 122,922... opening, 130,930... surface electrode, 132... EQR electrode, 140,940... back electrode, 150,950... protective insulating film, A1... element formation region, A2... peripheral region

Claims

1. a semiconductor substrate; an insulating layer formed on the surface of the semiconductor substrate and having an opening exposing the surface of the semiconductor substrate; a surface electrode connected to the semiconductor substrate in the opening; The semiconductor substrate is a drift region of a first conductivity type; a second conductivity type impurity region formed in a surface layer portion of the drift region; a second conductivity type peripheral impurity region formed in a peripheral portion of the second conductivity type impurity region in a surface layer portion of the drift region, the peripheral impurity region having a region overlapping with the second conductivity type impurity region, and having an impurity concentration higher than that of the second conductivity type impurity region; the second conductivity type impurity region is formed at least in a portion overlapping with the peripheral impurity region, and has a high concentration region having an impurity concentration higher than that of other regions of the second conductivity type impurity region; Recombination centers are formed within the semiconductor substrate, an inner peripheral edge of the peripheral impurity region on the surface of the semiconductor substrate is located on the inner peripheral side of the edge of the opening, a length from an inner peripheral edge of the peripheral impurity region to an edge of the opening is 0.01 μm or more and less than 30 μm; a second conductivity type impurity region having a second conductivity type, the second conductivity type impurity region being formed on the inner periphery side of the opening;

2. 2. The semiconductor device according to claim 1, wherein the high concentration region is formed only in a region where the second conductivity type impurity region and the peripheral impurity region overlap.

3. The impurity concentration of the drift region is 1.0×10 １３ cm －３ ~1.0 x 10 １５ cm －３ 2. The semiconductor device according to claim 1, wherein the semiconductor device is in the range of .gtoreq..times ...

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