Semiconductor Devices

Abstract

This semiconductor device comprises: a semiconductor layer having a main surface; a first conductive-type well region formed on a surface layer portion of the main surface of the semiconductor layer; a first conductive-type first impurity region formed on a surface layer portion of the well region and having an inner wall portion; and a second conductive-type annular second impurity region formed on the surface layer portion of the well region inside the inner wall part so as to form a pn junction with the well region.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 listed below discloses a protection circuit having a diode for protecting circuit elements such as transistors and capacitors that constitute an integrated circuit (IC) from electrostatic discharge (ESD). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73594 Summary of the Invention [Problem to be solved by the invention]

[0004] Diodes used in protection circuits are required to have low capacitance, so one approach to reducing capacitance is to make the diodes smaller, but this can lead to a decrease in ESD resistance.

[0005] Therefore, one object of the present invention is to provide a semiconductor device that can reduce the electrostatic capacitance and prevent a decrease in ESD resistance. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a semiconductor layer having a main surface, a well region of a first conductivity type formed in a surface portion of the main surface of the semiconductor layer, a first impurity region of the first conductivity type formed in the surface portion of the well region and having an inner wall portion, and a ring-shaped second impurity region of a second conductivity type formed in the surface portion of the well region inside the inner wall portion so as to form a pn junction between the well region and the first impurity region.

[0007] According to this configuration, the well region and the second impurity region form a pn junction, so that charge is stored near the interface between the second impurity region and the well region. According to the above configuration, the second impurity region is annular. Therefore, compared to a configuration in which the second impurity region is not annular in plan view, but is, for example, circular, the area of ​​the interface between the second impurity region and the well region can be reduced. Therefore, the capacitance can be reduced.

[0008] The ESD current is dominated by the portion of the second impurity region closer to the first impurity region. Specifically, the contribution of the portion of the second impurity region farther from the first impurity region to the ESD current capability is much smaller than the contribution of the portion of the second impurity region closer to the first impurity region to the ESD current capability.

[0009] Therefore, if the second impurity region is annular, it is possible to ensure the same ESD current capability as a configuration in which the second impurity region has a circular shape in plan view. Therefore, it is possible to prevent a decrease in the ESD current capability. In other words, it is possible to prevent a decrease in ESD resistance.

[0010] In this way, if the second impurity region is annular, it is possible to suppress a decrease in ESD resistance and reduce the electrostatic capacitance.

[0011] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a plan view of a protection element and its periphery provided in the semiconductor device. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. [Figure 4]FIG. 4 is an enlarged view of region IV shown in FIG. [Figure 5] FIG. 5 is an enlarged view of the V region shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. [Figure 7] FIG. 7 is an enlarged view of region VII shown in FIG. [Figure 8] FIG. 8 is an enlarged view of region VIII shown in FIG. [Figure 9] FIG. 9 is a schematic diagram of an electric circuit of the semiconductor device shown in FIG. [Figure 10A] FIG. 10A is a schematic diagram for explaining how charges are stored in the first diode included in the protection element. [Figure 10B] FIG. 10B is a schematic diagram for explaining how an ESD current flows through the first diode. [Figure 11A] FIG. 11A is a schematic diagram for explaining how charges are stored in the second diode provided in the protection element. [Figure 11B] FIG. 11B is a schematic diagram for explaining how an ESD current flows through the second diode. [Figure 12] FIG. 12 is a plan view of the diode of the first modified example. [Figure 13] FIG. 13 is a plan view of a diode according to the second modification. [Figure 14] FIG. 14 is a plan view of a diode according to the third modification. [Figure 15] FIG. 15 is a plan view of a diode according to the fourth modification. [Figure 16A] FIG. 16A is a schematic diagram for explaining how charges are accumulated in the diode of the first reference example. [Figure 16B] FIG. 16B is a schematic diagram for explaining how an ESD current flows through the diode of the first reference example. [Figure 17A] FIG. 17A is a schematic diagram for explaining how charges are accumulated in the diode of the second reference example. [Figure 17B]FIG. 17B is a schematic diagram for explaining how an ESD current flows through the diode of the second reference example. DETAILED DESCRIPTION OF THE INVENTION

[0013] 1 is a plan view of an IC chip 1 as a semiconductor device according to one embodiment of the present invention. The IC chip 1 has a substantially cubic shape. The IC chip 1 includes a plurality of input / output wirings 2 for inputting and outputting signals from the outside, an internal circuit 3 as a protected element electrically connected to the plurality of input / output wirings 2, and a plurality of protection elements 4 for protecting the internal circuit 3 from overvoltage due to, for example, ESD. In this embodiment, the protection elements 4 are elements for protecting the internal circuit 3 mainly from ESD input to the input / output wirings 2, and therefore may also be referred to as, for example, ESD protection elements.

[0014] The IC chip 1 further includes a first power supply wiring 5 to which a first power supply voltage (e.g., 5 V) is applied, a second power supply wiring 6 to which a second power supply voltage (e.g., a reference voltage) is applied, and a plurality of pads respectively connected to the plurality of wirings (the plurality of input / output wirings 2, the first power supply wiring 5, and the second power supply wiring 6).

[0015] In FIG. 1, for the sake of convenience, the input / output wiring 2, the first power supply wiring 5, and the second power supply wiring 6 are shown by solid lines, but this does not mean that these components appear on the surface of the IC chip 1.

[0016] The multiple pads include multiple input / output pads 7 electrically connected to the multiple input / output wirings 2, a first power supply pad 8 electrically connected to the first power supply wiring 5, and a second power supply pad 9 electrically connected to the second power supply wiring 6. A connecting member (not shown) such as a bonding wire is connected to each pad (each input / output pad 7, first power supply pad 8, and second power supply pad 9).

[0017] The first power supply wiring 5 includes, in a plan view, a first annular power supply wiring 5A that extends in a substantially annular shape so as to surround the internal circuit 3, and a first connection wiring 5B that is electrically connected to the first annular power supply wiring 5A, the first power supply pad 8, and the internal circuit 3.

[0018] The second power supply wiring 6 includes, in a plan view, a second annular power supply wiring 6A that extends in a substantially annular shape so as to surround the internal circuit 3 outside the first power supply wiring 5, and a second connection wiring 6B that is electrically connected to the second annular power supply wiring 6A, the second power supply pad 9, and the internal circuit 3.

[0019] Each protection element 4 is arranged at a position overlapping with the first annular power supply wiring 5A of the first power supply wiring 5 and the second annular power supply wiring 6A of the second power supply wiring 6 in a planar view. Each protection element 4 includes a plurality of first protection elements 4A electrically connected to the first power supply wiring 5 and the input / output wiring 2, and a second protection element 4B electrically connected to the second power supply wiring 6 and the input / output wiring 2. In each protection element 4, the first protection element 4A is arranged at a position overlapping with the first annular power supply wiring 5A of the first power supply wiring 5 in a planar view, and the second protection element 4B is arranged at a position overlapping with the second annular power supply wiring 6A of the second power supply wiring 6 in a planar view.

[0020] The IC chip 1 further includes a large-capacity protection element 95 having a larger capacitance than the protection element 4. The large-capacity protection element 95 is configured, for example, by an NMOS (Negative-channel Metal Oxide Semiconductor) transistor and a diode.

[0021] In this embodiment, a plurality of large-capacity protection elements 95 are provided. The plurality of large-capacity protection elements 95 are arranged in positions overlapping with the first annular power supply wiring 5A of the first power supply wiring 5 and the second annular power supply wiring 6A of the second power supply wiring 6 in a planar view. The plurality of large-capacity protection elements 95 include a plurality of first large-capacity protection elements 95A arranged in positions not overlapping with the first connection wiring 5B and the second connection wiring 6B in a planar view, a second large-capacity protection element 95B arranged in a position overlapping with the first connection wiring 5B of the first power supply wiring 5 in a planar view, and a third large-capacity protection element 95C arranged in a position overlapping with the second connection wiring 6B of the second power supply wiring 6 in a planar view.

[0022] FIG. 2 is a plan view of the protection element 4 and its surroundings.

[0023] In Figure 2, the first contact electrode 67A, second contact electrode 72A, third contact electrode 67B, fourth contact electrode 72B, first connection structure 65A, second connection structure 70A, third connection structure 65B, fourth connection structure 70B, first interlayer insulating film 60A and second interlayer insulating film 60B, which will be described later, have been removed.

[0024] The protection element 4 has a semiconductor layer 10 and a region partition structure 15 that partitions a first active region 8A in which the first protection element 4A is formed and a second active region 8B in which the second protection element 4B is formed.

[0025] The semiconductor layer 10 is made of, for example, single crystal Si. The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side (see FIGS. 3 and 6 described later).

[0026] The region partitioning structure 15 includes a first element isolation portion 16A that is endless in plan view and surrounds the first active region 8A, and a second element isolation portion 16B that is endless in plan view and surrounds the second active region 8B. In this embodiment, the first element isolation portion 16A and the second element isolation portion 16B are formed in a rectangular ring shape in plan view (hereinafter simply referred to as "plan view") as seen from the normal direction Z of the first main surface 11 and the second main surface 12 (see also FIG. 3). The first active region 8A and the second active region 8B are each partitioned by the region partitioning structure 15 into a rectangular shape in plan view.

[0027] 2, the first element isolation portion 16A and the second element isolation portion 16B of the region partition structure 15 are integrally formed between the first active region 8A and the second active region 8B. The integrally formed first element isolation portion 16A and second element isolation portion 16B are formed as an isolation portion 17 that separates the first active region 8A and the second active region 8B.

[0028] Unlike the example shown in Figure 1, when the first element isolation portion 16A and the second element isolation portion 16B are formed with a gap between them, the isolation portion 17 of the region partition structure 15 is composed of the first element isolation portion 16A and the second element isolation portion 16B that face each other across a portion of the semiconductor layer 10.

[0029] The direction in which one side of the first element isolation portion 16A extends in a plan view is defined as a first direction X. The direction perpendicular to both the first direction X and the normal direction Z is defined as a second direction Y. In this embodiment, the first active region 8A and the second active region 8B face each other in the first direction X.

[0030] The region defining structure 15 includes a trench 18 formed by digging the first main surface 11 toward the second main surface 12, and an insulating filling material 19 filled in the trench 18. The insulating filling material 19 may be made of any insulator. The insulating filling material 19 may include at least one of silicon oxide (SiO2) and silicon nitride (SiN). In this embodiment, the insulating filling material 19 is made of silicon oxide.

[0031] Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 2. Fig. 4 is an enlarged view of region IV shown in Fig. 3. Fig. 5 is an enlarged view of region V shown in Fig. 2.

[0032] 3, the semiconductor layer 10 includes an n-type first well region 20A formed in a surface layer portion of the first main surface 11 in the first active region 8A. The first main surface 11 in the first active region 8A is also the surface of the first well region 20A.

[0033] As the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), etc. are used. The n-type impurity concentration of the first well region 20A is 1.0×10 15 cm -3 Over 1.0x10 18 cm -3 The thickness TW1 of the first well region 20A is, for example, not less than 1 μm and not more than 1.4 μm, and preferably 1.4 μm.

[0034] The first protection element 4A includes a plurality (six in this embodiment) of n-type (first conductivity type) first n-type impurity regions 30A (first impurity regions) formed in a surface layer portion of the surface of the first well region 20A, and a plurality (six in this embodiment) of p-type (second conductivity type) first p-type impurity regions 40A (second impurity regions) formed in a surface layer portion of the surface of the first well region 20A (see also FIG. 2). In FIG. 2, a plurality of regions in the n-type impurity region surrounding the plurality of first p-type impurity regions 40A are defined as first n-type impurity regions 30A. In FIG. 2, the plurality of first n-type impurity regions 30A are connected to form an integrated unit. However, unlike the example shown in FIG. 2, the first n-type impurity regions 30A may be separated from each other by an insulating film or the like. The number of first p-type impurity regions 40A is the same as the number of first n-type impurity regions 30A.

[0035] 3 and 4, the n-type impurity concentration of each first n-type impurity region 30A is, for example, 10×10 17 cm -3 Over 10x10 20 cm -3 The n-type impurity may be, for example, N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), etc. The thickness T1 of the first n-type impurity region 30A is, for example, 140 nm.

[0036] The first n-type impurity region 30A has a first inner wall portion 31A having a circular shape in a plan view, and a first bottom wall portion 32A that is connected to the first inner wall portion 31A and in contact with the first well region 20A. The first bottom wall portion 32A includes a curved portion that protrudes to the side opposite to the first main surface 11 of the semiconductor layer 10, and a flat portion that connects the curved portions together.

[0037] Each first p-type impurity region 40A is located inside the corresponding first inner wall portion 31A. That is, each first p-type impurity region 40A faces the corresponding first n-type impurity region 30A with a gap therebetween. Each first p-type impurity region 40A is formed in an endless ring shape. In the example of FIG. 2, each first p-type impurity region 40A is formed in a circular ring shape in a plan view.

[0038] The p-type impurity concentration of each first p-type impurity region 40A is, for example, 10×10 17 cm -3 Over 10x10 20 cm -3 The p-type impurity may be, for example, B (boron), Al (aluminum), or BF2 (a compound containing boron and fluorine). The thickness T2 of the first p-type impurity region 40A is greater than the thickness T1 of the first n-type impurity region 30A. The thickness T2 of each first p-type impurity region 40A is, for example, 180 nm.

[0039] The first protection element 4A includes a first intermediate insulating layer 35A located between the first n-type impurity region 30A and the first p-type impurity region 40A, and a first inner insulating layer 36A located inside the first p-type impurity region 40A.

[0040] The first intermediate insulating layer 35A is embedded in a first intermediate trench 37A formed by digging down the first main surface 11 toward the second main surface 12. The first intermediate insulating layer 35A may be made of any insulator. The first intermediate insulating layer 35A may contain at least one of silicon oxide and silicon nitride.

[0041] The first inner insulating layer 36A is embedded in a first inner trench 38A formed by digging down the first main surface 11 toward the second main surface 12. The first inner insulating layer 36A may be made of any insulator. The first inner insulating layer 36A may include at least one of silicon oxide and silicon nitride.

[0042] The first p-type impurity region 40A has a first outer wall 41A in contact with the first intermediate insulating layer 35A and facing the first inner wall portion 31A via the first intermediate insulating layer 35A, a first inner wall 42A in contact with the first inner insulating layer 36A, and a first bottom sidewall 43A connecting the first outer wall 41A and the first inner wall 42A.

[0043] The first outer sidewall 41A is surrounded by the first intermediate insulating layer 35A and is in contact with the first intermediate insulating layer 35A. The first inner sidewall 42A surrounds the first inner insulating layer 36A and is in contact with the first inner insulating layer 36A. The first bottom sidewall 43A is in contact with the first well region 20A. The first bottom sidewall 43A includes an outer curved portion and an inner curved portion that protrude toward the side opposite the first main surface 11 of the semiconductor layer 10, and a flat portion that connects the outer curved portion and the inner curved portion.

[0044] The first p-type impurity region 40A forms a p-n junction PJ1 with the first well region 20A. The p-n junction PJ1 is formed near the contact interface between the first p-type impurity region 40A and the first well region 20A. More specifically, the p-n junction PJ1 is formed at the contact interface between the first bottom sidewall 43A and the first well region 20A.

[0045] 5, the first inner wall portion 31A of the first n-type impurity region 30A and the first outer wall 41A of the corresponding first p-type impurity region 40A extend parallel to each other. A distance L1 between the first inner wall portion 31A of the first n-type impurity region 30A and the first outer wall 41A of the corresponding first p-type impurity region 40A is constant along the circumferential direction of the first inner wall portion 31A (which is also the circumferential direction of the first outer wall 41A). Furthermore, a distance L2 between the first inner wall 42A of the first p-type impurity region 40A and the first outer wall 41A (the width of the first bottom sidewall 43A of the first p-type impurity region 40A) is also constant along the circumferential direction of the first inner wall 42A.

[0046] The first well region 20A, the first n-type impurity region 30A, and the first p-type impurity region 40A form a first diode 50A. In the first active region 8A, the first diodes 50A are formed in the same number as the first p-type impurity regions 40A, i.e., a plurality of first diodes 50A are formed (see FIG. 2). In the example of FIG. 2, six first diodes 50A are provided.

[0047] The first protection element 4A further includes a plurality of (five in the example of FIG. 3) first interlayer insulating films 60A stacked on the first main surface 11 of the semiconductor layer .

[0048] The first annular power supply wiring 5A is formed on one of the plurality of first interlayer insulating films 60A so as to be in contact with the first interlayer insulating film 60A. The input / output wiring 2 is formed on a different first interlayer insulating film 60A from the first power supply wiring 5 so as to be in contact with the first interlayer insulating film 60A. In the example of FIG. 3, the first annular power supply wiring 5A is formed on the first interlayer insulating film 60A that is farthest from the first main surface 11, and the input / output wiring 2 is formed on the third first interlayer insulating film 60A from the first main surface 11.

[0049] The first n-type impurity region 30A of the first protection element 4A is electrically connected to the first power supply wiring 5, and the first p-type impurity region 40A of the first protection element 4A is electrically connected to the input / output wiring 2. In detail, the first protection element 4A further includes a first connection structure 65A that electrically connects the first n-type impurity region 30A and the first annular power supply wiring 5A, and a second connection structure 70A that electrically connects the first p-type impurity region 40A and the input / output wiring 2.

[0050] The first connection structure 65A includes a plurality of first via holes 66A that penetrate any of the plurality of first interlayer insulating films 60A, a plurality of first contact electrodes 67A that are embedded in each of the plurality of first via holes 66A, and a plurality of first connection wirings 68A that are formed on the first interlayer insulating film 60A and connect the plurality of first contact electrodes 67A to each other.

[0051] The second connection structure 70A includes a plurality of second via holes 71A that penetrate any of the plurality of first interlayer insulating films 60A, a plurality of second contact electrodes 72A that are embedded in each of the plurality of second via holes 71A, and a plurality of second connection wirings 73A that are formed on the first interlayer insulating film 60A and connect the plurality of second contact electrodes 72A to each other.

[0052] The multiple second contact electrodes 72A formed in the first interlayer insulating film 60A in contact with the first main surface 11 are located between the first inner sidewall 42A and the first outer sidewall 41A in a plan view (see FIG. 5). The multiple second contact electrodes 72A formed in the first interlayer insulating film 60A in contact with the first main surface 11 are arranged at equal intervals along the outer shape (first outer sidewall 41A) of the first p-type impurity region 40A.

[0053] Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 2. Fig. 7 is an enlarged view of region VII shown in Fig. 6. Fig. 8 is an enlarged view of region VIII shown in Fig. 2.

[0054] 6, the semiconductor layer 10 further includes a p-type second well region 20B formed in a surface layer portion of the first main surface 11 in the second active region 8B. The first main surface 11 in the second active region 8B is also the surface of the second well region 20B. Examples of p-type impurities that can be used include B (boron), Al (aluminum), and BF2 (a compound containing boron and fluorine). The p-type impurity concentration in the second well region 20B is 1.0×10 15 cm -3 Over 1.0x10 18 cm -3 The thickness TW2 of the second well region 20B is, for example, not less than 1 μm and not more than 1.4 μm, and preferably 1.0 μm.

[0055] The second protection element 4B includes a plurality of second p-type impurity regions 30B (first impurity regions) of p-type (first conductivity type) formed in a surface layer portion of the surface of the second well region 20B, and a plurality of second n-type impurity regions 40B (second impurity regions) of n-type (second conductivity type) formed in a surface layer portion of the surface of the second well region 20B. The number of second n-type impurity regions 40B is the same as the number of second p-type impurity regions 30B (see FIG. 2). In FIG. 2, a plurality of regions in the p-type impurity region surrounding the plurality of second n-type impurity regions 40B are each defined as a second p-type impurity region 30B. In FIG. 2, the plurality of second p-type impurity regions 30B are connected to form an integrated structure. However, unlike the example shown in FIG. 2, the second p-type impurity regions 30B may be separated from each other by an insulating film or the like.

[0056] 6 and 7, the p-type impurity concentration of each second p-type impurity region 30B is, for example, 10×10 17 cm -3 Over 10x10 20 cm -3 The p-type impurity may be, for example, B (boron), Al (aluminum), or BF2 (a compound containing boron and fluorine). The second p-type impurity region 30B has a thickness T3 of, for example, 180 nm.

[0057] The second p-type impurity region 30B has a second inner wall portion 31B having a circular shape in a plan view, and a second bottom wall portion 32B that is connected to the second inner wall portion 31B and in contact with the second well region 20B. The second bottom wall portion 32B includes a curved portion that protrudes to the side opposite to the first main surface 11 of the semiconductor layer 10, and a flat portion that connects the curved portions together.

[0058] Each second n-type impurity region 40B is located more inward than the corresponding second inner wall portion 31B. That is, each second n-type impurity region 40B faces the corresponding second p-type impurity region 30B across an interval. Each second n-type impurity region 40B is formed in an endless ring shape. In the example of FIG. 2, each second n-type impurity region 40B is formed in a circular ring shape in a plan view.

[0059] The p-type impurity concentration of each second n-type impurity region 40B is, for example, 10×10 17 cm -3 Over 10x10 20 cm -3 The following is true. Examples of n-type impurities include nitrogen (N), phosphorus (P), and arsenic (As). The thickness T4 of the second n-type impurity region 40B is smaller than the thickness T3 of the second p-type impurity region 30B. The thickness T4 of each second n-type impurity region 40B is, for example, 140 nm.

[0060] The second protection element 4B includes a second intermediate insulating layer 35B located between the second p-type impurity region 30B and the second n-type impurity region 40B, and a second inner insulating layer 36B located inside the second n-type impurity region 40B.

[0061] The second intermediate insulating layer 35B is embedded in a second intermediate trench 37B formed by digging down the first main surface 11 toward the second main surface 12. The second intermediate insulating layer 35B may be made of any insulator. The second intermediate insulating layer 35B may contain at least one of silicon oxide and silicon nitride.

[0062] The second inner insulating layer 36B is embedded in a second inner trench 38B formed by digging down the first main surface 11 toward the second main surface 12. The second inner insulating layer 36B may be made of any insulator. The second inner insulating layer 36B may include at least one of silicon oxide and silicon nitride.

[0063] The second n-type impurity region 40B has a second outer wall 41B in contact with the second intermediate insulating layer 35B and facing the second inner wall portion 31B via the second intermediate insulating layer 35B, a second inner wall 42B in contact with the second inner insulating layer 36B, and a second bottom side wall 43B connecting the second outer wall 41B and the second inner wall 42B.

[0064] The second outer sidewall 41B is surrounded by the second intermediate insulating layer 35B and is in contact with the second intermediate insulating layer 35B. The second inner sidewall 42B surrounds the second inner insulating layer 36B and is in contact with the second inner insulating layer 36B. The second bottom sidewall 43B is in contact with the second well region 20B. The second bottom sidewall 43B includes an outer curved portion and an inner curved portion that protrude toward the side opposite the first main surface 11 of the semiconductor layer 10, and a flat portion that connects the outer curved portion and the inner curved portion.

[0065] The second n-type impurity region 40B forms a pn junction PJ2 with the second well region 20B. The pn junction PJ2 is formed near the contact interface between the second n-type impurity region 40B and the second well region 20B. More specifically, the pn junction PJ2 is formed at the contact interface between the second bottom sidewall 43B and the second well region 20B.

[0066] 8, the second inner wall portion 31B of the second p-type impurity region 30B and the second outer wall 41B of the corresponding second n-type impurity region 40B extend parallel to each other. A distance L3 between the second inner wall portion 31B of the second p-type impurity region 30B and the second outer wall 41B of the corresponding second n-type impurity region 40B is constant along the circumferential direction of the second inner wall portion 31B (which is also the circumferential direction of the second outer wall 41B). Furthermore, a distance L4 between the second inner wall 42B of the second n-type impurity region 40B and the second outer wall 41B (the width of the second bottom sidewall 43B of the second n-type impurity region 40B) is also constant along the circumferential direction of the second inner wall 42B.

[0067] In the second well region 20B, second diodes 50B are formed by a plurality of second p-type impurity regions 30B and second n-type impurity regions 40B. In the second active region 8B, the number of second diodes 50B is the same as the number of second n-type impurity regions 40B, i.e., a plurality of second diodes 50B are formed (see FIG. 2). In the example of FIG. 2, six second diodes 50B are provided.

[0068] The second protection element 4B further includes a plurality of (five in the example of FIG. 6) second interlayer insulating films 60B stacked on the first main surface 11 of the semiconductor layer .

[0069] The second annular power supply wiring 6A is formed on one of the plurality of second interlayer insulating films 60B so as to be in contact with the second interlayer insulating film 60B. The input / output wiring 2 is formed on the second interlayer insulating film 60B so as to be in contact with the second interlayer insulating film 60B different from the second power supply wiring 6. In the example of FIG. 6, the second annular power supply wiring 6A is formed on the second interlayer insulating film 60B that is farthest from the first main surface 11, and the input / output wiring 2 is formed on the second interlayer insulating film 60B that is the third layer from the first main surface 11.

[0070] The second n-type impurity region 40B of the second protection element 4B is electrically connected to the input / output wiring 2, and the second p-type impurity region 30B of the second protection element 4B is electrically connected to the second power supply wiring 6. In detail, the second protection element 4B further includes a third connection structure 65B that electrically connects the second p-type impurity region 30B and the second power supply wiring 6, and a fourth connection structure 70B that electrically connects the second n-type impurity region 40B and the input / output wiring 2.

[0071] The third connection structure 65B includes a plurality of third via holes 66B that penetrate any of the plurality of second interlayer insulating films 60B, a plurality of third contact electrodes 67B that are embedded in each of the plurality of third via holes 66B, and a plurality of third connection wirings 68B that are formed on the second interlayer insulating film 60B and connect the third contact electrodes 67B to each other.

[0072] The fourth connection structure 70B includes a plurality of fourth via holes 71B that penetrate any of the plurality of second interlayer insulating films 60B, a plurality of fourth contact electrodes 72B that are embedded in each of the plurality of fourth via holes 71B, and a plurality of fourth connection wirings 73B that are formed on the second interlayer insulating film 60B and connect the fourth contact electrodes 72B to each other.

[0073] The multiple fourth contact electrodes 72B formed in the second interlayer insulating film 60B in contact with the first main surface 11 are located between the second inner wall 42B and the second outer wall 41B in a plan view (see FIG. 8). The multiple fourth contact electrodes 72B formed in the second interlayer insulating film 60B in contact with the first main surface 11 are arranged at equal intervals along the outer shape (second outer wall 41B) of the first p-type impurity region 40A.

[0074] FIG. 9 is a schematic diagram of the electric circuit of the IC chip 1 shown in FIG.

[0075] A signal input to the input / output pad 7 is input to the internal circuit 3 via the input / output wiring 2. A signal output from the internal circuit 3 is output from the input / output pad 7 via the input / output wiring 2 to the outside.

[0076] An overvoltage due to ESD or the like may be input to the input / output pad 7. If the overvoltage input to the input / output pad 7 is a positive overvoltage, the potential of the input / output pad 7 increases. This causes the first protection element 4A to operate in the forward direction, causing an ESD current to flow through the first power supply wiring 5. As a result, the internal circuit 3 is protected from the positive overvoltage.

[0077] If the overvoltage input to the I / O pad 7 is a negative overvoltage, the potential between the I / O pad 7 and the second power supply pad 9 decreases, causing the second protection element 4B to operate in the forward direction and causing the ESD current to flow through the second power supply wiring 6. As a result, the internal circuit 3 is protected from the negative overvoltage.

[0078] FIG. 10A is a schematic diagram for explaining how charges are stored in the first diode 50A of the first protection element 4A.

[0079] Since the first well region 20A and the first p-type impurity region 40A form a pn junction PJ1 (see FIG. 4), an electric charge E1 is accumulated near the interface between the first bottom sidewall 43A of the first p-type impurity region 40A and the first well region 20A.

[0080] Here, unlike this embodiment, a diode 100 of a first reference example is assumed in which the shape of a p-type impurity region 103 located inside an n-type impurity region 102 in the surface layer portion of the main surface of a well region 101 is not annular, but is, for example, circular in plan view, as shown in FIG. 16A.

[0081] In the first diode 50A according to the embodiment shown in FIG. 10A, the first p-type impurity region 40 has a circular ring shape in a planar view, and therefore the area of ​​the interface between the first p-type impurity region 40A and the first well region 20A can be reduced compared to the diode 100 of the first reference example shown in FIG. 16A.

[0082] Therefore, the charge E1 (see FIG. 10A) accumulated near the interface between the first p-type impurity region 40A and the first well region 20A is smaller than the charge E01 (see FIG. 16A) accumulated near the interface between the p-type impurity region 103 and the well region 101 of the diode 100 of the first reference example. Therefore, the capacitance of the first diode 50A is smaller than the capacitance of the diode 100 of the first reference example.

[0083] In particular, if the thickness T2 of the first p-type impurity region 40A is smaller than the width W1 of the first p-type impurity region 40A in a planar view, the increase in the area of ​​the interface between the first p-type impurity region 40A and the first well region 20A can be reduced. Therefore, the capacitance can be further reduced. If the first p-type impurity region 40A has a circular shape in a planar view, the width W1 of the first p-type impurity region 40A is the outer diameter of the first p-type impurity region 40A.

[0084] FIG. 10B is a schematic diagram for explaining how an ESD current flows through the first diode 50A.

[0085] The ESD current C1 flows through a portion of the first p-type impurity region 40A that contacts the first well region 20A. The ESD current C1 is dominant in a portion of the first p-type impurity region 40A that is close to the first n-type impurity region 30A. Specifically, the contribution of the portion of the first p-type impurity region 40A that is far from the first n-type impurity region 30A to the ESD current capability is much smaller than the contribution of the portion of the first p-type impurity region 40A that is close to the first n-type impurity region 30A to the ESD current capability. In other words, the amount of current in the portion of the first p-type impurity region 40A that is far from the first n-type impurity region 30A is smaller than the amount of current in the portion of the first p-type impurity region 40A that is close to the first n-type impurity region 30A.

[0086] Therefore, if the first p-type impurity region 40A has a ring-shaped planar configuration as shown in FIG. 10B, the portion of the first p-type impurity region 40A close to the first n-type impurity region 30A can maintain contact with the first well region 20A, thereby improving the ESD current C1 per capacitance, i.e., the efficiency. Therefore, an ESD current capability equivalent to that of the configuration shown in FIG. 16B in which the p-type impurity region 103 has a circular shape in a planar configuration can be ensured. Therefore, even if the first p-type impurity region 40A has a ring-shaped configuration, a sufficient ESD current capability can be ensured. In other words, a decrease in ESD resistance can be suppressed.

[0087] In the diode 100 of the first reference example shown in FIG. 16B, the contact interface between the central portion of the p-type impurity region 103, which is circular in plan view, and the well region 101 has almost no effect on the ESD resistance.

[0088] In this way, if the first p-type impurity region 40 has a ring shape, it is possible to suppress a decrease in ESD resistance and reduce the electrostatic capacitance.

[0089] FIG. 11A is a schematic diagram for explaining how charges are stored in the second diode 50 of the second protection element 4B.

[0090] Since the second well region 20B and the second n-type impurity region 40B form a pn junction PJ2 (see FIG. 7), an electric charge E2 is accumulated near the interface between the second bottom sidewall 43B of the second n-type impurity region 40B and the second well region 20B.

[0091] Here, unlike this embodiment, a diode 200 of a second reference example is considered in which the shape of the n-type impurity region 203 located inside the p-type impurity region 202 in the surface layer portion of the main surface of the well region 201 is not annular, but is, for example, circular in plan view, as shown in FIG. 17A.

[0092] In the second diode 50B according to the embodiment shown in FIG. 11A, the second n-type impurity region 40B has a circular ring shape in a planar view, and therefore the area of ​​the interface between the second n-type impurity region 40B and the second well region 20B can be reduced compared to the diode 200 of the second reference example shown in FIG. 17A.

[0093] Therefore, the charge E2 (see FIG. 11A) accumulated near the interface between the second n-type impurity region 40B and the second well region 20B is smaller than the charge E02 (see FIG. 17A) accumulated near the interface between the n-type impurity region 203 and the well region 201 of the diode 200 of the second reference example. Therefore, the capacitance of the second diode 50B is smaller than the capacitance of the diode 200 of the second reference example.

[0094] In particular, if the thickness T4 of the second n-type impurity region 40B is smaller than the width W2 of the second n-type impurity region 40B in a planar view, the increase in the area of ​​the interface between the second n-type impurity region 40B and the second well region 20B can be reduced. Therefore, the capacitance can be further reduced. If the second n-type impurity region 40B has a circular shape in a planar view, the width W2 of the second n-type impurity region 40B is the outer diameter of the second n-type impurity region 40B.

[0095] FIG. 11B is a schematic diagram for explaining how an ESD current flows through the second diode 50B.

[0096] Similar to the ESD current C1 in FIG. 10B, the ESD current C2 is dominant in the portion of the second n-type impurity region 40B close to the second p-type impurity region 30B. Therefore, if the second n-type impurity region 40B has a ring-like shape in plan view as shown in FIG. 11B, the portion of the second n-type impurity region 40B close to the second p-type impurity region 30B can maintain contact with the second well region 20B, thereby improving the ESD current C2 per capacitance, i.e., the efficiency. Therefore, an ESD current capability equivalent to that of the configuration in which the n-type impurity region 203 has a circular shape in plan view as shown in FIG. 17B can be ensured. Therefore, even if the second n-type impurity region 40B has a ring-like shape, a sufficient ESD current capability can be ensured. In other words, a decrease in ESD resistance can be suppressed.

[0097] In the diode 200 of the second reference example shown in FIG. 17B, the contact interface between the central portion of the n-type impurity region 203, which is circular in plan view, and the well region 201 has almost no effect on the ESD resistance.

[0098] In this way, if the second n-type impurity region 40B has a ring shape, it is possible to suppress a decrease in ESD resistance and reduce the electrostatic capacitance.

[0099] According to this embodiment, the first p-type impurity region 40A and the second n-type impurity region 40B are annular, which reduces the amount of charge in the first p-type impurity region 40A and the second n-type impurity region 40B connected to the input / output wiring 2. This improves the speed of the electrical signal input to the internal circuit 3.

[0100] Next, first to fifth modified examples of the diodes 50A and 50B of the protection element 4 according to this embodiment will be described.

[0101] Fig. 12 is a plan view of a first diode 50A of a first modified example. Unlike the first diode 50A shown in Fig. 6, the first diode 50A of the first modified example has a first p-type impurity region 40A that is annular with ends. The first p-type impurity region 40A has, for example, a C-shape.

[0102] Since the first p-type impurity region 40A has an annular shape with ends, the first intermediate insulating layer 35A and the first inner insulating layer 36A are connected by the connecting insulating layer 39A.

[0103] When the first p-type impurity region 40A has an annular shape with ends in a plan view, the width W1 of the first p-type impurity region 40A is the outer diameter of the first p-type impurity region 40A.

[0104] Although not shown, a similar modification can be applied to the second diode 50B. That is, the second n-type impurity region 40B may have an annular shape with ends (for example, a C-shape). In this case, the second intermediate insulating layer 35B and the second inner insulating layer 36B are connected by a connecting insulating layer.

[0105] Fig. 13 is a plan view of a first diode 50A of a second modified example, Fig. 14 is a plan view of a first diode 50A of a third modified example, and Fig. 15 is a plan view of a first diode 50A of a fourth modified example.

[0106] 13 to 15, the first p-type impurity region 40A may have a polygonal ring shape in plan view. Specifically, the first p-type impurity region 40A may have an octagonal ring shape as shown in FIG. 13, a hexagonal ring shape as shown in FIG. 14, or a square ring shape as shown in FIG. 15. The first p-type impurity region 40A may have a polygonal ring shape other than an octagonal ring, a hexagonal ring, or a square ring, such as a triangular ring. In the first diodes 50A of the second to fourth modifications, the first p-type impurity region 40A is an endless ring shape that surrounds the first inner insulating layer 36A in plan view.

[0107] When the first p-type impurity region 40A has a polygonal ring shape in plan view, if the multiple second contact electrodes 72A formed in the first interlayer insulating film 60A in contact with the first main surface 11 are arranged on the corners 40a of the first p-type impurity region 40A, ESD current may concentrate at the corners 40a. Therefore, in the first diodes 50A of the second to fourth modifications, the multiple second contact electrodes 72A are arranged along the outline 40b of the first p-type impurity region 40A in plan view so as to avoid the corners 40a of the first p-type impurity region 40A. This makes it possible to suppress the concentration of ESD current at the corners 40a of the first p-type impurity region 40A.

[0108] In the first diodes 50A of the second to fourth modifications, the width W1 of the first p-type impurity region 40A is the distance between a pair of sides extending parallel to each other in the outline of the first p-type impurity region 40A.

[0109] Although not shown, a similar modification can be applied to the second diode 50 B. That is, the second n-type impurity region 40 B may have a polygonal ring shape in a plan view.

[0110] The present invention can be embodied in still other forms.

[0111] For example, even when the first p-type impurity region 40A has a polygonal ring shape in plan view, as in the first diodes 50A of the second to fourth modifications, the first p-type impurity region 40A may have an end shape. The same applies to the modifications of the second diode 50B. That is, even when the second n-type impurity region 40B has a polygonal ring shape in plan view, the second n-type impurity region 40B may have an end shape.

[0112] The IC chip 1 according to the above-described embodiment can be used in ICs that handle relatively large currents, such as power supply ICs and ICs that control the drive of motors (motor drivers), and in electrical equipment that uses such ICs.

[0113] The semiconductor device according to the present invention can also be applied to various electrical devices, such as mobile communication devices such as mobile phones and PHS (Personal Handyphone System), and information processing devices such as personal computers, etc. The operation of such electrical devices is controlled by the IC chip 1 according to the above-described embodiment.

[0114] Moreover, unlike the above-described embodiment, the protection element 4 is not limited to a protection element that protects the internal circuitry of an IC chip, but can be used as a protection element that protects, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0115] In the above-described embodiment, each of the protection elements 4A and 4B is configured by a plurality of diodes 50A and 50B. However, each of the protection elements 4A and 4B may be configured by a single diode 50A and 50B.

[0116] Examples of features extracted from this specification and drawings are given below: [A1] to [A14] below provide a semiconductor device with a reduced barrier height.

[0117] [A1] a semiconductor device comprising: a semiconductor layer having a main surface; a well region of a first conductivity type formed in a surface portion of the main surface of the semiconductor layer; a first impurity region of the first conductivity type formed in the surface portion of the well region and having an inner wall portion; and a second annular impurity region of a second conductivity type formed in the surface portion of the well region on the inside of the inner wall portion so as to form a pn junction between the well region and the first impurity region.

[0118] According to this configuration, the well region and the second impurity region form a pn junction, so that charge is stored near the interface between the second impurity region and the well region. According to the above configuration, the second impurity region is annular. Therefore, compared to a configuration in which the second impurity region is not annular in plan view, but is, for example, circular, the area of ​​the interface between the second impurity region and the well region can be reduced. Therefore, the capacitance can be reduced.

[0119] Furthermore, if the second impurity region is annular, it is possible to ensure an ESD current capability equivalent to that of a configuration in which the second impurity region has a circular shape in plan view. Therefore, it is possible to prevent a decrease in the ESD current capability. In other words, it is possible to prevent a decrease in ESD resistance.

[0120] In this way, if the second impurity region is annular, it is possible to suppress a decrease in ESD resistance and reduce the electrostatic capacitance.

[0121] [A2] The semiconductor device according to A1, wherein the second impurity region has an outer wall facing the inner wall portion, an inner wall in contact with the well region, and a bottom sidewall connecting the outer wall and the inner wall.

[0122] [A3] the first impurity region has a bottom wall portion connected to the inner wall portion and in contact with the well region; The semiconductor device according to A2, wherein the bottom wall portion of the first impurity region is located closer to the main surface of the semiconductor layer than the bottom sidewall of the second impurity region.

[0123] [A4] The semiconductor device according to A2 or A3, further including an intermediate insulating layer located between the first impurity region and the second impurity region and in contact with the outer wall.

[0124] [A5] The semiconductor device according to any one of A2 to A4, further including an inner insulating layer located inside the second impurity region and in contact with the inner wall.

[0125] [A6] The semiconductor device according to any one of A1 to A5, wherein the thickness of the second impurity region is smaller than the width of the second impurity region in a plan view.

[0126] [A7] The semiconductor device according to any one of A1 to A6, wherein the second impurity region has a circular ring shape in a plan view.

[0127] [A8] The semiconductor device according to any one of A1 to A5, wherein the second impurity region has a polygonal ring shape in plan view.

[0128] [A9] The semiconductor device according to A8, further comprising: an insulating film formed on the semiconductor layer and having a plurality of via holes formed therein; and a plurality of contact electrodes formed in the plurality of via holes, respectively, and connected to the second impurity region, wherein the plurality of contact electrodes are arranged, in a planar view, along the outline of the second impurity region so as to avoid corners of the second impurity region.

[0129] [A10] The semiconductor device according to any one of A1 to A9, wherein the first impurity region is endless in plan view.

[0130] [A11] The semiconductor device according to any one of A1 to A10, further including a plurality of diodes formed by the well region, the first impurity region, and the second impurity region, and a region partition structure that partitions an active region in which the plurality of diodes are formed.

[0131] [A12] The semiconductor device according to A11, wherein the first impurity regions of the plurality of diodes are integrally formed.

[0132] [A13] The semiconductor device according to A11 or A12, including an input / output wiring for inputting or outputting a signal, a protected element connected to the input / output wiring, and a protection element formed by the diode for protecting the protected element from an overvoltage applied to the input / output wiring.

[0133] [A14] A semiconductor device according to A13, further including a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage lower than the first power supply voltage is applied, wherein the protection element includes a first protection element having the first impurity region electrically connected to the first power supply wiring and the second impurity region electrically connected to the input / output wiring, and a second protection element having the first impurity region electrically connected to the second power supply wiring and the second impurity region electrically connected to the input / output wiring.

[0134] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0135] This application corresponds to Patent Application No. 2020-215445 filed with the Japan Patent Office on December 24, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0136] 1: IC chip (semiconductor device) 2: Input / output wiring 3: Internal circuit (protected element) 4: Protective element 4A: First protection element 4B: Second protection element 5: 1st power supply wiring 6:Second power supply wiring 8A: First active area 8B: Second active area 10: Semiconductor layer 11: First main surface 15: Area division structure 30A: 1st n-type impurity region (1st impurity region) 30B: 2nd p-type impurity region (1st impurity region) 31A: 1st inner wall part 31B: Second inner wall part 32A: 1st bottom wall part 32B: 2nd bottom wall part 40A: 1st p-type impurity region (2nd impurity region) 40B: Second n-type impurity region (second impurity region) 41A: 1st outer wall 41B: 2nd outer wall 42A: First inner wall 42B: Second inner wall 43A: 1st bottom side wall 43B: 2nd bottom side wall 50A: First diode 50B: Second diode 60A: First interlayer insulating film 60B: Second interlayer insulating film 71A: Second via hole 71B: 4th beer hole 72A: Second contact electrode 72B: Fourth contact electrode PJ1 :pn junction PJ2 :pn junction T2: Thickness T4: Thickness

Claims

1. a semiconductor layer having a major surface; a first conductivity type well region formed in a surface layer portion of the main surface of the semiconductor layer; a first impurity region of a first conductivity type formed in a surface layer portion of the well region and having an inner wall portion; a second impurity region of a second conductivity type formed in a surface layer portion of the well region on the inner side of the inner wall portion so as to form a pn junction between the well region and the second impurity region; the second impurity region has an outer wall facing the inner wall portion, an inner wall in contact with the well region, and a bottom sidewall connecting the outer wall and the inner wall, the first impurity region has a bottom wall portion connected to the inner wall portion and in contact with the well region; a bottom wall portion of the first impurity region located closer to the main surface of the semiconductor layer than the bottom sidewall of the second impurity region;

2. 2. The semiconductor device according to claim 1, further comprising an intermediate insulating layer located between said first impurity region and said second impurity region and in contact with said outer sidewall.

3. 3. The semiconductor device according to claim 1, further comprising an inner insulating layer located inside said second impurity region and in contact with said inner wall.

4. 4. The semiconductor device according to claim 1, wherein the thickness of said second impurity region is smaller than the width of said second impurity region in a plan view.

5. 5. The semiconductor device according to claim 1, wherein the second impurity region has a circular ring shape in a plan view.

6. 4. The semiconductor device according to claim 1, wherein the second impurity region has a polygonal ring shape in a plan view.

7. an insulating film formed on the semiconductor layer and having a plurality of via holes; a plurality of contact electrodes formed in the plurality of via holes, respectively, and connected to the second impurity region; 7. The semiconductor device according to claim 6, wherein the plurality of contact electrodes are arranged along an outer shape of the second impurity region so as to avoid corners of the second impurity region in a plan view.

8. 8. The semiconductor device according to claim 1, wherein the first impurity region has an endless shape in a plan view.

9. a plurality of diodes formed by the well region, the first impurity region, and the second impurity region; 9. The semiconductor device according to claim 1, further comprising: a region defining structure defining an active region in which a plurality of said diodes are formed.

10. 10. The semiconductor device according to claim 9, wherein said first impurity regions of a plurality of said diodes are integrally formed.

11. Input / output wiring for inputting or outputting signals; a protected element connected to the input / output wiring; 11. The semiconductor device according to claim 9, further comprising a protection element formed by said diode, said protection element protecting said protected element from an overvoltage applied to said input / output wiring.

12. a first power supply wiring to which a first power supply voltage is applied; a second power supply wiring to which a second power supply voltage lower than the first power supply voltage is applied, 12. The semiconductor device according to claim 11, wherein the protection elements include a first protection element having the first impurity region electrically connected to the first power supply wiring and the second impurity region electrically connected to the input / output wiring, and a second protection element having the first impurity region electrically connected to the second power supply wiring and the second impurity region electrically connected to the input / output wiring.

13. a semiconductor layer having a major surface; a first conductivity type well region formed in a surface layer portion of the main surface of the semiconductor layer; a first impurity region of a first conductivity type formed in a surface layer portion of the well region and having an inner wall portion; a second impurity region of a second conductivity type formed in a surface layer portion of the well region on the inner side of the inner wall portion so as to form a pn junction between the well region and the second impurity region; the second impurity region has a polygonal ring shape in a plan view, an insulating film formed on the semiconductor layer and having a plurality of via holes; a plurality of contact electrodes formed in the plurality of via holes, respectively, and connected to the second impurity region; a plurality of the contact electrodes are arranged along an outer shape of the second impurity region so as to avoid corners of the second impurity region in a plan view;

14. a semiconductor layer having a major surface; a first conductivity type well region formed in a surface layer portion of the main surface of the semiconductor layer; a first impurity region of a first conductivity type formed in a surface layer portion of the well region and having an inner wall portion; a second impurity region of a second conductivity type formed in a surface layer portion of the well region on the inner side of the inner wall portion so as to form a pn junction between the well region and the second impurity region; one of the first impurity region and the second impurity region is an n-type impurity region, and the other is a p-type impurity region; a depth of the p-type impurity region in a cross-sectional view being greater than a depth of the n-type impurity region;

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