Power semiconductor devices

Abstract

To provide a power semiconductor device whose package is downsized.SOLUTION: A power semiconductor device according to the present disclosure includes a conductor plate, an insulator, a lead frame, and a plurality of semiconductor elements in the order stated, and is provided with a first mold package that is encapsulated with resin so that the principal plane opposite the side where the insulator of the conductor plate is disposed, is exposed, and a second mold package that encapsulates the first mold package with resin so that the principal plane is exposed. The lead frame has a plurality of terminals protruding from one side face of the first mold package, the plurality of terminals being bent inside of the second mold package in a direction opposite the principal plane of the conductor plate and protruding from the surface of the second mold package on the side opposite the conductor plate, with the plurality of terminals arranged in a staggering pattern at a position close to one side of the surface in a plan view.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power semiconductor device, and more particularly to a power semiconductor device with a miniaturized package. [Background technology]

[0002] In conventional power semiconductor devices, for example, as disclosed in Patent Document 1, a first semiconductor package in which a semiconductor element is sealed with a first resin is further sealed with a second resin, and the tips of the terminals protrude from the top surface of a second semiconductor package made of the second resin. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-120619 Summary of the Invention [Problem to be solved by the invention]

[0004] In the power semiconductor device of Patent Document 1, multiple terminals are arranged close to each other, so it is not possible to ensure a sufficient creepage distance between the terminals. If an attempt is made to ensure a sufficient creepage distance between the terminals, the package would become larger, which is a problem.

[0005] The present disclosure has been made to solve the above problems, and has an object to provide a power semiconductor device with a miniaturized package. [Means for solving the problem]

[0006] A power semiconductor device according to the present disclosure includes a first molded package having therein a conductor plate, an insulator provided on the conductor plate, a lead frame provided on the insulator, and a plurality of semiconductor elements provided on the lead frame, the first molded package being resin-sealed so that a main surface of the conductor plate opposite to the side on which the insulator is provided is exposed, and a second molded package being resin-sealed with the first molded package so that the main surface is exposed, the lead frame having a plurality of terminals protruding from one of the side surfaces of the first molded package, the plurality of terminals being bent within the second molded package in a direction opposite to the main surface of the conductor plate and protruding from a surface of the second molded package opposite to the conductor plate, and the plurality of terminals being alternately arranged in a staggered arrangement near one side of the surface in a plan view. the plurality of terminals include a plurality of first terminals and a plurality of second terminals, the plurality of first terminals being arranged at positions closer to the one side than the plurality of second terminals in a plan view; the side surface of the first molded package from which the plurality of terminals protrude has an uneven shape in which portions from which the plurality of first terminals protrude are convex and portions from which the plurality of second terminals protrude are concave; the plurality of semiconductor elements include a plurality of first semiconductor elements electrically connected to the plurality of first terminals respectively and a plurality of second semiconductor elements electrically connected to the plurality of second terminals respectively; the plurality of first semiconductor elements are arranged at positions closer to the side surface of the first molded package than the plurality of second semiconductor elements; and the plurality of semiconductor elements are arranged alternately on the lead frame so as to be in a staggered arrangement in a plan view. do. [Effects of the Invention]

[0007] According to the power semiconductor device of the present disclosure, the terminals protrude from the surface of the second molded package opposite the main surface of the conductor plate, thereby increasing the creepage distance from the conductor plate of the second molded package to the terminals. Furthermore, the terminals are alternately arranged in a staggered pattern, thereby ensuring a sufficient creepage distance between the terminals not only in a direction parallel to the terminal lead-out side of the second molded package but also in a direction perpendicular to the side. This allows the length of the second molded package in the direction parallel to the side to be shorter than conventional devices, thereby miniaturizing the external dimensions of the second molded package while ensuring a sufficient creepage distance between the terminals, making it possible to encapsulate a semiconductor element with a high power consumption. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a terminal arrangement of a power semiconductor device according to a first embodiment of the present disclosure. [Figure 2] 1 is a cross-sectional view showing a configuration of a power semiconductor device according to a first embodiment of the present disclosure. [Figure 3]1 is a cross-sectional view showing a configuration of a power semiconductor device according to a first embodiment of the present disclosure. [Figure 4] 3A to 3C are cross-sectional views illustrating a method for manufacturing the power semiconductor device according to the first embodiment of the present disclosure. [Figure 5] 5A to 5C are cross-sectional views illustrating a method for manufacturing the power semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 10 is a plan view showing a terminal arrangement of a power semiconductor device according to a second embodiment of the present disclosure. [Figure 7] FIG. 11 is a plan view showing a terminal arrangement of a power semiconductor device according to a third embodiment of the present disclosure. [Figure 8] FIG. 11 is a plan view showing a terminal arrangement of a power semiconductor device according to a fourth embodiment of the present disclosure. [Figure 9] FIG. 10 is a cross-sectional view showing a configuration of a power semiconductor device according to a fourth embodiment of the present disclosure. [Figure 10] FIG. 11 is a plan view showing a terminal arrangement of a power semiconductor device according to a fifth embodiment of the present disclosure. [Figure 11] FIG. 10 is a cross-sectional view showing a configuration of a power semiconductor device according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Introduction> In the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and do not relate to the directions in which the embodiments are actually implemented.

[0010] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0011] <First Embodiment> <Device configuration> Fig. 1 is a plan view showing the terminal arrangement of a power semiconductor device 100 according to a first embodiment of the present disclosure, as viewed from the top surface side from which the terminals protrude. As shown in Fig. 1, in power semiconductor device 100, a plurality of terminals 21 (first terminals) and a plurality of terminals 22 (second terminals) are arranged in a staggered manner on the top surface of a molded package 7 (second molded package) that is rectangular in plan view, near one of two short sides. That is, terminals 21 are arranged alternately near the outer side of molded package 7, and terminals 22 are arranged alternately near the inner side of molded package 7. Furthermore, a plurality of terminals 20 are arranged in a row along the other short side near the other short side.

[0012] In this way, by arranging terminals 21 and 22 in a staggered manner, it is possible to ensure a creepage distance between the terminals not only in the direction parallel to the terminal lead-out side of molded package 7 but also in the direction perpendicular thereto. As a result, the length of molded package 7 in the direction parallel to the terminal lead-out side can be made shorter than before, and the external shape of molded package 7 can be made smaller while ensuring a creepage distance between the terminals.

[0013] 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG.

[0014] 2, an insulator 4 is mounted on a conductor plate 5, and a lead frame 2 is mounted on the insulator 4. A semiconductor element 1A and a semiconductor element 1B are mounted on the lead frame 2. The semiconductor elements 1A and 1B have characteristics required for the operation of the power semiconductor device 100, and are connected to the lead frame 2 by soldering or the like.

[0015] The lead frame 2 is separated into a portion on which the semiconductor element 1A is mounted and a portion on which the semiconductor element 1B is mounted, and the portion on which the semiconductor element 1B is mounted is integrated with a terminal 20, which is bent vertically toward the upper surface of the molded package 7 and whose tip protrudes from the upper surface of the molded package 7.

[0016] The portion on which the semiconductor element 1A is mounted is separated from the terminals 21, but the top electrodes of the semiconductor element 1A are electrically connected to the terminals 21 via the wires 3. The terminals 21 are bent vertically toward the top surface of the molded package 7, with their tips protruding from the top surface of the molded package 7.

[0017] The lead frame 2 may be made of a copper material having a thickness of, for example, 1 mm and flat top and bottom surfaces. The wire 3 is a thin metal wire made of, for example, aluminum.

[0018] The insulator 4 preferably has high thermal conductivity, and may be made of, for example, an epoxy resin containing a highly thermally conductive filler.

[0019] The conductive plate 5 is formed integrally with the insulator 4, and the width and depth of the insulator 4 and the conductive plate 5 are equal in plan view. The conductive plate 5 may be made of a material such as copper or aluminum. The bottom surface of the conductive plate 5 is flush with the bottom surface of the molded package 7.

[0020] Except for the lower surface of the conductor plate 5, the insulator 4, lead frame 2, wires 3, and semiconductor elements 1A and 1B are sealed with mold resin to form a molded package 6 (first molded package). Furthermore, the outside of the molded package 6, excluding the lower surface, is covered with a molded package 7, and the power semiconductor device 100 is a transfer mold type package.

[0021] The material of molded package 6 and molded package 7 contains a thermosetting resin material, and since they are formed by transfer molding, the material has fluidity during resin sealing, but the composition is set so that the temperature at which the resin of molded package 6 melts is higher than the temperature at which the resin of molded package 7 melts.

[0022] The terminals 20 to 22 have their tips protruding from the upper surface of the package, and are sealed with the resin that constitutes the molded package 7 except for the protruding portions.

[0023] There are no particular limitations on the number, thickness, tip shape, etc. of the terminals 20 to 22. There are also no particular limitations on the volume of the package as long as it can seal the molded package 6 excluding the bottom surface and the terminals 20 to 22 excluding the portions protruding from the top surface, but from the perspective of miniaturization, it is desirable to make it as small as possible.

[0024] When the power semiconductor device 100 is mounted on a heat sink or the like for heat dissipation, the conductor plate 5 comes into contact with the heat sink, so it is desirable that the entire lower surface thereof be exposed.

[0025] The cross-sectional structure shown in Fig. 3 is basically the same as that shown in Fig. 2, but in the cross section of Fig. 3, the portion on which semiconductor element 1A is mounted is integrated with terminal 22, and terminal 22 is bent vertically toward the top surface of molded package 7, with its tip protruding from the top surface of molded package 7. In this way, terminals 21 and 22 are individually connected to semiconductor element 1A, and since a difference in the amount of power occurs between the terminals, they are arranged in a staggered manner to ensure the creepage distance between the terminals that is required due to the difference in the amount of power. Therefore, by arranging terminals 21 and 22 in a staggered manner as shown in Fig. 1, it is possible to ensure the creepage distance between the terminals and to reduce the external size of molded package 7.

[0026] In this disclosure, a transfer mold type package such as that shown in Figures 2 and 3 has been described, but the structures shown in Figures 2 and 3 are merely examples, and this disclosure can also be applied to packages of other structures as long as they are transfer mold type.

[0027] In this disclosure, a configuration has been shown in which the bottom surfaces of semiconductor elements 1A and 1B are joined to lead frame 2 by soldering or the like, but this disclosure can also be applied to a configuration in which both surfaces of a semiconductor element are joined to a lead frame by soldering or the like.

[0028] <Manufacturing method> 4 and 5, a method for manufacturing the power semiconductor device 100 will be described. Fig. 4 is a cross-sectional view showing the molded package 6 sealed with resin, and corresponds to Fig. 2.

[0029] 4, a lead frame 2 is mounted on an insulator 4 that is integral with a conductive plate 5, and semiconductor elements 1A and 1B are joined to the lead frame 2 by soldering or the like. The upper surface electrodes of the semiconductor element 1A are electrically connected via wires 3 to the lead frame 2 that is integral with terminals 21.

[0030] These are sealed with resin, and lead frames 2 integrated with terminals 20 and 21 protrude horizontally from two opposing side surfaces of molded package 6, i.e., in a direction parallel to the bottom surface of conductive plate 5. Lead frames 2 are bent vertically midway, i.e., in a direction perpendicular to the bottom surface of conductive plate 5, and their tips are located higher than the top surface of molded package 6.

[0031] FIG. 5 is an example of a cross-sectional view showing a state in which a molded package 6 sealed with resin 6 is placed in a sealing mold.

[0032] In Figure 5, the sealing mold is composed of an upper mold 9 and a lower mold 10. The upper mold 9 has a plurality of openings OP into which the terminals 20 to 22 are inserted when the power semiconductor device 100 is placed in the lower mold 10 and the upper mold 9 is placed over the power semiconductor device 100. The plurality of openings OP are formed according to the arrangement pattern of the terminals 20 to 22, and are formed to a size that leaves almost no gaps when the terminals 20 to 22 are inserted into each opening. Therefore, when the resin material that forms the molded package 7 is injected into the sealing mold, the resin material does not seep into the openings OP and does not adhere to the surfaces of the terminals 20 to 22.

[0033] In the sealing process, the upper mold 9 and the lower mold 10 are placed on top of each other and then heated to heat and melt the sealing resin to a low viscosity state. The resin is then injected into the cavity formed by the upper mold 9 and the lower mold 10 through a runner 11 that penetrates the side of the sealing mold, and after filling is complete, the pressure is maintained to allow the resin to harden.

[0034] As explained above, the temperature at which the resin of molded package 6 melts is higher than the temperature at which the resin of molded package 7 melts, so the sealing resin is heated and melted at a temperature that does not melt molded package 6. Through the above steps, the power semiconductor device 100 shown in FIGS. 1 to 3 can be obtained.

[0035] <Embodiment 2> 6 is a plan view showing the terminal arrangement of power semiconductor device 200 according to the second embodiment of the present disclosure, as viewed from the top surface side from which the terminals protrude. For convenience, molded package 7 is shown in dashed lines in FIG. 6, and only molded package 6 is shown in solid lines. As shown in FIG. 6, molded package 6 of power semiconductor device 200 has an uneven shape on the side from which terminals 21 and 22 protrude, corresponding to the staggered arrangement of terminals 21 and 22.

[0036] That is, the portion from which terminal 21 protrudes is a convex portion 61, and the portion from which terminal 22 protrudes is a concave portion 62 whose side surface is recessed inward from convex portion 61, and convex portions 61 and concave portions 62 are arranged alternately.

[0037] The terminals 21 protruding horizontally from the protrusions 61 are bent vertically midway toward the upper surface of the molded package 7.

[0038] The side of the molded package 6 from which the multiple terminals 20 protrude is flat, and the terminals 20 protruding horizontally from the flat side are bent vertically halfway toward the top surface of the molded package 7, and the multiple terminals 20 are arranged in a row along the short side of the molded package 7.

[0039] In this way, terminals 21 and 22 are arranged in a staggered pattern by protruding from the side surfaces of convex portions 61 and concave portions 62 provided on the side surfaces of molded package 6, so that the creepage distance between the terminals can be secured not only in the direction parallel to the terminal pull-out side of molded package 7 but also in the direction perpendicular thereto. As a result, the length of molded package 7 in the direction parallel to the terminal pull-out side can be made shorter than before, and the external shape of molded package 7 can be made smaller while securing the creepage distance between the terminals.

[0040] Furthermore, by providing the protrusions 61, it is possible to ensure space within the molded package 6, and to provide more variety in the arrangement of the lead frame 2 and wires 3 inside.

[0041] Furthermore, since the terminal 22 placed in the recess 62 is arranged to be contained within the recess 62 when viewed in a plane, the surrounding area is protected by the recess 62, and defects such as deformation of the terminal 22 due to transportation errors during the terminal bending process and transportation process can be suppressed.

[0042] The method for manufacturing the power semiconductor device 200 is the same as the method for manufacturing the power semiconductor device 100 described with reference to FIGS. 4 and 5, and the power semiconductor device 200 is placed in a sealing mold and sealed with resin.

[0043] As a result, similarly to the first embodiment, a configuration is obtained in which a plurality of terminals 21 and terminals 22 are arranged in a staggered pattern near one of the two short sides on the top surface of molded package 7, which has a rectangular shape in a plan view.

[0044] <Third Embodiment> 7 is a plan view showing the terminal arrangement of power semiconductor device 300 according to embodiment 3 of the present disclosure, as viewed from the top surface side from which the terminals protrude. For convenience, molded package 7 is shown in FIG. 7 by a dashed line, and only molded package 6 is shown by a solid line. As shown in FIG. 7, molded package 6 of power semiconductor device 300 has an uneven shape on the side from which terminals 21 and 22 protrude, in accordance with the staggered arrangement of terminals 21 and 22, as in embodiment 2.

[0045] That is, the portion from which terminal 21 protrudes is a convex portion 61, and the portion from which terminal 22 protrudes is a concave portion 62 whose side surface is recessed inward from convex portion 61, and convex portions 61 and concave portions 62 are arranged alternately.

[0046] The terminals 21 protruding horizontally from the protrusions 61 are bent vertically midway toward the upper surface of the molded package 7.

[0047] The side of the molded package 6 from which the multiple terminals 20 protrude is flat, and the terminals 20 protruding horizontally from the flat side are bent vertically halfway toward the top surface of the molded package 7, and the multiple terminals 20 are arranged in a row along the short side of the molded package 7.

[0048] In this way, terminals 21 and 22 are arranged in a staggered pattern by protruding from the side surfaces of convex portions 61 and concave portions 62 provided on the side surfaces of molded package 6, so that the creepage distance between the terminals can be secured not only in the direction parallel to the terminal pull-out side of molded package 7 but also in the direction perpendicular thereto. As a result, the length of molded package 7 in the direction parallel to the terminal pull-out side can be made shorter than before, and the external shape of molded package 7 can be made smaller while securing the creepage distance between the terminals.

[0049] Furthermore, not only are terminals 21 and 22 arranged in a staggered arrangement, but semiconductor elements 1A arranged inside molded package 6 are also arranged in a staggered arrangement. That is, semiconductor elements 1A electrically connected to terminals 21 are arranged closer to protrusions 61, and semiconductor elements 1A connected to terminals 22 are arranged at positions set back from recesses 62.

[0050] The semiconductor elements 1B connected to the terminals 20 are arranged in a row along the short side of the molded package 6.

[0051] In this way, in the power semiconductor device 300 of embodiment 3, by also staggering the semiconductor elements 1A arranged inside the molded package 6, the distance between the semiconductor elements 1A in the direction parallel to the terminal lead-out side of the molded package 7 can be further narrowed, and the external shape of the molded package 7 can be further reduced.

[0052] The method for manufacturing the power semiconductor device 300 is the same as the method for manufacturing the power semiconductor device 100 described with reference to FIGS. 4 and 5, and the power semiconductor device 300 is placed in a sealing mold and sealed with resin.

[0053] As a result, similarly to the first embodiment, a configuration is obtained in which a plurality of terminals 21 and terminals 22 are arranged in a staggered pattern near one of the two short sides on the top surface of molded package 7, which has a rectangular shape in a plan view.

[0054] <Fourth Embodiment> FIG. 8 is a plan view showing the terminal arrangement of a power semiconductor device 400 according to a fourth embodiment of the present disclosure, and is a plan view of the power semiconductor device 400 viewed from the top side from which the terminals protrude, and FIG. 9 is a cross-sectional view taken along the arrow BB in FIG.

[0055] As shown in FIG. 8, the power semiconductor device 400 is the same as the power semiconductor device 100 of the first embodiment in that the plurality of terminals 21 and 22 are arranged in a staggered pattern in a plan view, but a protrusion 71 is provided between the staggered array of the plurality of terminals 21 and the staggered array of the plurality of terminals 22, extending in a direction parallel to both arrays.

[0056] 9, the protrusions 71 can be formed integrally with the molded package 7 by being formed at the same time as the molded package 7. Providing the protrusions 71 can further increase the creepage distance between the terminals 21 and 22 by the cross-sectional lengths of both side surfaces and the top surface of the protrusions 71, making it possible to increase the power capacity of the power semiconductor device 400 and reduce the external size of the molded package 7. Providing protrusions between the drawn-out terminals ensures a creepage distance between each terminal, thereby enabling a further increase in the power capacity.

[0057] Although Figure 8 shows an example in which one protrusion 71 integrated with the molded package 7 is arranged between an array of multiple terminals 21 and an array of multiple terminals 22, the shape, number of arrangements, and protrusion height can be set arbitrarily as long as the necessary creepage distance between the terminals can be secured.

[0058] <Fifth Embodiment> FIG. 10 is a plan view showing the terminal arrangement of a power semiconductor device 500 according to embodiment 5 of the present disclosure, which is a plan view of the power semiconductor device 500 viewed from the top side from which the terminals protrude, and FIG. 11 is a cross-sectional view taken along line BB in FIG.

[0059] 10, power semiconductor device 500 is the same as power semiconductor device 100 of the first embodiment in that a plurality of terminals 21 and terminals 22 are arranged in a staggered pattern in plan view, but groove-like recessed portions 72 extending in a direction parallel to both the staggered arrangements of terminals 21 and terminals 22 are provided between the staggered arrangements of terminals 21 and terminals 22. Recessed portions 72 can be formed simultaneously with the formation of molded package 7.

[0060] As shown in FIG. 11, by providing the recess 72, the creepage distance between the terminals 21 and 22 can be further increased by the length of the cross section of both side surfaces and the bottom surface of the recess 72, thereby enabling the power semiconductor device 500 to have a larger power capacity and the molded package 7 to have a smaller external size.

[0061] Although Figure 10 shows an example in which one recess 72 is placed between an array of multiple terminals 21 and an array of multiple terminals 22, the shape, number of placements, and depth of the recess can be set arbitrarily as long as the necessary creepage distance between the terminals can be secured.

[0062] <Applicable semiconductor elements> In the above-described embodiments 1 to 5, the semiconductor material of semiconductor elements 1A and 1B is not particularly limited, but semiconductor elements 1A and 1B can be silicon semiconductor elements using silicon (Si) as the semiconductor material, or silicon carbide semiconductor elements using silicon carbide (SiC) as the semiconductor material.

[0063] Switching elements made of SiC have low switching loss and are capable of high-speed switching operations.

[0064] Furthermore, switching elements made of SiC have low power loss and high heat resistance, which means that when equipped with a cooling unit such as a heat sink, the heat dissipation fins of the heat sink can be made smaller, making it possible to miniaturize the semiconductor module.

[0065] Wide band gap semiconductors other than SiC can also be made of gallium nitride-based materials, gallium oxide-based materials, diamond, or the like.

[0066] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0067] The present disclosure described above will be summarized as an appendix.

[0068] (Appendix 1) Conductor plate, an insulator provided on the conductive plate; a lead frame disposed on the insulator; a first mold package having a plurality of semiconductor elements provided on the lead frame therein and sealed with resin such that a main surface of the conductor plate opposite to the side on which the insulator is provided is exposed; a second molded package formed by resin-sealing the first molded package so that the main surface is exposed; the lead frame has a plurality of terminals protruding from one of the sides of the first molded package; the plurality of terminals are bent in the second molded package in a direction opposite to the main surface of the conductor plate and protrude from a surface of the second molded package opposite to the conductor plate; The plurality of terminals include: The power semiconductor device is arranged alternately in a staggered arrangement near one side of the surface in a plan view.

[0069] (Appendix 2) The plurality of terminals include: a plurality of first terminals and a plurality of second terminals; The plurality of first terminals include: the terminals are arranged closer to the one side than the plurality of second terminals in a plan view, The first molded package includes: The side surface from which the plurality of terminals protrude is 2. The power semiconductor device according to claim 1, wherein the protruding portions of the plurality of first terminals are convex portions and the protruding portions of the plurality of second terminals are concave portions, forming an uneven shape.

[0070] (Appendix 3) Each of the plurality of second terminals includes: 3. The power semiconductor device according to claim 2, wherein the power semiconductor device is accommodated in the recess in a plan view.

[0071] (Appendix 4) The plurality of semiconductor elements include: a plurality of first semiconductor elements electrically connected to the plurality of first terminals, respectively; and a plurality of second semiconductor elements electrically connected to the plurality of second terminals, respectively; The plurality of first semiconductor elements include: 4. The power semiconductor device according to claim 2, wherein the plurality of second semiconductor elements are arranged closer to the side surface of the first molded package than the plurality of second semiconductor elements, and the plurality of semiconductor elements are arranged alternately on the lead frame in a staggered arrangement in a planar view.

[0072] (Appendix 5) The plurality of terminals include: a plurality of first terminals and a plurality of second terminals; The plurality of first terminals include: the terminals are arranged closer to the one side than the plurality of second terminals in a plan view, 2. A power semiconductor device as described in Appendix 1, wherein the second molded package has a protrusion on the surface between the array of the plurality of first terminals and the array of the plurality of second terminals, extending in a direction parallel to both arrays.

[0073] (Appendix 6) The plurality of terminals include: a plurality of first terminals and a plurality of second terminals; The plurality of first terminals include: the terminals are arranged closer to the one side than the plurality of second terminals in a plan view, 2. The power semiconductor device of claim 1, wherein the second molded package has a recess on the surface between the array of the plurality of first terminals and the array of the plurality of second terminals, the recess extending in a direction parallel to both arrays. [Explanation of symbols]

[0074] 1A semiconductor element, 2 lead frame, 4 insulator, 5 conductive plate, 6, 7 molded package, 21, 22 terminal, 61 convex portion, 62 concave portion, 71 protrusion portion, 72 recess portion.

Claims

1. Conductor plate, an insulator provided on the conductive plate; a lead frame disposed on the insulator; a first mold package having a plurality of semiconductor elements provided on the lead frame therein and sealed with resin such that a main surface of the conductor plate opposite to the side on which the insulator is provided is exposed; a second molded package formed by resin-sealing the first molded package so that the main surface is exposed; the lead frame has a plurality of terminals protruding from one of the sides of the first molded package; the plurality of terminals are bent in the second molded package in a direction opposite to the main surface of the conductor plate and protrude from a surface of the second molded package opposite to the conductor plate; The plurality of terminals include: are alternately arranged in a staggered pattern near one side of the surface in a plan view, The plurality of terminals include: a plurality of first terminals and a plurality of second terminals; The plurality of first terminals include: the second terminals are disposed at a position closer to the one side than the second terminals in a plan view, The first molded package includes: The side surface from which the plurality of terminals protrude is a concave-convex shape in which the protruding portions of the plurality of first terminals are convex portions and the protruding portions of the plurality of second terminals are concave portions; The plurality of semiconductor elements include: a plurality of first semiconductor elements electrically connected to the plurality of first terminals, respectively; and a plurality of second semiconductor elements electrically connected to the plurality of second terminals, respectively; The plurality of first semiconductor elements A power semiconductor device, wherein the plurality of second semiconductor elements are arranged closer to the side surface of the first molded package than the plurality of second semiconductor elements, and the plurality of semiconductor elements are arranged alternately on the lead frame in a staggered arrangement in a planar view.

2. Each of the plurality of second terminals includes: The power semiconductor device according to claim 1 , wherein the power semiconductor device is accommodated in the recess in a plan view.

3. The plurality of terminals include: a plurality of first terminals and a plurality of second terminals; The plurality of first terminals include: the second terminals are disposed at a position closer to the one side than the second terminals in a plan view, 2. The power semiconductor device according to claim 1, wherein the second molded package has a protrusion on the surface between the array of the plurality of first terminals and the array of the plurality of second terminals, the protrusion extending in a direction parallel to both arrays.

4. The plurality of terminals include: a plurality of first terminals and a plurality of second terminals; The plurality of first terminals include: the second terminals are disposed at a position closer to the one side than the second terminals in a plan view, 2. The power semiconductor device according to claim 1, wherein the second molded package has a recess on the surface between the array of the first terminals and the array of the second terminals, the recess extending in a direction parallel to both arrays.

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