Semiconductor device and manufacturing method thereof

Abstract

To suppress local polishing in the manufacturing process of semiconductor devices.SOLUTION: A semiconductor device has a base substrate B including a wiring layer, and chips C1, C2, C3, C4, C5, and C6 on the base substrate B, and electrodes and protective film P are provided between the chips C1, C2, C3, C4, C5, and C6, and the protective film P is also provided on the sides.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment is a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art As an example of a semiconductor device and a method for manufacturing the semiconductor device, a stacked device chip and a method for manufacturing the stacked device chip are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-194936 Summary of the Invention [Problem to be solved by the invention]

[0004] This allows for narrower pitches in semiconductor devices. [Means for solving the problem]

[0005] This embodiment is a semiconductor device comprising a base substrate including a wiring layer and a plurality of chips stacked on the base substrate, with electrodes and protective films provided between the plurality of chips and a protective film also provided on the side of the chips. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 is a diagram for explaining the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] 2A to 2C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. [Figure 3] 2A to 2C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. [Figure 4] 2A to 2C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. [Figure 5]2A to 2C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. [Figure 6] 2A to 2C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. [Figure 7] 2A to 2C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. [Figure 8] FIG. 8 is an enlarged view of a portion XI in FIG. 7. [Figure 9] 2A to 2C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. [Figure 10] FIG. 2 is a diagram for explaining a chip included in the semiconductor memory device shown in FIG. [Figure 11] 11 is a diagram for explaining a state in which the chip shown in FIG. 10 is bonded to a base substrate. FIG. [Figure 12] 12A and 12B are diagrams for explaining a modified example of the base substrate shown in FIG. [Figure 13] 12 is a diagram for explaining a state in which another chip is bonded to the chip shown in FIG. 11. FIG. [Figure 14] 10A and 10B are diagrams for explaining a state in which chips are joined to each other; [Figure 15] 10A and 10B are diagrams for explaining a state in which a chip is bonded to a substrate. [Figure 16] 10A and 10B are diagrams for explaining a state in which a chip is bonded to a substrate. [Figure 17] FIG. 10 is a diagram for explaining a configuration of a semiconductor memory device according to a modified example. [Figure 18] FIG. 10 is a diagram for explaining the configuration of a semiconductor memory device according to a second embodiment. [Figure 19] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 20] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 21] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 22] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 23] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 24] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 25] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 26] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 27] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. [Figure 28] 19A to 19C are diagrams for explaining a method for manufacturing the semiconductor memory device shown in FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0008] 1 is a cross-sectional view illustrating the structure of a semiconductor memory device E according to the first embodiment. The semiconductor memory device E includes a base substrate B and chips C1, C2, C3, C4, C5, and C6. The chip C1 is bonded onto the base substrate B. A plurality of metal balls BE are bonded to the surface of the base substrate B opposite to the surface to which the chip C1 is bonded.

[0009] Chip C2 is bonded to the surface of chip C1 opposite to the surface bonded to base substrate B. Chip C3 is bonded to the surface of chip C2 opposite to the surface bonded to chip C1. Chip C4 is bonded to the surface of chip C3 opposite to the surface bonded to chip C2. Chip C5 is bonded to the surface of chip C4 opposite to the surface bonded to chip C3. Chip C6 is bonded to the surface of chip C5 opposite to the surface bonded to chip C4. In this way, chips C1, C2, C3, C4, C5, and C6 are stacked on base substrate B.

[0010] A protective film P is provided to cover the side surfaces of chips C1, C2, C3, C4, C5, and C6. The protective film P also covers at least a portion of the base substrate B. In this embodiment, as an example, the protective film P is provided so that it is relatively thick on the chip C1 side and relatively thin on the chip C6 side. The thickness of the protective film P is not limited to this, and it may be provided so that it is uniform. The protective film P may be provided so that it is relatively thick on the chip C6 side and relatively thin on the chip C1 side. The protective film P may be removed. A molded resin layer M is provided to cover the protective film P.

[0011] Next, a method for manufacturing the semiconductor memory device E will be described with reference to Figures 2 to 9. Figures 2 to 9 show the manufacturing of two semiconductor memory devices E, but it is also possible to manufacture three or more semiconductor memory devices E simultaneously.

[0012] As shown in Figure 2, a base substrate B is prepared by laminating a support substrate SB on the support substrate SB. Alternatively, a wiring layer may be formed on the support substrate SB to form the base substrate B. A predetermined number of individual chips C1 are bonded to predetermined positions on the base substrate B. The silicon C1a of each chip C1 is thick. The through-silicon vias (TSVs) T1 extending from the chip C1 are embedded in the silicon C1a.

[0013] Subsequently, as shown in FIG. 3, reactive ion etching (RIE) is performed on the silicon C1a to expose the top of the through electrode T1.

[0014] Next, as shown in FIG. 4, a protective film P1 is formed to cover the chip C1, silicon C1a, and base substrate B. The protective film P1 is a resin film containing oxide, nitride, or carbide formed by chemical vapor deposition (CVD). The protective film P1 may be formed of, for example, SiO2, SiOC, SiN, or SiCN. The protective film P1 may be formed of an insulating film formed by coating. The insulating film formed by coating may be formed of an organic film or a polymer material. Spin coating, inkjet printing, screen printing, or the like may be used for coating. Whether formed by coating or chemical deposition, the protective film P1 is formed conformally along the outer shape of the chip C1.

[0015] Next, as shown in FIG. 5, the protective film P1 is thinned by chemical mechanical polishing (CMP). By performing CMP, the through electrodes T1 and the protective film P1 form the same surface. The through electrodes T1 and the protective film P1 form a bonding surface. The pitch of the through electrodes T1 may be, for example, 10 μm to 50 μm. The diameter of the rib electrode T1 may be 5 μm to 30 μm. The through electrodes T1 and the protective film P1 may be such that the through electrodes T1 protrude from the protective film P1 by 0 to several μm. After final polishing, the thickness of the chip C1 becomes about several tens of μm. Preferably, it is about 20 μm to 70 μm. The thickness of the protective film P1 on the bonding surface after polishing may be about 3 μm to 5 μm.

[0016] Next, as shown in FIG. 6, the next chip C2 is bonded to the bonding surface of chip C1. Thereafter, the procedure described with reference to FIGS. 2 to 5 is repeated to stack chips C3, C4, C5, and C6 to form a chip stack. As shown in FIG. 7, a protective film is formed each time a chip is stacked. Therefore, when chip C6 is stacked, the protective film P is thicker on the side of chip C1 than on the side of chip C6. An electrode is formed on the surface of chip C2 facing the bonding surface of chip C1, and an insulating film is formed around the electrode. The electrode and the insulating film may be flush with each other. The electrode and the insulating film may protrude from the insulating film by approximately 0 to several μm. The insulating film formed on the surface of chip C2 facing the bonding surface of chip C1 may be an organic film or a polymer material, or may be an inorganic film such as an oxide film or a nitride film. The insulating films formed on the bonding surface of chip C1 and the surface of chip C2 facing the bonding surface of chip C1 may be made of the same material or different materials.

[0017] FIG. 8 shows an enlarged view of portion XI in FIG. 7. As shown in FIG. 8, protective films P1, P2, P3, P4, P5, and P6 are stacked in this order. The protective film P1 is a laminated film that is stacked when chip C1 is provided, as described above. The protective film P2 is a laminated film that is stacked when chip C2 is provided on chip C1. The protective film P3 is a laminated film that is stacked when chip C3 is provided on chip C2. The protective film P4 is a laminated film that is stacked when chip C4 is provided on chip C3. The protective film P5 is a laminated film that is stacked when chip C5 is provided on chip C4. The protective film P6 is a laminated film that is stacked when chip C6 is provided on chip C5. After chip C6 is provided, a heat treatment may be performed to strengthen the bond between the contacting electrodes by metal diffusion. The heat treatment may be performed, for example, after chip C2 is stacked on chip C1, and then after chip C3 is stacked on chip C2. However, in this case, the chip C1 will be subjected to multiple heat treatments, so it is preferable to heat all the chips once after stacking them.

[0018] On the side surface of the chip C1, six laminated films each having a protective film stacked thereon are provided, as shown in Fig. 8. Similarly, six laminated films each having a protective film stacked thereon are provided on the base substrate B.

[0019] The side of chip C2 does not have protective film P1 formed thereon, but is layered starting from protective film P2, resulting in five layers of laminated films with protective films stacked on it. The side of chip C3 does not have protective film P1 or P2 formed thereon, but is layered starting from protective film P3, resulting in four layers of laminated films with protective films stacked on it.

[0020] The side surfaces of chip C4 do not have protective films P1, P2, and P3 formed thereon, and protective film P4 is layered on top of them, resulting in three layers of laminated films with protective films. The side surfaces of chip C5 do not have protective films P1, P2, P3, and P4 formed thereon, and protective film P5 is layered on top of them, resulting in two layers of laminated films with protective films. The side surfaces of chip C6 do not have protective films P1, P2, P3, P4, and P5 formed thereon, and protective film P6 is layered on top of them, resulting in one layer of laminated films with protective films.

[0021] In this case, since there is nothing to connect the through electrode T1 to in the top chip C6, it may not be necessary to thin the chip C6. In this case, no laminated film is provided on the side surface of the chip C6. Therefore, the protective film P6 shown in FIG. 8 is not formed. Five layers of protective film are provided on the side surface of the chip C1. In this case, five layers of protective film are provided on the base substrate B.

[0022] Next, as shown in FIG. 9, a mold resin layer M is formed. Thereafter, the support substrate SB is removed and the semiconductor memory device E shown in FIG. 1 is obtained by dividing the semiconductor memory device E. A protective film P is partially exposed from the side of the mold resin M. The exposed protective film P is a laminated film in which SiN is repeated multiple times along a direction perpendicular to the surface of the base substrate B. The number of repetitions may be equal to the number of stacked chips or may be one less. The protective film P on the base substrate B may be removed before forming the mold resin layer M. In this case, the protective film P is not exposed from the side of the mold resin layer M.

[0023] Next, chip C1 will be further described with reference to Fig. 10. Fig. 10 is a cross-sectional view of chip C1, showing the state described with reference to Fig. 2. As shown in Fig. 10, chip C1 is a three-dimensional memory in which an array chip 1 and a circuit chip 2 are bonded together. The array chip 1 includes a memory cell array 11, an insulating film 12, a substrate 13, and an insulating film 14. The memory cell array 11 includes a plurality of memory cells. The insulating film 12 is provided below the memory cell array 11. The substrate 13 is provided below the insulating film 12. The insulating film 14 is provided below the substrate 13.

[0024] The array chip 1 further includes an interlayer insulating film 15 and an insulating film 16. The interlayer insulating film 15 is provided on the memory cell array 11. The insulating film 16 is provided on the interlayer insulating film 15. The insulating films 12, 14, and 16 are, for example, silicon oxide films or silicon nitride films. The substrate 13 is, for example, a semiconductor substrate such as a silicon substrate.

[0025] The circuit chip 2 is provided on the array chip 1. The symbol S indicates the bonding surface between the array chip 1 and the circuit chip 2. The array chip 1 and the circuit chip 2 are formed separately and then bonded together. The circuit chip 2 includes an insulating film 17, an interlayer insulating film 18, and a semiconductor 19. The interlayer insulating film 18 is provided on the insulating film 17. The semiconductor 19 is provided on the interlayer insulating film 18. The insulating film 17 is, for example, a silicon oxide film or a silicon nitride film.

[0026] 10 shows the X and Y directions as being parallel to and perpendicular to surfaces S1 and S2 of substrate 13, surface S3 of semiconductor 19, and surface S4 of substrate 60, and the Z direction as being perpendicular to surfaces S1 and S2, and surfaces S3 and S4. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. For example, memory cell array 11 is located below substrate 60 and above substrate 13. The −Z direction may or may not coincide with the direction of gravity.

[0027] The array chip 1 includes a plurality of word lines WL, a back gate BG, and a select gate SG as electrode layers in the memory cell array 11. Figure 10 shows a staircase structure 21 of the memory cell array 11. The array chip 1 and the circuit chip 2 are bonded to each other.

[0028] 10, each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. The back gate BG is electrically connected to a back gate wiring layer 25 via a contact plug 24. The select gate SG is electrically connected to a select gate wiring layer 27 via a contact plug 26. A columnar portion CL is provided so as to penetrate the select gate SG. The word line WL, back gate BG, and columnar portion CL are electrically connected to a bit line BL via a plug 28, and are also electrically connected to the substrate 13.

[0029] The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32, a source diffusion layer (not shown), and a drain diffusion layer (not shown). The gate electrode 32 is provided on the semiconductor 19 via a gate insulating film (not shown). The source diffusion layer and the drain diffusion layer are provided within the semiconductor 19.

[0030] The circuit chip 2 further includes plugs 33, wiring layers 34, and wiring layers 35. A plurality of plugs 33 are provided on the source diffusion layer or the drain diffusion layer of each transistor 31. A plurality of wiring layers 34 are provided on these plugs 33 and include a plurality of wires. A plurality of wiring layers 35 are provided on these wiring layers 34 and include a plurality of wires.

[0031] The circuit chip 2 further includes via plugs 36 and metal pads 37. A plurality of via plugs 36 are provided on the wiring layer 35. A plurality of metal pads 37 are provided in the insulating film 17 on these via plugs 36.

[0032] The circuit chip 2 further includes a substrate 60 and a through electrode 61. The substrate 60 is provided on the surface S4 of the semiconductor 19. The substrate 60 is, for example, a semiconductor substrate made of silicon oxide film or silicon. The through electrode 61 is provided in the interlayer insulating film 18, the semiconductor 19, and the substrate 60, and is provided on the wiring layer 34. The substrate 60 corresponds to silicon C1a in FIG. 2 and the like. The through electrode 61 corresponds to the through electrode T1 in FIG. 2 and the like. The through electrode 61 is formed so as to be embedded in the substrate 60, for example, before the wiring layer 34 is formed. The circuit chip 2 includes a CMOS control circuit (logic circuit) that controls the array chip 1.

[0033] The array chip 1 includes metal pads 41, via plugs 42, and a wiring layer 43. A plurality of metal pads 41 are provided on the metal pads 37 within the insulating film 16. A plurality of via plugs 42 are provided on the metal pads 41. A plurality of wiring layers 43 are provided on the via plugs 42 and include a plurality of wirings. Each word line WL and each bit line BL is electrically connected to a corresponding wiring in the wiring layer 43.

[0034] The array chip 1 further includes plugs 44, plugs 46, and metal pads 47. The plugs 44 are provided in the interlayer insulating film 15 or the insulating film 12, and are provided on the wiring layer 43. The plugs 46 are provided in the substrate 13 or the insulating film 14 via an insulating film 45, and are provided on the plugs 44. The metal pads 47 are provided in the insulating film 14, and are provided on the plugs 46. The metal pads 47 are provided so as to be flush with the lower surface of the insulating film 14. The metal pads 47 are external connection pads for the chip C1.

[0035] 11 is a cross-sectional view showing a state in which a chip C1 is bonded to a base substrate B. The base substrate B includes external terminals 70, a wiring layer 71, plugs 72, and metal pads 73. A plurality of external terminals 70 are provided below the base substrate B. The external terminals 70 are metal terminals for external connection, and play a role similar to that of the metal balls BE described with reference to FIG.

[0036] The wiring layer 71 is provided inside the base substrate B and includes a plurality of wires. The plug 72 is provided inside the base substrate B and on the wiring layer 71. The metal pad 73 is provided on the plug 72. The metal pad 73 is provided inside the base substrate B and is provided so as to be flush with the upper surface of the base substrate B.

[0037] The metal pads 47 of the chip C1 and the metal pads 73 of the base substrate B are arranged so that the pads located at corresponding positions face each other and are joined by bonding.

[0038] A controller may be provided inside the base substrate. Fig. 12 shows an example of a base substrate Ba having a controller 74 provided therein. The controller 74 is a controller for controlling the chip C1 and the like. The controller 74 and the metal pad 73 are connected by a plug 72.

[0039] FIG. 13 is a cross-sectional view showing a state in which a chip C2 is further bonded to the chip C1 shown in FIG. 11 by bonding. From the state shown in FIG. 11, the through electrodes 61 of the chip C1 are exposed by the method described with reference to FIGS. 3 to 6, and the chip C2 is placed on the chip C1. The through electrodes 61 of the chip C1 and the metal pads 47 of the chip C2 are arranged opposite each other and bonded by bonding. The surface of the chip C2 facing the chip C1 side may be formed of an insulating film such as a silicon oxide film, and may be formed flush with the pads 47. The surface of the chip C1 facing the chip C2 side may be formed of an insulating film such as a silicon oxide film, and may be formed flush with the through electrodes 61.

[0040] As shown in Figure 14, the case where the through electrodes 61 of the chip C1 and the metal pads 47 of the chip C2 are arranged will be described as an example. Figure 14 shows the top surface of the chip C1 and the bottom surface of the chip C2. In the example shown in Figure 14, the through electrodes 61a correspond to the metal pads 47a, and the through electrodes 61b correspond to the metal pads 47b. The chip C2 is placed on the chip C1 and bonded so that these corresponding electrodes are arranged opposite each other.

[0041] 15 illustrates the case where chip C1 is bonded to base substrate B. FIG. 15 shows the upper surface of base substrate B and the lower surface of chip C1. In the example illustrated in FIG. 15, metal pad 73a corresponds to metal pad 47a, and metal pad 73b corresponds to metal pad 47b. Bonding is performed by placing chip C1 on base substrate B so that these corresponding pads are arranged opposite each other.

[0042] In Figure 15, an example is described in which the metal pad 73 is arranged linearly along the short side of the base substrate B, and the metal pad 47 is also arranged linearly along the short side of the chip C1, but the arrangement of the metal pad 73 and the metal pad 47 is not limited to this.

[0043] As shown in FIG. 16, the metal pads may be arranged in an irregular pattern. FIG. 16 shows the top surface of the base substrate BD and the bottom surface of the chip C1D. In the example shown in FIG. 16, metal pad 73Da corresponds to metal pad 47Da, and metal pad 73Db corresponds to metal pad 47Db. The chip C1D is placed on the base substrate BD and bonded so that these corresponding pads are arranged opposite each other. As shown in FIG. 16, the arrangement of the metal pads on the chip C1 may be changed depending on the arrangement of the metal pads on the base substrate BD, or the arrangement of the metal pads on the chip C1 shown in FIG. 15 may be rewired to accommodate this.

[0044] FIG. 17 is a diagram for explaining a semiconductor memory device E1 using the base substrate Ba described with reference to FIG. 12. As shown in FIG. 17, the base substrate Ba includes a controller 74 therein. A wiring layer 71 is provided inside the base substrate Ba. Chips C are stacked on the base substrate Ba. The chips C are not limited to a configuration in which a memory substrate and a CMOS (Complementary Metal-Oxide Semiconductor) are bonded together, as in the chip C1 described with reference to FIG. 10 etc., and may be composed of, for example, a memory substrate alone. A protective film P is provided around the outer periphery of the stacked chips C. A molded resin layer M is provided around the protective film P.

[0045] 18 is a cross-sectional view illustrating the structure of a semiconductor memory device E2 according to the second embodiment. The semiconductor memory device E2 includes a base substrate B and multiple chips C. The chips C are supported and held on the base substrate B by adhesive portions 81. The base substrate B and the chips C are electrically connected by connection electrodes 82. Multiple metal balls BE are bonded to the surface of the base substrate B opposite to the surface to which the chips C are bonded.

[0046] Each of the plurality of chips C is provided with a through electrode T. A protective film P is provided so as to cover the side surfaces of the plurality of chips C. The protective film P may be removed. A mold resin layer M is provided so as to cover the protective film P.

[0047] Next, a method for manufacturing the semiconductor memory device E2 will be described with reference to Figures 19 to 28. Figures 19 to 28 illustrate an example in which two chips C are mounted.

[0048] A support substrate SB is prepared as shown in Fig. 19. The support substrate SB is a substrate that is removed during the manufacturing process.

[0049] 20, the chip C is bonded onto the support substrate SB with an adhesive or the like. Inside the chip C, a through electrode T is provided.

[0050] 21, a protective film P is provided on the chip C bonded on the support substrate SB, the chip C is exposed to expose the through electrodes T, and the next chip C is bonded. The through electrodes T of the bonded chips C are bonded to each other. The bonding of the chips C to each other is performed by bonding.

[0051] Subsequently, as shown in FIG. 22, a protective film P is provided on the chip C arranged above, and the chip C is exposed to expose the through electrodes T.

[0052] 23, the control chip CT is connected to the chip C arranged above. The control chip CT is joined to the through electrodes T of the chip C arranged above.

[0053] Next, as shown in FIG. 24, a base substrate B is prepared. The base substrate B has a wiring layer (not shown). The base substrate B has metal pads 83 on the top. The support substrate SB and chip C shown in FIG. 23 are turned upside down and bonded to the base substrate B. Bonding is performed by adhesive portions 81. The adhesive portions 81 also serve as support for holding the chip C at a predetermined distance from the base substrate B. The chip C and the base substrate B are electrically connected by electrodes 82. The electrodes 82 are connected to the through electrodes T and the metal pads 83.

[0054] Next, the support substrate SB is removed as shown in Fig. 25. Next, as shown in Fig. 26, a molding resin is filled so as to cover the chip C on the base substrate B, and a molding resin layer M is formed.

[0055] Next, as shown in FIG. 27, metal balls BE are bonded to the lower side of the base substrate B. The metal balls BE are bonded to metal pads 83 provided on the lower surface of the base substrate B. Next, as shown in FIG. 28, the semiconductor memory device E2 is obtained by cutting along cut lines L and dividing into individual pieces. At this time, the protective film P may be partially exposed from the side surface of the molded resin layer M. Unlike the semiconductor device E in FIG. 1, the protective film P is exposed near the end of the chip C farthest from the base substrate B. The protective film P may be removed before the molded resin layer M is formed. In this case, the protective film P is not exposed from the molded resin layer M.

[0056] The semiconductor devices E, E1, and E2 according to the above embodiments comprise a base substrate B including a wiring layer and a plurality of chips C stacked on the base substrate B, with electrodes and a protective film P provided between the plurality of chips, and a protective film P also provided on the side of the chip C.

[0057] The protective film P includes at least one of SiO2, SiOC, SiN, and SiCN. The protective film P is an insulating film formed by coating.

[0058] The protective film P provided on the side surface of the chip C has a different thickness on the base substrate B side and on the upper end side of the chip C. The protective film P provided on the side surface of the chip C is provided in multiple layers.

[0059] The manufacturing method of the semiconductor devices E, E1, and E2 according to the above embodiments includes preparing a base substrate B including a wiring layer, bonding a chip C including electrodes onto the base substrate B, forming a protective film P on the chip C, thinning the protective film P on the chip C, and exposing the electrodes on the chip C.

[0060] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Design modifications to these specific examples made by a person skilled in the art as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements of the above-described specific examples, as well as their arrangement, conditions, shape, etc., are not limited to those exemplified and can be modified as appropriate. The elements of the above-described specific examples can be combined in various ways as appropriate, as long as no technical contradictions arise. [Explanation of symbols]

[0061] 1: Array chip 2: Circuit chip 60: insulating film 61:Through electrode 70: External terminal 71: Wiring layer 72: Plug 73: Metal pad B: Base board C, C1, C2, C3, C4, C5, C6: Chip C1a: Silicon E: Semiconductor memory device M: Mold resin layer P:Protective film

Claims

1. A semiconductor device, a base substrate including a wiring layer; a first chip stacked on the base substrate, the first chip having a first surface facing the base substrate, a second surface opposite to the first surface, a first electrode and a first protective film provided on the second surface, the first electrode and the first protective film being flush with each other; a second chip stacked on the first chip, the second chip having a third surface facing the second surface, a fourth surface opposite the third surface, a second electrode provided on the third surface and directly connected to the first electrode, a third electrode provided on the fourth surface, and a second protective film, the third electrode and the second protective film being flush with each other; a third chip stacked on the second chip, the third chip having a fifth surface facing the fourth surface, a sixth surface opposite the fifth surface, and a fourth electrode provided on the fifth surface and directly connected to the third electrode; a molding resin that covers the base substrate, the first chip, the second chip, and the third chip, the first protective film is also formed on a side surface of the first chip, and the second protective film is also formed on side surfaces of the first chip and the second chip; the first protective film and the second protective film are exposed from a side surface of the molding resin. Semiconductor device.

2. 2. The semiconductor device according to claim 1, The first protective film and the second protective film are made of SiO ２ , SiOC, SiN, and SiCN.

3. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the first protective film and the second protective film are insulating films formed by coating.

4. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the first protective film and the second protective film are provided on the side surfaces of the first chip, the second protective film is provided on the side surfaces of the second chip, and no protective film is provided on the side surfaces of the third chip.

5. A method for manufacturing a semiconductor device, comprising: providing a base substrate including a wiring layer; a first chip having a first surface and a second surface opposite to the first surface is disposed on the base substrate such that the first surface faces the base substrate; thinning the first chip from the second surface side; forming a first protective film so as to cover the first electrode exposed on the second surface side and the base substrate; processing the first protective film so that the first electrode and the first protective film are flush with each other and the first protective film remains on the side surface of the first chip; a second chip having a third surface facing the second surface and a fourth surface opposite to the third surface is disposed on the first chip such that a second electrode provided on the third surface is directly connected to the first electrode; thinning the second chip from the fourth surface side; forming a second protective film so as to cover the third electrode exposed on the fourth surface side, the first protective film, and the base substrate; processing the second protective film so that the second protective film and the third electrode are flush with each other and the second protective film remains on the side surfaces of the first chip and the second chip; a third chip having a fifth surface facing the fourth surface and a sixth surface opposite the fifth surface is disposed on the second chip such that a fourth electrode provided on the fifth surface is directly connected to the third electrode; a molding resin is provided so as to cover the base substrate, the first chip, the second chip, and the third chip; the molding resin is cut so that the first protective film and the second protective film are exposed from the side surfaces of the molding resin.

6. 6. The method for manufacturing a semiconductor device according to claim 5, A method for manufacturing a semiconductor device, wherein the first protective film and the second protective film are provided on the side surfaces of the first chip, the second protective film is provided on the side surfaces of the second chip, and no protective film is provided on the side surfaces of the third chip.

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