Detection Device

Abstract

To provide a detection device capable of suppressing deterioration in detection accuracy.SOLUTION: A detection device includes a plurality of detection elements arranged in a matrix in a detection region and having photoelectric conversion elements to which a reverse bias voltage is applied when detection is performed, and an initialization circuit that applies an initialization voltage higher than the reverse bias voltage to the photoelectric conversion element before applying the reverse bias voltage to the photoelectric conversion element.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a detection device. [Background technology]

[0002] Optical detection devices are known in which a plurality of photoelectric conversion elements, such as PIN photodiodes, are arranged on a substrate. Such optical detection devices are used as biosensors that detect biometric information, such as fingerprint sensors and vein sensors. The plurality of photoelectric conversion elements are arranged at intervals according to the detection resolution. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-85559 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, for PIN photodiodes that make up the photoelectric conversion element, the higher the reverse bias voltage, the greater the individual variation in reverse bias current, and the lower the reverse bias voltage, the longer it takes for the reverse bias current to stabilize. For this reason, depending on the reverse bias voltage setting, there is a possibility that detection accuracy will decrease.

[0005] An object of the present invention is to provide a detection device that can suppress a decrease in detection accuracy. [Means for solving the problem]

[0006] A detection device according to one aspect of the present disclosure includes a plurality of detection elements arranged in a matrix in a detection region, each having a photoelectric conversion element to which a reverse bias voltage is applied when performing detection, and an initialization circuit that applies an initialization voltage greater than the reverse bias voltage to the photoelectric conversion elements before applying the reverse bias voltage to the photoelectric conversion elements.

[0007] A detection device according to one embodiment of the present disclosure comprises a plurality of detection elements arranged in a matrix in a detection region, each having a photoelectric conversion element to which a reverse bias voltage is applied when performing detection, and an initialization circuit that initializes the plurality of detection elements, wherein the initialization circuit comprises a first wiring that supplies the reverse bias voltage to the photoelectric conversion elements, a second wiring that supplies an initialization voltage that is greater than the reverse bias voltage to the photoelectric conversion elements, and a switch circuit that connects either the first wiring or the second wiring to the plurality of detection elements. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device according to a modified example. [Figure 3] FIG. 3 is a plan view showing the detection device according to the embodiment. [Figure 4] FIG. 4 is a block diagram illustrating an example of the configuration of a detection device according to an embodiment. [Figure 5] FIG. 5 is a circuit diagram showing a plurality of detection elements. [Figure 6] FIG. 6 is a timing waveform diagram showing an example of the operation of the detection element during the detection period. [Figure 7] FIG. 7 is a timing chart showing an example of output timing of the reset control signal during the detection period. [Figure 8] FIG. 8 is a diagram illustrating the operation of the detection element during the reset period. [Figure 9A] FIG. 9A is a diagram showing the relationship between the reverse bias voltage and the reverse bias current of a PIN photodiode. [Figure 9B] FIG. 9B is a diagram showing the relationship between the reverse bias voltage and the reverse bias current of the PIN photodiode. [Figure 9C] FIG. 9C is a diagram showing the relationship between the reverse bias voltage and the reverse bias current of a PIN photodiode. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of the initialization circuit of the detection device according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing a specific example of a configuration to which the initialization circuit of the detection device according to the first embodiment is applied. [Figure 12] FIG. 12 is a timing chart illustrating the operation of the initialization circuit of the detection device according to the first embodiment. [Figure 13] FIG. 13 is a diagram showing the relationship between the reverse bias voltage and the reverse bias current of the PIN photodiode when the initialization circuit of the detection device according to the first embodiment is applied. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of an initialization circuit of the detection device according to the second embodiment. [Figure 15] FIG. 15 is a diagram showing a specific example of a configuration to which the initialization circuit of the detection device according to the second embodiment is applied. [Figure 16] FIG. 16 is a timing chart illustrating the operation of the initialization circuit of the detection device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Modes for carrying out the invention (embodiments) will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, for clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements similar to those previously described with reference to the preceding figures are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] Fig. 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with an illumination device having a detection device according to an embodiment. As shown in Fig. 1, a detection device with an illumination device 120 has a detection device 1, an illumination device 121, and a cover glass 122. The illumination device 121, the detection device 1, and the cover glass 122 are stacked in this order in a direction perpendicular to the surface of the detection device 1.

[0011] The illumination device 121 has a light irradiation surface 121a that emits light, and emits light L1 from the light irradiation surface 121a toward the detection device 1. The illumination device 121 is a backlight. The illumination device 121 may be, for example, a so-called side-light type backlight that has a light guide plate provided at a position corresponding to the detection area AA and a plurality of light sources lined up at one end or both ends of the light guide plate. For example, a light-emitting diode (LED) that emits light of a predetermined color is used as the light source. The illumination device 121 may also be a so-called direct-type backlight that has a light source (e.g., an LED) provided directly below the detection area AA. The illumination device 121 is not limited to a backlight, and may be provided to the side or above the detection device 1, and may emit light L1 from the side or above the finger Fg.

[0012] The detection device 1 is disposed opposite the light irradiation surface 121a of the illumination device 121. Light L1 emitted from the illumination device 121 passes through the detection device 1 and the cover glass 122. The detection device 1 is, for example, a light-receiving biosensor, and can detect irregularities on the surface of the finger Fg (e.g., a fingerprint) by detecting light L2 reflected from the surface of the finger Fg. Alternatively, the detection device 1 may detect information about the living body by detecting light L2 reflected inside the finger Fg in addition to detecting a fingerprint. The information about the living body includes, for example, an image of blood vessels such as veins, a pulse rate, a pulse wave, etc. The color of the light L1 from the illumination device 121 may be varied depending on the detection target.

[0013] The cover glass 122 is a member for protecting the detection device 1 and the illumination device 121, and covers the detection device 1 and the illumination device 121. The cover glass 122 is, for example, a glass substrate. Note that the cover glass 122 is not limited to a glass substrate, and may be a resin substrate or the like. Also, the cover glass 122 may not be provided. In this case, a protective layer is provided on the surface of the detection device 1, and the finger Fg comes into contact with the protective layer of the detection device 1.

[0014] The detection device 120 with an illumination device may be provided with a display panel instead of the illumination device 121. The display panel may be, for example, an organic light-emitting diode (OLED) display panel or an inorganic light-emitting diode (micro LED, mini LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using liquid crystal elements as display elements, or an electrophoretic display panel (EPD: Electrophoretic Display) using electrophoretic elements as display elements. Even in this case, display light emitted from the display panel passes through the detection device 1, and based on light L2 reflected by the finger Fg, information about the fingerprint and biometrics of the finger Fg can be detected.

[0015] Fig. 2 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with an illumination device according to a modified example. As shown in Fig. 2, detection device with an illumination device 120 has the detection device 1, an illumination device 121, and a cover glass 122 stacked in this order in a direction perpendicular to the surface of the detection device 1. In this modified example, a display panel such as an organic EL display panel 126 can be used instead of the illumination device 121.

[0016] Light L1 emitted from the illumination device 121 passes through the cover glass 122 and is then reflected by the finger Fg. Light L2 reflected by the finger Fg passes through the cover glass 122 and then passes through the illumination device 121. The detection device 1 receives the light L2 that has passed through the illumination device 121, thereby enabling detection of information related to a living body, such as a fingerprint.

[0017] 3 is a plan view showing a detection device according to an embodiment. As shown in FIG. 3, the detection device 1 includes a substrate 21, a sensor unit 10, a first gate line driving circuit 15A, a second gate line driving circuit 15B, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

[0018] A control board 101 is electrically connected to the substrate 21 via a wiring board 110. The wiring board 110 is, for example, a flexible printed circuit board or a rigid board. A detection circuit 48 is provided on the wiring board 110. A control circuit 102 and a power supply circuit 103 are provided on the control board 101. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 supplies voltage signals such as a power supply potential Vsf and a reference potential Vcom (see FIG. 5 ) to the sensor unit 10, the first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16.

[0019] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area that overlaps with the multiple detection elements 3 of the sensor unit 10. The peripheral area GA is an area outside the detection area AA that does not overlap with the detection elements 3. In other words, the peripheral area GA is an area between the periphery of the detection area AA and the periphery of the substrate 21. The first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 are provided in the peripheral area GA.

[0020] Each of the multiple detection elements 3 of the sensor unit 10 is an optical sensor having a photoelectric conversion element 30. The photoelectric conversion element 30 is a photodiode that outputs an electrical signal corresponding to the light irradiated thereon. More specifically, the photoelectric conversion element 30 is a PIN (Positive Intrinsic Negative) photodiode. The detection elements 3 are arranged in a matrix in the detection area AA. The photoelectric conversion elements 30 of the multiple detection elements 3 perform detection in accordance with gate drive signals (e.g., a reset control signal RST and a read control signal RD) supplied from the first gate line drive circuit 15A and the second gate line drive circuit 15B. The multiple photoelectric conversion elements 30 output an electrical signal corresponding to the light irradiated thereon as a detection signal Vdet to the signal line selection circuit 16. The detection device 1 detects information related to a living body based on the detection signals Vdet from the multiple detection elements 3.

[0021] The first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the first gate line driving circuit 15A and the second gate line driving circuit 15B are provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48. The first gate line driving circuit 15A and the second gate line driving circuit 15B are arranged on either side of the detection area AA in the first direction Dx. However, the first gate line driving circuit 15A and the second gate line driving circuit 15B may be formed as a single circuit and arranged along one side of the detection area AA.

[0022] The first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the substrate 21.

[0023] Fig. 4 is a block diagram showing an example of the configuration of a detection device according to an embodiment. As shown in Fig. 4, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Some or all of the functions of the detection control circuit 11 are included in a control circuit 102. In addition, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

[0024] The detection control circuit 11 is a circuit that supplies control signals to the first gate line drive circuit 15A, the second gate line drive circuit 15B, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals, such as a start signal STV and a clock signal CK, to the first gate line drive circuit 15A and the second gate line drive circuit 15B. In addition, the detection control circuit 11 supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16 during a detection period in which detection processing is performed.

[0025] The first gate line driving circuit 15A and the second gate line driving circuit 15B are circuits that drive multiple gate lines (read control scanning lines GLrd and reset control scanning lines GLrst (see FIG. 5)) based on various control signals. The first gate line driving circuit 15A and the second gate line driving circuit 15B sequentially or simultaneously select multiple gate lines and supply gate driving signals (e.g., reset control signal RST, read control signal RD) to the selected gate lines. In this way, the first gate line driving circuit 15A and the second gate line driving circuit 15B select multiple photoelectric conversion elements 30 connected to the gate lines.

[0026] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal lines SL (see FIG. 5). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on a selection signal ASW supplied from the detection control circuit 11. As a result, the signal line selection circuit 16 outputs the detection signal Vdet from the detection element 3 to the detection unit 40. Note that the signal line selection circuit 16 may not be provided. In this case, the output signal line SL may be directly connected to the detection circuit 48.

[0027] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a memory circuit 46, and a detection timing control circuit 47. Based on a control signal supplied from the detection control circuit 11, the detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 so that they operate in synchronization.

[0028] The detection circuit 48 is, for example, an analog front end (AFE) circuit. The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplifier circuit 42 and an A / D conversion circuit 43. The detection signal amplifier circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal.

[0029] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg comes into contact with or close to the detection surface, the signal processing circuit 44 can detect a fingerprint, which is an uneven surface of the finger Fg, based on the signal from the detection circuit 48. The signal processing circuit 44 may also detect information about the living body based on the signal from the detection circuit 48. The information about the living body may include, for example, a blood vessel image of the finger Fg, a pulse wave, a pulse rate, and blood oxygen saturation. Note that, in this embodiment, the detection device uses the finger Fg (fingerprint) as the detection object (detection target), but the detection object may be not only the finger Fg, but also any part of the living body, such as the palm, wrist, or sole.

[0030] The memory circuit 46 temporarily stores the signals calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0031] The coordinate extraction circuit 45 is a logic circuit that calculates the detected coordinates of the unevenness of the surface of the finger Fg or the like when the signal processing circuit 44 detects contact or proximity of the finger Fg. The coordinate extraction circuit 45 is also a logic circuit that calculates the detected coordinates of the blood vessels of the finger Fg or the palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from each detection element 3 of the sensor unit 10 to generate two-dimensional information that indicates the shape of the unevenness of the surface of the finger Fg or the like. Note that the coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0032] Next, an example of the circuit configuration and operation of the detection device 1 will be described. Fig. 5 is a circuit diagram showing a plurality of detection elements. As shown in Fig. 5, the detection element 3 has a photoelectric conversion element 30, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. Furthermore, the detection element 3 is provided with a reset control scanning line GLrst and a readout control scanning line GLrd as detection drive lines (gate lines), and an output signal line SL as wiring for signal readout.

[0033] The reset control scanning line GLrst, the readout control scanning line GLrd, and the output signal line SL are each connected to a plurality of detection elements 3. Specifically, the reset control scanning line GLrst and the readout control scanning line GLrd extend in a first direction Dx (see FIG. 3) and are connected to a plurality of detection elements 3 arranged in the first direction Dx. Furthermore, the output signal line SL extends in a second direction Dy and is connected to a plurality of detection elements 3 arranged in the second direction Dy. The output signal line SL is a wiring through which signals from a plurality of transistors (readout transistors Mrd and source follower transistors Msf) are output.

[0034] The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are provided for one photoelectric conversion element 30. Each of the multiple transistors in the detection element 3 is configured as an n-type TFT (Thin Film Transistor). However, without being limited to this, each transistor may be configured as a p-type TFT.

[0035] A reference potential Vcom is applied to the anode of the photoelectric conversion element 30. The cathode of the photoelectric conversion element 30 is connected to a node N1. The node N1 is connected to one of the source or drain of the reset transistor Mrst and the gate of the source follower transistor Msf. When light is irradiated onto the photoelectric conversion element 30, a signal (charge) output from the photoelectric conversion element 30 is accumulated in a capacitance element formed at the node N1.

[0036] The gate of the reset transistor Mrst is connected to a reset control scanning line GLrst. A reset potential Vrst is supplied to the other of the source or drain of the reset transistor Mrst. When the reset transistor Mrst is turned on (conductive) in response to a reset control signal RST supplied from the first gate line driving circuit 15A, the potential of the node N1 is reset to the reset potential Vrst. The reference potential Vcom has a potential lower than the reset potential Vrst, and the photoelectric conversion element 30 is reverse-bias driven.

[0037] The source follower transistor Msf is connected between a terminal to which a power supply potential Vsf is supplied and the readout transistor Mrd (node ​​N2). The gate of the source follower transistor Msf is connected to the node N1. A signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30 is supplied to the gate of the source follower transistor Msf. As a result, the source follower transistor Msf outputs a signal voltage corresponding to the signal (charge) generated in the photoelectric conversion element 30 to the readout transistor Mrd.

[0038] The readout transistor Mrd is connected between the source (node ​​N2) of the source follower transistor Msf and the output signal line SL. The gate of the readout transistor Mrd is connected to the readout control scanning line GLrd. When the readout transistor Mrd is turned on in response to a readout control signal RD supplied from the second gate line drive circuit 15B, the signal output from the source follower transistor Msf, i.e., a signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30, is output to the output signal line SL as the detection signal Vdet.

[0039] 5, the reset transistor Mrst and the readout transistor Mrd each have a single-gate structure, but the reset transistor Mrst and the readout transistor Mrd may each have a so-called double-gate structure in which two transistors are connected in series, or may have a structure in which three or more transistors are connected in series. Furthermore, the circuit of one detection element 3 is not limited to a structure having three transistors: the reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd. The detection element 3 may have two transistors, or may have four or more transistors.

[0040] 6 is a timing waveform diagram showing an example of the operation of the detection element during the detection period. As shown in FIG. 6, the detection element 3 performs detection during the detection period in the order of the reset period Prst, the accumulation period Pch, and the readout period Pdet. The power supply circuit 103 supplies the reference potential Vcom to the anode of the photoelectric conversion element 30 over the reset period Prst, the accumulation period Pch, and the readout period Pdet.

[0041] At time t0, the control circuit 102 sets the reset control signal RST supplied to the reset control scanning line GLrst to high (high-level voltage), starting the reset period Prst. During the reset period Prst, the reset transistor Mrst is turned on (conductive), and the potential at the node N1 rises to the reset potential Vrst. As a result, the photoelectric conversion element 30 is reverse-biased by the potential difference between the reset potential Vrst and the reference potential Vcom. Furthermore, because the readout transistor Mrd is off (non-conductive), the source of the source follower transistor Msf is charged by the power supply potential Vsf, and the potential at the node N2 rises.

[0042] At time t1, the control circuit 102 sets the read control signal RD supplied to the read control scanning line GLrd to high (high-level voltage). This turns on the read transistor Mrd (conducting state), and the potential of the node N2 becomes (Vrst-Vthsf). Note that Vthsf is the threshold voltage Vthsf of the source follower transistor Msf.

[0043] At time t2, the control circuit 102 sets the reset control signal RST to low (low-level voltage), ending the reset period Prst and starting the accumulation period Pch. During the accumulation period Pch, the reset transistor Mrst is turned off (non-conductive). A signal corresponding to the light irradiated on the photoelectric conversion element 30 is accumulated, and the potential of the node N1 drops to (Vrst-Vphoto). Note that Vphoto is a signal (voltage fluctuation) corresponding to the light irradiated on the photoelectric conversion element 30.

[0044] At time t3, the potential of the detection signal Vdet1 output from the output signal line SL becomes (Vrst-Vthsf-Vrdon), where Vrdon is the voltage drop caused by the on-resistance of the read transistor Mrd.

[0045] At time t3, the control circuit 102 sets the read control signal RD low (low-level voltage). This turns the read transistor Mrd off (non-conducting state), and the potential of the node N2 becomes constant at (Vrst-Vthsf). In addition, a load is applied so that the potential of the detection signal Vdet output from the output signal line SL becomes low (low-level voltage).

[0046] At time t4, the control circuit 102 sets the read control signal RD to high (high-level voltage). This turns on the read transistor Mrd (conducting state), ends the accumulation period Pch, and starts the read period Pdet. The potential of the node N2 changes to (Vrst-Vthsf-Vphoto) in accordance with the signal Vphoto. The potential of the detection signal Vdet2 output during the read period Pdet drops by the signal Vphoto from the potential of the detection signal Vdet1 acquired at time t3, to (Vrst-Vthsf-Vrdon-Vphoto).

[0047] The detection unit 40 can detect light irradiated onto the photoelectric conversion element 30 based on a signal (Vphoto) that is the difference between the detection signal Vdet1 at time t3 and the detection signal Vdet2 at time t5. Although Fig. 6 shows an example of the operation of one detection element 3, the first gate line drive circuit 15A and the second gate line drive circuit 15B sequentially scan the reset control scanning line GLrst and the readout control scanning line GLrd in a time-division manner, thereby enabling detection by the detection elements 3 throughout the entire detection area AA.

[0048] FIG. 7 is a timing chart showing an example of output timing of the reset control signal during the detection period.

[0049] As shown in FIG. 7, at the start of the detection period, the start signal STV is controlled to be "H" (high level voltage) at time t10, and the reset control signal RST <1> ,RST <2> ,RST <3> ,... is controlled to "H" (high level voltage). Reset control signal RST <1> The "H" (high level voltage) period is the reset period Prst in the first row of the plurality of detection elements 3 arranged in the first direction Dx of the detection area AA. <1> The reset control signal RST <2> The "H" (high level voltage) period of the reset period Prst in the second row of the plurality of detection elements 3 arranged in the first direction Dx of the detection area AA <2> The reset control signal RST <3> The "H" (high level voltage) period of the reset period Prst <3> Corresponds to.

[0050] 8 is a diagram illustrating the operation of the detection element during the reset period. As described above, the photoelectric conversion element 30 is reverse-biased during the reset period Prst. At this time, a reverse bias voltage Vpn, which is the potential difference between the reset potential Vrst and the reference potential Vcom, is applied to the photoelectric conversion element 30. As a result, a reverse bias current Ipn flows through the photoelectric conversion element 30.

[0051] 9A, 9B, and 9C are diagrams showing the relationship between the reverse bias voltage and the reverse bias current of a PIN photodiode. FIG. 9A shows the change over time of the reverse bias current when the reverse bias voltage Vpn is relatively small. FIG. 9C shows the change over time of the reverse bias current when the reverse bias voltage Vpn is relatively large. FIG. 9B shows the change over time of the reverse bias current when the reverse bias voltage Vpn is larger than that shown in FIG. 9A and smaller than that shown in FIG. 9C. In the examples shown in FIGS. 9A, 9B, and 9C, the solid lines indicate the change over time of the reverse bias current Ipn in the bright region, and the dashed lines indicate the change over time of the reverse bias current Ipn in the dark region. In addition, in FIGS. 9A, 9B, and 9C, the solid and dashed arrows conceptually indicate the relative magnitude of the variation in the reverse bias current Ipn.

[0052] 9A, 9B, and 9C, the PIN photodiode constituting the photoelectric conversion element 30 of the detection element 3 generally exhibits greater variations in the reverse bias current Ipn as the reverse bias voltage Vpn increases. For this reason, it is preferable that the reverse bias voltage Vpn applied to the photoelectric conversion element 30 be as small as possible.

[0053] 9A, 9B, and 9C, the smaller the reverse bias voltage Vpn, the longer the time it takes for the reverse bias current Ipn to stabilize after the reverse bias voltage Vpn is applied. For this reason, for example, when acquiring the detection signal Vdet over multiple frames (multiple times) to improve detection accuracy, the value of the detection signal Vdet acquired in each frame may change, making accurate detection processing impossible.

[0054] 7, an initialization period is provided in which an initialization voltage greater than the reverse bias voltage Vpn applied to the photoelectric conversion element 30 during the detection period is applied, thereby shortening the stabilization time of the reverse bias current Ipn during the detection period and suppressing a decrease in detection accuracy. Below, a configuration and operation for applying an initialization voltage greater than the reverse bias voltage Vpn applied to the photoelectric conversion element 30 during the detection period during the initialization period before the detection period will be described.

[0055] (Embodiment 1) Fig. 10 is a diagram showing an example of the configuration of the initialization circuit of the detection device according to embodiment 1. Fig. 11 is a diagram showing a specific example of a configuration to which the initialization circuit of the detection device according to embodiment 1 is applied. Fig. 12 is a timing chart explaining the operation of the initialization circuit of the detection device according to embodiment 1. Fig. 13 is a diagram showing the relationship between the reverse bias voltage and reverse bias current of a PIN photodiode when the initialization circuit of the detection device according to embodiment 1 is applied.

[0056] As shown in FIG. 10, the initialization circuit 17 includes a reset transistor Mrst<m,n> a first transistor Tr1 that applies a reset potential Vrst (first potential) to the cathode (node ​​N1) of the photoelectric conversion element 30 via a reset transistor Mrst<m,n> and a logic inversion circuit INV that inverts the control logic of the first transistor Tr1 and the second transistor Tr2. In other words, the initialization circuit 17 includes a wiring (first wiring) that applies a reverse bias voltage to the photoelectric conversion element 30 by supplying the reset potential Vrst (first potential) to the cathode of the photoelectric conversion element 30, and also includes a wiring (second wiring) that applies an initialization voltage that is a higher reverse bias voltage to the photoelectric conversion element 30 by supplying the high potential VGH (second potential) that is higher than the reset potential Vrst (first potential) to the cathode of the photoelectric conversion element 30. Furthermore, the initialization circuit 17 includes a switch circuit (a first transistor Tr1, a second transistor Tr2, and a logic inversion circuit INV) that connects either a wiring (a first wiring) that supplies a reset potential Vrst (a first potential) or a wiring (a second wiring) that supplies a high potential VGH (a second potential) to the detection element 3. The high potential VGH (a second potential) may be, for example, the power supply potential Vsf.

[0057] As shown in FIG. 11, the initialization circuit 17 may be configured to have a first transistor Tr1 and a second transistor Tr2 for each column of the detection elements 3 arranged in the second direction Dy of the detection area AA, or may be configured to have a first transistor Tr1 and a second transistor Tr2 for each of multiple columns of the detection elements 3 arranged in the second direction Dy of the detection area AA.

[0058] The initialization circuit 17 is provided in the peripheral area GA. Specifically, in the configuration shown in Fig. 11, the initialization circuit 17 is provided in an area of ​​the peripheral area GA that extends along the first direction Dx. Alternatively, the initialization circuit 17 may be provided, for example, between the sensor unit 10 and the detection circuit 48.

[0059] As shown in FIGS. 10 and 11, an initialization signal INIT is input to the initialization circuit 17. The initialization signal INIT is input to the gate of the second transistor Tr2, and a signal obtained by logically inverting the initialization signal INIT by a logic inverter circuit INV is input to the gate of the first transistor Tr1. The initialization signal INIT is controlled to "H" (high-level voltage) during the initialization period and then controlled to "L" (low-level voltage). The initialization signal INIT may be output from, for example, the detection control circuit 11 (see FIG. 4). Furthermore, in a configuration including a signal line selection circuit 16, the initialization signal INIT may be, for example, a selection signal ASW supplied during the detection period. In this case, the selection signal ASW may be controlled to "H" (high-level voltage) during the initialization period and then controlled to "L" (low-level voltage).

[0060] As shown in FIG. 12, in the initialization period provided immediately before the detection period, the initialization signal INIT and the reset control signal RST <n>is controlled to "H" (high level voltage), and the potential VN1 of the node N1<m,n> becomes a high potential VGH (second potential) applied via the second transistor Tr2, and a high potential VGH (second potential) higher than the reset potential Vrst (first potential) is applied to the cathode of the photoelectric conversion element 30. As a result, the photoelectric conversion element 30 is reverse biased by the difference voltage (potential difference) between the high potential VGH (second potential) applied to the cathode (node ​​N1) and the reference potential Vcom applied to the anode (Vpn<m,n> =VGH-Vcom).

[0061] After that, the initialization signal INIT is controlled to be "L" (low level voltage), and the potential VN1 of the node N1<m,n> becomes the reset potential Vrst (first potential) applied via the first transistor Tr1. As a result, the photoelectric conversion element 30 is reverse biased by the differential voltage (potential difference) between the reset potential Vrst (first potential) applied to the cathode (node ​​N1) and the reference potential Vcom applied to the anode (Vpn<m,n> =Vrst-Vcom).

[0062] While FIG. 12 illustrates an example in which the reference potential Vcom is a positive potential (Vcom>GND), the reference potential Vcom may be a GND potential or a negative potential (Vcom≦GND). The configuration of the initialization circuit 17 is not limited to the configurations shown in FIGS. 10 and 11 , and may be any configuration in which a reverse bias voltage Vpn (initialization voltage) greater than that during the detection period is applied to the photoelectric conversion element 30. Alternatively, an initialization signal INIT may be input to the gate of the first transistor Tr1, and a signal obtained by logically inverting the initialization signal INIT via a logic inverter circuit INV may be input to the gate of the second transistor Tr2. In this case, the initialization signal INIT may be controlled to “L” (low-level voltage) and then “H” (high-level voltage) during the initialization period. Furthermore, the logic inverter circuit INV is not necessarily required. For example, a signal XINIT obtained by logically inverting the initialization signal INIT may be input in addition to the initialization signal INIT.

[0063] As described above, in the first embodiment, in the initialization period before the detection period, a high potential VGH (second potential) higher than the reset potential Vrst (first potential) is applied to the cathode of the photoelectric conversion element 30. As a result, in the initialization period, a reverse bias voltage Vpn (initialization voltage) higher than that in the detection period is applied to the photoelectric conversion element 30. As a result, as shown in FIG. 13 , the stabilization time of the reverse bias current Ipn in the detection period is shortened, and it is possible to suppress a decrease in detection accuracy when acquiring the detection signal Vdet over multiple frames (multiple times).

[0064] (Embodiment 2) Fig. 14 is a diagram showing a configuration example of an initialization circuit of the detection device according to embodiment 2. Fig. 15 is a diagram showing a specific example of a configuration to which the initialization circuit of the detection device according to embodiment 2 is applied. Fig. 16 is a timing chart illustrating the operation of the initialization circuit of the detection device according to embodiment 2.

[0065] As shown in FIG. 14, the initialization circuit 17a according to the second embodiment is configured to initialize the anode PD of the photoelectric conversion element 30.<m,n> a first transistor Tr1a that applies a reference potential Vcom (first potential) to the anode PD of the photoelectric conversion element 30;<m,n> The initialization circuit 17a includes a second transistor Tr2a that applies a low potential VGL (second potential) lower than a reference potential Vcom (first potential) to the anode of the photoelectric conversion element 30, and a logic inversion circuit INVa that inverts the control logic of the first transistor Tr1a and the second transistor Tr2a. In other words, the initialization circuit 17a includes wiring (first wiring) that applies a reverse bias voltage to the photoelectric conversion element 30 by supplying the reference potential Vcom (first potential) to the anode of the photoelectric conversion element 30, and also includes wiring (second wiring) that applies an initialization voltage that is a higher reverse bias voltage to the photoelectric conversion element 30 by supplying a low potential VGL (second potential) lower than the reference potential Vcom (first potential) to the anode of the photoelectric conversion element 30. Furthermore, the initialization circuit 17a includes a switch circuit (a first transistor Tr1, a second transistor Tr2, and a logic inversion circuit INV) that connects either a wiring (a first wiring) that supplies a reference potential Vcom (a first potential) or a wiring (a second wiring) that supplies a low potential VGL (a second potential) to the detection element 3. The low potential VGL (a second potential) may be, for example, the GND potential.

[0066] As shown in FIG. 15, the initialization circuit 17a may be configured to have a first transistor Tr1a and a second transistor Tr2a for each column of the detection elements 3 arranged in the second direction Dy of the detection area AA, or may be configured to have a first transistor Tr1a and a second transistor Tr2a for each of multiple columns of the detection elements 3 arranged in the second direction Dy of the detection area AA.

[0067] The initialization circuit 17a is provided in the peripheral area GA. Specifically, in the configuration shown in Fig. 15, the initialization circuit 17a is provided in a region of the peripheral area GA that extends along the first direction Dx. Alternatively, the initialization circuit 17a may be provided, for example, between the sensor unit 10 and the detection circuit 48.

[0068] As shown in FIGS. 14 and 15, an initialization signal INIT is input to the initialization circuit 17a. The initialization signal INIT is input to the gate of the second transistor Tr2a, and a signal obtained by logically inverting the initialization signal INIT by a logic inverter circuit INV is input to the gate of the first transistor Tr1a. The initialization signal INIT is controlled to "H" (high-level voltage) during the initialization period and controlled to "L" (low-level voltage) during the detection period. The initialization signal INIT may be output from, for example, the detection control circuit 11 (see FIG. 4). Furthermore, in a configuration including a signal line selection circuit 16, the initialization signal INIT may be, for example, a selection signal ASW supplied during the detection period. In this case, the selection signal ASW may be controlled to "H" (high-level voltage) during the initialization period and then controlled to "L" (low-level voltage).

[0069] As shown in FIG. 16, in the initialization period provided immediately before the detection period, the initialization signal INIT and the reset control signal RST <n>is controlled to "H" (high level voltage), and a low potential VGL (second potential) lower than the reference potential Vcom (first potential) is applied to the anode of the photoelectric conversion element 30 via the second transistor Tr2a. As a result, the photoelectric conversion element 30 is reverse biased by the differential voltage (potential difference) between the reset potential Vrst applied to the cathode (node ​​N1) and the low potential VGL (second potential) applied to the anode (Vpn<m,n> =Vrst-VGL).

[0070] Thereafter, the initialization signal INIT is controlled to "L" (low-level voltage), and the potential of the anode of the photoelectric conversion element 30 becomes the reference potential Vcom (first potential) applied via the first transistor Tr1a. As a result, the photoelectric conversion element 30 is reverse-biased by the differential voltage (potential difference) between the reset potential Vrst applied to the cathode (node ​​N1) and the reference potential Vcom (first potential) applied to the anode (Vpn<m,n> =Vrst-Vcom).

[0071] In FIG. 16, an example is shown in which the reference potential Vcom is a positive potential (Vcom > GND) and the low potential VGL (second potential) is a positive potential (Vcom > VGL > GND). However, the low potential VGL (second potential) may be the GND potential or a negative potential (VGL ≤ GND). Also, the reference potential Vcom may be the GND potential or a negative potential (Vcom ≤ GND). In this case, the low potential VGL (second potential) may be a negative potential lower than the reference potential Vcom (VGL < Vcom ≤ GND). Further, the configuration of the initialization circuit 17a is not limited to the configurations shown in FIGS. 14 and 15, and any mode in which a reverse bias voltage Vpn (initialization voltage) larger than the detection period is applied to the photoelectric conversion element 30 during the initialization period is acceptable. Also, it is acceptable that an initialization signal INIT is input to the gate of the first transistor Tr1 and a signal obtained by logically inverting the initialization signal INIT by a logic inverter circuit INV is input to the gate of the second transistor Tr2. In this case, the initialization signal INIT may be controlled to "L" (low-level voltage) during the initialization period and then controlled to "H" (high-level voltage). Furthermore, the logic inverter circuit INVa is not necessarily required. For example, in addition to the initialization signal INIT, a signal XINIT obtained by logically inverting the initialization signal INIT may be input.

[0072] As described above, in Embodiment 2, a low potential VGL (second potential) lower than the reference potential Vcom (first potential) is applied to the anode of the photoelectric conversion element 30 during the initialization period before the detection period. As a result, a reverse bias voltage Vpn (initialization voltage) larger than the detection period is applied to the photoelectric conversion element 30 during the initialization period. As a result, similar to Embodiment 1, as shown in FIG. 13, the stabilization time of the reverse bias current Ipn during the detection period is shortened, and a decrease in detection accuracy when acquiring a detection signal Vdet over a plurality of frames (a plurality of times) can be suppressed.

[0073] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0074] 1. Detection device 3. Detector element 10 Sensor section 15A First gate line driving circuit 15B Second gate line driving circuit 16 Signal line selection circuit 17 Initialization circuit 21 PCB 30 Photoelectric conversion element 48 Detection circuit AA detection area GA peripheral area GLrst Reset control scan line GLrd Readout control scan line INV, INVa Logic inversion circuit Mrst Reset Transistor Mrd readout transistor Msf Source Follower Transistor RST Reset control signal RD Read control signal SL output signal line Tr1, Tr1a First transistor Tr2, Tr2a Second transistor Vcom reference potential VGH High potential (1st potential) VGL low potential (second potential) Vrst Reset potential Vsf Power supply potential< / n> < / n>

Claims

1. A sensor unit in which a plurality of detection elements each having a photoelectric conversion element to which a reverse bias voltage is applied when performing detection are arranged in a first direction and a second direction intersecting the first direction, and in which a reset period is provided for each row of the plurality of detection elements arranged in the first direction during a detection period after detection starts; an initialization circuit that applies an initialization voltage greater than the reverse bias voltage to the photoelectric conversion element during an initialization period before the detection period; Equipped with Detection device.

2. The initialization circuit a first transistor that applies a first potential to a cathode of the photoelectric conversion element; a second transistor that applies a second potential higher than the first potential to the cathode of the photoelectric conversion element; Including, The detection device according to claim 1 .

3. The initialization circuit a first transistor that applies a first potential to an anode of the photoelectric conversion element; a second transistor that applies a second potential lower than the first potential to the anode of the photoelectric conversion element; Including, The detection device according to claim 1 .

4. The detection element is a reset transistor that applies a reset potential to the cathode of the photoelectric conversion element; a source follower transistor that outputs a signal corresponding to the potential generated in the photoelectric conversion element; a read transistor that reads out an output signal of the source follower transistor; Equipped with 4. A detection device according to any one of claims 1 to 3.

5. A sensor unit in which a plurality of detection elements each having a photoelectric conversion element to which a reverse bias voltage is applied when performing detection are arranged in a first direction and a second direction intersecting the first direction, and in which a reset period is provided for each row of the plurality of detection elements arranged in the first direction during a detection period after detection starts; an initialization circuit that initializes the plurality of detection elements during an initialization period before the detection period; Equipped with The initialization circuit a first wiring that supplies the reverse bias voltage to the photoelectric conversion element; a second wiring for supplying an initialization voltage greater than the reverse bias voltage to the photoelectric conversion element; a switch circuit that connects either the first wiring or the second wiring to the plurality of detection elements; Equipped with Detection device.

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