Package including a substrate and a high density interconnect integrated device

Abstract

The package includes a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, an interconnect integrated device coupled to the first integrated device and the second integrated device, and underfill. The substrate includes a cavity. The interconnect integrated device is positioned over the cavity in the substrate. The underfill is disposed (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device.

Description

[Technical Field]

[0001] Cross-reference / claiming priority to related applications This patent application claims priority to and the benefit of pending non-provisional application Ser. No. 17 / 094,303, filed with the U.S. Patent and Trademark Office on November 10, 2020, the contents of which are incorporated herein for all applicable purposes as if fully set forth below.

[0002] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates. [Background technology]

[0003] 1 shows a package 100 including a substrate 102, an integrated device 104, and an integrated device 106. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. There is an ongoing need to provide more compact packages that can accommodate high-density interconnects and / or high pin counts. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates.

[0005] One example provides a package including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, an interconnect integrated device coupled to the first integrated device and the second integrated device, and an underfill. The substrate includes a cavity. The interconnect integrated device is positioned above the cavity in the substrate. The underfill is disposed (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device.

[0006] Another example provides an apparatus including a substrate including a cavity, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, means for integrated device interconnection coupled to the first integrated device and the second integrated device and positioned above the cavity in the substrate, and underfill disposed between (i) the first integrated device and the substrate, (ii) the second integrated device and the substrate, (iii) between the means for integrated device interconnection and the first integrated device, and (iv) between the means for integrated device interconnection and the second integrated device.

[0007] In another example, a method for manufacturing a package is provided. The method includes providing a substrate including a cavity. The method includes bonding a first integrated device to the substrate. The method includes bonding a second integrated device to the substrate. The method includes bonding an interconnect integrated device to the first integrated device and the second integrated device, the interconnect integrated device overlying the cavity in the substrate. The method includes forming underfill (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a side view of a package including an integrated device and a substrate. [Figure 2] FIG. 1 is a side view of a package containing a high density interconnect integrated device. [Figure 3] FIG. 10 is a side view of another package including a high density interconnect integrated device. [Figure 4] 1 is a diagram of possible electrical paths within a package including a high density interconnect integrated device bonded to a substrate. [Figure 5] FIG. 10 is a side view of another package including a high density interconnect integrated device. [Figure 6] FIG. 10 is a side view of another package including a high density interconnect integrated device. [Figure 7] 1 is a diagram of possible electrical paths within a package containing a high density interconnect integrated device. [Figure 8A] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 8B] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 8C] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 8D] 1A-1C illustrate an exemplary sequence for fabricating a high density interconnect integrated device. [Figure 9] 1 is an exemplary flow diagram of a method for manufacturing a high density interconnect integrated device. [Figure 10] 1A and 1B are side views of an integrated device and an interconnected integrated device including pillar interconnects. [Figure 11] 1A and 1B are side views of an integrated device and an interconnected integrated device including pillar interconnects. [Figure 12A] 1A-1C illustrate an exemplary sequence for fabricating an interconnected integrated device having pillar interconnects. [Figure 12B]1A-1C illustrate an exemplary sequence for fabricating an interconnected integrated device having pillar interconnects. [Figure 13A] 10A-10C illustrate another exemplary sequence for fabricating an integrated device having pillar interconnects. [Figure 13B] 10A-10C illustrate another exemplary sequence for fabricating an integrated device having pillar interconnects. [Figure 14] 1 is an exemplary flow diagram of a method for fabricating an integrated device having pillar interconnects. [Figure 15A] FIG. 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 15B] FIG. 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 15C] FIG. 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 16] 1 is an exemplary flow diagram of a method for manufacturing a substrate. [Figure 17A] 1A-1C illustrate an exemplary sequence for manufacturing a package containing a high density interconnect integrated device. [Figure 17B] 1A-1C illustrate an exemplary sequence for manufacturing a package containing a high density interconnect integrated device. [Figure 18] 1 is an exemplary flow diagram of a method for manufacturing a package including a high density interconnect integrated device. [Figure 19] 1A-1C illustrate various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (PIDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following description, specific details are set forth to enable a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, an interconnect integrated device coupled to the first integrated device and the second integrated device, and underfill. The substrate includes a cavity. The interconnect integrated device is positioned over the cavity in the substrate. Underfill is disposed (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device. The interconnect integrated device may include a high-density interconnect integrated device configured with interconnects having minimum widths and spacings that are smaller than the minimum widths and spacings of the interconnects from the substrate. The interconnect integrated device may be configured to allow current to bypass the substrate while traveling between the integrated devices, where the substrate has a larger minimum width and / or spacing for the interconnects. The interconnected integrated device may enable a package to have a small, compact form factor while simultaneously providing a high input / output (I / O) pin count. The interconnected integrated device may provide improved voltage drop to the integrated device, shorter paths between the integrated devices, and / or lower inductance. The underfill may help provide strong structural integrity to the interconnected integrated device, which in turn helps provide a package with reliable interconnects between two or more integrated devices.

[0012] Exemplary Packages Containing High Density Interconnect Integrated Devices 2 shows a side view of a package 200 containing high-density interconnected integrated devices. Package 200 can be coupled to a board (e.g., a printed circuit board (PCB)) through multiple solder interconnects 280. Package 200 provides a package with a high input / output pin count while simultaneously having a compact, small form factor. As described further below, package 200 provides shorter paths between integrated devices, lower inductance, and / or fewer routing constraints.

[0013] 2 , package 200 includes interconnected integrated device 201, substrate 202, first integrated device 204, second integrated device 206, and underfill 208. Interconnected integrated device 201 may be configured as a bridge (e.g., a bridge die) between two or more integrated devices. As described further below, integrated devices (e.g., 204, 206) and interconnected integrated device 201 may be coupled together such that when at least one electrical signal (e.g., first electrical signal, second electrical signal) travels between at least two integrated devices (e.g., 204, 206), the electrical signal travels through interconnected integrated device 201 and bypasses substrate 202. The at least one electrical signal may travel through at least one electrical path defined by the package interconnects, integrated devices, substrate, and / or interconnected integrated devices.

[0014] The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226. The substrate 202 also includes a cavity 209 extending through the substrate 202. The cavity 209 may extend through the at least one dielectric layer 220, the first solder resist layer 224, and the second solder resist layer. The cavity 209 may have any shape (e.g., rectangular, square). The cavity 209 may have a lateral dimension that is greater than a lateral dimension of the interconnect integrated device 201. The substrate 202 may include two or more cavities 209.

[0015] The plurality of interconnects 222 may be configured to provide at least one electrical path to and / or from the board. The plurality of interconnects 222 may be configured to provide at least one electrical path to at least one integrated device (e.g., 204, 206). The plurality of interconnects 222 may be configured to provide at least one electrical path (e.g., electrical connection) between two or more integrated devices (e.g., 204, 206). The plurality of interconnects 222 may have a first minimum pitch and a first minimum line and spacing (L / S). In some implementations, the first minimum line and spacing (L / S) for the plurality of interconnects 222 is in the range of approximately 9 / 9 to 12 / 12 micrometers (μm) (e.g., a minimum line width of approximately 9 to 12 micrometers (μm) and a minimum spacing of approximately 9 to 12 micrometers (μm)). Various implementations may use different substrates. The substrate 202 can be a laminate substrate, a coreless substrate, an organic substrate, and / or a core substrate (e.g., including a core layer). In some implementations, the at least one dielectric layer 220 can include a core layer and / or a prepreg layer. The at least one dielectric layer 220 can have a dielectric constant in the range of approximately 3.5 to 3.7. An example of manufacturing the substrate is further described below in FIGS. 15A-15C. As further described below, in some implementations, the substrate 202 can be manufactured using a modified semi-adaptive process (mSAP) or a semi-adaptive process (SAP).

[0016] The first integrated device 204 is coupled to a first surface (e.g., a top surface) of the substrate 202. In some implementations, the first integrated device 204 is coupled to the substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. The plurality of pillar interconnects 240 and / or the plurality of solder interconnects 242 may be coupled to a plurality of interconnects 222 of the substrate 202. A portion of the first integrated device 204 may be located above the cavity 209. A front surface of the first integrated device 204 may face the substrate 202.

[0017] The second integrated device 206 is coupled to a first surface of the substrate 202. In some implementations, the second integrated device 206 is coupled to the substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. The plurality of pillar interconnects 260 and / or the plurality of solder interconnects 262 may be coupled to the plurality of interconnects 222. A portion of the second integrated device 206 may be located above the cavity 209. A front surface of the second device 206 may face the substrate 202.

[0018] The interconnect integrated device 201 is coupled to the first integrated device 204 and the second integrated device 206 through a plurality of pillar interconnects 230 and / or a plurality of solder interconnects 232. For example, a first plurality of pillar interconnects 230a and / or a first plurality of solder interconnects 232a may be used to couple the interconnect integrated device 201 to the first integrated device 204. A second plurality of pillar interconnects 230b and / or a second plurality of solder interconnects 232b may be used to couple the interconnect integrated device 201 to the second integrated device 206. A front surface of the interconnect integrated device 201 may face a front surface of the first integrated device 204 and a front surface of the second integrated device 206. The interconnect integrated device 201 is located above a cavity 209 in the substrate 202. In some implementations, the interconnect integrated device 201 may be located at least partially within the cavity 209. In some implementations, the interconnect integrated device 201 may be located entirely within a cavity 209 in the substrate 202. The cavity 209 may create space for the interconnect integrated device 201 to fit underneath the first integrated device 204 and / or the second integrated device 206. The use of pillar interconnects may also help provide space for the interconnect integrated device 201 to fit underneath the first integrated device 204 and / or the second integrated device 206.

[0019] The interconnect integrated device 201 may be a high-density interconnect integrated device including interconnects having a second minimum pitch and a second minimum line width and spacing (L / S). In some implementations, the second minimum line width and spacing (L / S) for the interconnects of the interconnect integrated device (e.g., 201) is in the range of approximately 2 1 / 2 to 5 1 / 5 micrometers (μm) (e.g., a minimum line width of approximately 2 to 5 micrometers (μm), a minimum spacing of approximately 2 to 5 micrometers (μm)). The pitch may be defined as the center-to-center distance between two adjacent interconnects. The second minimum line width and spacing (L / S) for the interconnects of the interconnect integrated device 201 is smaller than the minimum line width and spacing for the interconnects of the substrate 202. The interconnect integrated device (e.g., 201) is a localized integrated device configured to be placed in a region close to the integrated device. The size of the interconnect integrated device may vary with various implementations.

[0020] An interconnect integrated device 201 with a higher density of interconnects allows the package 200 to provide a higher I / O pin count without having to increase the size of the package 200. For example, using an interconnect integrated device 201 may allow the substrate 202 to have a fewer number of metal layers, which may help reduce the overall height of the package 200. One or more interconnect integrated devices 201 may help reduce congestion and / or entanglement in some areas of the substrate 202 (e.g., areas close to the integrated devices) due to a high pin count and / or a large netlist. The interconnect integrated device 201 may have a lower height than the first integrated device 204 and / or the second integrated device 206. Providing at least one electrical path between integrated devices that bypasses the substrate 202 may help improve the performance of the package 200 by reducing routing congestion within the substrate 202 and / or by reducing paths for current (e.g., signals) between the integrated devices. The end result is a package with a more compact form factor and improved electrical performance. Additionally, the interconnected integrated device 201 can help lower the cost of the substrate 202 because the interconnects of the interconnected integrated device 201 support near-die breakout, and therefore the interconnects of the substrate 202 do not need to be as close together (e.g., lower L / S) to achieve near-die breakout. As described further below, the interconnected integrated device (e.g., 201) can be configured as a bridge. The interconnected integrated device (e.g., 201) can include die (e.g., passive device die, bridge die). An interconnected integrated device configured as a bridge die and / or passive device die may be devoid of active devices such as transistors.

[0021] 2 , underfill 208 is disposed (i) between first integrated device 204 and substrate 202, (ii) between second integrated device 206 and substrate 202, (iii) between interconnect integrated device 201 and first integrated device 204, and (iv) between interconnect integrated device 201 and second integrated device 206. Underfill 208 may be disposed laterally of interconnect integrated device 201. For example, underfill 208 may laterally surround interconnect integrated device 201. Underfill 208 may surround multiple pillar interconnects (e.g., 230, 240, 260) and / or multiple solder interconnects (e.g., 232, 242, 262). As described further below, underfill 208 may be disposed elsewhere, such as within cavity 209 and / or over first integrated device 204 and second integrated device 206.

[0022] The underfill 208 helps provide structural stability to the package 200. In particular, the underfill 208 helps provide a strong and reliable mechanical bond between the interconnect integrated device 201, the first integrated device 204, and the second integrated device 206. By helping to structurally hold the interconnect integrated device 201, the first integrated device 204, and the second integrated device 206 together, the underfill 208 helps ensure that a strong and reliable electrical connection (e.g., electrical path) exists between the first integrated device 204 and the second integrated device 206.

[0023] Various implementations may provide underfill 208 with different materials and / or properties. Underfill 208 may include one or more underfills (e.g., underfill layers). For example, underfill 208 may be formed from a single component of underfill. In some implementations, underfill 208 may correspond to several portions and / or layers of separately formed and cured underfill. In some implementations, underfill 208 may include a viscosity of approximately 10 to 30 Pascal-seconds (Pa·s). These viscosity values ​​may be for a temperature of approximately 80 degrees Celsius. In some implementations, underfill 208 may include a coefficient of thermal expansion (CTE) of approximately 10 to 15 parts per million (ppm). In some implementations, underfill 208 may include a filler amount equivalent to approximately 50 to 90 percent of the weight of underfill 208. As described further below, the underfill 208 may have capillary properties that allow the underfill 208 to fill small spaces between integrated devices and / or between the integrated device and the substrate. For example, the viscosity values ​​described above for the underfill 208 allow the underfill 208 to readily fill small spaces between integrated devices and / or between the integrated device and the substrate. The underfill 208 and / or other materials that may be placed around pillars and between the integrated device and the substrate are described further below.

[0024] The integrated devices (e.g., 204, 206) may include a die (e.g., a semiconductor bare die). The integrated devices may include a logic die, a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated devices (e.g., 204, 206) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0025] 2 shows that the interconnect integrated device 201 includes at least one dielectric layer 210, a plurality of interconnects 212, a passivation layer 214, and a substrate 216. The substrate 216 may include silicon (Si), glass, or quartz. The substrate 216 may be a die substrate. The interconnect integrated device 201 may include a front side and a back side. The back side of the interconnect integrated device 201 may be the side that includes the substrate 216. The front side of the interconnect integrated device 201 may be the side that includes the passivation layer 214 and / or the side to which the solder interconnects are bonded to the interconnect integrated device 201. The front side of the interconnect integrated device 201 may be the side opposite the back side of the interconnect integrated device 201. As described further below, the interconnect integrated device 201 (and / or any of the interconnect integrated devices described in this disclosure) may be configured as a bridge. The interconnect integrated device 201 may include a die (e.g., a passive device die, a bridge die). An interconnected integrated device configured as a bridge and / or passive device die may be devoid of active devices such as transistors. Thus, an interconnected integrated device configured as a bridge and / or passive device die may be devoid of transistors (e.g., no transistors coupled to a circuit). As described above, the interconnects of the interconnected integrated device may have a higher density (e.g., a lower minimum pitch and / or a lower minimum L / S) than the interconnects of the substrate 202. A passivation layer 214 is disposed on a first surface of the interconnected integrated device 201. A plurality of pillar interconnects 230 are coupled to the first surface of the interconnected integrated device 201. However, in some implementations, a plurality of solder interconnects 232 are coupled to the first surface of the interconnected integrated device 201.

[0026] Figure 3 shows a package 300 that includes an interconnected integrated device. Package 300 is similar to package 200 of Figure 2 and, therefore, includes the same or similar components as package 200. As shown in Figure 3, interconnected integrated device 201 is separately coupled to first integrated device 204 and second integrated device 206.

[0027] The interconnected integrated device 201 is coupled to a plurality of solder interconnects 332. The plurality of solder interconnects 332 is coupled to a plurality of pillar interconnects 340 and 360. Thus, the interconnected integrated device 201 is coupled to the first integrated device 204 through the plurality of solder interconnects 332 and the plurality of pillar interconnects 340. Similarly, the interconnected integrated device 201 is coupled to the second integrated device 206 through the plurality of solder interconnects 332 and the plurality of pillar interconnects 360.

[0028] As mentioned above, interconnect integrated devices can be components coupled to the substrate 202, thereby allowing the package (e.g., 200, 300) to provide a higher I / O pin count and / or shorter paths between integrated devices without having to increase the overall size of the package. In some implementations, one or more electrical signals to and from one or more integrated devices can travel through one or more interconnect integrated devices. One or more interconnect integrated devices (e.g., 201) can help reduce congestion and / or tangles in some areas of the substrate due to a large pin count and / or a large number of netlists. A netlist is the arrangement of components of a circuit and how the components are electrically coupled together. One or more interconnect integrated devices 201 result in shorter paths between integrated devices, aiding in lower inductance and / or reducing routing constraints. Underfill 208 helps provide structural stability to the package, such as structural stability between the interconnect integrated device 201 and the integrated devices (e.g., 204, 206).

[0029] Figure 4 shows a diagram of how electrical signals may be conceptually configured to travel within a package. Figure 4 shows a package 400 including an interconnected integrated device 201, a substrate 202, a first integrated device 204, and a second integrated device 206. Package 400 may conceptually represent any of the packages described in this disclosure. Figure 4 shows (i) a first electrical path 410 for a first electrical signal, (ii) a second electrical path 411 for a second electrical signal, (iii) a third electrical path 412 for a third electrical signal, (iv) a fourth electrical path 440 for a fourth electrical signal, and (v) a fifth electrical path 460 for a fifth electrical signal.

[0030] First electrical pathway 410, second electrical pathway 411, and third electrical pathway 412 illustrate examples of electrical pathways between integrated devices that bypass or skip interconnects from substrate 202. First electrical pathway 410 may be configured to allow at least one signal to travel between first integrated device 204 and second integrated device 206 through interconnect integrated device 201. Second electrical pathway 411 may be configured to allow at least one signal to travel between first integrated device 204 and second integrated device 206 through interconnect integrated device 201. Third electrical pathway 412 may be configured to allow at least one signal to travel between first integrated device 204 and second integrated device 206 through interconnect integrated device 201. For example, one or more of the electrical paths (e.g., 410, 411, 412) between integrated devices may be defined to include a first plurality of solder interconnects (e.g., 232a, 332), a first plurality of pillar interconnects (e.g., 230a, 340), a plurality of interconnects 212, a second plurality of pillar interconnects (e.g., 230b, 360), and / or a second plurality of solder interconnects (e.g., 232b, 332).

[0031] The fourth electrical pathway 440 may be configured to allow at least one signal to travel between the first integrated device 204 and the substrate 202. The fourth electrical pathway 440 may be defined to include a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. The fifth electrical pathway 460 may be configured to allow at least one signal to travel between the second integrated device 206 and the substrate 202. The fifth electrical pathway 460 may be defined to include a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. Note that two or more of the various electrical pathways described in this disclosure may be configured to be electrically coupled to each other. The electrical signal may include an I / O signal. Instead of an I / O signal, the example pathways shown in this disclosure may also be applicable to power and / or ground.

[0032] FIG. 5 illustrates a package 500 including interconnected integrated devices. The package 500 is similar to the package 200 of FIG. 2 and, therefore, includes the same or similar components as the package 200. As shown in FIG. 5, the package 500 also includes an encapsulation layer 508. The encapsulation layer 508 is disposed on a first surface (e.g., a top surface) of the substrate 202 such that the encapsulation layer 508 encapsulates the first integrated device 204 and the second integrated device 206. The encapsulation layer 508 may be disposed on a back surface of the first integrated device 204 and a back surface of the second integrated device 206. The encapsulation layer 508 may surround the underfill 208. The encapsulation layer 508 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 508 may be a means for encapsulation. The encapsulation layer 508 may provide additional structural strength to the package and help provide a strong and reliable mechanical bond between the first integrated device 204, the second integrated device 206, and the interconnect integrated device 201. Note that the encapsulation layer 508 may optionally be placed within the cavity 209.

[0033] FIG. 6 shows a package 600 including an interconnected integrated device. The package 600 is similar to the package 200 of FIG. 2 and therefore includes the same or similar components as the package 200. As shown in FIG. 6, the package 600 includes an encapsulation layer 608. The encapsulation layer 608 is disposed (i) between the first integrated device 204 and the substrate 202, (ii) between the second integrated device 206 and the substrate 202, (iii) between the interconnected integrated device 201 and the first integrated device 204, and (iv) between the interconnected integrated device 201 and the second integrated device 206. The encapsulation layer 608 may be disposed laterally around the interconnected integrated device 201. For example, the encapsulation layer 608 may laterally surround the interconnected integrated device 201. The encapsulation layer 608 may surround the pillar interconnects (e.g., 230, 240, 260) and / or the solder interconnects (e.g., 232, 242, 262). The encapsulation layer 608 may replace the function of the underfill 208 in FIG. 2 . The encapsulation layer 608 is disposed on a first surface (e.g., a top surface) of the substrate 202 such that the encapsulation layer 608 encapsulates the first integrated device 204 and the second integrated device 206. The encapsulation layer 608 may be disposed on a back surface of the first integrated device 204 and a back surface of the second integrated device 206. The encapsulation layer 608 may be disposed within the cavity 209 of the substrate 202. The encapsulation layer 608 may extend beyond the bottom surface of the substrate 202. Providing the encapsulation layer 608 for the entire package may be more cost-effective than providing an underfill and an encapsulation layer for the package. Encapsulating layer 608 may be the same as, similar to, or different from encapsulating layer 508. Encapsulating layer 608 may include a mold underfill (MUF).

[0034] As mentioned above, underfill 208, encapsulation layer 508, and / or encapsulation layer 608 may have certain properties to ensure that the space around the pillar interconnects and the space between the integrated device and the substrate is properly filled to ensure a strong and secure bond between the integrated device and the substrate.

[0035] For example, the underfill 208 may include a capillary underfill with good fluidity. The capillary underfill (CUF) may include a polymer composite of silica particles and an epoxy liquid. One characteristic of the capillary underfill is its good fluidity upon heating, allowing it to flow into the narrow space between the integrated device and the substrate, driven by capillary forces. The capillary underfill may have sufficient silica filler to obtain a final cured material with a low CTE. The capillary underfill is typically a liquid type that freezes at -40 degrees Celsius or below and can be thawed and heated before application.

[0036] The encapsulation layer 508 may include an encapsulant and / or an epoxy molding compound (EMC) used to cover the entire package after applying the capillary underfill, thus protecting the entire package. The encapsulation layer 508 may include a solid pellet that can be stored at room temperature. The encapsulation layer 508 can be heated to become a liquid and processed under a transfer molding flow to cover the integrated device.

[0037] In some implementations, a molded underfill (MUF) can be used instead of or in conjunction with the underfill 208 and / or encapsulation layer 508. The molded underfill can be a combination of a capillary underfill (e.g., underfill 208) and an EMC (e.g., encapsulation 508). The material properties and application format of the molded underfill are the same or similar to those of regular EMC, but with a very fine filler size; therefore, the molded underfill can be pressed into the gaps of the substrate during the transfer molding process into the integrated device. In this way, the molded underfill can replace the capillary underfill and reduce process steps.

[0038] EMC and MUF can have very high filler loadings, up to 90 wt%, and therefore, the cured material properties are better than capillary underfill, which has a lower CTE and high elasticity. In some implementations, MUF can be used to replace CUF if the package requires an encapsulation layer. For packages without an encapsulation layer, only CUF can be used. Table 1 below shows exemplary properties of various materials, underfills, and encapsulation layers. Note that the values ​​for materials are examples. Different materials may have different properties. Furthermore, the values ​​shown in Table 1 are not limiting.

[0039] [Table 1]

[0040] Note that encapsulation layer 508 may be applicable to package 300 of FIG. 3 or any package described in this disclosure. As mentioned above, a package may include two or more integrated devices. For example, a package may include four integrated devices arranged in a 2×2 array.

[0041] FIG. 7 illustrates a package 700 including a substrate 202, an integrated device 201, a first integrated device 204, a second integrated device 206, a third integrated device 704, and a fourth integrated device 706. The first integrated device 204, the second integrated device 206, the third integrated device 704, and the fourth integrated device 706 may be coupled to a first surface of the substrate 202. The first integrated device 204, the second integrated device 206, the third integrated device 704, and the fourth integrated device 706 may be arranged in a 2×2 array. The spacing between the integrated devices may be in the range of approximately 0.1 to 1.5 millimeters (mm). As illustrated in at least FIGS. 2 and 3, multiple solder interconnects and / or multiple pillar interconnects may be used to couple each integrated device to the substrate 202. Package 700 may be similar to packages 200, 300, 500, and / or 600 and, therefore, may include similar or the same components as packages 200, 300, 500, and / or 600. Substrate 202 includes a cavity 209. A portion of each of the integrated devices may be located above cavity 209.

[0042] The integrated devices can be configured to be electrically coupled to one another through the interconnected integrated device 201. Figure 7 shows (i) a first electrical path 714 for a first electrical signal, (ii) a second electrical path 716 for a second electrical signal, (iii) a third electrical path 744 for a third electrical signal, (iv) a fourth electrical path 746 for a fourth electrical signal, (v) a fifth electrical path 766 for a fifth electrical signal, and (vi) a sixth electrical path 777 for a sixth electrical signal. The first electrical path 714, the second electrical path 716, the third electrical path 744, the fourth electrical path 746, the fifth electrical path 766, and the sixth electrical path 777 illustrate examples of electrical paths between integrated devices that bypass or skip interconnects from the substrate 202.

[0043] The first electrical pathway 714 may be configured to allow at least one signal to travel between the first integrated device 204 and the fourth integrated device 706 through the interconnected integrated device 201. The second electrical pathway 716 may be configured to allow at least one signal to travel between the third integrated device 704 and the second integrated device 206 through the interconnected integrated device 201. The third electrical pathway 744 may be configured to allow at least one signal to travel between the first integrated device 204 and the third integrated device 704 through the interconnected integrated device 201. The fourth electrical pathway 746 may be configured to allow at least one signal to travel between the first integrated device 204 and the second integrated device 206 through the interconnected integrated device 201. The fifth electrical pathway 766 may be configured to allow at least one signal to travel between the second integrated device 206 and the fourth integrated device 706 through the interconnected integrated device 201. The sixth electrical pathway 777 may be configured to allow at least one signal to travel between the third integrated device 704 and the fourth integrated device 706 through the interconnected integrated device 201.

[0044] It should be noted that each of the integrated devices may include additional electrical paths between each other and / or between each and the substrate 202. It should be noted that the paths of electrical signals shown in this disclosure are exemplary and / or conceptual. Various implementations may use different paths for the electrical signals. Moreover, the electrical signals and / or electrical paths may travel through various types of interconnects (e.g., vias, traces, pads, pillars), solder interconnects, and / or components (e.g., passive devices). Thus, for example, in some implementations, an electrical signal traveling between an integrated device and an interconnected integrated device may travel through at least one intervening component (e.g., passive device, capacitor) between the integrated device and the interconnected integrated device. The paths shown for the electrical signals may also apply to power and / or ground. It should also be noted that two or more interconnected integrated devices may be used to facilitate substrate bypass. The terms “first side” and “second side” of a substrate are arbitrary and may refer to either surface of the substrate. For example, the first side of the substrate can be the bottom side of the substrate, and the second side of the substrate can be the top side of the substrate. In another example, the first side of the substrate can be the top side of the substrate, and the second side of the substrate can be the bottom side of the substrate. The interconnected integrated device (e.g., 201) can be a means for interconnecting integrated devices. One example of a method for fabricating an interconnected integrated device is shown and described in Figures 8A-8D below.

[0045] Exemplary Sequence for Fabricating High Density Interconnect Integrated Devices 8A-8D illustrate an example sequence for providing or manufacturing a high-density interconnect integrated device. In some implementations, the sequence of Figures 8A-8D can be used to provide or manufacture the interconnect integrated device 201 of Figure 2 or any of the interconnect integrated devices described in this disclosure.

[0046] 8A-8D may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing an interconnected integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. Various implementations may manufacture interconnected integrated devices differently.

[0047] 8A, stage 1 represents the state after a substrate 216 is provided. The substrate 216 may include glass, quartz, and / or silicon.

[0048] Stage 2 shows the state after a plurality of interconnects 822 have been formed on the substrate 216. The plurality of interconnects 822 may include traces and / or pads. Forming the plurality of interconnects 822 may include forming a seed layer, performing a lithography process, a plating process, a removal process, and / or an etching process. The plurality of interconnects 822 may be part of the plurality of interconnects 212.

[0049] Stage 3 shows the state after a dielectric layer 830 is formed over the plurality of interconnects 822 and the substrate 216. The dielectric layer 830 may be deposited and / or coated over the plurality of interconnects 822 and the dielectric layer 820. The dielectric layer 830 may include a polymer. The dielectric layer 830 may be similar to the dielectric layer 211.

[0050] Stage 4 shows the state after a cavity 831 has been formed in the dielectric layer 830. An etching process may be used to form the cavity 831.

[0051] Stage 5, as shown in FIG. 8B , depicts the state after a plurality of interconnects 832 are formed on the dielectric layer 830. The plurality of interconnects 832 may include vias, traces, and / or pads. Forming the plurality of interconnects 832 may include performing lithography processes, plating processes, removal processes, and / or etching processes. The plurality of interconnects 832 may be part of the plurality of interconnects 212.

[0052] Stage 6 shows the state after a dielectric layer 840 is formed over the plurality of interconnects 832 and the dielectric layer 830. The dielectric layer 840 may be deposited and / or coated over the plurality of interconnects 832 and the dielectric layer 830. The dielectric layer 840 may include a polymer. The dielectric layer 840 may be similar to the dielectric layer 830.

[0053] Stage 7 shows the state after a cavity 841 has been formed in the dielectric layer 840. An etching process may be used to form the cavity 841.

[0054] Stage 8 shows the state after a plurality of interconnects 842 are formed on the dielectric layer 840. The plurality of interconnects 842 may include vias, traces, and / or pads. Forming the plurality of interconnects 842 may include performing lithography processes, plating processes, removal processes, and / or etching processes. The plurality of interconnects 842 may be part of the plurality of interconnects 212.

[0055] Stage 9, as shown in FIG. 8C , depicts the state after a dielectric layer 850 is formed over the plurality of interconnects 842 and the dielectric layer 840. The dielectric layer 850 may be deposited and / or coated over the plurality of interconnects 842 and the dielectric layer 840. The dielectric layer 850 may include a polymer. The dielectric layer 850 may be similar to the dielectric layer 840.

[0056] Stage 10 shows the state after a cavity 851 has been formed in the dielectric layer 850. An etching process may be used to form the cavity 851. The cavity 851 may expose a portion of the plurality of interconnects 842.

[0057] Stage 11 shows the state after a plurality of interconnects 852 are formed on the dielectric layer 850. The plurality of interconnects 852 may include vias, traces, and / or pads. Forming the plurality of interconnects 852 may include performing lithography processes, plating processes, removal processes, and / or etching processes. The plurality of interconnects 852 may be part of the plurality of interconnects 212.

[0058] Stage 12, as shown in FIG. 8D , depicts the state after a passivation layer 214 has been formed over the at least one dielectric layer 210. A deposition process may be used to form the passivation layer 214. The at least one dielectric layer 210 may represent dielectric layers 830, 840, and 850. Stage 12 may depict a plurality of interconnects 212, which may include a plurality of interconnects 832, 842, and / or 852.

[0059] Stage 13 shows the state after a plurality of solder interconnects 332 have been bonded to the interconnect integrated device 201. Stage 13 may represent an example of the interconnect integrated device 201 described in Figure 2. In some implementations, the interconnect integrated device 201 is part of a wafer, and singulation may be performed to cut the wafer into individual interconnect integrated devices.

[0060] It should be noted that a pillar interconnect may be formed on an interconnect integrated device and a plurality of solder interconnects 332 may be coupled to the pillar interconnect. For example, a pillar interconnect may be coupled to a plurality of interconnects 212 and a plurality of solder interconnects 332 may be coupled to the pillar interconnect. Figures 10-12 show examples of how pillar interconnects may be formed on an interconnect integrated device.

[0061] Illustrative flow diagram of a method for fabricating a high density interconnect integrated device In some implementations, manufacturing a package including a high-density interconnect integrated device involves several processes. Figure 9 shows an example flow diagram of a method 900 for providing or manufacturing a high-density interconnect integrated device. In some implementations, the method 900 of Figure 9 may be used to provide or manufacture the high-density interconnect integrated device (e.g., 201) of Figure 2 described in this disclosure. However, the method 900 may be used to provide or manufacture any of the interconnect integrated devices described in this disclosure.

[0062] 9 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an interconnected integrated device. In some implementations, the order of the processes may be changed or modified.

[0063] The method provides (at 905) a substrate (e.g., 216). The substrate 216 can include glass, quartz, and / or silicon. Stage 1 of Figure 8A shows an example of a substrate.

[0064] The method forms (at 910) a first metal layer by forming a plurality of interconnects 822 over a substrate (e.g., 216). Forming the plurality of interconnects may include performing a lithography process, performing a plating process, performing a removal process, and / or performing an etching process. Stage 2 of Figure 8A illustrates an example of forming a first metal layer for a high-density interconnect integrated device.

[0065] The method forms (at 915) a second metal layer by forming a dielectric layer (e.g., 830) and a plurality of interconnects (e.g., 832) over the first metal layer. The dielectric layer may include a polymer. Forming the dielectric layer and the plurality of interconnects may include depositing a dielectric layer 830 over the dielectric layer 820 and the interconnects 822, performing a lithography process, performing a plating process, performing a removal process, and / or performing an etching process. Stages 3-5 of FIGS. 8A-8B illustrate an example of forming a second metal layer (e.g., a redistribution layer, a redistribution metal layer) for a high-density interconnect integrated device. The redistribution layer (RDL) may be in the form of a metallization layer. The RDL may include interconnects that include a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side shapes of the interconnects and / or the redistribution interconnects. The U-shaped interconnects and V-shaped interconnects may have a top and a bottom. The bottom of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or V-shaped interconnect). Forming the metal and dielectric layers may include using wiring or back end of line (BEOL) processes.

[0066] The method forms (at 920) an additional metal layer by forming one or more dielectric layers (e.g., 840, 850) and a plurality of interconnects (e.g., 842, 852) over the second metal layer. The dielectric layers may include a polymer. Forming the dielectric layer and the plurality of interconnects may include depositing one or more dielectric layers (e.g., 840, 850) over the dielectric layer 830 and the interconnects 832, performing a lithography process, performing a plating process, performing a removal process, and / or performing an etching process. Stages 7-11 of Figures 8B-8C illustrate an example of forming an additional metal layer for a high-density interconnect integrated device. Forming the additional metal layer and additional dielectric layer may include using an interconnect process or back-end of line (BEOL) process.

[0067] The method forms (at 925) a passivation layer (e.g., 214) on the dielectric layer of the interconnect integrated device (e.g., 201). The passivation layer (e.g., 214) may be deposited on the dielectric layer 210. Stage 12 of Figure 8D illustrates an example of a passivation layer formed on the dielectric layer of the interconnect integrated device. Stage 12 may illustrate an example of an interconnect integrated device (e.g., 201).

[0068] The method includes (at 930) bonding a plurality of solder interconnects (e.g., 332) to an interconnect integrated device (e.g., 201). A reflow solder process may be used to bond the plurality of solder interconnects to the interconnect integrated device. Stage 13 of Figure 8D may show an example of solder interconnects bonded to an interconnect integrated device.

[0069] In some implementations, the interconnected integrated device 201 is part of a wafer, and singulation may be performed to cut the wafer into individual interconnected integrated devices. The method 900 may be used to fabricate an interconnected integrated device 201 that includes multiple interconnects 212.

[0070] Exemplary Integrated Devices Including Pillar Interconnects 10 and 11 show examples of integrated and interconnected integrated devices including pillar interconnects. FIG. 10 shows a first integrated device 204 and an interconnected integrated device 201. The first integrated device 204 includes a seed layer 1010, a plurality of pillar interconnects 1040, a plurality of solder interconnects 1012, and a plurality of solder interconnects 1042. The seed layer 1010 is disposed on the front side of the first integrated device 204. The seed layer 1010 can be bonded to the interconnects of the first integrated device 204. The plurality of solder interconnects 1012 are bonded to the seed layer 1010. The plurality of pillar interconnects 1040 are bonded to the seed layer 1010. The plurality of solder interconnects 1042 are bonded to the plurality of pillar interconnects 1040.

[0071] The interconnect integrated device 201 includes a seed layer 1011, a plurality of pillar interconnects 1030, and a plurality of solder interconnects 1032. The seed layer 1011 can be bonded to the interconnects of the interconnect integrated device 201. The plurality of pillar interconnects 1030 are bonded to the seed layer 1011. The plurality of solder interconnects 1032 are bonded to the plurality of pillar interconnects 1030.

[0072] The interconnected integrated device 201 may be coupled to the first integrated device 204 through the seed layer 1011, the plurality of pillar interconnects 1030, the plurality of solder interconnects 1032, the plurality of solder interconnects 1012, and the seed layer 1010. The plurality of solder interconnects 1012 and the plurality of solder interconnects 1032 may combine to form a plurality of solder interconnects 232 (e.g., 232a). The first integrated device 204 may be coupled to the substrate through the seed layer 1010, the plurality of pillar interconnects 1040, and the plurality of solder interconnects 1042. The plurality of pillar interconnects 1040 may represent the plurality of pillar interconnects 240. The plurality of solder interconnects 1042 may represent the plurality of solder interconnects 242.

[0073] 11 shows another configuration of a first integrated device 204 and an interconnected integrated device 201. The first integrated device 204 includes a seed layer 1010, a plurality of pillar interconnects 1040, a plurality of pillar interconnects 1130, a plurality of solder interconnects 1012, and a plurality of solder interconnects 1042. The seed layer 1010 is disposed on a front surface of the first integrated device 204. The seed layer 1010 can be bonded to the interconnects of the first integrated device 204. The plurality of pillar interconnects 1130 are bonded to the seed layer 1010. The plurality of solder interconnects 1012 are bonded to the plurality of pillar interconnects 1130. The plurality of pillar interconnects 1040 are bonded to the seed layer 1010. The plurality of solder interconnects 1042 are bonded to the plurality of pillar interconnects 1040.

[0074] The interconnect integrated device 201 includes a seed layer 1011 and a plurality of solder interconnects 1032. The seed layer 1011 can be bonded to the interconnects of the interconnect integrated device 201. The plurality of solder interconnects 1032 are bonded to the seed layer 1011.

[0075] The interconnected integrated device 201 may be coupled to the first integrated device 204 through the seed layer 1011, the plurality of solder interconnects 1032, the plurality of solder interconnects 1012, the plurality of pillar interconnects 1130, and the seed layer 1010. The plurality of solder interconnects 1012 and the plurality of solder interconnects 1032 may combine to form the plurality of solder interconnects 332. The first integrated device 204 may be coupled to the substrate through the seed layer 1010, the plurality of pillar interconnects 1040, and the plurality of solder interconnects 1042. The plurality of pillar interconnects 1040 may represent the plurality of pillar interconnects 240. The plurality of solder interconnects 1042 may represent the plurality of solder interconnects 242.

[0076] The seed layer, pillar interconnects, and solder interconnects described in Figures 10 and 11 may be applicable to any of the integrated devices of the present disclosure, including the second integrated device 206, the third integrated device 704, and / or the fourth integrated device 706.

[0077] Exemplary Sequence for Fabricating High Density Interconnect Integrated Devices with Pillar Interconnects 12A-12B illustrate an exemplary sequence for providing or fabricating a high-density interconnect integrated device having pillar interconnects. In some implementations, the sequence of FIG. 12A-12B can be used to provide or fabricate the interconnect integrated device 201 of FIG. 2 or any of the interconnect integrated devices described in this disclosure.

[0078] 12A-12B may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing an interconnected integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. Various implementations may manufacture interconnected integrated devices differently.

[0079] As shown in Figure 12A, Stage 1 shows the state after an interconnected integrated device 201 is prepared. Stages 1-12 of Figures 8A-8D illustrate an example of fabricating an interconnected integrated device. The interconnected integrated device 201 can be configured as a bridge (e.g., a bridge die) between integrated devices (e.g., dies).

[0080] Stage 2 shows the state after a seed layer 1011 has been formed on the front side of the interconnect integrated device 201. The seed layer 1011 may include a metal layer. The seed layer 1011 may be deposited on the interconnect integrated device 201. A plating process may be used to form the seed layer 1011.

[0081] Stage 3 shows the state after a photoresist layer 1200 has been formed on the seed layer 1011. The photoresist layer 1200 may be deposited on the seed layer 1011.

[0082] Stage 4 shows the state after the photoresist layer 1200 has been patterned to create at least one opening in the photoresist layer 1200 that exposes a portion of the seed layer 1011 .

[0083] 12B , stage 5 depicts the state after a plurality of pillar interconnects 1030 and a plurality of solder interconnects 1032 have been placed on the seed layer 1011 through openings in the photoresist layer 1200. The plurality of pillar interconnects 1030 may be formed on the seed layer 1011 through a plating process. The plurality of solder interconnects 1032 may be formed on the plurality of pillar interconnects 1030 through a deposition process.

[0084] Stage 6 shows the state after the photoresist layer 1200 has been removed and portions of the seed layer 1011 have been removed (e.g., etched). Removing the photoresist layer 1200 may include stripping the photoresist layer 1200.

[0085] Stage 7 shows the state after a reflow solder process that couples (e.g., bonds) the plurality of solder interconnects 1032 to the plurality of pillar interconnects 1030. Stage 7 may show an interconnected integrated device (e.g., 201) having pillar interconnects that may be coupled to two or more integrated devices.

[0086] Exemplary Sequence for Fabricating an Integrated Device with Pillar Interconnects 13A-13B show an example sequence for providing or manufacturing an integrated device having pillar interconnects. In some implementations, the sequence of Figures 13A-13B can be used to provide or manufacture the first integrated device 204 of Figure 2 or any of the integrated devices described in this disclosure (e.g., 206, 704, 706).

[0087] 13A-13B may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing an integrated device having pillar interconnects. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. Various implementations may manufacture integrated devices differently.

[0088] 13A, stage 1 shows the state after a first integrated device 204 is prepared. The first integrated device 204 may include a die having active devices such as transistors.

[0089] Stage 2 shows the state after a seed layer 1010 has been formed on the front side of the first integrated device 204. The seed layer 1010 may include a metal layer. The seed layer 1010 may be deposited on the first integrated device 204. A plating process may be used to form the seed layer 1010.

[0090] Stage 3 shows the state after a photoresist layer 1200 has been formed and patterned over the seed layer 1010. The photoresist layer 1200 may be deposited over the seed layer 1010 and patterned to create at least one opening in the photoresist layer 1200 that exposes a portion of the seed layer 1010.

[0091] Stage 4 shows the state after a plurality of solder interconnects 1012 have been placed on the seed layer 1010 through openings in the photoresist layer 1200. The plurality of solder interconnects 1012 may be formed on the seed layer 1010 through a deposition process.

[0092] Stage 5 shows the state after the photoresist layer 1200 has been removed. Removing the photoresist layer 1200 may include stripping the photoresist layer 1200.

[0093] 13B, stage 6 depicts the state after a photoresist layer 1300 has been formed and patterned over the seed layer 1010 and the plurality of solder interconnects 1012. The photoresist layer 1300 may be deposited over the seed layer 1010 and patterned to create at least one opening in the photoresist layer 1300 that exposes a portion of the seed layer 1010.

[0094] Stage 7 shows the state after a plurality of pillar interconnects 1040 and a plurality of solder interconnects 1042 have been placed on the seed layer 1010 through openings in the photoresist layer 1300. The plurality of pillar interconnects 1040 may be formed on the seed layer 1010 through a plating process. The plurality of solder interconnects 1042 may be formed on the plurality of pillar interconnects 1040 through a deposition process.

[0095] Stage 8 shows the state after the photoresist layer 1300 has been removed and portions of the seed layer 1010 have been removed (e.g., etched). Removing the photoresist layer 1300 may include stripping the photoresist layer 1300.

[0096] Stage 9 includes bonding a plurality of solder interconnects 1042 to a plurality of pillar interconnects 1040 and a plurality of solder interconnects 1012 to a seed layer 1010. The state is shown after a reflow solder process to bond (eg, join) Stage 9 may represent an integrated device (eg, 204, 206, 704, 706) that may be bonded to an interconnected integrated device and / or substrate.

[0097] 1 is an exemplary flow diagram of a method for fabricating an integrated device including pillar interconnects; In some implementations, fabricating an integrated device having pillar interconnects involves several processes. Figure 14 shows an example flow diagram of a method 1400 for providing or fabricating an interconnected integrated device having pillar interconnects. In some implementations, the method 1400 of Figure 14 may be used to provide or fabricate the integrated devices of Figure 2 described in this disclosure (e.g., 204, 206). However, the method 1400 may be used to provide or fabricate any of the integrated devices and / or interconnected integrated devices (e.g., 201) described in this disclosure.

[0098] 14 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing an integrated device having pillar interconnects. In some implementations, the order of the processes may be changed or modified.

[0099] The method provides (at 1405) an integrated device (e.g., 204, 206). Stage 1 of Figure 13A shows a first integrated device 204 being provided. The first integrated device 204 may include a die having active devices such as transistors. In some implementations, the integrated device being provided is an interconnected integrated device (e.g., 201).

[0100] The method forms (at 1410) a seed layer (e.g., 1010) on the front side of the integrated device. The seed layer 1010 may include a metal layer. The seed layer 1010 may be deposited on the integrated device 204. A plating process may be used to form the seed layer 1010. Stage 2 of Figure 13A illustrates and describes an example of forming a seed layer.

[0101] The method includes (at 1415) forming a photoresist layer (e.g., 1200) over the seed layer (e.g., 1010). The photoresist layer 1200 may be formed and patterned over the seed layer 1010. The photoresist layer 1200 may be deposited over the seed layer 1010 and patterned to create at least one opening in the photoresist layer 1200 that exposes a portion of the seed layer 1010. Stage 3 of Figure 13A illustrates and describes an example of forming a photoresist layer over a seed layer.

[0102] The method forms (at 1420) a plurality of pillar interconnects (e.g., 1040) and / or solder interconnects (e.g., 1042) on the seed layer (e.g., 1010) through openings in the photoresist layer (e.g., 1200). The plurality of solder interconnects may be formed on the seed layer through a deposition process. The plurality of pillar interconnects may be formed on the seed layer through a plating process. The plurality of solder interconnects may be formed on the plurality of pillar interconnects through a deposition process. Stages 4 and 7 of Figures 13A and 13B show examples of forming a plurality of pillar interconnects and / or a plurality of solder interconnects.

[0103] The method removes (at 1425) the photoresist layer (e.g., 1200). Removing the photoresist layer may include removing the photoresist layer. Stages 5 and 8 of FIGS. 13A and 13B show examples of removing the photoresist layer. In some implementations, a portion of the seed layer may also be removed. An etching process may be used to remove a portion of the seed layer. Stage 8 of FIG. 13B shows an example of a portion of the seed layer being removed. Note that forming the photoresist layer, pillar interconnects and / or solder interconnects, and removing the photoresist layer may be repeated, as described at 1415, 1420, and 1425.

[0104] The method performs (at 1430) a reflow solder process that bonds (e.g., joins) the plurality of solder interconnects (e.g., 1042) to the plurality of pillar interconnects (e.g., 1040) and / or the plurality of solder interconnects (e.g., 1012) to the seed layer (e.g., 1010). Stage 9 of Figure 13B illustrates and describes one example of a reflow solder process.

[0105] In some implementations, the integrated devices are part of a wafer and singulation may be performed to cut the wafer into individual integrated devices. Method 1400 may be used to fabricate any integrated device described in this disclosure, including interconnected integrated devices.

[0106] Exemplary Sequence for Fabricating a Substrate In some implementations, manufacturing a substrate includes several processes. Figures 15A-15C show an example sequence for providing or manufacturing a substrate. In some implementations, the sequence of Figures 15A-15C may be used to provide or manufacture substrate 202 of Figure 2. However, the processes of Figures 15A-15C may be used to manufacture any of the substrates described in this disclosure.

[0107] 15A-15C may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0108] 15A, stage 1 represents the state after a carrier 1500 is provided and a metal layer is formed on the carrier 1500. The metal layer may be patterned to form interconnects 1502. Plating and etching processes may be used to form the metal layer and the interconnects.

[0109] Stage 2 shows the state after a dielectric layer 1520 is formed over the carrier 1500 and interconnects 1502. The dielectric layer 1520 may include polyimide, although various implementations may use different materials for the dielectric layer.

[0110] Stage 3 shows the state after multiple cavities 1510 have been formed in the dielectric layer 1520. The multiple cavities 1510 may be formed using an etching process (e.g., a photoetching process) or a laser process.

[0111] Stage 4 shows the state after interconnects 1512 have been formed in and on the dielectric layer 1520. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0112] Stage 5 shows the state after another dielectric layer 1522 is formed over dielectric layer 1520. Dielectric layer 1522 can be the same material as dielectric layer 1520. However, various implementations may use different materials for the dielectric layers.

[0113] Stage 6, as shown in Figure 15B, depicts the state after a plurality of cavities 1530 have been formed in the dielectric layer 1522. An etching process or a laser process may be used to form the cavities 1530.

[0114] Stage 7 shows the state after interconnects 1514 have been formed in and on dielectric layer 1522. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0115] Stage 8 shows the state after another dielectric layer 1524 is formed over dielectric layer 1522. Dielectric layer 1524 can be the same material as dielectric layer 1520. However, various implementations may use different materials for the dielectric layers.

[0116] Stage 9 shows the state after a plurality of cavities 1540 have been formed in the dielectric layer 1524. An etching process or a laser process may be used to form the cavities 1540.

[0117] Stage 10, as shown in Figure 15C, depicts the state after interconnects 1516 have been formed in and on dielectric layer 1524. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0118] Some or all of the interconnects 1502, 1512, 1514 and / or 1516 may define the plurality of interconnects 222 of the substrate 202. The dielectric layers 1520, 1522, 1524 may be represented by at least one dielectric layer 220.

[0119] Stage 11 shows the state after the carrier 1500 has been decoupled (e.g., removed or polished away) from the dielectric layer 220 and separated from the substrate 202, which includes at least one dielectric layer 220 and multiple interconnects 222.

[0120] Stage 12 shows the state after a first solder resist layer 224 and a second solder resist layer 226 have been formed on the substrate 202 .

[0121] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0122] 1 is an exemplary flow diagram of a method for manufacturing a substrate; In some implementations, manufacturing a substrate includes several processes. Figure 16 shows an example flow diagram of a method 1600 for providing or manufacturing a substrate. In some implementations, the method 1600 of Figure 16 can be used to provide or manufacture the substrate of Figure 2. For example, the method of Figure 16 can be used to manufacture the substrate 202.

[0123] 16 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0124] The method provides (at 1605) a carrier 1500. Various implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or carrier tape. Stage 1 of Figure 15A shows the state after the carrier is provided.

[0125] The method forms (at 1610) a metal layer on the carrier 1500. The metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and interconnects. Stage 1 of Figure 15A shows an example of a metal layer and interconnects 1502 being formed.

[0126] The method forms (at 1615) a dielectric layer 1520 over the carrier 1500 and the interconnects 1502. The dielectric layer 1520 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1510) in the dielectric layer 1520. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Stages 2-3 of FIG. 15A show an example of forming the dielectric layer and the cavities in the dielectric layer.

[0127] The method forms (at 1620) interconnects in and on the dielectric layer. For example, interconnects 1512 may be formed in and on dielectric layer 1520. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Stage 4 of Figure 15A shows an example of forming interconnects in and on the dielectric layer.

[0128] The method forms (at 1625) a dielectric layer 1522 over the dielectric layer 1520 and the interconnects. The dielectric layer 1522 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1530) in the dielectric layer 1522. The plurality of cavities may be formed using an etching process or a laser process. Stages 5-6 of Figures 15A-15B show an example of forming the dielectric layer and the cavities in the dielectric layer.

[0129] The method forms (at 1630) interconnects in and / or on the dielectric layer. For example, interconnects 1514 may be formed. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and in the dielectric layer. Stage 7 of FIG. 15B shows an example of forming interconnects in and on the dielectric layer.

[0130] The method may form additional dielectric layers and additional interconnects as described at 1625 and 1630. Stages 8-10 of Figures 15B-15C show an example of forming interconnects in and on a dielectric layer.

[0131] Once all the dielectric layers and additional interconnects have been formed, the method may decouple (e.g., remove or polish away) the carrier (e.g., 1500) from the dielectric layers 1520, leaving the substrate. In some implementations, the method may form a solder resist layer (e.g., 224, 226) over the substrate.

[0132] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0133] Exemplary Sequence for Manufacturing a Package Containing a High Density Interconnect Integrated Device 17A-17B illustrate an exemplary sequence for providing or manufacturing a package including a high-density interconnected integrated device. In some implementations, the sequence of Figures 17A-17B can be used to provide or manufacture a package 500 including the substrate 202 and interconnected integrated device 201 of Figure 5, or any of the packages described in this disclosure.

[0134] It should be noted that the sequence of Figures 17A-17B may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. The sequence of Figures 17A-17B may be used to manufacture one package or several packages simultaneously (as part of a wafer).

[0135] As shown in FIG. 17A, stage 1 represents the state after the substrate 202 is prepared. The substrate 202 may be provided by a supplier or may be manufactured. A process similar to that shown in FIGS. 15A-15C may be used to manufacture the substrate 202. However, various implementations may use different processes to manufacture the substrate 202. Examples of processes that may be used to manufacture the substrate 202 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer. In some implementations, the at least one dielectric layer 220 may include a core layer and / or a prepreg layer. The substrate 202 includes a cavity 209. The cavity 209 may be manufactured using a laser process (e.g., laser cutting).

[0136] Stage 2 shows the state after integrated device 204 and integrated device 206 are bonded to a first surface (e.g., top surface) of substrate 202. Integrated device 204 is bonded to substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. Integrated device 206 is bonded to substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. Portions of integrated device 204 and integrated device 206 may be located above cavity 209. Integrated device 204 may be bonded to substrate 202 such that a front surface (e.g., active surface) of integrated device 204 faces substrate 202. Similarly, integrated device 206 may be bonded to substrate 202 such that a front surface of integrated device 206 faces substrate 202.

[0137] Stage 3 shows the state after underfill 1740 has been provided (e.g., formed) between substrate 202 and integrated device 204, and underfill 1760 has been provided (e.g., formed) between substrate 202 and integrated device 206. The underfill (e.g., 1740, 1760) may be provided around pillar interconnects (e.g., 240, 260) and / or solder interconnects (e.g., 242, 262) via capillary action and / or capillary forces. The capillary properties of the underfill allow it to fill small spaces and / or small gaps between the integrated device and the substrate.

[0138] Stage 4 shows the state after interconnected integrated device 201 has been bonded to integrated device 204 and integrated device 206. Interconnected integrated device 201 is bonded to integrated device 204 through a plurality of pillar interconnects 230 and / or a plurality of solder interconnects 232. Similarly, interconnected integrated device 201 is bonded to integrated device 206 through a plurality of pillar interconnects 230 and a plurality of solder interconnects 232. In some implementations, substrate 202 and integrated devices 204 and 206 are inverted before interconnected integrated device 201 is bonded to integrated devices 204 and 206. A reflow solder process may be used to bond interconnected integrated device 201 to integrated devices 204 and 206.

[0139] As shown in FIG. 17B , stage 5 depicts the state after underfill 208 has been applied (formed) between interconnect integrated device 201 and integrated devices 204 and 206. Underfill 208 may be applied via capillary action and / or capillary forces. The capillary properties of the underfill allow it to fill small spaces and / or gaps between the integrated device and the substrate. Underfill 208 may include underfill 1740 and underfill 1760. Underfill 208 may represent one or more layers of underfill. As described above, underfill 208 helps to provide a mechanical bond between interconnect integrated device 201 and integrated devices 204 and 206, which helps to hold interconnect integrated device 201 and integrated devices 204 and 206 together, thereby providing a strong and reliable electrical connection between interconnect integrated device 201 and integrated devices 204 and 206. A flux process may be applied before underfill 208 is applied.

[0140] Stage 6 depicts the state after encapsulation layer 508 has been formed on the first surface of substrate 202 such that encapsulation layer 508 encapsulates first integrated device 204 and second integrated device 206. The process of forming and / or depositing encapsulation layer 508 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that in some implementations, encapsulation layer 508 may replace underfill (e.g., 1740, 1760, 208), as shown in FIG. 7 . Thus, in some implementations, encapsulation layer 508 may be formed and disposed within the area occupied by underfill 208.

[0141] Stage 7 shows the state after multiple solder interconnects 280 have been bonded to substrate 202. A reflow solder process may be used to bond the multiple solder interconnects. Stage 8 may show package 200 including substrate 202, first integrated device 204, second integrated device 206, interconnected integrated device 201, underfill 208, and encapsulation layer 508, as described at least in FIG. 5 .

[0142] The packages described in this disclosure (eg, 200, 300, 400, 500, 600, 700) may be manufactured one at a time, or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0143] Illustrative flow diagram of a method for manufacturing a package containing a high density interconnect integrated device In some implementations, manufacturing a package including a high-density interconnect integrated device includes several processes. Figure 18 shows an example flow diagram of a method 1800 for providing or manufacturing a package including a high-density interconnect integrated device bonded to a substrate. In some implementations, the method 1800 of Figure 18 may be used to provide or manufacture the package 500 of Figure 5 described in this disclosure. However, the method 1800 may be used to provide or manufacture any of the packages described in this disclosure.

[0144] 18 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package including a high-density interconnect integrated device. In some implementations, the order of the processes may be changed or modified.

[0145] The method includes (at 1805) providing a substrate (e.g., 202). The substrate 202 may be provided by a supplier or may be manufactured. The substrate 202 includes a first side and a second side. The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The substrate 202 may include at least one cavity 209. Various implementations may include different substrates. A process similar to that shown in FIGS. 15A-15C may be used to manufacture the substrate 202. However, various implementations may use different processes to manufacture the substrate 202. Stage 1 of FIG. 17A illustrates an example of providing a substrate.

[0146] The method bonds (at 1810) the integrated device to a substrate. For example, the method may bond integrated device 204 and integrated device 206 to a first surface (e.g., top surface) of substrate 202. Integrated device 204 is bonded to substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. Integrated device 206 is bonded to substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. Portions of integrated device 204 and integrated device 206 may be located above cavity 209. Integrated device 204 may be bonded to substrate 202 such that a front surface (e.g., active surface) of integrated device 204 faces substrate 202. Similarly, integrated device 206 may be bonded to substrate 202 such that a front surface of integrated device 206 faces substrate 202. Stage 2 of FIG. 17A illustrates and describes an example of bonding an integrated device to a substrate.

[0147] The method forms (at 1815) at least one underfill between the integrated device and the substrate. For example, the method may provide underfill 1740 between the substrate 202 and the integrated device 204, or may provide underfill 1760 between the substrate 202 and the integrated device 206. The underfill (e.g., 1740, 1760) may be provided around the pillar interconnects (e.g., 240, 260) and / or the solder interconnects (e.g., 242, 262) via capillary action and / or capillary forces. The capillary properties of the underfill enable it to fill small spaces and / or small gaps between the integrated device and the substrate. Stage 3 of FIG. 17A illustrates and describes an example of providing the underfill.

[0148] The method bonds (at 1820) the interconnected integrated device to the integrated device. For example, the method may bond the interconnected integrated device 201 to the integrated device 204 and the integrated device 206. The interconnected integrated device 201 is bonded to the integrated device 204 through a plurality of pillar interconnects 230 and / or a plurality of solder interconnects 232. Similarly, the interconnected integrated device 201 is bonded to the integrated device 206 through a plurality of pillar interconnects 230 and / or a plurality of solder interconnects 232. In some implementations, the substrate 202 and the integrated devices 204 and 206 are inverted before the interconnected integrated device 201 is bonded to the integrated devices 204 and 206. A reflow solder process may be used to bond the interconnected integrated device 201 to the integrated devices 204 and 206. Stage 4 of FIG. 17A shows and describes an example of bonding the interconnected integrated devices to the integrated devices.

[0149] The method may also provide (at 1820) an underfill between the interconnect integrated device and the integrated device. For example, the method may provide underfill 208 between interconnect integrated device 201 and integrated devices 204 and 206. Underfill 208 may be provided via capillary action and / or capillary forces. The capillary properties of the underfill allow it to fill small spaces and / or small gaps between the integrated device and the substrate. Underfill 208 may include underfill 1740 and underfill 1760. As described above, underfill 208 helps to provide a mechanical bond between interconnect integrated device 201 and integrated devices 204 and 206. Stage 5 of FIG. 17B illustrates and describes an example of providing an underfill.

[0150] The method may form (at 1825) an encapsulation layer over the substrate. For example, the method may form encapsulation layer 508 over the first surface of substrate 202 such that encapsulation layer 508 encapsulates first integrated device 204 and second integrated device. The process of forming and / or depositing encapsulation layer 508 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that in some implementations, encapsulation layer 508 may replace underfill (e.g., 1740, 1760, 208), as shown in FIG. 7 . Thus, in some implementations, encapsulation layer 508 may be formed and disposed in the area occupied by the underfill. Stage 6 of FIG. 17B illustrates and describes an example of forming an encapsulation layer.

[0151] The method continues (at 1830) by bonding a plurality of solder interconnects (e.g., 280) to the second side of the substrate (e.g., 202). A reflow solder process may be used to bond the plurality of solder interconnects. Stage 7 of Figure 17B illustrates and describes an example of bonding the solder interconnects to the substrate.

[0152] Exemplary Electronic Devices 19 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-packages (PoPs), systems-in-packages (SiPs), or systems-on-chips (SoCs). For example, a mobile phone device 1902, a laptop computer device 1904, a fixed location terminal device 1906, a wearable device 1908, or an automobile 1910 may include a device 1900 as described herein. The device 1900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1902, 1904, 1906, and 1908 and the vehicle 1910 illustrated in FIG. 19 are merely examples. Other electronic devices may also feature device 1900, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, eyeglasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0153] One or more of the components, processes, features, and / or functions shown in Figures 2-7, 8A-8D, 9, 10-11, 12A-12B, 13A-13B, 14, 15A-15C, 16, 17A-17B, and / or 18-19 may be rearranged and / or combined into a single component, process, feature, or function, or may be incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 2-7, 8A-8D, 9, 10-11, 12A-12B, 13A-13B, 14, 15A-15C, 16, 17A-17B, and / or 18-19 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 2-7, 8A-8D, 9, 10-11, 12A-12B, 13A-13B, 14, 15A-15C, 16, 17A-17B, and / or 18-19 and their corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0154] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, for clarity, not all components and / or parts are shown. In some examples, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0155] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects of the present disclosure. Likewise, the term “aspect” does not require all aspects of the present disclosure to include the described feature, advantage, or mode of operation. The term “coupled” is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, object A and object C may still be considered to be coupled to each other even though they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between them. The use of the terms "first," "second," "third," and "fourth" (and / or more than fourth) is arbitrary. Any of the described components may be the first, second, third, or fourth component. For example, a component referred to as a second component may be the first, second, third, or fourth component. The term "encapsulate" means that an object may partially or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located on top may be located above a component located on the bottom. A top component may also be considered a bottom component, and vice versa. As described in this disclosure, a first component located "on" a second component may mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined.In another example, a first component may be disposed over (e.g., above) a first surface of a second component, and a third component may be disposed over (e.g., below) a second surface of the second component, with the second surface facing the first surface. It is further noted that the term "over," as used herein in the context of one component being disposed over another component, may be used to refer to a component located on and / or within (e.g., located on the surface of or embedded in) the other component. Thus, for example, a first component being disposed over a second component may mean that (1) the first component is disposed over, but not in direct contact with, the second component, (2) the first component is disposed on (e.g., on the surface of) the second component, and / or (3) the first component is disposed within (e.g., embedded in) the second component. A first component disposed "in" a second component can be disposed partially within the second component or completely within the second component. As used in this disclosure, the term "about the value of X" or "approximately the value of X" means within 10 percent of the "value of X." For example, a value of about 1 or approximately 1 means a value within the range of 0.9 to 1.1.

[0156] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Various implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0157] Also, it should be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0158] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above-described aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

[0159] A first embodiment includes a package including a substrate including a cavity, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, an interconnect integrated device coupled to the first and second integrated devices and positioned over the cavity in the substrate, and underfill disposed (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device. The first integrated device, the second integrated device, and the interconnect integrated device can be configured to provide an electrical path between the first integrated device and the second integrated device for electrical signals that extend through the interconnect integrated device and bypass the substrate. The underfill can have a viscosity of approximately 10 to 30 Pascal-seconds (Pa·s). The underfill can have a coefficient of thermal expansion (CTE) of approximately 10 to 15 parts per million (ppm). The underfill may include a filler equivalent to approximately 50 to 90 percent of the weight of the underfill. The underfill may include an encapsulation layer. The interconnect integrated device may include a die substrate, at least one dielectric layer, and a plurality of interconnects. The die substrate may include silicon, glass, and / or quartz. The interconnect integrated device may include a high-density interconnect integrated device configured with interconnects having a minimum width and spacing that is smaller than the minimum width and spacing of the interconnects from the substrate. The minimum width for the plurality of interconnects of the interconnect integrated device may be within a range of approximately 2 to 5 micrometers (μm), and the minimum spacing for the plurality of interconnects of the interconnect integrated device may be within a range of approximately 2 to 5 micrometers (μm). The interconnect integrated device may include a die without transistors coupled to a circuit. The interconnect integrated device may be at least partially located within a cavity in the substrate. The underfill may be further disposed over the first integrated device and the second integrated device. The underfill may be further disposed within the cavity in the substrate. The package may further include an encapsulation layer disposed over the substrate.The package may further include an encapsulation layer disposed within the cavity in the substrate.The interconnect integrated device can be coupled to the first integrated device through a first plurality of solder interconnects and a first plurality of pillar interconnects. The interconnect integrated device can be coupled to the second integrated device through a second plurality of solder interconnects and a second plurality of pillar interconnects. The underfill can include a capillary underfill and / or a molded underfill.

[0160] A second embodiment includes an apparatus including a substrate including a cavity, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, means for integrated device interconnection coupled to the first integrated device and the second integrated device and positioned above the cavity in the substrate, and underfill disposed (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the means for integrated device interconnection and the first integrated device, and (iv) between the means for integrated device interconnection and the second integrated device. The first integrated device, the second integrated device, and the means for integrated device interconnection may be configured to provide an electrical path for electrical signals between the first integrated device and the second integrated device that extends through the means for integrated device interconnection and bypasses the substrate. The underfill may include a capillary underfill and / or a molded underfill. The underfill may have a viscosity of about 10 to 30 Pascal seconds (Pa·s). The underfill may have a coefficient of thermal expansion (CTE) of approximately 10 to 15 parts per million (ppm). The underfill may include a filler amounting to approximately 50 to 90 percent of the underfill's weight. The means for interconnecting integrated devices may include a die substrate, at least one dielectric layer, and a plurality of interconnects. The die substrate may include silicon, glass, and / or quartz. A minimum width for the plurality of interconnects of the interconnected integrated device may be in the range of approximately 2 to 5 micrometers (μm). A minimum spacing for the plurality of interconnects of the interconnected integrated device may be in the range of approximately 2 to 5 micrometers (μm). The means for interconnecting integrated devices may include a transistor-less die coupled to a circuit. The apparatus may include a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

[0161] A third aspect includes a method for manufacturing a package. The method provides a substrate including a cavity. The method bonds a first integrated device to the substrate. The method bonds a second integrated device to the substrate. The method bonds an interconnected integrated device to the first integrated device and the second integrated device, the interconnected integrated device overlying the cavity in the substrate. The method forms an underfill (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnected integrated device and the first integrated device, and (iv) between the interconnected integrated device and the second integrated device. The first integrated device, the second integrated device, and the interconnected integrated device can be configured to provide an electrical path between the first integrated device and the second integrated device for electrical signals that extend through the interconnected integrated device and bypass the substrate. The underfill can have a viscosity of about 10 to 30 Pascal seconds (Pa·s). The underfill may have a coefficient of thermal expansion (CTE) of approximately 10-15 parts per million (ppm). The underfill may include a filler amounting to approximately 50-90 percent of the weight of the underfill. The interconnect integrated device may include a die substrate, at least one dielectric layer, and a plurality of interconnects. The interconnect integrated device may include a die without transistors coupled to a circuit. The underfill may include capillary underfill and / or molded underfill. [Explanation of symbols]

[0162] 100 packages 102 Circuit Board 104 Integrated Devices 106 Integrated Devices 120 dielectric layer 122 Interconnection 124 Solder Interconnects 144 Solder Interconnects 164 Solder Interconnects 200 packages 201 Interconnected Integrated Devices 202 Substrate 204 Integrated Devices 206 Integrated Devices 208 Underfill 210 Dielectric layer 212 Interconnection 214 Passivation Layer 216 Substrate 220 Dielectric Layer 222 Interconnection 224 First solder resist layer 226 Second solder resist layer 230 Pillar Interconnection 230a First Plurality of Pillar Interconnects 232 Multiple Solder Interconnects 232a first plurality of solder interconnects 232b second plurality of solder interconnects 240 Pillar Interconnection 242 Multiple Solder Interconnects 260 Pillar Interconnection 262 Multiple Solder Interconnects 280 Multiple Solder Interconnects 300 packages 332 Multiple Solder Interconnects 340 Multiple Pillar Interconnection 360 Multiple Pillar Interconnections 400 packages 410 First Electrical Path 411 Second Electrical Path 412 Third Electrical Path 440 Fourth Electrical Path 460 Fifth Electrical Path 500 packages 508 Encapsulation Layer 600 packages 608 Encapsulation Layer 700 packages 704 The third integrated device 706 The fourth integrated device 714 First Electrical Path 716 Second Electrical Path 744 Third Electrical Path 746 Fourth Electrical Path 766 Fifth Electrical Path 777 Sixth Electrical Path 822 Interconnection 830 Dielectric layer 831 Cavity 832 Interconnection 840 Dielectric Layer 841 Cavity 842 Interconnection 850 dielectric layer 851 Cavity 852 Interconnection 900 ways 1010 seed layer 1011 seed layer 1012 Multiple solder interconnections 1030 Multiple Pillar Interconnect 1032 Multiple solder interconnections 1040 Multiple Pillar Interconnect 1042 Multiple Solder Interconnects 1200 photoresist layers 1300 photoresist layer 1400 methods 1500 Carriers 1502 Interconnection 1512 Interconnection Cormorant 1514 Interconnection 1516 Interconnection 1520 Dielectric layer 1522 dielectric layer 1524 dielectric layer 1600 methods 1740 Underfill 1760 Underfill 1800 methods 1900 devices 1902 Mobile Phone Devices 1904 Laptop Computer Device 1906 Fixed Location Terminal Device 1908 Wearable Devices 1910 Automobile

Claims

1. a substrate including a cavity, the cavity extending through an entire thickness of the substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; an interconnection integrated device coupled to the first integrated device and the second integrated device and positioned above the cavity in the substrate; (i) an encapsulation layer disposed between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnected integrated device and the first integrated device, and (iv) between the interconnected integrated device and the second integrated device, the encapsulation layer laterally surrounding the interconnected integrated devices and encapsulating the first integrated device and the second integrated device, and further disposed within the cavity of the substrate, the encapsulation layer providing a mechanical coupling between the interconnected integrated device, the first integrated device, and the second integrated device.

2. 10. The package of claim 1, wherein the first integrated device, the second integrated device, and the interconnected integrated device are configured to provide an electrical path between the first integrated device and the second integrated device for electrical signals that extend through the interconnected integrated device and bypass the substrate.

3. The package of claim 1 , wherein the interconnect integrated device includes a die substrate, at least one dielectric layer, and a plurality of interconnects.

4. The package of claim 3 , wherein the die substrate comprises silicon, glass, and / or quartz.

5. a minimum width for the plurality of interconnects of the interconnect integrated device is in the range of about 2 to 5 micrometers (μm); 4. The package of claim 3, wherein the minimum spacing for the plurality of interconnects of the interconnect integrated device is in the range of about 2 to 5 micrometers (μm).

6. The package of claim 1 , wherein the interconnect integrated device comprises a transistor-less die coupled to a circuit.

7. The package of claim 1 , wherein the interconnect integrated device is located at least partially within the cavity of the substrate.

8. the interconnected integrated device is coupled to the first integrated device through a first plurality of solder interconnects and a first plurality of pillar interconnects; The package of claim 1 , wherein the interconnected integrated device is coupled to the second integrated device through a second plurality of solder interconnects and a second plurality of pillar interconnects.

9. 1. A method for manufacturing a package, comprising: providing a substrate including a cavity, the cavity extending through an entire thickness of the substrate; bonding a first integrated device to the substrate; bonding a second integrated device to the substrate; coupling an interconnected integrated device to the first integrated device and the second integrated device, the interconnected integrated device being located above the cavity in the substrate; forming an encapsulation layer between (i) the first integrated device and the substrate, (ii) the second integrated device and the substrate, (iii) the interconnected integrated device and the first integrated device, and (iv) the interconnected integrated device and the second integrated device, wherein the encapsulation layer laterally surrounds the interconnected integrated devices, encapsulates the first integrated device and the second integrated device, and is further disposed within the cavity of the substrate, wherein the encapsulation layer provides a mechanical coupling between the interconnected integrated device, the first integrated device, and the second integrated device.

10. 10. The method of claim 9, wherein the first integrated device, the second integrated device, and the interconnected integrated device are configured to provide an electrical path between the first integrated device and the second integrated device for electrical signals that extend through the interconnected integrated device and bypass the substrate.

11. The method of claim 9 , wherein the interconnected integrated device includes a die substrate, at least one dielectric layer, and a plurality of interconnects.

12. 10. The method of claim 9, wherein the interconnected integrated device comprises a die without transistors coupled to circuitry.

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