Imaging device

Abstract

To provide an imaging apparatus with a new construction.SOLUTION: An imaging apparatus includes an imaging region to which a plurality of pixels are provided. In the plurality of pixels provided in the imaging region, a first pixel and a second pixel are contained. The imaging apparatus includes a function for selecting first or second regions. The first region contains as many pixels as that in the second region. The first region contains at least first and second pixel, and the second region contains at least the second pixel. The pixel provided to the first or second region includes a function for outputting an imaging signal acquired. The imaging apparatus reads out the imaging signal to be output by the pixel provided in the first region at the seme time, and calculates them to generate first image data. The imaging apparatus reads the imaging signal to be output by the pixel provided in the second region at the same time, and calculates them to generate second image data. A first imaging image can be generated by using the first and second image data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device or an imaging system including the imaging device.

[0002] One embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the present invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In particular, one embodiment of the present invention relates to a semiconductor device, an imaging device, a light-receiving device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to an element, circuit, device, or the like that can function by utilizing semiconductor characteristics. As one example, a semiconductor element such as a transistor, a diode, a light receiving element, or a light emitting element is a semiconductor device. As another example, a circuit having a semiconductor element is a semiconductor device. As yet another example, a device including a circuit having a semiconductor element is a semiconductor device. [Background technology]

[0004] In recent years, the development of image recognition using artificial intelligence (AI) has progressed. The recognition rate of what is in an image as a subject continues to improve. However, while AI can handle content it has already learned, it has difficulty recognizing or describing the components in an image from an image it has not learned before.

[0005] For example, in production processes, visual inspections are performed to check for foreign objects that may be mixed in during production, manufacturing defects, etc. Recently, developments have been made to efficiently perform visual inspections by incorporating image inspections into visual inspections. For example, various detection algorithms have been proposed for machine vision (image processing systems that use computer systems). Among these, an algorithm inspired by the human visual mechanism has been proposed (Patent Document 1). This algorithm is inspired by the peripheral vision and fixational eye movement of the human visual mechanism, and is capable of detecting abnormalities that exist within regular patterns. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-185862 Summary of the Invention [Problem to be solved by the invention]

[0007] When an algorithm for extracting features from an image is digitally processed using a processor or a graphics processing unit (GPU) without using training data, power consumption increases in proportion to the amount of calculation. In other words, the size of the target image is proportional to the amount of calculation and power consumption. Furthermore, when using this algorithm, processing time increases in proportion to the amount of calculation. Furthermore, this algorithm requires a data area larger than the image size to handle data larger than the image size during intermediate processing.

[0008] In view of the above problems, an object of one embodiment of the present invention is to provide an imaging device with a novel structure.An object of one embodiment of the present invention is to provide an imaging device that can handle data larger than an imaging area.An object of one embodiment of the present invention is to provide an imaging device that suppresses an increase in calculation processing time.An object of one embodiment of the present invention is to provide an imaging device that suppresses an increase in power consumption.

[0009] An object of one embodiment of the present invention is to provide an imaging system with a novel configuration.An object of one embodiment of the present invention is to provide an imaging system that can handle data larger than an imaging area.An object of one embodiment of the present invention is to provide an imaging system that suppresses an increase in calculation processing time.An object of one embodiment of the present invention is to provide an imaging system that suppresses an increase in power consumption.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is an imaging device having an imaging area including a first region and a second region, wherein the first region and the second region have the same number of pixels, the first region including a first pixel and a second pixel among the pixels, and the second region including a second pixel among the pixels, wherein first image data is generated in response to imaging signals output by the pixels in the first region, second image data is generated in response to imaging signals output by the pixels in the second region, and a first image is generated in response to the first image data and the second image data.

[0012] In the above configuration, it is preferable that the first image data is generated by averaging the image signals output by the multiple pixels in the first region, and the second image data is generated by averaging the image signals output by the multiple pixels in the second region.

[0013] In each of the above configurations, it is preferable that each of the plurality of pixels in the first region has a function of converting the imaging signals output by the plurality of pixels into a first imaging signal by being given a weighting coefficient, and each of the plurality of pixels in the second region has a function of converting the imaging signals output by the pixel into a second imaging signal by being given a weighting coefficient, and that the first image data is generated by adding up the first imaging signals output by each of the plurality of pixels in the first region, and that the second image data is generated by adding up the second imaging signals output by each of the plurality of pixels in the second region.

[0014] In each of the above configurations, the first and second regions are preferably configured by pixels selected in units of integer rows and integer columns.

[0015] In each of the above structures, it is preferable that the pixel further includes a first circuit, the first circuit has a function of holding a potential, and the first circuit has a function as a substitute for a pixel in the first region or the first region.

[0016] In each of the above structures, the transistor included in the pixel preferably includes a metal oxide in a semiconductor layer included in the transistor.

[0017] Another aspect of the present invention is an imaging system having an imaging area in which a plurality of pixels are provided, wherein the imaging area includes a first pixel, a second pixel, and a third pixel among the plurality of pixels, the imaging system comprising the steps of: acquiring imaging signals from the plurality of pixels; setting a first area in the imaging area having the first pixel to the third pixel; generating first phase image data according to imaging signals acquired by the first pixel and the second pixel included in the first area; generating second phase image data according to imaging signals acquired by the second pixel and the third pixel included in the first area; and generating the first image data by calculating the first phase image data and the second phase image data.

[0018] In each of the above configurations, the first image data is preferably an image in which features are extracted from an imaging signal. [Effects of the Invention]

[0019] In view of the above problems, one embodiment of the present invention can provide an imaging device with a novel structure. One embodiment of the present invention can provide an imaging device that can handle data larger than an imaging area. One embodiment of the present invention can provide an imaging device that suppresses an increase in calculation processing time. One embodiment of the present invention can provide an imaging device that suppresses an increase in power consumption.

[0020] One embodiment of the present invention can provide an imaging system with a novel configuration. One embodiment of the present invention can provide an imaging system that can handle data larger than an imaging area. One embodiment of the present invention can provide an imaging system that suppresses an increase in calculation processing time. One embodiment of the present invention can provide an imaging system that suppresses an increase in power consumption.

[0021] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a diagram illustrating an imaging device. [Figure 2] 2A to 2D are diagrams for explaining the imaging region. [Figure 3] 3A to 3C are diagrams illustrating the imaging area. [Figure 4] FIG. 4 is a diagram illustrating the imaging device. [Figure 5] Fig. 5A is a diagram illustrating the imaging device, and Fig. 5B is a diagram illustrating the circuit 332. [Figure 6] FIG. 6 is a diagram illustrating an imaging device. [Figure 7] 7A to 7C are circuit diagrams illustrating pixels. [Figure 8] FIG. 8 is a timing chart illustrating the operation of the imaging device. [Figure 9] FIG. 9 is a diagram illustrating a signal output from the imaging region. [Figure 10] FIG. 10 is a diagram illustrating the circuit 304 and the circuit 305. As shown in FIG. [Figure 11] FIG. 11 is a diagram illustrating the circuit 305. [Figure 12] FIG. 12 is an image diagram illustrating a processing method of the imaging system. [Figure 13] FIG. 13 is a flowchart illustrating the imaging system. [Figure 14] FIG. 14 is a flowchart illustrating the imaging system. [Figure 15] FIG. 15 is an image diagram illustrating a processing method of the imaging system. [Figure 16] FIG. 16 is a flowchart illustrating the imaging system. [Figure 17] 17A to 17D are diagrams illustrating the configuration of a pixel in an imaging device. [Figure 18] 18A to 18C are diagrams illustrating the configuration of a photoelectric conversion device. [Figure 19] FIG. 19 is a cross-sectional view illustrating a pixel. [Figure 20] 20A to 20C are diagrams illustrating a Si transistor. [Figure 21] FIG. 21 is a cross-sectional view illustrating a pixel. [Figure 22] FIG. 22 is a cross-sectional view illustrating a pixel. [Figure 23] 23A to 23D illustrate OS transistors. [Figure 24] FIG. 24 is a cross-sectional view illustrating a pixel. [Figure 25] 25A1 to 25A3 and 25B1 to 25B3 are perspective views of a package and a module that house an imaging device. [Figure 26] 26A, 26B, 26C, 26D, 26E, and 26F are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0024] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0025] In addition, in top views (also called "plan views"), perspective views, and the like, some components may be omitted to make the drawings easier to understand.

[0026] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0027] In this specification, the term "resistance" may refer to a resistance value determined by the length of the wiring. Alternatively, the resistance may be formed by connecting a conductive layer having a different resistance from the conductive layer used in the wiring via a contact. Alternatively, the resistance value may be determined by doping impurities into a semiconductor layer.

[0028] In this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0029] In this specification, the terms "above," "upper," "lower," or "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Furthermore, the expression "conductive layer D above conductive layer C" does not require that conductive layer D be formed in direct contact with conductive layer C, and does not exclude cases where other components are included between conductive layer C and conductive layer D. Furthermore, "above" or "lower" does not exclude cases where components are arranged diagonally.

[0030] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0031] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows for the exchange of electrical signals between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only an extending wiring. Furthermore, even when the expression "directly connected" is used, it includes cases where wiring is formed on different conductive layers via contacts. Therefore, in wiring, there may be cases where different conductive layers contain one or more of the same elements or different elements.

[0032] Furthermore, in this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.

[0033] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "same," "equal," or "uniform" are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0034] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0035] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0036] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0037] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0038] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0039] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0040] In this specification, the high power supply voltage VDD (hereinafter simply referred to as "VDD," "H voltage," or "H") refers to a power supply voltage that is higher than the low power supply voltage VSS (hereinafter simply referred to as "VSS," "L voltage," or "L"). VSS refers to a power supply voltage that is lower than VDD. The ground voltage (hereinafter simply referred to as "GND" or "GND voltage") can also be used as VDD or VSS. For example, when VDD is the ground voltage, VSS is a voltage lower than the ground voltage, and when VSS is the ground voltage, VDD is a voltage higher than the ground voltage.

[0041] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0042] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0043] In this specification, the term "drain" refers to a drain region, a drain electrode, and part or all of a drain wiring. The term "drain region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or wiring.

[0044] (Embodiment 1) In this embodiment, an imaging device according to one embodiment of the present invention will be described. The imaging device has an imaging region including a plurality of pixels. The plurality of pixels in the imaging region include a first pixel and a second pixel. As an example, the imaging device can select a first region and a second region. The first region or the second region is configured by pixels designated in units of integer rows and integer columns. Therefore, a group of pixels designated as the first region can be treated as a single unit. In other words, this means that the imaging region is divided by the first regions. Furthermore, it is preferable that the second region includes the same number of pixels as the first region. Note that it is preferable that the first region includes at least the first pixel and the second pixel, and that the second region includes at least the second pixel. The pixels in the first region or the second region output imaging signals acquired by the respective pixels.

[0045] The imaging device can generate first image data by simultaneously reading out and calculating the image signals output by the pixels in the first region. The imaging device can also generate second image data by simultaneously reading out and calculating the image signals output by the pixels in the second region. Note that the calculation preferably includes averaging processing.

[0046] Note that the pixels in the first region may be given a weighting factor so that the imaging signals output by the pixels are converted into first imaging signals. Also, the pixels in the second region may be given a weighting factor so that the imaging signals output by the pixels are converted into second imaging signals. Therefore, by adding the first imaging signals to the imaging signals output by the pixels in the first region, the same value as that obtained when the imaging signals output by the pixels in the first region are averaged can be obtained. Also, by adding the second imaging signals to the imaging signals output by the pixels in the second region, the same value as that obtained when the imaging signals output by the pixels in the second region are averaged can be obtained.

[0047] Therefore, the imaging device can generate a first image using the first image data and the second image data. The first image is an image in which discontinuous features are extracted from an image captured by the imaging device.

[0048] When the second region is set, the second region may extend outside the imaging region. In other words, the number of pixels that the second region must include may be insufficient within the imaging region. In the above case, the imaging device preferably has a first circuit that functions as a substitute for the pixels that are insufficient for the second region. The first circuit preferably functions as a memory device, and the memory device preferably can hold a voltage.

[0049] Note that it is preferable that a transistor included in a pixel of an imaging device and a transistor included in a memory device include a metal oxide in a semiconductor layer of the transistor and further include a back gate.

[0050] Next, an imaging device according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating an imaging device 100. The imaging device 100 has an imaging region 300. The imaging region 300 has a plurality of pixels. As an example, the imaging region 300 shown in FIG. 1 has pixels P(1,1) to P(4,4). Note that the number of pixels included in the imaging region 300 is not limited. For example, the imaging region 300 can have pixels P(1,1) to P(m,n), where m and n are positive integers.

[0051] The imaging device 100 can divide the imaging region 300 into a plurality of regions, each of which is a first region. As an example, if the first region is specified as a unit of two pixels in the row direction and two pixels in the column direction, the first region corresponds to pixels P(1,1) to P(2,2) included in region a11, and the second region corresponds to pixels P(2,1) to P(3,2) included in region a21. It is preferable that the first region includes the same number of pixels as the second region. Furthermore, the pixels P included in the first region or the second region output imaging signals acquired by the respective pixels P.

[0052] Here, the positional relationship between the first region and the second region in the imaging region 300 will be described. As shown in Fig. 1, pixels P(2,1) and P(2,2) in the first region are included in the second region. However, pixels P(1,1) and P(1,2) in the first region are not included in the second region. In other words, the second region is a region specified by moving the first region by one pixel in the x-axis direction.

[0053] Similarly, area a31 is an area specified by moving the second area by one pixel in the x-axis direction, and area a13 is an area specified by moving the first area by two pixels in the y-axis direction. Therefore, the imaging area 300 can be represented by compressing information into areas a11 to a33.

[0054] Although not shown in FIG. 1, area a41 is an area specified by moving area a31 by one pixel in the x-axis direction. However, area a41 must be composed of pixels P(4,1) to P(5,2). However, in the example shown in FIG. 1, the imaging area 300 does not have pixels P(5,1) and P(5,2). Therefore, when specifying area a41, dummy pixels must be prepared in place of pixels P(5,1) and P(5,2).

[0055] That is, the imaging device 100 can output image data corresponding to areas a11 to a33 by performing calculations on the image signals output by each pixel P among pixels P(1,1) to P(4,4) for each area. Note that the image data corresponding to areas a11 to a33 is output as image data d11 to d33. Note that the calculations include addition, subtraction, multiplication, division, and averaging processes that combine these.

[0056] 2A to 2D are diagrams illustrating the imaging region 300. As an example, the imaging region 300 has pixels P(1,1) to P(8,9). In FIGS. 2A to 2D, the first region is configured with four pixels (specified in units of two pixels in the row direction and two pixels in the column direction, which may be referred to as a grid size). Therefore, phase image data IM1 to IM4 having four different phases can be generated, each of which is based on pixels P(1,1) to P(2,2) included in the first region. Note that the phase image data IM1 to IM4 are generated by performing calculations using image data output by the same number of pixels in each region.

[0057] The phase image data IM1 to IM4 will be described in detail. The phase image data IM1 shown in Fig. 2A has regions a111 to a144 and image data d111 to d144. The phase image data IM2 shown in Fig. 2B has regions a211 to a244 and image data d211 to d244. The phase image data IM3 shown in Fig. 2C has regions a311 to a344 ​​and image data d311 to d344. The phase image data IM4 shown in Fig. 2D has regions a411 to a444 and image data d411 to d444.

[0058] As an example, the phase image data IM2 shown in Fig. 2B is set with a base point located at a pixel obtained by shifting the region specified by the phase image data IM1 by one pixel in the x-axis direction. The phase image data IM3 shown in Fig. 2C is set with a base point located at a pixel obtained by shifting the region specified by the phase image data IM1 by one pixel in the y-axis direction. The phase image data IM3 shown in Fig. 2D is set with a base point located at a pixel obtained by shifting the region specified by the phase image data IM1 by one pixel in each of the x-axis and y-axis directions.

[0059] In the example of phase image data IM2 shown in Figure 2B, pixels DD(9,1) to DD(9,8) are added as dummy pixels in place of pixels where the imaging area 300 does not exist in areas a241, a242, a243, and a244.

[0060] In addition, in the example of phase image data IM4 shown in Figure 2D, pixels DD(9,2) to DD(9,9) are added as dummy pixels in place of pixels where the imaging area 300 does not exist in areas a441, a442, a443, and a444.

[0061] As mentioned above, the process of adding dummy pixels that do not exist in the actual pixel area to make the number of data equal during calculation is sometimes called padding.

[0062] 3A to 3C are diagrams illustrating the imaging region 300. Similar to FIG. 2, the imaging region 300 has pixels P(1,1) to P(8,9). However, in FIGS. 3A to 3C, the first region is composed of 16 pixels (grid size: 4×4). Therefore, phase image data IM1 to IM16 having 16 different phases can be generated, each of which is based on pixels P(1,1) to P(4,4) included in the first region. Note that the phase image data IM1 to IM16 are generated by calculation using image data output by the same number of pixels in each region. Note that in FIG. 3, only the phase image data IM1, phase image data IM2, and phase image data IM16 are described, and a description of the others is omitted.

[0063] The phase image data IM1, IM2, and IM16 will be described in detail. The phase image data IM1 shown in Fig. 3A has regions a0111 to a0122 and image data d0111 to d0122. The phase image data IM2 shown in Fig. 3B has regions a0211 to a0222 and image data d0211 to d0222. The phase image data IM16 shown in Fig. 3C has regions a1611 to a1622 and image data d1611 to d1622.

[0064] For example, the phase image data IM2 shown in Fig. 3B is set to have its base point shifted by one pixel in the x-axis direction from the region where the phase image data IM1 is set as its base point, while the phase image data IM16 shown in Fig. 3C is set to have its base point shifted by three pixels in each of the x-axis and y-axis directions from the region where the phase image data IM1 is set as its base point.

[0065] In the example of the phase image data IM2 shown in FIG. 3B, pixels DD(9,1) to DD(9,8) are added as dummy pixels in place of pixels where the imaging region 300 does not exist in the region a0221 and the region a0222.

[0066] In addition, in the example of phase image data IM16 shown in Figure 3C, instead of pixels in areas a1621, a1612, and a1622 where the imaging area 300 does not exist, dummy pixels DD(9,4) to dummy pixel DD(11,9) are specified in the x-axis direction, and dummy pixels DD(4,10) to dummy pixel DD(11,11) are specified in the y-axis direction.

[0067] An example of the phase image data IM16 will now be described in detail. The region a1611 is made up of pixels P(4,4) through P(7,7). The region a1621 is made up of pixels P(8,4) through P(8,7) and dummy pixels DD(9,4) through dummy pixels DD(11,7). The region a1612 is made up of pixels P(4,8) through P(7,9) and dummy pixels DD(4,10) through dummy pixels DD(7,11). The region a1622 is made up of pixels P(8,8) and P(8,9), dummy pixels DD(9,8) through dummy pixels DD(11,9), and dummy pixels DD(8,10) through dummy pixels DD(11,11). It is preferable that the dummy signals provided to the dummy pixels be changeable as needed.

[0068] 4 is a diagram illustrating the imaging device 100. The imaging device 100 has an imaging region 300, a circuit 301, a circuit 302, a circuit 303, a circuit 304, and a circuit 305. The imaging region 300 has a plurality of pixels P.

[0069] The circuit 301 functions as a read selection driver. For example, the circuit 301 is electrically connected to a plurality of pixels P through a wiring 122. The pixels P are electrically connected to a circuit 302 through a wiring 113. The circuit 302 is electrically connected to a circuit 303. The circuit 303 is electrically connected to a circuit 304. The circuit 304 is electrically connected to a circuit 305.

[0070] The circuit 302 functions as a switch module. The circuit 303 has a function of converting an image signal output by a pixel as a current into a potential. The circuit 304 functions as a correlated double sampling circuit (CDS circuit). The circuit 305 functions as a memory device.

[0071] The circuit 301 can select a pixel P from which to read out an imaging signal by applying a selection signal to the wiring 122. Furthermore, the circuit 301 can simultaneously apply selection signals to multiple wirings 122. By simultaneously applying selection signals to multiple wirings 122, imaging signals can be simultaneously read out from a group of pixels selected by the grid size described above.

[0072] The circuit 302 is a switch module that switches the readout path to treat the pixel group selected by the grid size as a single region. Therefore, the circuit 302 can calculate the image signals output by the pixel group to generate image data. The calculation is preferably an integration. If the region selected by the grid size includes dummy pixels, the padding circuit in the circuit 302 can provide dummy data in place of the missing pixels.

[0073] The circuit 303 converts the image data output as a current into a potential. The image data converted into a potential corresponds to the result of integrating the image signals output from a plurality of pixels.

[0074] Circuit 304 is a CDS circuit that removes variations and offset components that the imaging device 100 has in order to generate phase image data. More specifically, circuit 304 generates image data from which variations and offset components due to parasitic capacitance or resistance components of each wiring, pixel, circuit 302, circuit 303, etc. have been removed. The output of circuit 304 is stored in circuit 305. Circuit 305 is preferably an analog memory that can hold potential values. The analog memory will be described in detail with reference to FIG. 12.

[0075] 5A is a diagram illustrating the imaging device 100. For ease of explanation, the same reference numerals are used for parts having similar functions, and the repeated explanations will be omitted.

[0076] 5A is a diagram illustrating in detail the imaging region 300 and the circuit 302 included in the imaging device 100. The imaging region 300 includes a plurality of pixels P, wirings 113(1) to 113(k), and wirings 122(i) to 122(i+1). As an example, the imaging region 300 includes pixels P(1,i) to P(k,i+1), where i and k are positive integers.

[0077] The circuit 302 includes a plurality of circuits: a circuit 320, a circuit 330a, a circuit 330b, and a circuit 350. The circuit 320 includes a circuit 321, a switch 322, and a switch 323. Note that it is preferable to provide k-1 circuits 320. The circuit 330a includes a circuit 331 and a circuit 332. The circuit 330b includes a circuit 331, a circuit 332, and a switch 333.

[0078] Circuit 350 is a control circuit. Circuit 350 controls switches 322 and 323 via circuit 321 functioning as a decoder circuit, and controls switch 333 via circuit 331 functioning as a decoder circuit. Circuits 330a and 330b function as padding circuits and can perform padding processing.

[0079] Next, a description will be given of the electrical connections of the imaging device 100 illustrated in Fig. 5A. As an example, a description will be given of a case where the imaging region 300 has at least an area a111 and an area a121, and the area a111 and the area a121 are each configured by four pixels.

[0080] The region a111 is composed of pixel P(1,i), pixel P(2,i), pixel P(1,i+1), and pixel P(2,i+1). The wiring 122(i) is electrically connected to pixel P(1,i) and pixel P(2,i). The wiring 122(i+1) is electrically connected to pixel P(1,i+1) and pixel P(2,i+1). The wiring 113(1) is electrically connected to pixel P(1,i) and pixel P(1,i+1). The wiring 113(2) is electrically connected to pixel P(2,i) and pixel P(2,i+1).

[0081] Area a121 is composed of pixel P(3,i), pixel P(4,i), pixel P(3,i+1), and pixel P(4,i+1). Wiring 122(i) is electrically connected to pixel P(3,i) and pixel P(4,i). Wiring 122(i+1) is electrically connected to pixel P(3,i+1) and pixel P(4,i+1). Wiring 113(3) is electrically connected to pixel P(3,i) and pixel P(3,i+1). Wiring 113(4) is electrically connected to pixel P(4,i) and pixel P(4,i+1).

[0082] Furthermore, the wiring 122(i) is electrically connected to the pixel P(k,i). The wiring 122(i+1) is electrically connected to the pixel P(k,i+1). The wiring 113(k) is electrically connected to the pixel P(k,i) and the pixel P(k,i+1).

[0083] The wiring 113(1) is electrically connected to the circuit 332 included in the circuit 330a, and to the terminal 1 of the switch 322 and the terminal 1 of the switch 323 included in the circuit 320(1). The terminal 2 of the switch 322 included in the circuit 320(1) is electrically connected to the wiring 113(2), and to the terminal 1 of the switch 322 and the terminal 1 of the switch 323 included in the circuit 320(2). The terminal 2 of the switch 323 included in the circuit 320(1) is electrically connected to the circuit 303(1).

[0084] A terminal 2 of the switch 323 included in the circuit 320(2) is electrically connected to the circuit 303(2). A terminal 2 of the switch 322 included in the circuit 320(2) is electrically connected to the wiring 113(3), and a terminal 1 of the switch 322 and a terminal 1 of the switch 323 included in the circuit 320(3).

[0085] A terminal 2 of the switch 323 included in the circuit 320(3) is electrically connected to the circuit 303(3). A terminal 2 of the switch 322 included in the circuit 320(3) is electrically connected to the wiring 113(4), and a terminal 1 of the switch 322 and a terminal 1 of the switch 323 included in the circuit 320(4).

[0086] Terminal 2 of the switch 323 included in the circuit 320(4) is electrically connected to the circuit 303(4). Terminal 2 of the switch 322 included in the circuit 320(4) is electrically connected to a wiring 113(5) (not shown) and terminals 1 of the switch 322 and 323 included in the circuit 320(5) (not shown).

[0087] Next, the circuit 330b will be described. The circuit 330b is electrically connected to the wiring 113(k). The wiring 113(k) is electrically connected to a terminal 2 of a switch 322 included in the circuit 320(k-1) (not shown) and to a circuit 332 and a terminal 1 of a switch 333 included in the circuit 330b. The terminal 2 of the switch 333 is electrically connected to the circuit 303(k).

[0088] Next, the circuit 350 will be described. The circuit 350 is electrically connected to the circuit 332 via the circuit 331 included in the circuit 330a. The circuit 350 is electrically connected to the circuit 332 and to the terminal 3 of the switch 333 included in the circuit 330b via the circuit 331 included in the circuit 330b. The circuit 350 is also electrically connected to the terminal 3 of the switch 322 and the terminal 3 of the switch 323 included in the circuit 320(1) via the circuit 321 included in the circuit 320(1). The circuit 350 is also electrically connected to the terminal 3 of the switch 322 and the terminal 3 of the switch 323 included in the circuit 320(2) via the circuit 321 included in the circuit 320(2). The circuit 350 is also electrically connected to the terminal 3 of the switch 322 and the terminal 3 of the switch 323 included in the circuit 320(3) via the circuit 321 included in the circuit 320(3). The circuit 350 is also electrically connected to a terminal 3 of a switch 322 and a terminal 3 of a switch 323 included in the circuit 320(4) via a circuit 321 included in the circuit 320(4).

[0089] As an example, the wiring 113(1) can be electrically connected to the wiring 113(2) by turning on the switch 322 included in the circuit 320(1). Furthermore, when the switch 323 included in the circuit 320(1) is turned on and the switches 322 and 323 included in the circuit 320(2) are turned off, the imaging signals output from the pixels P(1,i), P(2,i), P(1,i+1), and P(2,i+1) are provided to the circuit 303(1). Therefore, the image data output from the region a111 is generated by adding up the imaging signals output from the pixels P(1,i), P(2,i), P(1,i+1), and P(2,i+1).

[0090] As another example, when a region including dummy pixels is provided including pixels connected to wiring 113(1), circuit 330a functions as a padding circuit. Circuit 330a operates in place of dummy pixels. Image data of the region including dummy data is output to circuit 303(1). Similarly, when a region including dummy pixels is provided including pixels connected to wiring 113(k), circuit 330b functions as a padding circuit. Circuit 330b operates in place of dummy pixels. Image data of the region including dummy data is output to circuit 303(k) via switch 333.

[0091] 5B is a diagram illustrating circuit 332 that functions as a padding circuit. Circuit 332 has a register 340 and a plurality of switches. Register 340 has memories 341a to 341c, and switches 332a to 332c corresponding to the memories, respectively.

[0092] The memory 341a is electrically connected to the wiring 113 through a switch 332a. The memory 341b is electrically connected to the wiring 113 through a switch 332b. The memory 341c is electrically connected to the wiring 113 through a switch 332c. The on / off states of the switches 332a to 332c are independently controlled by the circuit 331. The operation of the circuit 331 is preferably controlled by an instruction from the circuit 350.

[0093] It is preferable that the memories 341a to 341c are analog memories. Any potential stored in the analog memories can be used as the dummy data. Therefore, the memories included in the register 340 correspond to dummy pixels. Therefore, the number of memories included in the register 340 is not limited. As an example, it is preferable that a potential corresponding to an intermediate value of the imaging signal is stored as dummy data in each memory. It is preferable that the dummy data be supplied from memories equal to the number of pixels added as dummy pixels.

[0094] Note that the switches 322, 323, 333, and 332a to 332c can be formed using transistors. The analog memory includes a selection switch that uses a transistor. The pixel P includes a plurality of switches that use a transistor.

[0095] The semiconductor layer of the transistor preferably includes an oxide semiconductor. A transistor including an oxide semiconductor (OS), which is a type of metal oxide, in a semiconductor layer in which a channel of the transistor is formed is called an "OS transistor" or an "OS-FET." OS transistors are known to have small fluctuations in electrical characteristics due to temperature changes. Furthermore, because the energy gap of the semiconductor layer of an OS transistor is large, it can exhibit extremely low off-state current characteristics of several yA / μm (current value per 1 μm of channel width). Therefore, OS transistors are preferably applied to memory devices. OS transistors will be described in detail in Embodiment 3.

[0096] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range from room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Furthermore, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device with stable operation and high reliability can be realized even in a high-temperature environment.

[0097] Furthermore, the OS transistor can be formed by sputtering during a back-end-of-line (BEOL) process for forming wiring in a semiconductor device. Therefore, a single imaging device 100 can be formed using transistors with different transistor characteristics. In other words, the use of OS transistors makes it easy to form a system on chip (SOC).

[0098] Fig. 6 is a diagram illustrating the imaging device 100. Fig. 6 illustrates the area a111, circuits 302, and circuits 303 of the imaging device 100. To simplify the explanation, the same reference numerals are used for parts having similar functions, and the repeated explanations will be omitted.

[0099] In FIG. 6, an explanation will be given using pixels P(1, i) to P(2, i+1) included in the area a111 as an example.

[0100] The pixel P(1,i) and the pixel P(1,i+1) are electrically connected to the wiring 113(1). The wiring 113(1) is electrically connected to a circuit 320(1) included in the circuit 302. The circuit 320(1) is electrically connected to a circuit 303(1) included in the circuit 303.

[0101] The pixel P(2,i) and the pixel P(2,i+1) are electrically connected to the wiring 113(2). The wiring 113(2) is electrically connected to a circuit 320(2) included in the circuit 302. The circuit 320(2) is electrically connected to a circuit 303(2) included in the circuit 303.

[0102] The circuit 320(1) can be electrically connected to the circuit 320(2) under the control of the circuit 350. Although not shown, it can also be connected to the circuit 320(k). Furthermore, unlike FIG. 5A, a circuit 330a is electrically connected to each of the wirings 113. The circuit 330a connected to the wiring 113 is set when dummy pixels are provided in the y-axis direction of the imaging region 300. By providing the circuit 330a to each of the wirings 113, dummy data can be supplied when dummy pixels are provided.

[0103] Next, the circuit 303 will be described in detail. Here, the circuit 303(2) will be described as an example. The circuit 303(2) includes a capacitor 202, a transistor 203, a transistor 204, a transistor 205, a transistor 206, and a resistor 207.

[0104] One electrode of the capacitor 202 is electrically connected to one of the source or drain of the transistor 203. The one of the source or drain of the transistor 203 is electrically connected to the gate of the transistor 204. The one of the source or drain of the transistor 204 is electrically connected to one of the source or drain of the transistor 205. The one of the source or drain of the transistor 205 is electrically connected to one of the source or drain of the transistor 206. One electrode of the resistor 207 is electrically connected to the other electrode of the capacitor 202.

[0105] The other electrode of the capacitor 202 is electrically connected to the wiring 113 through the circuit 320. The other of the source and the drain of the transistor 203 is electrically connected to a wiring 218. The other of the source and the drain of the transistor 204 is electrically connected to a wiring 219. The other of the source and the drain of the transistor 205 is electrically connected to a reference power supply line such as a GND wiring. The other of the source and the drain of the transistor 206 is electrically connected to a wiring 313. The other electrode of the resistor 207 is electrically connected to a wiring 217. The gate of the transistor 203 is electrically connected to a wiring 216. The gate of the transistor 205 is electrically connected to a wiring 215. The gate of the transistor 206 is electrically connected to a wiring 213.

[0106] The wiring 217, the wiring 218, and the wiring 219 can function as power supply lines. For example, the wiring 218 can function as a wiring that supplies a dedicated potential for readout. The wiring 217 and the wiring 219 can function as high-potential power supply lines. The wiring 213, the wiring 215, and the wiring 216 can function as signal lines that control the conduction of each transistor. The wiring 313(2) is an output line and can be electrically connected to, for example, the circuit 304 shown in FIG. 4.

[0107] The transistor 203 can have a function of resetting the potential of the wiring 211 to the potential of the wiring 218. The transistors 204 and 205 can function as source follower circuits. The transistor 206 can have a function of controlling reading. Note that the wiring 211 is a wiring that electrically connects one electrode of the capacitor 202, one of the source and drain of the transistor 203, and the gate of the transistor 204.

[0108] Note that a capacitor may be used instead of the resistor 207. By using such a capacitor, it is possible to suppress leakage current and perform current-voltage conversion with reduced power consumption. Furthermore, when such a capacitor is used, the capacitor 202 can be eliminated from the components. Furthermore, when such a capacitor is used, it is preferable to use a pixel P shown in FIG. 7B or 7C, which will be described later.

[0109] 7A to 7C are circuit diagrams illustrating a pixel P. As shown in FIG. 7A, the pixel P can have a photoelectric conversion device 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, and a transistor 108.

[0110] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to one of the source and drain of the transistor 103. The other of the source and drain of the transistor 103 is electrically connected to one electrode of the capacitor 104. One electrode of the capacitor 104 is electrically connected to the gate of the transistor 105. The other of the source and drain of the transistor 105 is electrically connected to one of the source and drain of the transistor 108. The other electrode of the capacitor 104 is electrically connected to a wiring 112.

[0111] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 114. The gate of the transistor 102 is electrically connected to a wiring 116. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 115. The gate of the transistor 103 is electrically connected to a wiring 117. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 118. The other of the source and the drain of the transistor 108 is electrically connected to a wiring 113. The gate of the transistor 108 is electrically connected to a wiring 122.

[0112] Here, the electrical connection point (wiring) between the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 104, and the gate of the transistor 105 is referred to as a node N.

[0113] The wiring 114 and the wiring 115 can function as power supply lines. For example, the wiring 114 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. The wiring 116, the wiring 117, and the wiring 122 can function as signal lines that control the conduction of each transistor. The wiring 112 can function as a wiring that supplies a potential corresponding to a weighting coefficient to the pixel P. The wiring 113 can function as a wiring that electrically connects the pixel P and the circuit 303.

[0114] The wiring 113 may be electrically connected to an amplifier circuit or a gain adjustment circuit.

[0115] A photodiode can be used as the photoelectric conversion device 101. If it is desired to increase the light detection sensitivity at low illuminance, it is preferable to use an avalanche photodiode.

[0116] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The transistor 105 can have a function of controlling the amount of current supplied to the circuit 303 in accordance with the potential of the node N. The transistor 108 can have a function of selecting a pixel. Note that the transistor 108 may be provided between the wiring 118 and the transistor 105.

[0117] As an example, a case will be described in which the wiring 112 is electrically connected to all pixels P included in the imaging region 300. A potential applied to the wiring 112 can be applied to a node N via a capacitor 104, which corresponds to a weighting coefficient. When image signals in regions divided into a grid pattern, which is one embodiment of the present invention, are simultaneously processed, weighting coefficients can be simultaneously applied to target pixels.

[0118] 7A, the transistor 105 is preferably an n-channel FET. When the transistor 105 is an n-channel FET, the wiring 118 functions as a low-potential power supply line. When the wiring 118 functions as a low-potential power supply line, the potential between the gate and source of the transistor 105 is determined by the node N. Therefore, in the pixel P, a current flows from the wiring 113 to the wiring 118 through the transistor 105. Note that the transistor 102, the transistor 103, or the transistor 108 may be an n-channel FET or a p-channel FET.

[0119] 7B, the transistor 105 is preferably a p-channel FET. When the transistor 105 is a p-channel FET, the wiring 118 functions as a high-potential power supply line. When the wiring 118 functions as a high-potential power supply line, the potential between the gate and source of the transistor 105 is determined by the node N. Therefore, in the pixel P, a current flows from the wiring 118 to the wiring 113 through the transistor 105. Note that the transistor 102, the transistor 103, or the transistor 108 may be an n-channel FET or a p-channel FET.

[0120] Figure 7C is a circuit diagram illustrating a pixel P different from that in Figure 7B. Figure 7C differs from Figure 7B in that it includes transistors 102a, 103a, and 108a. Transistors 102a, 103a, and 108a each have a back gate.

[0121] For example, when an avalanche photodiode is used as the photoelectric conversion device 101, a high potential may be applied, and therefore, a high-voltage transistor is preferably used as a transistor connected to the photoelectric conversion device 101. For example, an OS transistor using a metal oxide in a channel formation region can be used as the high-voltage transistor. Specifically, OS transistors are preferably used as the transistors 102 and 102a. Note that the OS transistors preferably have a back gate. By providing a back gate to the OS transistor, the threshold voltage of the OS transistor can be controlled.

[0122] In addition, OS transistors have an extremely low off-state current. By using OS transistors for the transistors 102, 102a, 103, and 103a, the period during which charge can be held at the node N can be significantly extended. Therefore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration or operation method. Furthermore, while an image signal is held at the node N, multiple calculations can be performed using the image signal.

[0123] Alternatively, OS transistors can be used as the transistors 108 and 108a. The pixel P can reduce variations and noise components caused by leakage current to the wiring 113 by utilizing the extremely low off-state current of the OS transistors.

[0124] On the other hand, it is desirable that the transistor 105 have excellent amplification characteristics. Therefore, it is preferable that the transistor 105 be a transistor using silicon for a channel formation region (hereinafter referred to as a Si transistor).

[0125] Note that the present invention is not limited to the above, and a combination of OS transistors and Si transistors may be used, or all the transistors may be OS transistors, or all the transistors may be Si transistors.

[0126] The potential of the node N in the pixel P is determined by capacitive coupling between a potential (image pickup signal) obtained by adding a potential generated by photoelectric conversion by the photoelectric conversion device 101 to a reset potential supplied from the wiring 115, and a potential corresponding to a weighting coefficient supplied from the wiring 112. That is, a current corresponding to the potential obtained by assigning an arbitrary weighting coefficient to the image pickup signal flows through the transistor 105.

[0127] 8 is a timing chart illustrating the operation of acquiring data with imaging and data without imaging in the area a111 and the circuit 303. Note that for convenience, the timing at which each signal changes is also shown, but in reality, the timing within the circuit can be compressed for operation. Also, the timing can be shifted to take into account delays in the timing within the circuit.

[0128] First, the acquisition of image-captured data will be described. In the following description, high potential is "H" and low potential is "L."

[0129] In a period T1, the potential of the wiring 117 is set to "H", the potential of the wiring 116 is set to "H", and the node N of the pixel P is set to a reset potential. In addition, the potential of the wiring 112 is set to "L", thereby initializing the weighting coefficient.

[0130] In period T2, the potential of the wiring 116 is maintained at "H". Furthermore, by setting the potential of the wiring 117 to "L", the potential X (imaging signal) of the node N is updated by the current generated by photoelectric conversion of the photoelectric conversion device 101. Furthermore, by setting the wiring 216 to "H", the potential Vr of the wiring 218 is written to the wiring 211. The operations in periods T1 and T2 correspond to the acquisition of data with imaging, and this data is represented as the potential Vr of the wiring 211.

[0131] In period T3, a potential corresponding to the weighting factor W is applied to the wiring 112. The weighting factor W is added to the node N of each pixel P in the imaging region 300 (first and second rows) via the capacitance of the capacitor 104.

[0132] During period T4, the potentials of the wirings 122_1 and 122_2 are set to "H" to select all pixels P in the region a111. At this time, a current corresponding to the potential W+X flows through the transistors 105 of the pixels P in the first and second rows. Here, a potential is generated by the current flowing to the resistor 207 via the wiring 113. The potential Y generated by the current flowing to the resistor 207 is added to the potential Vr of the wiring 211 via the capacitor 202. Therefore, the potential of the wiring 211 becomes "Vr+Y." Here, if Vr=0, Y is the difference itself, and data with imaging has been calculated. Furthermore, by setting the wirings 213 and 215 to "H," the circuit 303 can output a signal potential corresponding to the data with imaging of the region a111 by source follower operation.

[0133] Next, acquisition of data without imaging will be described.

[0134] In period T5, the potential of the wiring 117 is set to "H", the potential of the wiring 116 is set to "H", and the node N of the pixel P is set to a reset potential. In addition, the potential of the wiring 112 is set to "L", thereby initializing the weighting coefficient. In addition, the potential of the wiring 216 is set to "H", thereby writing the potential Vr of the wiring 218 to the wiring 211.

[0135] In a period T6, a potential corresponding to the weighting factor W is applied to the wiring 112. The weighting factor W is added to the node N of each pixel P in the imaging region 300 (first and second rows) via the capacitance of the capacitor 104.

[0136] During period T7, the potentials of the wirings 122_1 and 122_2 are set to "H" to select all pixels P in the region a111. At this time, a current corresponding to the potential W+X flows through the transistors 105 of the pixels P in the first and second rows. Here, a potential is generated by the current flowing through the resistor 207 via the wiring 113. The potential Y generated by the current flowing through the resistor 207 is added to the potential Vr of the wiring 211 via the capacitor 202. Therefore, the potential of the wiring 211 becomes "Vr+Y." Here, if Vr=0, Y is the difference itself, and data without imaging is calculated. Furthermore, by setting the wirings 213 and 215 to "H," the circuit 303 can output a signal potential corresponding to the data without imaging of the region a111 through source follower operation. Note that the data without imaging includes circuit variations and unnecessary offset components.

[0137] The data with imaging and data without imaging output from circuit 303 by the above operation are input to circuit 304. Circuit 304 performs an operation to find the difference between the data with imaging and the data without imaging, thereby removing unnecessary offset components.

[0138] Fig. 9 is a diagram illustrating signals output from the imaging region 300. For simplicity of explanation, Fig. 9 shows, as an example, four regions a (region a111, region a112, region a121, and region a122) divided into a grid, each region a having four pixels P (P11, P12, P21, and P22).

[0139] The generation of a signal will be described using area a111 as an example, but signals can also be output through similar operations in areas a121, a112, and a122. Note that although the case where area a111 includes four pixels will be described, the number of pixels included in area a111 is not limited.

[0140] In the region a111, the image signals P11, P12, P21, and P22 are stored in the node N of each pixel P. Here, a case where a weighting factor W is assigned to each pixel P will be described. The image signals output by the pixels assigned the weighting factor W can be corrected by the weighting factor W. When the region a111 has four pixels, it is preferable that the image signals output by the pixels assigned the weighting factor W be one-fourth the size. The image data generated by simultaneously reading out the four pixels can have the same value as when image data generated by reading out the pixels without assigning the weighting factor W is averaged in post-processing.

[0141] This will be explained in further detail. h11 (h11 = P11 × W + P12 × W + P21 × W + P22 × W), which is the calculation result of the image pickup signals of P11, P12, P21, and P22, is output via the wiring 113(1) and the circuit 303(1). This obtains the same calculation result as h11 = (P11 + P12 + P21 + P22) × W. In other words, the same effect can be obtained as when the image pickup signals output by each pixel in the area a111 are added and output, and then a calculation using the weighting coefficient W is performed on the output result. Therefore, the calculation process (hardware processing or software processing) can be simplified. Furthermore, simplifying the calculation process can reduce power consumption.

[0142] In parallel, through the same process as above, h21, which is the calculation result of the imaging signal, is output from the area a121 via the wiring 113(2) and the circuit 303(2), completing the output of the first row of the area a.

[0143] Next, in the second row of area a, the same process as above is performed, and h12, which is the calculation result of the imaging signal, is output from area a112 via wiring 113(1) and circuit 303(1). In parallel, h22, which is the calculation result of the imaging signal, is output from area a122 via wiring 113(2) and circuit 303(2), completing the output of the second row of area a.

[0144] The above operation is repeated as necessary. Note that the above-mentioned h11, h21, h12, and h22 correspond to data with imaging, and b11, b21, b12, and b22 correspond to data without imaging.

[0145] FIG. 10 is a diagram illustrating circuits 304 and 305. Circuit 304 functions as a CDS circuit. The CDS circuit may also be referred to as a difference detection circuit. The signal processing method will be described using the output of circuit 303(1) as an example, but circuit 303(2) can also output a signal with a similar operation. Note that in FIG. 10, the description of circuit 302 is omitted.

[0146] The circuit 304 (circuit 304a, circuit 304b) has a selector circuit 361, a frame memory 362, and a difference circuit 363. First, the selector circuit 361 is supplied with image data (image capture data or image non-capturing data) output from the circuit 303(1) via the wiring 313(1). The selector circuit 361 supplies the image capture data or image non-capturing data to the frame memory 362. The frame memory 362 stores the image capture data in even addresses (EV) and stores the image non-capturing data in odd addresses (OD). The frame memory 362 is preferably an analog memory. The analog memory stores the image capture data or image non-capturing data as analog data (voltage values). Using an analog memory can reduce the conversion cost and packaging area required to quantize the image capture data or image non-capturing data.

[0147] A FIFO (First In First Out) circuit using an analog memory can be used instead of the frame memory 362. Note that, although Fig. 10 shows an example in which imaged data h11 to h14 are stored and non-imaged data b11 to b14 are stored, it is preferable that the number of pieces of data that can be stored can be set as needed.

[0148] It is preferable to use a differential amplifier suitable for comparing analog data in the difference circuit 363. By using a differential amplifier in the difference circuit 363, the difference between the no-imaging data stored in the odd addresses and the imaging data stored in the even addresses is output as image data (e.g., d11=h11-b11).

[0149] The image data output by the difference circuit 363 is stored in the circuit 305. FIG. 10 shows an example in which image data d11 to d44 are stored in the circuit 305. Therefore, the image data d11 to d44 correspond to phase image data. It is preferable that the number of data that can be stored in the circuit 305 can be set as needed. Furthermore, it is preferable that the circuit 305 is an analog memory. By using an analog memory, the circuit 305 can achieve the same effect as a frame memory.

[0150] It should be noted that the frame memory 362 or the circuit 305 can use a digital memory. To use a digital memory, the data with imaging, the data without imaging, or the image data must be quantized. It should be noted that quantizing the data with imaging, the data without imaging, or the image data increases the resistance to noise. In addition, the increased resistance to noise allows for faster operation. In addition, power consumption can be reduced by lowering the memory voltage.

[0151] The difference circuit 363 can further have a comparison function. The comparison function can binarize the image data output by the difference circuit 363. The binarized image data can further emphasize and extract the features of the image data. Furthermore, the binarized image data can be compressed, so the memory capacity can be reduced. Furthermore, by reducing the memory capacity, the mounting area can be reduced and power consumption can be reduced.

[0152] FIG. 11 is a diagram illustrating a circuit 305. The circuit 305 includes a plurality of memory cells 335. FIG. 11 illustrates, as an example, memory cells 335(1, i) to 335(2, i+1). Note that the memory cells 335 all have the same configuration and include a transistor 161, a transistor 162, and a capacitor 163.

[0153] One of the source and the drain of the transistor 161 is electrically connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, a point where one of the source and the drain of the transistor 161, the gate of the transistor 162, and one electrode of the capacitor 163 are connected is referred to as a node NM.

[0154] A gate of the transistor 161 is electrically connected to a wiring WL. The other electrode of the capacitor 163 is electrically connected to a wiring RW. One of the source and the drain of the transistor 162 is electrically connected to a reference potential wiring such as a GND wiring.

[0155] In the memory cell 335, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WD. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BL.

[0156] The wiring WL is preferably connected to a decoder, a shift register, or the like.

[0157] A signal for reading image data written in the memory cell 335 is applied to the wiring RW. When image data is applied to the memory cell 335, a low potential is applied to the wiring RW. When image data is read from the memory cell 335, a high potential is applied to the wiring RW.

[0158] The wiring WD is electrically connected to the differential circuit 363. Therefore, image data is provided to the wiring WD. The image data is preferably provided as analog data. Alternatively, the image data is provided as digital data obtained by binarizing analog data.

[0159] The wiring BL can read out image data stored in the memory cell 335. If the image data is analog data, the wiring BL is connected to the control unit (processor) via an analog-to-digital conversion circuit. Alternatively, if the image data is binarized digital data, the wiring BL is connected to the control unit via a register.

[0160] As described above, one embodiment of the present invention can provide an imaging device with a novel configuration that can handle outputs from multiple pixels included in a grid-shaped region as a single imaging signal. Another embodiment of the present invention can provide an imaging device that processes part of a calculation using a weighting factor. Another embodiment of the present invention can provide an imaging device that can handle data larger than the imaging region by performing padding processing. Another embodiment of the present invention can provide an imaging device that can suppress an increase in processing time for calculation using a weighting factor and padding processing. Another embodiment of the present invention can provide an imaging device that can suppress an increase in power consumption by reducing the amount of calculation through calculation using a weighting factor and padding processing.

[0161] This embodiment can be carried out by combining parts thereof as appropriate.

[0162] (Embodiment 2) This embodiment describes an imaging system using the imaging device of Embodiment 1. The imaging system according to one embodiment of the present invention can reduce the amount of calculation, processing time required for calculation, and power consumption by using the imaging device.

[0163] 12 is a conceptual diagram illustrating an imaging system using an imaging device according to one embodiment of the present invention. The imaging system can detect abnormalities from imaging data acquired by the imaging device. The imaging system includes at least the imaging device and a processor (not shown) that controls the imaging device.

[0164] First, a processing method of the imaging system will be described with reference to Fig. 12. The imaging system acquires imaging data to be evaluated using an imaging device. It is preferable that the imaging data has a regularity.

[0165] STEP 1 is a step for setting a grid size KM to be applied to the imaging data. Multiple grid sizes can be set. As an example, if the imaging data has periodicity, it can be determined that the imaging data has regularity. Therefore, if the image data has periodicity, it is preferable to set the periodically appearing feature as the grid size interval. Furthermore, it is preferable to set multiple grid sizes centered around the interval set by the periodically appearing feature. As an example, in FIG. 12, grid sizes KM1 to KMn are set.

[0166] STEP 2 is a step in which phase image data is generated using grid size KM. First, a method for generating phase image data will be described. As an example, when grid size KM1 is used, area a selected by grid size KM1 includes four pixels. The phase image data is generated using multiple image data generated by calculating the imaging signals output by the pixels included in area a. Therefore, four types of phase image data, phase image data IM11 to phase image data IM14, are generated using grid size KM1.

[0167] As another example, for grid size KM2, region a selected by grid size KM2 includes 16 pixels. Therefore, 16 types of phase image data, IM21 to IM216, are generated using grid size KM2. Therefore, the larger the grid size, the more types of phase image data are generated. Note that for grid size KMn, region a selected by grid size KMn includes n pixels. Therefore, n types of phase image data are generated using grid size KMn.

[0168] STEP 3 is a step in which the phase image data generated using each grid size is calculated to generate a pop-up image. Note that this calculation preferably uses multiplication or accumulation.

[0169] As an example of preprocessing, first image data is generated by accumulating phase image data IM11 through IM14 generated using grid size KM1. Next, second image data is generated by accumulating phase image data IM21 through IM216 generated using grid size KM2. Next, n types of phase image data generated using grid size KMn are accumulated to generate nth image data.

[0170] Next, the first image data through the nth image data are integrated to generate a pop-up image. However, there is a problem in that the first image data through the nth image data are each composed of a different number of image data.

[0171] Therefore, the grid size used when creating the first to nth image data is used to divide the original imaging area into pixels, and first to nth image data_b having the same number of image data are generated. Note that the first to nth image data_b are image data in which irregular areas are extracted as features by undergoing the generation of phase image data.

[0172] Next, the first image data_b to the n-th image data_b are integrated to generate a popup image.

[0173] FIG. 13 is a flowchart illustrating the imaging system.

[0174] In step S00, the imaging device acquires imaging data. Preferably, the imaging device acquires imaging data using a global shutter system. The pixels of the imaging device include OS transistors, which suppress degradation of imaging signals and enable the imaging signals to be maintained.

[0175] Step S01 is a step in which the imaging system sets a flag rflag for managing the processing mode. The processing modes include a mode in which imaging data is read and calculated, and a mode in which imaging data is initialized and calculated. In the mode in which imaging data is read and calculated, the flag rflag is set to "0." In the mode in which initialized imaging data is calculated, the flag rflag is set to "1." Note that imaging-enabled data is generated in the mode in which imaging data is read and calculated, and non-imaging data is generated in the mode in which imaging data output by initialized pixels is calculated.

[0176] Step S02 is a step of making various settings for the imaging system to process the imaging data. As an example, a grid size to be applied is set. Furthermore, the number of phases is set according to the grid size. Furthermore, a weighting coefficient is set according to the number of phases. Note that multiple types of grid sizes can be set. Furthermore, the imaging system can have a step of extracting regularity from the imaging data.

[0177] Step S03 is a step in which the imaging system divides the imaging area using a grid size. When dividing the imaging area, a base point is given according to the pixels included in the area set by the grid size. To divide the imaging area using the grid size, a switch module is appropriately set by a control unit using a processor or the like. If there are no actual pixels included in the area (insufficient pixels), dummy pixels are set. The dummy pixels are virtually added to the area by padding processing performed by a padding circuit. It is preferable that the dummy data output by the dummy pixels can be appropriately set.

[0178] Step S04 is a step for reading out image data. Each image data is output as an integrated value of the image signals output by the pixel group included in the area set by the grid size. By assigning a weighting coefficient to the area, the integrated value can be averaged and output.

[0179] Step S05 is a step for generating data with imaging or data without imaging. In the case of a mode in which imaging data is read and calculated, data with imaging is generated. Also, in the case of a mode in which initialized imaging data is calculated, data without imaging is generated. Note that the data with imaging or data without imaging is generated by reading image data from an area set by the grid size.

[0180] Step S06 is a step for determining whether data with imaging or data without imaging corresponding to the number of phases set by the grid size has been acquired. If data with imaging or data without imaging corresponding to the set number of phases has been acquired, the process proceeds to step S07; otherwise, the process proceeds to step S03.

[0181] Step S07 is a step for determining whether data with imaging or data without imaging corresponding to the set grid size type has been acquired. If data with imaging or data without imaging corresponding to the set grid size has been acquired, the process proceeds to step S08; otherwise, the process proceeds to step S02.

[0182] Step S08 is a step for determining whether the flag rflag is "0." If the mode for reading and calculating image data has just ended, the flag rflag is "0." Therefore, if the flag rflag is "0," the process proceeds to step S02A; otherwise, the process proceeds to step S09.

[0183] Step S02A will now be described. Step S02A is a step for initializing the imaging data acquired in S00 and transitioning to a calculation mode. The flag rflag is set to "1." Note that the information set in step S02 is used to set the grid size, the number of phases, the weighting coefficients, and so on.

[0184] Step S09 is a step of generating phase image data using the difference between the data with imaging and the data without imaging. The phase image data is generated according to the type of grid size that has been set.

[0185] Step S10 generates a pop-up image by calculating the plurality of phase image data generated in step S09.

[0186] FIG. 14 is a flowchart illustrating the creation of a popup image.

[0187] In step S10A, the imaging system generates image data by calculating the phase image data associated with each grid size, preferably using multiplication or accumulation.

[0188] As an example, first image data is generated by accumulating phase image data IM1 through IM4 generated using a grid size KM1. Next, second image data is generated by accumulating phase image data IM1 through IM16 generated using a grid size KM2. Next, n types of phase image data generated using a grid size KMn are accumulated to generate n-th image data.

[0189] Step S10B is a step in which the imaging system divides the image data into the same number of pixels as the imaging area. The reason is that the first image data to the nth image data are each composed of a different number of image data. Therefore, the grid size used when the first image data to the nth image data were created is used to divide the image data into the number of pixels of the original imaging area, and first image data_b to nth image data_b having the same number of image data are generated.

[0190] Step S10C is a step in which the imaging system generates a pop-up image. The imaging system generates a pop-up image from which features are extracted by accumulating the first image data_b to the n-th image data_b.

[0191] Fig. 15 is an image diagram illustrating an imaging system different from that of Fig. 12. In the configuration described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Therefore, detailed explanations of STEP 2 and STEP 3 will be omitted because they are the same as STEP 2 and STEP 3 described in Fig. 12.

[0192] FIG. 15 differs from FIG. 12 in that it includes STEP 2A. STEP 2A is a step for binarizing the phase image data. As an example, the phase image data IM11 to IM14 generated in STEP 2 are converted into phase image data IN11 to IN14 by binarization processing. The other phase image data are also binarized in a similar manner.

[0193] As an example, first image data is generated by calculating phase image data IN11 through IN14 generated using grid size KM1. Next, second image data is generated by calculating phase image data IN21 through IN216 generated using grid size KM2. Next, n types of phase image data generated using grid size KMn are calculated to generate n-th image data.

[0194] It is preferable to use multiplication for this calculation. For example, if the image data of a certain region in the phase image data is "0", the result of calculation with this image data will also be "0" regardless of the value of the image data of the same region in other phase image data. This reduces the amount of calculation.

[0195] 16 is a flowchart illustrating an imaging system having binarization processing. In the configuration described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted.

[0196] The imaging system described in FIG. 16 differs from that in FIG. 13 in that it includes step S20. By binarizing the phase image data generated in step S09, the amount of calculation required to generate a pop-up image in step S10 can be reduced.

[0197] As described above, one embodiment of the present invention can provide an imaging system with a novel configuration that can handle outputs from multiple pixels included in a grid-shaped region as a single imaging signal. Another embodiment of the present invention can provide an imaging system that processes part of a calculation using a weighting factor. Another embodiment of the present invention can provide an imaging system that can handle data larger than the imaging region by having an imaging device perform padding processing. Another embodiment of the present invention can provide an imaging system that suppresses an increase in processing time for calculation using a weighting factor and padding processing. Another embodiment of the present invention can provide an imaging system that suppresses an increase in power consumption by reducing the amount of calculation through calculation using a weighting factor and padding processing.

[0198] This embodiment can be carried out by combining parts thereof as appropriate.

[0199] (Embodiment 3) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0200] <Structure example> FIG. 17A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0201] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 18A. Note that the term "layer" may be replaced with "region" in some cases.

[0202] 18A is a pn junction photodiode, and for example, a p-type semiconductor may be used for the layer 565a and an n-type semiconductor may be used for the layer 565b. Alternatively, an n-type semiconductor may be used for the layer 565a and a p-type semiconductor may be used for the layer 565b.

[0203] The pn junction photodiode can be typically formed using single crystal silicon.

[0204] 18B, the photoelectric conversion device 101 included in the layer 561 may be a stack of layers 566a, 566b, 566c, and 566d. The photoelectric conversion device 101 shown in FIG. 18B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0205] The layer 566a is preferably a low-resistance metal layer, such as aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0206] The layer 566d is preferably a conductive layer that has a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0207] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material, which is a p-type semiconductor, and the layer 566c is made of an n-type semiconductor such as gallium oxide.

[0208] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In these photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. Furthermore, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production, such as the ability to fabricate thin-film photoelectric conversion layers. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering.

[0209] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0210] The n-type semiconductor is preferably formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer and can reduce dark current.

[0211] 18C, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e. The photoelectric conversion device 101 shown in FIG. 18C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0212] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0213] For example, molybdenum oxide can be used as the hole transport layer. For example, C 60 , C 70 or derivatives thereof can be used.

[0214] The photoelectric conversion layer may be a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor.

[0215] A silicon substrate, for example, can be used as the layer 563 shown in FIG. 17A. The silicon substrate has Si transistors and the like. Using the Si transistors, in addition to pixel circuits, circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, neural networks, communication circuits, and the like can be formed. Furthermore, memory circuits such as DRAMs (Dynamic Random Access Memory), CPUs (Central Processing Units), MCUs (Micro Controller Units), and the like may also be formed. In this embodiment, the above circuits excluding the pixel circuits are referred to as functional circuits.

[0216] For example, some or all of the transistors included in the pixel circuit (pixel P) and the functional circuits (circuits 301, 302, 303, 304, 305, and the like) described in Embodiment 1 can be provided in the layer 563.

[0217] Furthermore, the layer 563 may be a laminate of multiple layers as shown in FIG. 17B. Although FIG. 17B illustrates three layers, 563a, 563b, and 563c, two layers may be used. Alternatively, the layer 563 may be a laminate of four or more layers. These layers can be laminated using, for example, a bonding process. With this configuration, the pixel circuits and functional circuits can be distributed across multiple layers and stacked on top of each other, making it possible to manufacture a compact, highly functional imaging device.

[0218] Alternatively, the pixel may have a stacked structure of layers 561, 562, and 563 as shown in FIG. 17C.

[0219] The layer 562 can include OS transistors. One or more of the functional circuits described above can be formed using OS transistors. Alternatively, one or more of the functional circuits can be formed using the Si transistors in the layer 563 and the OS transistors in the layer 562.

[0220] For example, a normally-off CPU (also referred to as an "Noff-CPU") can be realized using OS transistors and Si transistors. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are off (off) even when the gate voltage is 0 V.

[0221] The Noff-CPU can stop the power supply to circuits within the Noff-CPU that are not in operation, putting those circuits into a standby state. When the power supply is stopped and the circuit is in a standby state, no power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, it is possible to quickly return from the standby state. In this way, the Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0222] Furthermore, layer 562 may be a laminate of multiple layers as shown in FIG. 17D. While FIG. 17D illustrates two layers, layers 562a and 563b, layer 562 may be a laminate of three or more layers. These layers may be formed by stacking them on layer 563, for example. Alternatively, layer 562 may be formed by bonding a layer formed on layer 563 with a layer formed on layer 561.

[0223] The semiconductor material used for an OS transistor can be a metal oxide with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. A typical example is an oxide semiconductor containing indium, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors that prioritize reliability. Furthermore, CAC-OS exhibits high mobility, making it suitable for transistors that operate at high speed.

[0224] Because of the large energy gap of the semiconductor layer, OS transistors exhibit extremely low off-state currents of a few yA / μm (current value per 1 μm of channel width). Furthermore, unlike Si transistors, OS transistors have characteristics such as the absence of impact ionization, avalanche breakdown, and short-channel effects, making them suitable for the formation of high-voltage, highly reliable circuits. Furthermore, OS transistors are less susceptible to variations in electrical characteristics due to non-uniformity in crystallinity, which is a problem with Si transistors.

[0225] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (one or more metals selected from aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, hafnium, and the like). The In-M-Zn oxide can typically be formed by a sputtering method. Alternatively, it may be formed by an atomic layer deposition (ALD) method.

[0226] The atomic ratio of the metal elements in a sputtering target used to form an In-M-Zn-based oxide by sputtering preferably satisfies In≧M and Zn≧M. Preferred atomic ratios of the metal elements in such sputtering targets are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratios of the semiconductor layer to be formed each have a variation of ±40% of the atomic ratio of the metal elements contained in the sputtering target.

[0227] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3or less, more preferably 1 × 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 or less, more preferably 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 An oxide semiconductor having a carrier density above or equal to this can be used. Such an oxide semiconductor is called a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and stable characteristics.

[0228] Note that the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0229] If silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor that constitutes the semiconductor layer, oxygen vacancies increase, resulting in n-type conductivity. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0230] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, it may generate carriers, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0231] Furthermore, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons acting as carriers are generated, increasing the carrier density and making the semiconductor layer more likely to be n-type. As a result, transistors using oxide semiconductors that contain nitrogen tend to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0232] Furthermore, if hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons that serve as carriers. Furthermore, some of the hydrogen may bond with oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0233] A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, oxide semiconductors are sometimes evaluated using carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration."

[0234] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0235] The semiconductor layer may also have a non-single-crystal structure. Examples of the non-single-crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0236] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain any crystalline components, or an amorphous oxide film has, for example, a completely amorphous structure and does not contain any crystalline parts.

[0237] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single-crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0238] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single-crystal semiconductor layer.

[0239] CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0240] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0241] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into mosaics, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0242] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0243] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0244] The crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals are connected together with their c-axis orientation and no orientation in the ab plane.

[0245] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. CAC-OS is a material structure containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, the crystal structure is a secondary element in CAC-OS.

[0246] Note that CAC-OS does not include a stacked structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0247] In addition, GaO X3The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary between the region where the main component is the chromatic aberration and the region where the chromatic aberration is the main component may not be observed.

[0248] When one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained instead of gallium, the CAC-OS has a structure in which some regions observed to be nanoparticles containing the metal element as the main component and some regions observed to be nanoparticles containing In as the main component are randomly dispersed in a mosaic pattern.

[0249] The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the better. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0250] CAC-OS has the characteristic that no clear peaks are observed when measured using the θ / 2θ scan by the out-of-plane X-ray diffraction (XRD) method, which indicates that the ab-plane and c-axis orientations of the measured region are not observed.

[0251] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nanobeam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern indicates that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0252] For example, in the case of CAC-OS made of In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 It can be seen that the region where the main component is the crystalline silicon is unevenly distributed and mixed.

[0253] CAC-OS has a different structure from IGZO compounds, in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The structure is such that the regions are separated into a mosaic of regions each containing one of the elements as the main component and a region each containing one of the elements as the main component.

[0254] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is exhibited.X2 Zn Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud-like shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0255] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing the above as a main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0256] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation due to X2 Zn Y2 O Z2 , or InO X1 The conductivity due to the gate insulating layer and the gate insulating layer work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ) can be achieved.

[0257] Furthermore, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0258] <Laminated structure 1> Next, the layered structure of the imaging device will be described using cross-sectional views. Note that the elements such as the insulating layer and conductive layer shown below are examples, and other elements may be included. Alternatively, some of the elements shown below may be omitted. Furthermore, the layered structure shown below can be formed using a bonding process, a polishing process, or the like, as necessary.

[0259] FIG. 19 is an example of a cross-sectional view of a laminate having layers 560, 561, and a layer 563, with a bonding surface between layers 563a and 563b that constitute layer 563.

[0260] <layer 563b> The layer 563b includes a functional circuit provided on the silicon substrate 611. Here, the capacitor 202, the transistor 203, and the transistor 204 included in the circuit 303 are shown as part of the functional circuit. One electrode of the capacitor 202, one of the source or drain of the transistor 203, and the gate of the transistor 204 are electrically connected to each other.

[0261] The layer 563b includes a silicon substrate 611 and insulating layers 612, 613, 614, 615, 616, 617, and 618. The insulating layer 612 functions as a protective film. The insulating layers 613, 613, 616, and 617 function as interlayer insulating films and planarizing films. The insulating layer 615 functions as a dielectric layer of the capacitor 202. The insulating layer 618 and the conductive layer 619 function as bonding layers. The conductive layer 619 is electrically connected to one electrode of the capacitor 202.

[0262] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic or polyimide film. The dielectric layer of the capacitor may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The bonding layer will be described later.

[0263] Conductors that can be used as wiring, electrodes, and plugs for electrical connection between devices may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may also be made of multiple layers composed of different materials.

[0264] <Layer 563a> The layer 563a has elements of the pixel P. Here, the transistor 102 and the transistor 108 are shown as part of the elements of the pixel P. In the cross-sectional view shown in FIG. 19, the electrical connection between them is not shown.

[0265] The layer 563a is provided with a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638, and conductive layers 636 and 639.

[0266] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as interlayer insulating films and planarizing films. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 from the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. Alternatively, the insulating layer 638 may be formed of the same material as the insulating layer 631.

[0267] The conductive layer 639 is electrically connected to the other of the source and the drain of the transistor 108 and the conductive layer 619. The conductive layer 636 is electrically connected to the wiring 113 (see FIG. 3A).

[0268] The Si transistor shown in Fig. 19 is a fin type having a channel formation region in a silicon substrate (silicon substrates 611 and 632). A cross section in the channel width direction (a cross section taken along A1-A2 in layer 563a in Fig. 19) is shown in Fig. 20A. The Si transistor may also be a planar type, as shown in Fig. 20B.

[0269] 20C, the transistor may have a silicon thin film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 611.

[0270] <layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Fig. 19 shows a configuration in which the organic photoconductive film shown in Fig. 18C is used as the photoelectric conversion layer for the photoelectric conversion device 101. Here, the layer 567a is the cathode, and the layer 567e is the anode.

[0271] Layer 561 is provided with insulating layers 651, 652, 653, 654 and a conductive layer 655.

[0272] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101 and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. An organic insulating film or the like is preferably used as the element isolation layer.

[0273] The layer 567a, which corresponds to the cathode of the photoelectric conversion device 101, is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e, which corresponds to the anode of the photoelectric conversion device 101, is electrically connected to the conductive layer 636 included in the layer 563a via the conductive layer 655.

[0274] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0275] The light-shielding layer 671 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. The metal layer may also be stacked with a dielectric film that functions as an anti-reflection film.

[0276] A color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning colors such as red (red), green (G), blue (B), yellow (Y), cyan (C), and magenta (M) to the color filter for each pixel.

[0277] Furthermore, if a wavelength cut filter is used in the optical conversion layer 672, an imaging device that can obtain images in various wavelength regions can be obtained.

[0278] For example, if a filter that blocks light with wavelengths equal to or shorter than visible light is used in the optical conversion layer 672, it can be used as an infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or shorter than near-infrared light is used in the optical conversion layer 672, it can be used as a far-infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or longer than visible light is used in the optical conversion layer 672, it can be used as an ultraviolet imaging device.

[0279] Furthermore, if a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation, such as for use in an X-ray imaging device. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting this light with the photoelectric conversion device 101. An imaging device having this configuration may also be used for a radiation detector or the like.

[0280] Scintillators contain materials that absorb the energy of radiation such as X-rays or gamma rays and emit visible or ultraviolet light when irradiated with such radiation. For example, materials such as Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, and ZnO dispersed in resin or ceramics can be used.

[0281] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, thereby enabling efficient photoelectric conversion. The microlens array 673 is preferably formed from a resin or glass that is highly translucent to visible light.

[0282] <Laminating> Next, the bonding of the layer 563b and the layer 563a will be described.

[0283] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that they are at the same height.

[0284] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that they are at the same height.

[0285] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component. The insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0286] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. Cu, Al, W, or Au is preferred for ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 618 and 631.

[0287] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded together at the boundary between them.

[0288] The conductive layers 619 and 639 may have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0289] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Furthermore, it is possible to obtain connection between the insulating layer 618 and the insulating layer 631 with sufficient mechanical strength.

[0290] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods create bonds at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0291] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or other methods, then surfaces that have been hydrophilically treated with oxygen plasma or other methods are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0292] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0293] For example, a method can be used in which the surface is polished, cleaned, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0294] By the above-described bonding, the circuit 303 included in the layer 563b and the elements of the pixel P included in the layer 563a can be electrically connected to each other.

[0295] <Modification of laminate structure 1> FIG. 21 shows a modified example of the stacked structure shown in FIG. 19, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 563a are different, and there is also a bonding surface between the layer 561 and the layer 563a.

[0296] Layer 561 includes photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers 135, 136.

[0297] The photoelectric conversion device 101 is a pn junction photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. The photoelectric conversion device 101 is a buried photodiode, and a thin p-type region (part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a can suppress dark current and reduce noise.

[0298] The insulating layer 661 and the conductive layers 135 and 136 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer. The insulating layer 665 functions to suppress the outflow of carriers.

[0299] Grooves that separate pixels are provided in the silicon substrate, and an insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. The insulating layer 665 can prevent carriers generated in the photoelectric conversion device 101 from flowing into adjacent pixels. The insulating layer 665 also has the function of preventing stray light from entering. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0300] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. The insulating layer 665 may be, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic. The insulating layer 665 may have a multi-layer structure.

[0301] A layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 135. A layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 136. The conductive layers 135 and 136 have regions buried in an insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 135 and 136 are flattened so that they are at the same height.

[0302] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. A conductive layer 133 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 134 electrically connected to the conductive layer 636 are formed.

[0303] The insulating layer 638 and the conductive layers 133 and 134 function as bonding layers. The conductive layers 133 and 134 have regions buried in the insulating layer 638. The surfaces of the insulating layer 638 and the conductive layers 133 and 134 are flattened so that they are at the same height.

[0304] Here, the conductive layers 133, 134, 135, and 136 are the same bonding layers as the above-described conductive layers 619 and 639. The insulating layers 638 and 661 are the same bonding layers as the above-described insulating layers 618 and 631.

[0305] Therefore, by bonding the conductive layer 133 and the conductive layer 135 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to either the source or the drain of the transistor 102. Also, by bonding the conductive layer 134 and the conductive layer 136 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 113 (see FIG. 3). Also, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 and the layer 563a.

[0306] <Laminated structure 2> 22 is an example cross-sectional view of a stack having layers 560, 561, 562, and 563 but no bonding surface. A Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Here, an example is described in which components of a memory circuit are provided in the layers 562 and 563, and a driver circuit for the memory circuit is provided in the layer 563. Note that the configurations of the layers 561 and 560 are the same as those shown in FIG. 19, and therefore description thereof is omitted here.

[0307] <layer 563> The layer 563 includes functional circuits provided over the silicon substrate 611. Here, a transistor 251 included in a driver circuit of the memory circuit and transistors 252 and 253 included in the memory circuit are shown as part of the functional circuits.

[0308] <layer 562b> Layer 562b is formed over layer 563. Layer 562b includes an OS transistor, shown here as transistor 254, as part of a memory circuit.

[0309] The layer 562b is provided with insulating layers 621, 622, 623, 624, 625, 626, 628, and 629. In addition, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 113 (see FIG. 3).

[0310] The insulating layer 621 functions as a blocking layer. The insulating layers 622, 623, 625, 626, 628, and 629 function as interlayer insulating films and planarizing films. The insulating layer 624 functions as a protective film.

[0311] The blocking layer is preferably a film that has a function of preventing hydrogen diffusion. In Si devices, hydrogen is required to terminate dangling bonds. However, hydrogen near an OS transistor can generate carriers in the oxide semiconductor layer, reducing reliability. Therefore, a hydrogen blocking film is preferably provided between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0312] The blocking film may be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0313] Here, the memory circuit included in the layer 563 and the layer 562b includes a memory cell including a transistor 254, a transistor 253, and a transistor 252. One of the source and the drain of the transistor 254 is electrically connected to the gate of the transistor 253. The gate of the transistor 254 is electrically connected to the transistor 251 included in the driver circuit of the memory circuit.

[0314] The memory cell uses the gate of the transistor 253 as a data storage portion, and data is written by the transistor 254. The memory cell is read by turning on the transistor 252. The data storage portion can be extended by using an OS transistor with low off-state current as the transistor 254 connected to the data storage portion. For details, see the description of NOSRAM and the like in the following embodiments.

[0315] 23A shows details of an OS transistor. The OS transistor shown in FIG. 23A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0316] The OS transistor can have a structure including a channel formation region, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the groove.

[0317] As shown in FIG. 23B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0318] Alternatively, as shown in FIG. 23C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0319] Although the OS transistor has a back gate 535, it may not necessarily have a back gate. The back gate 535 may be electrically connected to the front gate of a transistor located opposite the back gate, as shown in the cross-sectional view of the transistor in the channel width direction in FIG. 23D. Note that FIG. 23D illustrates the cross section of the transistor taken along line B1-B2 in FIG. 23A as an example, but the same applies to transistors with other structures. Furthermore, a fixed potential different from that of the front gate may be supplied to the back gate 535.

[0320] <Layer 562a> The layer 562a is formed on the layer 562b. The layer 562a includes elements of a pixel P having OS transistors. Here, the transistors 102 and 103 are shown as part of the elements of the pixel P.

[0321] The layer 562a is provided with insulating layers 641, 642, 643, 644, 645, and 647. In addition, a conductive layer 646 is provided.

[0322] The insulating layers 641, 642, 644, 645, and 647 function as interlayer insulating films and planarizing films. The insulating layer 643 functions as a protective film.

[0323] One of the source and drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561. The conductive layer 646 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561 and the conductive layer 627 included in the layer 562b.

[0324] 22, the pixel circuit included in the layer 562a can be electrically connected to the circuit 303 included in the layer 563. In addition, the circuit 303 can be electrically connected to other functional circuits.

[0325] <Modification of laminate structure 2> FIG. 24 shows a modified example of the stacked structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and the configuration of part of the layer 562a are different, and a bonding surface is provided between the layer 561 and the layer 562a.

[0326] The photoelectric conversion device 101 included in the layer 561 is a pn junction photodiode formed on a silicon substrate, and has the same configuration as that shown in FIG.

[0327] In the layer 562a, an insulating layer 648 is formed over the insulating layer 647. Furthermore, a conductive layer 138 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 139 electrically connected to the conductive layer 646 are formed.

[0328] The insulating layer 648 and the conductive layers 138 and 139 function as bonding layers. The conductive layers 138 and 139 have regions buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 133 and 134 are flattened so that they are at the same height.

[0329] Here, the conductive layers 138 and 139 are the same bonding layer as the above-described conductive layers 619 and 639. The insulating layer 648 is the same bonding layer as the above-described insulating layers 618 and 631.

[0330] Therefore, by bonding the conductive layer 138 and the conductive layer 135 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to either the source or the drain of the transistor 102. Also, by bonding the conductive layer 139 and the conductive layer 136 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 113 (see FIG. 3). Also, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 and the layer 562a.

[0331] When stacking multiple Si devices, multiple polishing and bonding processes are required. This poses challenges such as a large number of steps, the need for specialized equipment, low yields, and high manufacturing costs. OS transistors can be formed by stacking them on a silicon substrate on which devices are already formed, eliminating the need for bonding processes.

[0332] 25A1 is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see FIG. 25A3), a cover glass 420, and an adhesive 430 for bonding the two together.

[0333] 25A2 is a perspective view of the appearance of the underside of the package. The underside of the package has a BGA (Ball Grid Array) with solder balls as bumps 440. Note that the package is not limited to a BGA, and may have an LGA (Land Grid Array) or a PGA (Pin Grid Array), etc.

[0334] 26A3 is a perspective view of the package, with the cover glass 420 and part of the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and bumps 440 are electrically connected via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0335] 25B1 is a perspective view of the top surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451 (FIG. 25B3), a lens cover 421, and a lens 435. An IC chip 490 (FIG. 25B3) having functions such as a drive circuit for the imaging device and a signal conversion circuit is also provided between the package substrate 411 and the image sensor chip 451, and the camera module is configured as a SiP (System in Package).

[0336] 25B2 is a perspective view of the appearance of the underside of the camera module. The underside and side surfaces of package substrate 411 have a QFN (quad flat no-lead package) configuration with mounting lands 441 provided. Note that this configuration is just one example, and a QFP (quad flat package) or the aforementioned BGA may also be provided.

[0337] 25B3 is a perspective view of the module, omitting a portion of lens cover 421 and lens 435. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0338] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0339] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0340] (Fourth embodiment) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable types, portable data terminals, e-book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS.

[0341] 26A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting text, can be performed by touching the display portion 982 with a finger, a stylus, or the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the mobile phone.

[0342] 26B shows a portable data terminal including a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919 and output as voice through the speaker 913. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal.

[0343] FIG. 26C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling, enabling it to capture images of the entire periphery. The imaging device and its operating method according to one embodiment of the present invention can be applied to the elements for acquiring images in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the application. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0344] 26D shows a video camera including a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. An imaging device and an operation method thereof according to one embodiment of the present invention can be applied to the video camera.

[0345] 26E shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, etc. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this digital camera.

[0346] 26F shows a wristwatch-type information terminal including a display portion 932, a housing / wristband 933, a camera 939, and the like. The display portion 932 includes a touch panel for operating the information terminal. The display portion 932 and the housing / wristband 933 are flexible and therefore easily worn on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal.

[0347] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. [Explanation of symbols]

[0348] :a11:area, a13:area, a21:area, a31:area, a33:area, a41:area, a0111:area, a111:area, a112:area, a121:area, a0122:area, a122:area, a144:area, a0211:area, a211:area, a0221: area, a0222: area, a241: area, a242: area, a243: area, a244: area, a311: area, a344: area, a411: area, a441: area, a442: area, a443: area, a444: area, a1611: area, a1612: area, a1621: area area, a1622: area, d11: image data, d33: image data, d44: image data, d0111: image data, d111: image data, d0122: image data, d144: image data, d0211: image data, d211: image data, d0222: image data, d244: image data, d311: image data, d344: image data, d411: image data, d444: image data, d1611: image data, d1622: image data, IM1: phase image data, IM2: phase image data, IM3: phase image data, IM4: phase Image data, IM11: phase image data, IM14: phase image data, IM16: phase image data, IM21: phase image data, IM216: phase image data, IN11: phase image data, IN14: phase image data, IN21: phase image data, IN216: phase image data, KM1: grid size, KM2: grid size, 100: imaging device, 101: photoelectric conversion device, 102: transistor, 102a: transistor, 103: transistor, 103a: transistor, 104: capacitance, 105: transistor , 105a: transistor, 108: transistor, 108a: transistor, 112: wiring, 113: wiring, 114: wiring, 115: wiring, 116: wiring, 117: wiring, 118: wiring, 122: wiring, 133: conductive layer, 134: conductive layer, 135: conductive layer, 136: conductive layer, 138: conductive layer, 139: conductive layer, 161: transistor, 162: transistor, 163: capacitance, 202: capacitance, 203: transistor, 204: transistor, 205: transistor, 206: transistor, 207: resistor, 211: wiring, 212: wiring, 213: wiring,215: wiring, 216: wiring, 217: wiring, 218: wiring, 219: wiring, 251: transistor, 252: transistor, 253: transistor, 254: transistor, 300: imaging area, 301: circuit, 302: circuit, 303: circuit, 303(1): circuit, 303(2): circuit, 303e: circuit, 304: circuit, 304a: circuit, 305: circuit, 313: wiring, 320: circuit, 320(1): circuit, 320(2): circuit, 320(3): circuit, 321: circuit, 322: switch, 323: switch, 330a: circuit, 330b: circuit, 331: Circuit, 332: Circuit, 332a: Switch, 332b: Switch, 332c: Switch, 333: Switch, 335: Memory cell, 340: Register, 341a: Memory, 341b: Memory, 341c: Memory, 350: Circuit, 361: Selector circuit, 362: Frame memory, 363: Differential circuit, 410: Package substrate, 411: Package substrate, 420: Cover glass, 421: Lens cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image sensor chip, 451: Image sensor chip, 460: Electrode pad pad, 461: electrode pad, 470: wire, 471: wire, 490: IC chip, 535: back gate, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 562b: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 611: silicon substrate, 612: insulating layer, 613: insulating layer, 614: insulating layer, 615: insulating layer, 61 6: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 626: insulating layer, 627: conductive layer, 628: insulating layer, 629: insulating layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 641: insulating layer, 642: insulating layer, 643: insulating layer, 644: insulating layer, 645: insulating layer, 646: conductive layer, 647: insulating layer, 648: insulating layer, 651: insulating layer,652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 672: optical conversion layer, 673: microlens array, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing Body / wristband, 939: camera, 951: support stand, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation keys, 975: lens, 976: connection unit, 977: speaker, 978: microphone, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

1. An imaging device having M×N pixels (M and N are natural numbers) arranged in a matrix, During a first period, a plurality of first regions each including m×n pixels (m is a natural number smaller than M, and n is a natural number smaller than N) are set so as not to overlap with each other among the M×N pixels, and image signals of pixels included in each of the first regions are weighted by each pixel and then added together to output the weighted data, thereby creating first phase image data; During a second period, a plurality of first regions are set so that the first regions have a different pixel combination from that during the first period, each of which is composed of M×N pixels and does not overlap with each other, and image signals of pixels included in each of the first regions are weighted by each pixel and then added together to output the weighted data, thereby generating second phase image data; generating first image data by multiplying the first phase image data by the second phase image data; During a third period, a plurality of second regions each including p×q pixels (p is a natural number smaller than M, q is a natural number smaller than N, and p is different from m or q is different from n) are set so as not to overlap with the M×N pixels, and image signals of the pixels included in each of the second regions are weighted by each pixel and then added together to output the weighted data, thereby creating third phase image data; During a fourth period, the second regions are set so that the combination of pixels is different from that during the third period and does not overlap with each other in M×N pixels, and image signals of the pixels included in each of the second regions are weighted by each pixel and then added together to output the weighted data, thereby creating fourth phase image data; an imaging device that generates second image data by multiplying the third phase image data and the fourth phase image data;

2. In claim 1, Dividing each element of the first image data into m×n pieces to create third image data; Dividing each element of the second image data into p×q pieces to create fourth image data; The imaging device creates a pop-up image by multiplying the third image data and the fourth image data.

3. In claim 1 or claim 2, the pixel has a transistor; The imaging device, wherein the transistor has a semiconductor layer containing a metal oxide.

4. In claim 3, The imaging device, wherein the metal oxide comprises indium.

Images