Semiconductor element and semiconductor device

Abstract

Provided are a semiconductor element and a semiconductor device in which forward characteristics are improved and which are useful in particular in power devices. The semiconductor element is a laminated structure provided with a semiconductor layer containing a crystalline oxide semiconductor (e.g., α-Ga2O3, etc.) as a main component, an electrode layer laminated on the semiconductor layer, and an electroconductive substrate laminated on the electrode layer directly or with another layer interposed therebetween, the electroconductive substrate containing at least a first metal selected from metals in group 11 of the Periodic Table and a second metal having a linear thermal expansion coefficient different from that of the first metal. The semiconductor device is provided with said semiconductor element.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor element useful as a power device or the like. [Background technology]

[0002] As a next-generation switching element that can achieve high breakdown voltage, low loss, and high heat resistance, semiconductor devices using gallium oxide (Ga2O3), which has a large band gap, are attracting attention, and are expected to be applied to power semiconductor devices such as inverters. Furthermore, due to its wide band gap, it is also expected to be applied to light-emitting and receiving devices such as LEDs and sensors. According to Patent Document 1, the band gap of gallium oxide can be controlled by forming a mixed crystal with indium and aluminum, either individually or in combination, and it constitutes an extremely attractive material system as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors are X Al Y Ga Z O3 (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5), and can be viewed as the same material family containing gallium oxide.

[0003] As base substrates to be used for realizing semiconductor devices using these InAlGaO-based semiconductors, β-gallium oxide substrates and sapphire substrates have been considered. According to Patent Document 2, when a β-gallium oxide substrate is used, homoepitaxial growth of gallium oxide is possible, enabling high-quality aluminum gallium oxide thin films. However, the available substrate sizes are limited, making it difficult to increase the diameter compared to materials that are already in mass production, such as silicon and sapphire. According to Patent Documents 3 and 4, when a sapphire substrate is used, Al having a corundum structure X Ga YWhile it is possible to improve the quality of O3 (0≦X≦2, 0≦Y≦2, X+Y=2) thin films, it is difficult to improve the quality of β-gallia structure films. Another problem is that sapphire is an insulator, so current cannot be passed through the underlying material. In this case, electrodes cannot be formed on the underlying material, which limits the output current per unit area of ​​the semiconductor device. When increasing the diameter to 6 inches or 8 inches, there are concerns about stable procurement and rising procurement costs, as industrial applications of these large-diameter sapphires have not progressed very far.

[0004] Furthermore, the low thermal conductivity of gallium oxide and sapphire poses a problem in terms of heat generation and high-temperature operation associated with the increased current flowing through semiconductor devices. Furthermore, the characteristics of the underlying material also pose challenges in terms of electrical characteristics for achieving low-loss semiconductor devices. For example, to achieve high-voltage, low-loss semiconductors, it is necessary to reduce losses not only in the channel layer but also in other layers. For example, low loss is required in the contact regions that constitute the semiconductor device. Furthermore, in vertical semiconductor devices, low loss is required in the underlying material and in the layer between the underlying material and the channel layer.

[0005] Patent Document 5 describes a laminated semiconductor structure in which a support layer containing, as a main component, a conductive material with a thermal expansion coefficient different from that of the semiconductor layer is laminated on a semiconductor layer using an InAlGaO-based semiconductor via a conductive adhesive layer. However, the semiconductor structure described in Patent Document 5 is not practical in terms of forward characteristics, etc., and is also not fully satisfactory in terms of warpage, which is a problem specific to InAlGaO-based semiconductors. Therefore, a semiconductor structure with excellent heat dissipation and electrical characteristics that can fully exhibit the semiconducting properties of InAlGaO-based semiconductors has been desired.

[0006] Patent Document 1 and Patent Document 5 relate to patent applications filed by the present applicant. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2014 / 050793 [Patent Document 2] International Publication No. 2013 / 035842 [Patent Document 3] International Publication No. 2013 / 035844 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-58637 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-081946 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a semiconductor element having excellent electrical characteristics such as forward characteristics. [Means for solving the problem]

[0009] As a result of intensive research to achieve the above-mentioned object, the present inventors have found that, in the manufacturing (pre-process) of a semiconductor device using a semiconductor layer containing a crystalline oxide semiconductor as a main component, using a conductive substrate containing at least a first metal selected from the metals of Group 11 of the periodic table and a second metal having a linear thermal expansion coefficient different from that of the first metal, not only is adhesion between the electrodes and adhesive layers of the resulting semiconductor device improved, but warping is also suppressed, resulting in better electrical properties such as forward characteristics of the resulting semiconductor device. As a result of further research, the present inventors have found that a semiconductor device comprising a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer stacked on the semiconductor layer, and a conductive substrate stacked on the electrode layer directly or via another layer, wherein the conductive substrate contains at least a first metal selected from the metals of Group 11 of the periodic table and a second metal having a linear thermal expansion coefficient different from that of the first metal, has excellent electrical properties such as forward characteristics, and can solve the above-mentioned conventional problems at once. Furthermore, after obtaining the above findings, the present inventors conducted further studies and have now completed the present invention.

[0010] That is, the present invention relates to the following inventions. [1] A semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer stacked on the semiconductor layer, and a conductive substrate stacked on the electrode layer directly or via another layer, wherein the conductive substrate contains at least a first metal selected from the metals of Group 11 of the periodic table and a second metal having a linear thermal expansion coefficient different from that of the first metal. [2] The semiconductor element according to [1], wherein the first metal is copper. [3] The semiconductor element according to [1] or [2], wherein the second metal includes a metal of Group 6 of the periodic table. [4] The semiconductor device according to [3] above, wherein the metal of Group 6 of the periodic table is molybdenum. [5] The semiconductor element according to any one of [1] to [4], wherein the conductive substrate has a laminated structure in which at least one layer containing the first metal and at least one layer containing the second metal are laminated. [6] The semiconductor element according to [5], wherein the uppermost layer and / or the lowermost layer of the laminated structure contains the first metal. [7] The semiconductor device according to any one of [1] to [6], wherein the crystalline oxide semiconductor contains at least one metal selected from aluminum, indium, and gallium. [8] The semiconductor device according to any one of [1] to [7], wherein the crystalline oxide semiconductor contains at least gallium. [9] The semiconductor device according to any one of [1] to [8], further comprising another electrode layer on a surface of the semiconductor layer opposite to the surface on which the electrode layer is stacked.

[10] The semiconductor element according to any one of [1] to [9] above, which is a power device.

[11] A semiconductor device constructed by bonding at least a semiconductor element to a lead frame, a circuit board, or a heat dissipation substrate with a bonding member, wherein the semiconductor element is a semiconductor element according to any one of [1] to

[10] .

[12] A power conversion device using the semiconductor device according to

[11] .

[13] A control system using the semiconductor device according to

[11] . [Effects of the Invention]

[0011] The semiconductor device of the present invention has excellent electrical characteristics such as forward characteristics. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing an example of a laminate used in an embodiment of the present invention. [Figure 2] FIG. 1 is a diagram showing an example of a laminate used in an embodiment of the present invention. [Figure 3] 1 illustrates an example of a semiconductor structure used in an embodiment of the present invention. [Figure 4] 1 is a diagram schematically illustrating a preferred embodiment of a Schottky barrier diode (SBD) of the present invention. [Figure 5] 1 is a diagram schematically illustrating a preferred embodiment of a Schottky barrier diode (SBD) of the present invention. [Figure 6] FIG. 1 is a diagram schematically illustrating a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) of the present invention. [Figure 7] 5 is a schematic diagram for explaining a part of the manufacturing process of the metal oxide semiconductor field effect transistor (MOSFET) of FIG. 4. [Figure 8] FIG. 1 is a diagram schematically illustrating a preferred example of a static induction transistor (SIT) of the present invention. [Figure 9] 1 is a diagram schematically illustrating a preferred example of a Schottky barrier diode (SBD) according to the present invention. [Figure 10] FIG. 1 is a diagram schematically illustrating a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) of the present invention. [Figure 11] 1 is a diagram schematically illustrating a preferred example of a junction field effect transistor (JFET) of the present invention. [Figure 12] FIG. 1 is a diagram showing the configuration of a mist CVD apparatus used in an example of the present invention. [Figure 13] 1 is a diagram showing the results of IV measurement in an example, where the vertical axis represents current (A) and the horizontal axis represents voltage (V). [Figure 14] 1 is a diagram showing the results of IV measurement in a comparative example, where the vertical axis represents current (A) and the horizontal axis represents voltage (V). [Figure 15] 1A and 1B are diagrams schematically illustrating a preferred example of a semiconductor device. [Figure 16] 1 is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; [Figure 17] 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; [Figure 18] 1 is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; [Figure 19] 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; [Figure 20] FIG. 10 is a diagram showing a simulation result of thermal resistance in an embodiment of the present invention. [Figure 21] FIG. 10 is a diagram showing a simulation result of thermal resistance in an embodiment of the present invention. [Figure 22] FIG. 10 is a diagram showing a simulation result of thermal resistance in an embodiment of the present invention. [Figure 23] FIG. 1 is a diagram showing a preferred embodiment of a conductive substrate (Cu—Mo laminated substrate) in an embodiment of the present invention. [Figure 24] FIG. 10 is a diagram showing the results of warpage measurement in an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] The semiconductor element of the present invention is a semiconductor element comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer stacked on the semiconductor layer, and a conductive substrate stacked on the electrode layer directly or via another layer, characterized in that the conductive substrate contains at least a first metal selected from the metals of Group 11 of the periodic table and a second metal having a linear thermal expansion coefficient different from that of the first metal.

[0014] In an embodiment of the present invention, the semiconductor device can be suitably manufactured by a manufacturing method including, for example, (1) laminating the semiconductor layer on a base substrate directly or via another layer, (2) forming an electrode layer on the semiconductor layer, and (3) laminating the conductive substrate on the electrode layer, optionally via a conductive adhesive layer, and then removing the base substrate by known means. The main steps (1) to (3) of manufacturing the semiconductor device are described in more detail below with reference to the drawings.

[0015] In step (1), the semiconductor layer is stacked on a base substrate directly or via another layer. Step (1) can produce, for example, a stack as shown in FIG. 1. The stack shown in FIG. 1 has a crystalline semiconductor 101 stacked on a base substrate 108. In the present invention, the crystalline semiconductor film 101 obtained in step (1) can be used as the semiconductor layer (hereinafter also referred to as "semiconductor film"). Step (1) will be described below.

[0016] (Base substrate) The base substrate is not particularly limited as long as it is plate-shaped and serves as a support for the semiconductor film. It may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate. However, the base substrate is preferably an insulating substrate, and is also preferably a substrate having a metal film on its surface. Examples of the base substrate include a base substrate containing as its main component a substrate material having a corundum structure, a base substrate containing as its main component a substrate material having a β-gallia structure, and a base substrate containing as its main component a substrate material having a hexagonal crystal structure. Here, "main component" means that the substrate material having the specific crystal structure preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more, in atomic ratio, of the total components of the substrate material; it may be 100%.

[0017] The substrate material is not particularly limited, and may be any known material, as long as it does not impede the objectives of the present invention. Suitable examples of substrate materials having the corundum structure include α-Al2O3 (sapphire substrate) and α-Ga2O3, with more preferred examples including a-plane sapphire substrates, m-plane sapphire substrates, r-plane sapphire substrates, c-plane sapphire substrates, and α-type gallium oxide substrates (a-plane, m-plane, or r-plane). Examples of base substrates primarily composed of substrate materials having a β-gallium structure include β-Ga2O3 substrates and mixed crystal substrates containing Ga2O3 and Al2O3, with Al2O3 being greater than 0 wt% and less than 60 wt%. Examples of base substrates primarily composed of substrate materials having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates.

[0018] The semiconductor layer is not particularly limited as long as it contains a crystalline oxide semiconductor as a main component. The crystal structure of the crystalline oxide semiconductor is also not particularly limited as long as it does not impede the object of the present invention. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallia structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), a cubic structure, and a tetragonal structure. In an embodiment of the present invention, the crystalline oxide semiconductor preferably has a corundum structure, a β-gallia structure, or a hexagonal structure (e.g., an ε-type structure), and more preferably has a corundum structure. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In an embodiment of the present invention, the crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium, and gallium, more preferably contains at least gallium, and is most preferably α-Ga2O3 or a mixed crystal thereof. The term "main component" means that the crystalline oxide semiconductor preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the semiconductor layer, in atomic ratio, and may even be 100%. The thickness of the semiconductor layer is not particularly limited, and may be 1 μm or less or 1 μm or more, but in an embodiment of the present invention, it is preferably 1 μm or more. The surface area of ​​the semiconductor layer is not particularly limited, and may be 1 mm or less. 2 May be more than 1 mm 2 May be less than 10mm 2 ~300cm 2 Preferably, 100 mm 2 ~100cm 2It is more preferable that the semiconductor layer is a multilayer film including at least a first semiconductor layer and a second semiconductor layer. In the case where a Schottky electrode is provided on the first semiconductor layer, the semiconductor layer is a multilayer film in which the carrier density of the first semiconductor layer is lower than the carrier density of the second semiconductor layer. In this case, the second semiconductor layer usually contains a dopant, and the carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

[0019] The semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known one. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, and p-type dopants such as magnesium, calcium, or zinc. In an embodiment of the present invention, the n-type dopant is preferably Sn, Ge, or Si. The content of the dopant in the composition of the semiconductor layer is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the dopant concentration may be, for example, about 1×10 17 / cm 3 Furthermore, according to the present invention, the dopant may be present in a concentration as low as about 1×10 20 / cm 3 In an embodiment of the present invention, the concentration may be 1×10 17 / cm 3 It is preferable that the carrier concentration be equal to or higher than this.

[0020] The semiconductor layer may be formed by a known method. Examples of methods for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulsed growth, and ALD. In an embodiment of the present invention, the semiconductor layer is preferably formed by mist CVD or mist epitaxy. In the mist CVD or mist epitaxy method, a mist CVD apparatus, such as that shown in FIG. 12, is used to atomize a raw material solution (atomization step), suspend the droplets, and transport the atomized droplets to a substrate with a carrier gas (transport step). The atomized droplets are then thermally reacted in a film formation chamber to deposit a semiconductor film containing a crystalline oxide semiconductor as a main component on the substrate (film formation step), thereby forming the semiconductor layer.

[0021] (Atomization process) The atomization step atomizes the raw solution. The atomization means for the raw solution is not particularly limited as long as it can atomize the raw solution, and any known means may be used. However, in an embodiment of the present invention, an atomization means using ultrasonic waves is preferred. The atomized droplets obtained using ultrasonic waves have an initial velocity of zero and are suspended in the air, which is preferable. For example, rather than being sprayed like a spray, they are mist that floats in space and can be transported as a gas, which is highly suitable because they are not damaged by collision energy. The droplet size is not particularly limited and may be droplets of about several millimeters, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0022] (Raw material solution) The raw material solution is not particularly limited as long as it can be atomized or formed into droplets and contains a raw material capable of forming a semiconductor film, and may be an inorganic material or an organic material. In an embodiment of the present invention, the raw material is preferably a metal or a metal compound, and more preferably contains one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.

[0023] In an embodiment of the present invention, the raw material solution can be preferably prepared by dissolving or dispersing the metal in the form of a complex or salt in an organic solvent or water. Examples of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of the salt include organic metal salts (e.g., metal acetates, metal oxalates, and metal citrates), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, and metal iodides).

[0024] It is also preferable to mix additives such as hydrohalic acid and oxidizing agents into the raw material solution. Examples of hydrohalic acids include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among these, hydrobromic acid and hydroiodic acid are preferred because they can more efficiently suppress the generation of abnormal grains. Examples of the oxidizing agent include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

[0025] The raw material solution may contain a dopant. Adding a dopant to the raw material solution allows for better doping. The dopant is not particularly limited as long as it does not impair the objectives of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, and p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The content of the dopant is appropriately determined using a calibration curve showing the relationship between the desired carrier density and the dopant concentration in the raw material.

[0026] The solvent for the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In an embodiment of the present invention, the solvent preferably contains water, and more preferably is water or a mixed solvent of water and alcohol.

[0027] (Transportation process) In the transport step, the atomized droplets are transported into the film-forming chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not impede the objectives of the present invention. Suitable examples include oxygen, ozone, inert gases such as nitrogen and argon, and reducing gases such as hydrogen gas and forming gas. The carrier gas may be one type, or two or more types. A dilution gas with a reduced flow rate (e.g., a 10-fold dilution gas) may also be used as a second carrier gas. The number of carrier gas supply locations may be one or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, more preferably 0.1 to 1 L / min.

[0028] (Film forming process) In the film-forming process, the atomized droplets are thermally reacted in a film-forming chamber to form the semiconductor film on the substrate. The thermal reaction is not particularly limited as long as it heats the atomized droplets to react, and the reaction conditions are not particularly limited as long as they do not impede the objectives of the present invention. In this process, the thermal reaction is typically carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high (e.g., 1000°C or lower), more preferably 650°C or lower, and most preferably 300°C to 650°C. The thermal reaction may be carried out under vacuum, a non-oxygen atmosphere (e.g., an inert gas atmosphere), a reducing gas atmosphere, or an oxygen atmosphere, as long as it does not impede the objectives of the present invention. However, it is preferably carried out under an inert gas atmosphere or an oxygen atmosphere. The reaction may be carried out under atmospheric pressure, elevated pressure, or reduced pressure, but in this embodiment of the present invention, atmospheric pressure is preferred. The film thickness can be set by adjusting the film-forming time.

[0029] In an embodiment of the present invention, an annealing treatment may be performed after the film formation step. The annealing temperature is not particularly limited as long as it does not impede the object of the present invention, and is usually 300°C to 650°C, and preferably 350°C to 550°C. The annealing time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. The annealing may be performed in any atmosphere as long as it does not impede the object of the present invention. It may be an oxygen-free atmosphere or an oxygen atmosphere. Examples of the oxygen-free atmosphere include an inert gas atmosphere (e.g., a nitrogen atmosphere) or a reducing gas atmosphere. In an embodiment of the present invention, an inert gas atmosphere is preferred, and a nitrogen atmosphere is more preferred.

[0030] In an embodiment of the present invention, the semiconductor film may be provided directly on the base substrate, or may be provided via another layer such as a stress relaxation layer (e.g., a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. The means for forming each layer is not particularly limited and may be any known means, but in an embodiment of the present invention, a mist CVD method is preferred.

[0031] In step (2), an electrode layer 105b is formed on the semiconductor layer 101. Step (2) can provide a stack as shown in Fig. 2. The stack in Fig. 2 is composed of a base substrate 108, a semiconductor layer 101, and an electrode layer 105b.

[0032] The electrode layer is not particularly limited as long as it is conductive and does not impede the object of the present invention. The constituent material of the electrode layer may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the material of the electrode is preferably a metal. Suitable examples of the metal include at least one metal selected from Groups 4 to 10 of the periodic table. Examples of metals in Group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals in Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals in Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). In an embodiment of the present invention, the electrode layer preferably contains at least one metal selected from Groups 4 and 9 of the periodic table, and more preferably contains a metal in Group 9 of the periodic table. The thickness of the electrode layer is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. In an embodiment of the present invention, the electrode layer may be composed of two or more layers having different compositions.

[0033] The means for forming the electrode layer is not particularly limited and may be a known means. Specific examples of the means for forming the electrode layer or the other electrode layer include a dry method and a wet method. Examples of dry methods include sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating.

[0034] In step (3), the conductive substrate is laminated on the electrode layer, optionally with a conductive adhesive layer interposed therebetween, and then the base substrate is removed using known means. Step (3) can produce a laminate such as that shown in FIG. 3. The laminate shown in FIG. 3 has an electrode layer 105b bonded to a conductive substrate 107 via a conductive adhesive layer 106, and a semiconductor layer 101 laminated on the electrode layer 105b. Methods for removing the base substrate include, for example, a method of removing by applying mechanical impact, a method of removing by applying heat and utilizing thermal stress, a method of removing by applying vibrations such as ultrasonic waves, a method of removing by etching, a method of removing by grinding, a method of removing by heat treatment after ion implantation such as the Smart Cut method, a method of removing by laser lift-off, and a combination of these methods.

[0035] The conductive adhesive layer is not particularly limited as long as it can bond the electrode layer and the conductive substrate. Examples of materials for the conductive adhesive layer include metals containing at least one selected from Al, Au, Pt, Ag, Ti, Ni, Bi, Cu, Ga, In, Pb, Sn, and Zn, as well as oxides of these metals and eutectic materials (e.g., Au-Sn). In an embodiment of the present invention, the conductive adhesive layer preferably has a porous structure. Furthermore, when the conductive adhesive layer has a porous structure, the conductive adhesive layer preferably contains metal particles, more preferably metal particles containing at least one metal selected from Au, Pt, Ag, Ti, Ni, Bi, Cu, Ga, In, Pb, Sn, and Zn, and most preferably metal particles containing a noble metal. Examples of the noble metal include at least one metal selected from Au, Ag, Pt, Pd, Rh, Ir, Ru, and Os. In an embodiment of the present invention, the noble metal is preferably Ag. In an embodiment of the present invention, the conductive adhesive layer preferably contains a metal particle sintered body, and more preferably a silver particle sintered body. By using such a preferred conductive adhesive layer, the adhesion between the electrode layer and the conductive substrate can be improved without impairing the electrical characteristics of the semiconductor element. The conductive adhesive layer may be a single layer or a multilayer. The thickness of the conductive adhesive layer is not particularly limited as long as it does not impair the objectives of the present invention, but is preferably 10 nm to 200 μm, more preferably 30 nm to 50 μm. The conductive adhesive layer is usually amorphous, but may contain a secondary component such as a crystal. The means for forming the conductive adhesive layer is not particularly limited and may be a known coating method.

[0036] The conductive substrate is not particularly limited as long as it is conductive, can support the semiconductor layer, and contains at least a first metal selected from Group 11 metals of the periodic table, and a second metal having a linear thermal expansion coefficient different from that of the first metal. Examples of Group 11 metals of the periodic table include copper (Cu), silver (Ag), and gold (Au). In an embodiment of the present invention, the first metal is preferably copper (Cu). The second metal is not particularly limited as long as it has a linear thermal expansion coefficient different from that of the first metal. Note that the "linear thermal expansion coefficient" is measured according to JIS R 3102 (1995). In an embodiment of the present invention, the second metal is preferably the same metal as the first metal but has a different linear thermal expansion coefficient (for example, when the layer containing the first metal is a normal copper plating layer and the layer containing the second metal is a low linear expansion copper plating layer). In addition, in the present invention, the second metal is preferably a Group 6 metal of the periodic table. Examples of Group 6 metals in the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). In an embodiment of the present invention, the Group 6 metal in the periodic table is preferably molybdenum (Mo). In an embodiment of the present invention, it is preferable that the second metal contains a Group 6 metal in the periodic table, since this can further improve forward characteristics while suppressing warpage of the semiconductor device. In an embodiment of the present invention, when the conductive substrate contains molybdenum and copper, it is also preferable to use a Cu-Mo composite substrate (hereinafter simply referred to as a "Cu-Mo composite substrate") obtained by an impregnation method in which a molybdenum powder compact is impregnated with copper. In an embodiment of the present invention, the conductive substrate may have a metal film on its surface. Examples of the metals constituting the metal film include one or more metals selected from gallium, iron, indium, aluminum, vanadium, titanium, chromium, rhodium, nickel, cobalt, zinc, magnesium, calcium, silicon, yttrium, strontium, and barium.

[0037] In an embodiment of the present invention, the conductive substrate preferably has a laminated structure in which at least one layer containing the first metal and at least one layer containing the second metal are stacked, and more preferably has a laminated structure in which at least one layer containing molybdenum and at least one layer containing copper are alternately stacked. In this case, the thickness of each layer is preferably 5 μm or more, more preferably 10 μm or more. By configuring the conductive substrate in this preferred manner, the forward characteristics of the semiconductor element can be improved while the thermal resistance of the semiconductor element can be further reduced. In an embodiment of the present invention, when the conductive substrate has the laminated structure, it is preferable that the top and / or bottom layers in the laminated structure contain the first metal, as this can further improve the heat dissipation and mountability of the semiconductor element, and more preferably that the top and bottom layers contain the first metal. Furthermore, when the top and / or bottom layer of the laminated structure contains a first metal, the electrode layer can be bonded to the conductive substrate without using a conductive adhesive layer, thereby more effectively reducing warpage and thermal resistance of the semiconductor element. For example, by diffusion bonding a copper-containing layer located on the outermost surface of the electrode layer facing the conductive substrate with a copper-containing layer located on the outermost surface of the laminated structure of the conductive substrate facing the electrode layer, the electrode layer and the conductive substrate can be bonded industrially advantageously without using a conductive adhesive layer. The thickness of the conductive substrate is not particularly limited, but is preferably 200 μm or less, since this provides superior heat dissipation without impairing the electrical characteristics of the semiconductor element, and is more preferably 100 μm or less. The area of ​​the conductive substrate is also not particularly limited, but in this embodiment of the present invention, it is preferably approximately the same as the area of ​​the semiconductor layer. Note that "substantially the same" includes, for example, a case where the area of ​​the conductive substrate and the area of ​​the semiconductor layer are the same, and also includes a case where the ratio of the area of ​​the conductive substrate to the area of ​​the semiconductor layer is within a range of 0.9 to 1.4.

[0038] In an embodiment of the present invention, after step (3), the crystals of the crystalline semiconductor film may be regrown, or a different semiconductor layer, another electrode layer, etc. may be provided on the crystalline semiconductor film.

[0039] In an embodiment of the present invention, it is preferable that another electrode layer be further provided on the surface of the semiconductor layer opposite to the surface on which the electrode layer is laminated. Thus, by forming a stacked structure in which the conductive substrate, the conductive adhesive layer, the electrode layer, the semiconductor layer, and the other electrode layer are laminated in this order, the semiconductor element can be a vertical device in which current flows in the thickness direction of the semiconductor layer, and the forward characteristics of the semiconductor element can be improved. The other electrode layer is not particularly limited as long as it is conductive and does not impede the object of the present invention. The constituent material of the other electrode layer may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, it is preferable that the material of the other electrode is a metal. Suitable examples of the metal include at least one metal selected from Groups 8 to 13 of the periodic table. Examples of metals in Groups 8 to 10 of the periodic table include the metals exemplified as metals in Groups 8 to 10 of the periodic table in the description of the electrode layer. Examples of metals in Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). Examples of metals in Group 12 of the periodic table include zinc (Zn) and cadmium (Cd). Examples of metals in Group 13 of the periodic table include aluminum (Al), gallium (Ga), and indium (In). In an embodiment of the present invention, the other electrode layer preferably contains at least one metal selected from metals in Groups 11 and 13 of the periodic table, and more preferably contains at least one metal selected from silver, copper, gold, and aluminum. The thickness of the other electrode layer is not particularly limited, but is preferably 1 nm to 500 μm, more preferably 10 nm to 100 μm, and most preferably 0.5 μm to 10 μm.

[0040] The means for forming the other electrode layer is not particularly limited and may be a known means. Specific examples of the means for forming the electrode layer or the other electrode layer include a dry method and a wet method. Examples of dry methods include sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating.

[0041] The semiconductor element of the present invention is useful for various semiconductor devices, particularly power devices. Semiconductor elements can be classified into horizontal devices (horizontal devices) in which an electrode is formed on one side of the semiconductor layer and current flows perpendicular to the thickness direction of the semiconductor layer, and vertical devices (vertical devices) in which electrodes are formed on both the front and back sides of the semiconductor layer and current flows in the thickness direction of the semiconductor layer. In embodiments of the present invention, the semiconductor element can be suitably used for both horizontal and vertical devices, but is preferably used for vertical devices. Examples of the semiconductor element include a Schottky barrier diode (SBD), a metal semiconductor field-effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field-effect transistor (MOSFET), a static induction transistor (SIT), a junction field-effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light-emitting diode. In embodiments of the present invention, the semiconductor element is preferably an SBD, a MOSFET, a SIT, a JFET, or an IGBT, more preferably an SBD, a MOSFET, or a SIT, and most preferably an SBD.

[0042] Preferred examples of the semiconductor element will be described below with reference to the drawings, but the present invention is not limited to these embodiments. The semiconductor elements exemplified below may further include other layers (e.g., an insulating layer, a semi-insulating layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers) or may omit the buffer layer as appropriate, as long as the object of the present invention is not impaired.

[0043] (SBD) Fig. 4 shows an example of a Schottky barrier diode (SBD) according to the present invention. The SBD in Fig. 4 includes an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a conductive adhesive layer 106, a conductive substrate 107, a Schottky electrode 105a, and an ohmic electrode 105b.

[0044] The materials for the Schottky electrode and the ohmic electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0045] The Schottky electrode and the ohmic electrode can be formed by known means such as vacuum deposition or sputtering. More specifically, for example, when forming the Schottky electrode, a layer made of Mo and a layer made of Al are stacked, and the layer made of Mo and the layer made of Al are patterned using a photolithography technique.

[0046] In one embodiment of the present invention, the conductive substrate 107 contains at least a first metal selected from Group 11 metals of the periodic table and a second metal having a different linear thermal expansion coefficient from the first metal. In another embodiment of the present invention, the conductive substrate 107 preferably contains copper and a Group 6 metal, more preferably copper and molybdenum, and even more preferably a conductive substrate having a laminated structure in which at least one molybdenum-containing layer and at least one copper-containing layer are stacked. Using a conductive substrate with such a preferred configuration can improve the forward characteristics of the semiconductor device while further reducing the thermal resistance of the entire semiconductor device. Figure 23 shows a preferred embodiment of the conductive substrate. FIG. 23 shows a conductive substrate (hereinafter also referred to as a "Cu-Mo laminated substrate") having a laminated structure in which at least one layer containing molybdenum and one layer containing copper are stacked. The first metal layer 107a, the third metal layer 107c, and the fifth metal layer 107e are made of copper, and the second metal layer 107b and the fourth metal layer 107d are made of molybdenum. A simulation of the thermal resistance of the SBD structure shown in FIG. 4 was performed using a Si substrate, a Cu-Mo composite substrate (with a Mo content of 70% by mass and a Cu content of 30% by mass), and the Cu-Mo laminated substrate shown in FIG. 23 as the conductive substrate. The thickness of each conductive substrate was 100 μm. The results for the Si substrate are shown in FIG. 20, the Cu-Mo composite substrate (with a Mo content of 70% by mass and a Cu content of 30% by mass) is shown in FIG. 21, and the Cu-Mo laminated substrate is shown in FIG. 22. The results of this simulation showed that when a Cu-Mo composite substrate or Cu-Mo laminated substrate is used as the conductive substrate, the thermal resistance of the semiconductor device is reduced compared to when a Si substrate is used. Furthermore, it was found that the thermal resistance reduction effect is four times or more when a Cu-Mo laminated substrate is used compared to when a Cu-Mo composite substrate is used.These results show that the thermal resistance of a semiconductor element using an oxide semiconductor (e.g., gallium oxide) can be further improved by using a substrate having at least one layer containing a metal of Group 11 of the periodic table and at least one layer containing molybdenum stacked thereon as a conductive substrate.

[0047] Furthermore, when the Cu-Mo laminate substrate shown in FIG. 23 was used as the conductive substrate, the conductive elements were fabricated with molybdenum contents of 9%, 24%, and 30% by weight in the conductive substrate, and the warpage of the semiconductor elements was measured for each. The results are shown in FIG. 24. As is clear from FIG. 24, adjusting the molybdenum content in the conductive substrate can reduce the warpage of the entire semiconductor element. The molybdenum content can be appropriately adjusted by adjusting the thickness of the semiconductor layer in the semiconductor element and the thickness of the layer containing a metal from Group 11 of the periodic table. In this way, by using a conductive substrate containing a first metal selected from metals from Group 11 of the periodic table and a second metal having a linear thermal expansion coefficient different from that of the first metal, warpage of the semiconductor element can be effectively reduced. Furthermore, by using a laminate substrate such as that shown in FIG. 23 and adjusting the thickness and material of each layer, warpage of the semiconductor element can be more effectively reduced.

[0048] Fig. 5 shows an example of a Schottky barrier diode (SBD) according to the present invention. The SBD in Fig. 5 includes an insulator layer 104 in addition to the configuration of the SBD in Fig. 4. More specifically, the SBD includes an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a conductive adhesive layer 106, a conductive substrate 107, a Schottky electrode 105a, an ohmic electrode 105b, and an insulator layer 104.

[0049] Examples of materials for the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO, AlN, HfO, SiN, SiON, AlO, MgO, GdO, SiO, and SiN. In embodiments of the present invention, however, materials with a corundum structure are preferred. Using an insulator with a corundum structure for the insulator layer allows for favorable semiconductor properties at the interface. The insulator layer 104 is disposed between the n-type semiconductor layer 101 and the Schottky electrode 105a. The insulator layer can be formed by known methods such as sputtering, vacuum deposition, or CVD.

[0050] The formation and materials of the Schottky electrode and the ohmic electrode are the same as those in the case of the SBD of FIG. 4 above. Known techniques such as sputtering, vacuum deposition, pressure bonding, and CVD can be used to form electrodes made of, for example, metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; or mixtures of these.

[0051] The SBD of FIG. 5 has better insulation characteristics and higher current controllability than the SBD of FIG.

[0052] (MOSFET) An example of a semiconductor element of the present invention that is a MOSFET is shown in Fig. 6. The MOSFET in Fig. 6 is a trench MOSFET that includes an n-type semiconductor layer 131a, n+ type semiconductor layers 131b and 131c, a conductive adhesive layer 136, a conductive substrate 137, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c.

[0053] A conductive adhesive layer 136 having a thickness of, for example, 50 nm to 50 μm is formed on a conductive substrate 137. A drain electrode 135c is formed on the conductive adhesive layer 136. An n+ type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135c, and an n- type semiconductor layer 131a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 131b. An n+ type semiconductor layer 131c is formed on the n- type semiconductor layer 131a, and a source electrode 135b is formed on the n+ type semiconductor layer 131c.

[0054] Furthermore, a plurality of trenches are formed in the n-type semiconductor layer 131a and the n+ type semiconductor layer 131c, each of which penetrates the n+ type semiconductor layer 131c and reaches partway through the n- type semiconductor layer 131a. A gate electrode 135a is embedded in the trench with a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm interposed therebetween.

[0055] 6, when a voltage is applied between the source electrode 135b and the drain electrode 135c and a positive voltage is applied to the gate electrode 135a with respect to the source electrode 135b, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, electrons are injected into the n-type semiconductor layer, and the MOSFET is turned on. When the voltage of the gate electrode is set to 0V, no channel layer is formed, and the n-type semiconductor layer 131a is filled with a depletion layer, resulting in the MOSFET being turned off.

[0056] 7 shows a part of the manufacturing process of the MOSFET of FIG. 6. For example, using a stacked structure as shown in FIG. 7(a), an etching mask is provided in predetermined regions of the n-type semiconductor layer 131a and the n+-type semiconductor layer 131c. Using the etching mask as a mask, anisotropic etching is performed by reactive ion etching or the like to form a trench groove with a depth that reaches from the surface of the n+-type semiconductor layer 131c to partway through the n-type semiconductor layer 131a, as shown in FIG. 7(b). Next, as shown in FIG. 7(c), a gate insulating film 134 with a thickness of, for example, 50 nm to 1 μm is formed on the side and bottom surfaces of the trench groove by a known method such as thermal oxidation, vacuum deposition, sputtering, or CVD. Then, a gate electrode material such as polysilicon is formed in the trench groove to a thickness equal to or less than the thickness of the n-type semiconductor layer by CVD, vacuum deposition, sputtering, or the like.

[0057] Then, by using a known method such as vacuum deposition, sputtering, or CVD, a source electrode 135b is formed on the n+ type semiconductor layer 131c, and a drain electrode 135c is formed on the n+ type semiconductor layer 131b, thereby manufacturing a power MOSFET. The electrode materials for the source electrode and the drain electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0058] The MOSFET obtained in this manner has a higher breakdown voltage than conventional trench MOSFETs. While Fig. 6 shows an example of a trench-type vertical MOSFET, the present invention is not limited to this and can be applied to various MOSFET configurations. For example, the trench groove in Fig. 6 may be deepened to a depth that reaches the bottom surface of the n-type semiconductor layer 131a to reduce the series resistance.

[0059] (SIT) Fig. 8 shows an example of a semiconductor device of the present invention that is an SIT. The SIT in Fig. 8 includes an n-type semiconductor layer 141a, n+ type semiconductor layers 141b and 141c, a conductive adhesive layer 146, a conductive substrate 147, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0060] A conductive support layer 147 having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 145c, and a conductive adhesive layer 146 having a thickness of, for example, 50 nm to 50 μm is formed on the conductive support layer 147. An n+ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 μm is formed on the conductive adhesive layer 146, and an n- type semiconductor layer 141a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 141b. An n+ type semiconductor layer 141c is further formed on the n- type semiconductor layer 141a, and a source electrode 145b is formed on the n+ type semiconductor layer 141c.

[0061] Furthermore, multiple trenches are formed in the n-type semiconductor layer 141a, penetrating the n+ semiconductor layer 131c and reaching partway through the n-type semiconductor layer 131a. Gate electrodes 145a are formed on the n-type semiconductor layer in the trenches. In the on-state of the SIT shown in FIG. 8, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a positive voltage is applied to the gate electrode 145a relative to the source electrode 145b, a channel layer is formed in the n-type semiconductor layer 141a, electrons are injected into the n-type semiconductor layer, and the device is turned on. In the off-state, when the voltage of the gate electrode is set to 0V, no channel layer is formed, and the n-type semiconductor layer is filled with a depletion layer, resulting in the device being turned off.

[0062] In an embodiment of the present invention, the SIT of FIG. 8 can be manufactured in the same manner as the MOSFET of FIG. 7. More specifically, for example, an etching mask is provided in predetermined regions of the n-type semiconductor layer 141a and the n+-type semiconductor layer 141c. Using the etching mask, anisotropic etching is performed, for example, by reactive ion etching, to form a trench groove that extends from the surface of the n+-type semiconductor layer 141c to partway through the n-type semiconductor layer. Next, a gate electrode material, such as polysilicon, is formed in the trench groove to a thickness equal to or less than the thickness of the n-type semiconductor layer, using a CVD method, vacuum deposition method, sputtering method, or other known method. Furthermore, a source electrode 145b is formed on the n+-type semiconductor layer 141c, and a drain electrode 145c is formed on the n+-type semiconductor layer 141b, respectively, to manufacture the SIT. The electrode materials of the source electrode and the drain electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, and alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); polyaniline, polythiophene, and polypyrrole; Examples of the conductive material include organic conductive compounds such as cellulose, and mixtures thereof.

[0063] In the above example, an example was shown in which a p-type semiconductor was not used, but embodiments of the present invention are not limited to this and a p-type semiconductor may also be used. Examples using a p-type semiconductor are shown in Figures 9 to 11. These semiconductor elements can be manufactured in the same manner as in the above example. The p-type semiconductor may be made of the same material as the n-type semiconductor and contain a p-type dopant, or it may be a different p-type semiconductor.

[0064] The semiconductor element is particularly useful as a power device. Examples of the semiconductor element include diodes (e.g., PN diodes, Schottky barrier diodes, junction barrier Schottky diodes, etc.) and transistors (e.g., MESFETs, etc.), among which diodes are preferred, and Schottky barrier diodes (SBDs) are more preferred.

[0065] In addition to the above, the semiconductor element according to the embodiment of the present invention is preferably bonded to a lead frame, a circuit board, a heat dissipation substrate, or the like using a bonding member in accordance with conventional methods to form a semiconductor device, and is particularly preferably used as a power module, an inverter, or a converter, and further preferably used in a semiconductor system using, for example, a power supply. A preferred example of the semiconductor device is shown in FIG. 15. In the semiconductor device of FIG. 15, both surfaces of a semiconductor element 500 are bonded to a lead frame, a circuit board, or a heat dissipation substrate 502 by solder 501. This configuration allows for a semiconductor device with excellent heat dissipation properties. In the embodiment of the present invention, it is preferable that the periphery of the bonding member, such as the solder, is sealed with resin.

[0066] The semiconductor element or semiconductor device of the present invention described above can be applied to power conversion devices such as inverters and converters to achieve the above-mentioned functions. More specifically, it can be applied as a diode built into an inverter or converter, or as a switching element such as a thyristor, power transistor, IGBT (Insulated Gate Bipolar Transistor), or MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Fig. 16 is a block diagram showing an example of a control system using a semiconductor element or semiconductor device according to an embodiment of the present invention, and Fig. 17 is a circuit diagram of the same control system, which is particularly suitable for installation in an electric vehicle.

[0067] As shown in Fig. 16, control system 500 includes battery (power source) 501, boost converter 502, buck converter 503, inverter 504, motor (drive target) 505, and drive control unit 506, all of which are mounted on an electric vehicle. Battery 501 is a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores power by charging at a power supply station or by regenerating energy during deceleration, and can output a DC voltage required for operation of the electric vehicle's driving system and electrical equipment systems. Boost converter 502 is a voltage conversion device equipped with, for example, a chopper circuit, and can boost a DC voltage of, for example, 200 V supplied from battery 501 to, for example, 650 V using the switching operation of the chopper circuit, and output the boosted voltage to the driving system, such as the motor. The step-down converter 503 is also a voltage conversion device equipped with a chopper circuit, but by stepping down the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, about 12 V, it can output the voltage to the electrical system, including the power windows, power steering, and on-board electrical equipment.

[0068] Inverter 504 converts the DC voltage supplied from boost converter 502 into a three-phase AC voltage by switching operation and outputs it to motor 505. Motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from inverter 504, and transmits the rotational driving force to the wheels of the electric vehicle via a transmission or the like (not shown).

[0069] Meanwhile, various sensors (not shown) measure actual values ​​such as wheel rotation speed, torque, and accelerator pedal depression (acceleration amount) from the electric vehicle while it is running, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 functions as a controller, equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. It generates a control signal using the input measurement signal and outputs it as a feedback signal to the inverter 504, thereby controlling the switching operation of the switching elements. This allows the AC voltage provided by the inverter 504 to be instantly corrected, enabling accurate operation control of the electric vehicle and realizing safe and comfortable operation of the electric vehicle. The output voltage to the inverter 504 can also be controlled by providing a feedback signal from the drive control unit 506 to the boost converter 502.

[0070] 17 shows the circuit configuration of FIG. 16 excluding the step-down converter 503, i.e., the circuit configuration showing only the configuration for driving the motor 505. As shown in the figure, the semiconductor device of the present invention is used, for example, as a Schottky barrier diode in a step-up converter 502 and an inverter 504 to provide switching control. In the step-up converter 502, it is incorporated into a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated into a switching circuit including an IGBT to perform switching control. Note that an inductor (such as a coil) is inserted in the output of the battery 501 to stabilize the current, and capacitors (such as an electrolytic capacitor) are inserted between the battery 501, the step-up converter 502, and the inverter 504 to stabilize the voltage.

[0071] 17, the drive control unit 506 includes a calculation unit 507 made up of a CPU (Central Processing Unit) and a storage unit 508 made up of non-volatile memory. Signals input to the drive control unit 506 are given to the calculation unit 507, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 508 also temporarily stores the results of calculations performed by the calculation unit 507, and accumulates physical constants and functions necessary for drive control in the form of a table and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and storage unit 508 can be configured as known units, and their processing capabilities, etc. can be selected as desired.

[0072] As shown in FIGS. 16 and 17 , in the control system 500, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the switching operations of the boost converter 502, the buck converter 503, and the inverter 504. The use of gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements significantly improves switching characteristics. Furthermore, by applying the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, the effects of the present invention can be expected for each of the boost converter 502, the buck converter 503, and the inverter 504. The effects of the present invention can also be expected for any one of these, any combination of two or more of these, or any configuration including the drive control unit 506. The semiconductor device of the present invention can be applied to the control system 500 described above not only for electric vehicles but also for all kinds of control systems for boosting or lowering power from a DC power source, converting DC to AC, etc. Also, a power source such as a solar cell can be used as the battery.

[0073] FIG. 18 is a block diagram showing another example of a control system employing a semiconductor element or semiconductor device according to an embodiment of the present invention, and FIG. 19 is a circuit diagram of the same control system, which is suitable for installation in infrastructure equipment, home appliances, etc. that operate on power from an AC power source.

[0074] As shown in FIG. 18 , a control system 600 receives power supplied from, for example, an external three-phase AC power source (power source) 601. The control system 600 includes an AC / DC converter 602, an inverter 604, a motor (drive target) 605, and a drive control unit 606, and these components can be mounted in various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (such as a thermal power plant, a hydroelectric power plant, a geothermal power plant, or a nuclear power plant) operated by an electric power company. The output of the three-phase AC power source 601 is stepped down via a substation and supplied as an AC voltage. Alternatively, the AC / DC converter 602 may be installed in a building or a nearby facility as a private generator and supplied via a power cable. The AC / DC converter 602 is a voltage conversion device that converts AC voltage to DC voltage. It converts the 100V or 200V AC voltage supplied from the three-phase AC power source 601 to a predetermined DC voltage. Specifically, the voltage conversion converts the DC voltage to a commonly used desired voltage, such as 3.3V, 5V, or 12V. If the drive target is a motor, the voltage is converted to 12V. It is also possible to use a single-phase AC power supply instead of a three-phase AC power supply, in which case a similar system configuration can be achieved by using an AC / DC converter with a single-phase input.

[0075] Inverter 604 converts the DC voltage supplied from AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to motor 605. Motor 604 has different configurations depending on the controlled object, but is a three-phase AC motor for driving wheels if the controlled object is a train, pumps and various power sources if the controlled object is factory equipment, or compressors if the controlled object is a home appliance, and is rotationally driven by the three-phase AC voltage output from inverter 604, and transmits the rotational driving force to a driven object (not shown).

[0076] Note that, for example, among home appliances, there are many objects to be driven that can be supplied with the DC voltage output from AC / DC converter 302 as is (for example, personal computers, LED lighting equipment, video equipment, audio equipment, etc.), in which case inverter 604 is not required in control system 600, and the DC voltage is supplied to the object to be driven from AC / DC converter 602, as shown in Fig. 18. In this case, for example, a personal computer or the like is supplied with a DC voltage of 3.3 V, and an LED lighting equipment or the like is supplied with a DC voltage of 5 V.

[0077] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as the rotation speed and torque of the driven object, or the temperature and flow rate of the environment surrounding the driven object, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604 to control the switching operation of the switching element. This allows the AC voltage provided by the inverter 604 to be instantly corrected, thereby enabling accurate operation control of the driven object and achieving stable operation of the driven object. Furthermore, as described above, if the driven object can be driven by a DC voltage, it is also possible to perform feedback control of the AC / DC converter 602 instead of feedback to the inverter.

[0078] FIG. 19 shows the circuit configuration of FIG. 18. As shown in the figure, the semiconductor device of the present invention is used, for example, as a Schottky barrier diode in an AC / DC converter 602 and an inverter 604 to provide switching control. The AC / DC converter 602 uses, for example, Schottky barrier diodes configured in a bridge circuit, and performs DC conversion by converting the negative voltage component of the input voltage into a positive voltage and rectifying it. In the inverter 604, the semiconductor device is incorporated into a switching circuit of an IGBT to perform switching control. Note that an inductor (such as a coil) is interposed between the three-phase AC power supply 601 and the AC / DC converter 602 to stabilize the current, and a capacitor (such as an electrolytic capacitor) is interposed between the AC / DC converter 602 and the inverter 604 to stabilize the voltage.

[0079] 19, the drive control unit 606 includes a calculation unit 607 consisting of a CPU and a storage unit 608 consisting of a non-volatile memory. Signals input to the drive control unit 606 are given to the calculation unit 607, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 608 also temporarily stores the results of calculations performed by the calculation unit 607, and accumulates physical constants and functions required for drive control in the form of a table and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and storage unit 608 can be configured as known units, and their processing capabilities can be selected as desired.

[0080] In this control system 600, as in the control systems 500 shown in FIGS. 16 and 17, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC / DC converter 602 and inverter 604. The use of gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements improves switching characteristics. Furthermore, the application of the semiconductor film and semiconductor device according to the present invention not only promises excellent switching characteristics but also enables further miniaturization and cost reduction of the control system 600. In other words, the effects of the present invention can be expected for each of the AC / DC converter 602 and the inverter 604, and the effects of the present invention can be expected for any one of these, a combination of these, or any configuration including the drive control unit 606.

[0081] 18 and 19 show motor 605 as an example of a device to be driven, but the device to be driven is not necessarily limited to mechanically operated devices, and can be many devices that require AC voltage. Control system 600 can be applied as long as it inputs power from an AC power source to drive the device to be driven, and can be installed for drive control of devices such as infrastructure equipment (for example, power equipment in buildings and factories, communication equipment, traffic control equipment, water and sewage treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (for example, refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). [Example]

[0082] Examples of the present invention will be described below, but the present invention is not limited to these examples.

[0083] Example 1 1. Formation of n-type semiconductor layer 1-1. Film deposition equipment The mist CVD apparatus 1 used in this example will be described with reference to Figure 12. The mist CVD apparatus 1 includes a carrier gas source 2a for supplying a carrier gas, a flow rate control valve 3a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 2a, a carrier gas (diluted) source 2b for supplying a carrier gas (diluted), a flow rate control valve 3b for adjusting the flow rate of the carrier gas (diluted) delivered from the carrier gas (diluted) source 2b, a mist source 4 for containing a raw material solution 4a, a container 5 for containing water 5a, an ultrasonic vibrator 6 attached to the bottom of the container 5, a film formation chamber 7, a supply pipe 9 connecting the mist source 4 to the film formation chamber 7, a hot plate 8 installed within the film formation chamber 7, and an outlet 11 for discharging mist, droplets, and exhaust gases after the thermal reaction. A substrate 10 is placed on the hot plate 8.

[0084] 1-2. Formation of crystalline oxide semiconductor film Using the mist CVD apparatus shown in FIG. 12, an n-type semiconductor layer was formed on a sapphire substrate (substrate 10).

[0085] 1-3.Evaluation The phase of the film obtained in 1-2 above was identified using an XRD diffractometer, and it was found to be α-Ga2O3.

[0086] 2. Formation of n+ type semiconductor layer An n+ type semiconductor layer was formed on an n- type semiconductor layer in the same manner as in 1-2 above, except that tin was used as the dopant. The phase of the resulting film was identified using an XRD diffractometer, and it was found to be α-Ga2O3.

[0087] 3. Formation of Ohmic Electrodes A Ti layer and an Au layer were each deposited by sputtering on the n+ type semiconductor layer of the laminate obtained in step 2. The Ti layer had a thickness of 70 nm, and the Au layer had a thickness of 30 nm.

[0088] 4.Lamination of conductive substrates A Cu-Mo composite substrate (Mo content: 70% by mass, Cu content: 30% by mass) was laminated on the ohmic electrode of the laminate obtained in step 3 above, via a conductive adhesive layer made of a silver particle sintered body. The thickness of the conductive substrate was 200 μm.

[0089] 5. Substrate removal In the laminate obtained in 4 above, the sapphire substrate was removed.

[0090] 6. Formation of Schottky electrodes On the second n-type semiconductor layer of the laminate obtained in 5. above, a Co film (thickness 100 nm), a Ti film (thickness 50 nm), and an Al film (thickness 5 μm) were formed by EB deposition to serve as Schottky electrodes.

[0091] (Comparative Example 1) An SBD was fabricated in accordance with Example 1, except that a Si substrate was used as the conductive substrate.

[0092] (Evaluation of electrical characteristics) The IV characteristics of the semiconductor devices (SBDs) obtained in Example 1 and Comparative Example 1 were evaluated. The results are shown in Figures 13 and 14, respectively. Figures 13 and 14 show that the Schottky barrier diode of Example 1 has excellent electrical characteristics. Furthermore, when a Cu-Mo laminated substrate shown in Figure 23 is used as the conductive substrate, electrical characteristics equivalent to those of Example 1 are obtained.

[0093] The semiconductor element of the present invention can be used in a wide range of fields, including semiconductors (for example, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful as a power device. [Explanation of symbols]

[0094] 1. Film forming equipment (mist CVD equipment) 2a Carrier gas source 2b Carrier gas (dilution) source 3a Flow control valve 3b Flow control valve 4. Mist source 4a Raw material solution 4b Raw material fine particles 5 containers 5a water 6 ultrasonic transducer 7 Deposition chamber 8. Hot Plate 9 Supply pipe 10 Substrate 101 Semiconductor layer 101a n-type semiconductor layer 101b n+ type semiconductor layer 102 p-type semiconductor layer 103 Metal layer 104 Insulator layer 105 Electrode layer 105a Schottky electrode (other electrode layer) 105b Ohmic electrode (electrode layer) 106 Conductive adhesive layer 107 Conductive substrate 107a first metal layer 107b second metal layer 107c Third Metal Layer 107d Fourth Metal Layer 107e Fifth Metal Layer 108 Base substrate 131a n-type semiconductor layer 131b First n+ type semiconductor layer 131c second n+ type semiconductor layer 132 p-type semiconductor layer 134 Gate insulating film 135a gate electrode 135b Source electrode 135c Drain electrode 136 Conductive adhesive layer 137 Conductive Substrate 141a n-type semiconductor layer 141b First n+ type semiconductor layer 141c second n+ type semiconductor layer 142 p-type semiconductor layer 145a Gate electrode 145b Source electrode 145c Drain electrode 146 Conductive adhesive layer 147 Conductive Substrate 500 Control System 501 Battery (power supply) 502 Boost Converter 503 Buck Converter 504 Inverter 505 Motor (Driven object) 506 Drive control unit 507 Arithmetic section 508 Storage section 600 Control System 601 Three-phase AC power supply (power supply) 602 AC / DC Converter 604 Inverter 605 Motor (Driven object) 606 Drive control unit 607 Arithmetic section 608 Storage section

Claims

1. 1. A semiconductor device comprising at least a semiconductor layer containing a crystalline oxide semiconductor as a main component, an electrode layer stacked on the semiconductor layer, and a conductive substrate stacked on the electrode layer directly or via another layer, wherein the conductive substrate contains at least a first metal selected from the metals of Group 11 of the periodic table and a second metal having a linear thermal expansion coefficient different from that of the first metal, and wherein the semiconductor layer and the electrode layer have a warpage of 2 mm or less.

2. 2. The semiconductor device of claim 1, wherein said first metal is copper.

3. 3. The semiconductor device according to claim 1, wherein the second metal comprises a metal of Group 6 of the periodic table.

4. 4. The semiconductor device according to claim 3, wherein the metal of Group 6 of the periodic table is molybdenum.

5. 5. The semiconductor element according to claim 1, wherein the conductive substrate has a laminated structure in which at least one layer containing the first metal and at least one layer containing the second metal are laminated.

6. The semiconductor device according to claim 5 , wherein the uppermost layer and / or the lowermost layer of the laminated structure contains the first metal.

7. 7. The semiconductor device according to claim 1, wherein the crystalline oxide semiconductor contains at least one metal selected from the group consisting of aluminum, indium, and gallium.

8. 8. The semiconductor device according to claim 1, wherein the crystalline oxide semiconductor contains at least gallium.

9. 9. The semiconductor device according to claim 1, further comprising another electrode layer on a surface of said semiconductor layer opposite to the surface on which said electrode layer is laminated.

10. 10. The semiconductor element according to claim 1, which is a power device.

11. A semiconductor device constructed by bonding at least a semiconductor element to a lead frame, a circuit board, or a heat dissipation substrate with a bonding member, wherein the semiconductor element is the semiconductor element according to any one of claims 1 to 10.

12. A power conversion device using the semiconductor device according to claim 11.

13. A control system using the semiconductor device according to claim 11.

Images