Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device with reliability, capable of being easily formed, and stably securing a predetermined proof pressure.SOLUTION: A p-type outer peripheral region is formed by arranging first to fourth outer peripheral regions 15a, 13a, 28, and 27 in order from a front surface side of a semiconductor substrate 40 in an outer peripheral part 1b of an active region 1, and includes a plurality of steps each having same widths w1, w2, and w3 of 2 μm or more, which are gradually recessed to an internal side as separated as from the front surface of the semiconductor substrate 40 to a depth direction to an external side end part. Each of first, second, fourth outer peripheral regions 15a, 13a, and 27 is formed at the same time with each lower part 23 of a p++ type contact region 15d, a p-type base region 13, and a p+type region 22 of a center part 1a of the active region 1, respectively. An impurity density of the third outer peripheral region 28 is lower than that of an upper part 24 of the p+type region 22 of the center part 1a of the active region 1, and is 0.1 times or more and 0.5 times or less of the impurity density of the upper part 24 of the p+type region 22. A proof pressure structure 30 is contacted to an external side end part of the first outer peripheral region 15a.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, in silicon carbide semiconductor devices using silicon carbide (SiC) as a semiconductor material, a p-type peripheral region is provided at the periphery of the active region, which electrically connects the p-type region constituting the breakdown voltage structure of the edge termination region with the surface electrode on the front surface of the semiconductor substrate. The p-type peripheral region is formed by the p-type base region and p-type junction region constituting the element structure of the active region. ++ The p-type region, such as the contact region, extends to the vicinity of the boundary between the active region and the edge termination region, and a plurality of p-type regions with different impurity concentrations are arranged adjacent to each other in the depth direction.

[0003] Fig. 5 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in Fig. 5 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate (MOS gate) having a three-layer structure of metal-oxide film-semiconductor) with a trench gate structure that has a breakdown voltage structure 130 in an edge termination region 102 of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide.

[0004] The semiconductor substrate 140 is made of silicon carbide. + On the front surface of the starting substrate 141, - n type drift region 112 - The semiconductor substrate 140 is formed by epitaxially growing an n-type silicon carbide layer 142. - The main surface on the side of the silicon carbide layer 142 is the front surface, and + The main surface facing mold starting substrate 141 is referred to as the back surface. The front surface of semiconductor substrate 140 is flat over the entire area, with no steps between active region 101 and edge termination region 102. On the front surface of semiconductor substrate 140, edge termination region 102 is entirely covered with insulating layer 119.

[0005] The back surface (n + A drain electrode 145 is provided over the entire area of ​​the rear surface of the starting substrate 141. + The starting substrate 141 is n + The active region 101 is a type drain region 111. The active region 101 is disposed in the center of the semiconductor substrate 140 (chip center). The edge termination region 102 is between the active region 101 and the edge of the semiconductor substrate 140 (chip edge). In the center of the active region 101 (not shown), multiple unit cells of the MOSFET having the same structure (trench gate structure) are provided adjacent to each other.

[0006] In the peripheral portion 101b of the active region 101, the front surface of the semiconductor substrate 140 and the n - The p-type drift region 112 is formed in the entire region between the p-type drift region 112 and the semiconductor substrate 140, and the .... ++ a first outer peripheral region 115a of p-type, a second outer peripheral region 113a of p-type, and + In these regions, the outer periphery 101b of the active region 101 is in contact with the front surface of the semiconductor substrate 140 and the n-type region 122a (third and fourth outer periphery regions 124a and 123a, which will be described later). - A single p-type peripheral region 125 is formed across the entire area between the p-type drift region 112 and the p-type peripheral region 125 .

[0007] The first and second peripheral regions 115a and 113a are p regions that form a trench gate structure (not shown) in the center of the active region 101. ++ The first and second peripheral regions 115a and 113a are formed at the same time as the p-type contact region 115 and the p-type base region 113, and surround the central portion of the active region 101. The outer ends of the first and second peripheral regions 115a and 113a terminate at the boundary between the active region 101 and the edge termination region 102, and are on the same plane perpendicular to the front surface of the semiconductor substrate 140. + The p-type region 122a is located in the center of the active region 101. + It is formed at the same time as the mold region 122 .

[0008] p + The n-type region 122 is located at a position closer to the bottom of the trench (not shown) that constitutes the trench gate structure.+ The gate insulating film 112 extends to the gate-drain region 111 side (the rear surface side of the semiconductor substrate 140) and has the function of reducing the electric field applied to the gate insulating film at the bottom of the trench. + The n-type region 122 is located in the center of the active region 101. - The p-type base region 113 and the n-type silicon carbide layer 142 are formed inside the p-type silicon carbide layer 142. - The n-type drift region 112 is formed in two stages, and the upper stage (the front surface side of the semiconductor substrate 140) and the lower stage (the n-type drift region 112) are separated in the depth direction. + The portion on the side of the gate-type drain region 111 is adjacent to the gate-type drain region 112.

[0009] p + The type region 122a is p + The third and fourth outer peripheral regions 124a and 123a are formed in two stages at the same time as the mold region 122, and are adjacent to each other in the depth direction. + The impurity concentrations are the same as those in the upper and lower parts of mold region 122. The outer ends of third and fourth outer peripheral regions 124a, 123a terminate at the same position inside (towards the chip center) the outer end of second outer peripheral region 113a, and are on the same plane perpendicular to the front surface of semiconductor substrate 140.

[0010] The edge termination region 102 includes a predetermined breakdown voltage structure 130. The breakdown voltage structure 130 is, for example, a spatially modulated junction termination extension (JTE) structure that is a spatially modulated JTE structure. The JTE structure is a structure in which multiple p-type regions (hereinafter referred to as JTE regions) are concentrically arranged adjacent to each other around the active region, with the JTE regions having lower impurity concentrations as they move away from the inside to the outside (chip edge side).

[0011] The breakdown voltage structure 130 is connected to the front surface of the semiconductor substrate 140 and the n - A plurality of p-type regions 131 and a plurality of p-type regions 132 are selectively provided between the p-type drift region 112 and the p-type - The p-type region 131 and the p-type region 132 are -The p-type regions 132 are exposed on the front surface of the semiconductor substrate 140 and are in contact with the insulating layer 119 on the front surface of the semiconductor substrate 140. - The mold region 132 is formed at a shallow depth d101 of about 0.5 μm from the front surface of the semiconductor substrate 140.

[0012] The multiple p-type regions 131 are arranged concentrically around the active region 101, spaced apart from one another. The innermost p-type region 131 is arranged outside the first outer periphery region 115a and adjacent to the first outer periphery region 115a. - The p-type regions 132 are spaced apart from one another and concentrically arranged around the periphery of the active region 101. - The p-type regions 132 are provided between all of the adjacent p-type regions 131 and are adjacent to the p-type regions 131 on both sides in the radial direction from the inside to the outside within the plane of the front surface of the semiconductor substrate 140.

[0013] Innermost p - The p-type regions 132 extend inward beyond the outermost p-type regions 131. - The innermost p region 132 is fixed to the potential of the source electrode (not shown: surface electrode) via the first outer peripheral region 115a. - p outside type region 132 - The n-type region 132 is disposed outside the p-type region 131. - The drift region 112 is formed by all adjacent p - The p - The front surface of the semiconductor substrate 140 is exposed between the mold regions 132 .

[0014] A conventional silicon carbide semiconductor device has been proposed in which a p-type region constituting a breakdown voltage structure is disposed at a depth away from the front surface of the semiconductor substrate so that its bottom (the rear surface side edge of the semiconductor substrate) is at the same depth as the bottom of the p-type region forming the outermost peripheral edge (hereinafter referred to as the main junction edge) of the main junction (pn junction) of the active region (see, for example, Patent Documents 1 and 2 listed below). In Patent Document 1 listed below, electric field concentration at the main junction edge of the active region is suppressed by adjacent p-type regions of a JTE structure whose bottoms are aligned at the same depth outside the p-type region forming the main junction edge of the active region.

[0015] In addition, in Patent Document 1 below, in a structure in which the front surface of the semiconductor substrate is flat over the entire area without forming a step between the active region and the edge termination region, the p-type region of the active region and the p-type region constituting the JTE structure are formed at the same depth from the front surface of the semiconductor substrate, thereby improving the alignment accuracy by photolithography.In Patent Document 2 below below, the p-type region constituting the breakdown voltage structure and the p-type region of the active region are simultaneously formed at the same depth, thereby reducing the number of processes.

[0016] Another conventional silicon carbide semiconductor device has a p + A device has been proposed in which the outer edge of the p-type field relaxation region and the outer edge of the p-type region that constitutes the JTE structure in the edge termination region are spatially modulated (see, for example, Patent Document 3 below). + The outer edges of the electric field relaxation region of the type and the outer edges of the p-type region that constitutes the JTE structure are spatially modulated, and are arranged so that the depth becomes shallower toward the outside, thereby relaxing the electric field concentration in the depth direction as well. [Prior art documents] [Patent documents]

[0017] [Patent Document 1] Japanese Patent Publication No. 2020-202404 [Patent Document 2] Patent Publication No. 2021-048423 [Patent Document 3] Japanese Patent Application Publication No. 2019-087646 Summary of the Invention [Problem to be solved by the invention]

[0018] However, in conventional silicon carbide semiconductor device 110 (see FIG. 5), the impurity concentration of third outer peripheral region 124a and the outer end positions of first outer peripheral region 115a, second outer peripheral region 113a, third outer peripheral region 124a, and fourth outer peripheral region 123a that constitute p-type outer peripheral region 125 are not optimized. + The electric field applied to the die region 122a) and the outer edge (step portion) increases, reducing the breakdown voltage of the edge termination region 102. For example, if the design value (standard breakdown voltage) of the breakdown voltage of the active region 101 is 1600 V, the breakdown voltage of the edge termination region 102 will be as low as about 1180 V (see FIG. 4).

[0019] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems associated with the prior art, an object of the present invention is to provide a highly reliable silicon carbide semiconductor device that can be easily formed and can stably ensure a predetermined breakdown voltage. [Means for solving the problem]

[0020] In order to solve the above-mentioned problems and achieve the objects of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: A semiconductor substrate is made of silicon carbide and has a first main surface that is flat over the entire surface. An active region and a termination region are provided in the semiconductor substrate. The termination region surrounds the periphery of the active region. A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate, spanning from the active region to the termination region. A second semiconductor region of a second conductivity type is provided in the active region, between the first main surface and the first semiconductor region. An element structure is provided, including a pn junction between the first semiconductor region and the second semiconductor region, through which a current flows through the pn junction.

[0021] A second conductivity type peripheral region is provided between the first major surface and the first semiconductor region, between the device structure and the termination region. The second conductivity type peripheral region surrounds the periphery of the active region. In the termination region, between the first major surface and the first semiconductor region, a plurality of second conductivity type voltage withstanding regions are provided concentrically and spaced apart from one another around the periphery of the active region. A voltage withstanding structure is composed of the plurality of second conductivity type voltage withstanding regions. A first electrode is provided on the first major surface and electrically connected to the second semiconductor region and the second conductivity type peripheral region. A second electrode is provided on the second major surface of the semiconductor substrate and electrically connected to the first semiconductor region.

[0022] The element structure includes a first conductivity type third semiconductor region, a trench, a gate electrode, and a second conductivity type high concentration region. The third semiconductor region is selectively provided between the first major surface and the second semiconductor region and is electrically connected to the first electrode. The trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region. The gate electrode is provided inside the trench via a gate insulating film. The second conductivity type high concentration region is selectively provided between the first semiconductor region and the second semiconductor region, closer to the second major surface than a bottom surface of the trench. The second conductivity type high concentration region has a higher impurity concentration than the second semiconductor region.

[0023] The second conductivity type peripheral region has, at its outer end, a plurality of steps of the same width that are recessed inward in a stepwise manner as the region becomes farther away from the first main surface in the depth direction, and is composed of a plurality of peripheral regions that terminate more inward as the region becomes farther away from the first main surface according to the steps. The plurality of peripheral regions include first to fourth peripheral regions. The first peripheral region is in contact with the inner end of the breakdown voltage structure at the side closest to the first main surface. The second peripheral region is a portion of the second semiconductor region outer than the element structure, and is adjacent to the first peripheral region on the second main surface side. The third peripheral region is adjacent to the second peripheral region on the second main surface side. The fourth peripheral region is adjacent to the third peripheral region on the second main surface side, and has a lower surface at the same depth as the lower surface of the second conductivity type high concentration region.

[0024] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the third outer peripheral region is lower than the impurity concentration of the second conductivity type high concentration region.

[0025] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the third outer peripheral region is within a range of 0.1 to 0.5 times the impurity concentration of the second conductivity type high concentration region.

[0026] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the fourth outer peripheral region is equal to the impurity concentration of the second conductivity type high concentration region.

[0027] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the width of the step at the outer end of the second conductivity type peripheral region is not less than 1 μm and not more than 4 μm.

[0028] Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the second conductivity type high concentration region includes a first second conductivity type high concentration region and a second second conductivity type high concentration region. The first second conductivity type high concentration region is selectively provided between the first semiconductor region and the second semiconductor region and faces a bottom surface of the trench. The first second conductivity type high concentration region has a higher impurity concentration than the second semiconductor region. The second second conductivity type high concentration region is selectively provided between the first semiconductor region and the second semiconductor region, spaced apart from the trench and the first second conductivity type high concentration region and in contact with the second semiconductor region.

[0029] The second second-conductivity-type high-concentration region reaches the second main surface side beyond the bottom surface of the trench. The second second-conductivity-type high-concentration region has a higher impurity concentration than the second semiconductor region. The third periphery region has an upper surface at the same depth as the upper surface of the second second-conductivity-type high-concentration region and has a lower impurity concentration than the portion of the second second-conductivity-type high-concentration region on the first main surface side. The fourth periphery region has a lower surface at the same depth as the bottom surface of the second second-conductivity-type high-concentration region and has the same impurity concentration as the portion of the second second-conductivity-type high-concentration region on the second main surface side.

[0030] According to the above-described invention, the impurity concentration of the third outer peripheral region and the outer edge positions of the first to fourth outer peripheral regions are optimized, thereby alleviating the electric field applied to the second conductivity type outer peripheral region, which in turn suppresses localized electric field concentration at the main junction edge of the active region (the outer corner of the bottom of the second conductivity type outer peripheral region) and improves the avalanche breakdown capability at the main junction edge of the active region, thereby suppressing a decrease in breakdown voltage in the termination region.

[0031] Furthermore, according to the above-described invention, by appropriately changing the ion implantation mask pattern, a step can be formed at the outer edge of the second conductivity type peripheral region without changing the method for forming the element structure of the active region. Furthermore, by forming the third peripheral region at a timing different from that of each part of the active region, the impurity concentration of the third peripheral region can be appropriately set without changing the method for forming the element structure of the active region. [Effects of the Invention]

[0032] Advantageous Effects of Invention According to the silicon carbide semiconductor device of the present invention, it is possible to provide a highly reliable silicon carbide semiconductor device that can be easily formed and can stably ensure a predetermined breakdown voltage. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Figure 2]2 is a cross-sectional view showing a cross-sectional structure taken along the line A1-A2 in FIG. 1. [Figure 3] 2 is a cross-sectional view showing the cross-sectional structure taken along the line A2-A3 in FIG. 1. [Figure 4] FIG. 10 is a characteristic diagram showing the results of simulating the withstand voltage characteristics of the experimental example. [Figure 5] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0034] Preferred embodiments of a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0035] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described. Fig. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. Figs. 2 and 3 are cross-sectional views showing cross-sectional structures taken along cutting lines A1-A2 and A2-A3 in Fig. 1, respectively. A silicon carbide semiconductor device 10 according to an embodiment shown in Figs. 1 to 3 is a vertical MOSFET with a trench gate structure that includes a breakdown voltage structure 30 in an edge termination region 2 of a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC).

[0036] In the semiconductor substrate 40, a plurality of unit cells (functional units of an element) of the same structure (element structure) of the MOSFET are arranged adjacent to each other in the central portion 1a of the active region 1. The active region 1 is a region through which a main current (drift current) flows when the MOSFET is on. The active region 1 has a substantially rectangular planar shape and is arranged in the approximate center (chip center) of the semiconductor substrate 40. The active region 1 is located in the outermost p region (the end (chip end) side of the semiconductor substrate 40) as described later. ++ This is the portion extending from the outer end of the mold contact region 15a to the inner side (towards the center of the chip).

[0037] Edge termination region 2 is the region between active region 1 and the edge of the chip, and surrounds the periphery of active region 1 in a roughly rectangular shape. Edge termination region 2 is provided with a predetermined breakdown voltage structure 30. Breakdown voltage structure 30 has the function of maintaining breakdown voltage by mitigating the electric field near the boundary between active region 1 and edge termination region 2. The configuration of breakdown voltage structure 30 will be described later. Breakdown voltage is the limit voltage at which the drain-source voltage does not increase further even if the drain-source current increases due to avalanche breakdown at the pn junction.

[0038] The semiconductor substrate 40 is made of silicon carbide. + On the front surface of the starting substrate 41, - The semiconductor substrate 40 is formed by epitaxially growing an n-type silicon carbide layer 42. - The main surface on the silicon carbide layer 42 side is the front surface (first main surface), and + The main surface on the mold starting substrate 41 side is referred to as the back surface (second main surface). The front surface of the semiconductor substrate 40 is substantially flat over the entire area, with no steps occurring between the active region 1 and the edge termination region 2. "Substantially flat" means that the surface is horizontal within the range including tolerances due to process variations.

[0039] n + The starting substrate 41 is n + The n-type drain region 11. - The n-type silicon carbide layer 42 is formed by the n-type silicon carbide layer 42 when forming each part of the active region 1. - n-type drift region (first semiconductor region) 12 -The n-type silicon carbide layers 42a, 42b, and 42c are epitaxially grown in this order. - The n-type drift region 12 - This is a portion of the silicon carbide layer 42 where no diffusion region is formed by ion implantation and the impurity concentration remains the same as during epitaxial growth. - The n-type drift region 12 + It is in contact with the starting mold substrate 41 and is provided from the active region 1 to the edge of the chip.

[0040] The trench gate structure includes a p-type base region (second semiconductor region) 13, an n + type source region (third semiconductor region) 14, p ++ The p-type base region 13, the n-type contact region 15, the trench 16, the gate insulating film 17, and the gate electrode 18 are formed. + type source region 14 and p ++ The contact region 15 is the top n-type - The p-type base region 13 is a diffusion region formed by ion implantation inside the n-type silicon carbide layer 42c. The p-type base region 13 is located between the front surface of the semiconductor substrate 40 and the n-type silicon carbide layer 42c in the central portion 1a of the active region 1. - It is provided over the entire area between the mold drift region 12 and the substrate.

[0041] The p-type base region 13 extends outward and terminates within the outer periphery 1b of the active region 1. The portion 13a of the p-type base region 13 that extends to the outer periphery 1b of the active region 1 (hereinafter referred to as the second outer periphery region) constitutes a p-type outer periphery region 25, which will be described later. + type source region 14 and p ++ The p-type contact regions 15 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 13 in the active region 1, and are in contact with the p-type base region 13 at their bottoms (lower surface: the rear surface side edge of the semiconductor substrate 40).

[0042] n + The p-type source region 14 is provided only between adjacent trenches 16 in the central portion 1a of the active region 1. ++ The n-type contact region 15d (15) is formed between the adjacent trenches 16.+ At a position farther from the trench 16 than the n-type source region 14, + The n-type source region 14 is provided adjacent to the n-type source region 14. + type source region 14 and p ++ The contact region 15d is in ohmic contact with an ohmic electrode 43, which will be described later, on the front surface of the semiconductor substrate 40.

[0043] p of the peripheral portion 1b of the active region 1 ++ The contact regions 15c (15), 15a (15) are selectively provided between the front surface of the semiconductor substrate 40 and the second outer peripheral region 13a, and concentrically surround the central portion 1a of the active region 1. ++ The p-type contact regions 15c and 15a are formed in the central portion 1a of the active region 1. ++ The p-type contact region 15d is formed at the same time as the p-type contact region 15d and has approximately the same impurity concentration. ++ The bottoms of the mold contact regions 15d, 15c, and 15a are located at approximately the same depth from the front surface of the semiconductor substrate 40.

[0044] The term "substantially the same impurity concentration" and "substantially the same depth position" respectively means that the impurity concentration and the depth position are the same within the range including tolerances due to process variations. ++ The contact regions 15c and 15d may not be provided. ++ When the contact regions 15c and 15d are not provided, ++ Instead of the p-type contact regions 15c and 15d, the p-type base region 13 reaches the front surface of the semiconductor substrate 40 and contacts the ohmic electrode 43.

[0045] The innermost p of the peripheral portion 1b of the active region 1 ++ The contact region 15c is provided radially outward from the trench 16 within the surface of the semiconductor substrate 40, and is in ohmic contact with an ohmic electrode 43 (described later) on the surface of the semiconductor substrate 40. ++The p-type contact region 15c faces an n-type current diffusion region 20 (described later) in the depth direction. ++ The contact region 15c is formed in a p + It may be opposite the inner end of the mold area 26 .

[0046] The outermost p of the peripheral portion 1b of the active region 1 ++ The inner p-type contact region 15a ++ The outermost p-type contact region 15c of the peripheral portion 1b of the active region 1 is provided apart from the p-type contact region 15c. ++ The p-type contact region 15a extends outward from the p-type base region 13 (i.e., the second outer periphery region 13a) and terminates at the boundary between the active region 1 and the edge termination region 2. ++ The p-type contact region (hereinafter referred to as the first outer periphery region) 15a constitutes a p-type outer periphery region 25, which will be described later.

[0047] In the central portion 1a of the active region 1, n - Between the n-type drift region 12 and the p-type base region 13, there is a region closer to the n-type drift region 12 than the bottom surface of the trench 16. + The n-type current diffusion region 20 and the p-type current diffusion region 21 are formed at a deep position on the side of the n-type drain region 11 (the back surface side of the semiconductor substrate 40). + The n-type regions (second conductivity type high concentration regions (first and second second conductivity type high concentration regions)) 21 and 22 are selectively provided. + The type regions 21 and 22 are n - These are diffusion regions formed by ion implantation inside the silicon carbide layers 42a and 42b.

[0048] The n-type current diffusion region 20 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + The n-type current diffusion region 20 is in contact with the p-type base region 13 at its top surface and in contact with the n-type regions 21 and 22 at its bottom.- The n-type current diffusion region 20 is in contact with the p-type drift region 12. + Type region 21, 22 than n + It is preferable that the pores reach a deep position on the side of the drain region 11 .

[0049] The n-type current diffusion region 20 extends outward from the central portion 1a of the active region 1 and terminates within the peripheral portion 1b of the active region 1. + The n-type current diffusion region 20 surrounds the inner end of the n-type region 26. The n-type current diffusion region 20 may not be provided. When the n-type current diffusion region 20 is not provided, the n-type current diffusion region 20 may be replaced by an n - The p-type drift regions 12 are adjacent to each other. + The p-type base region 13 is connected to the p-type base region 13 by a connection between the p-type regions 21 and 22. + The insulating film 17 is in contact with the gate insulating film 17 and extends to the trench 16 in a direction parallel to the front surface of the semiconductor substrate 40 .

[0050] p + The n-type regions 21 and 22 are fixed to the potential of the source electrode 44, which will be described later, and have the function of depleting the n-type regions 21 and 22 (or depleting the n-type current diffusion region 20, or both) when the MOSFET (silicon carbide semiconductor device 10) is turned off, thereby mitigating the electric field applied to the gate insulating film 17. + The p-type region 21 is provided apart from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction. + The mold region 21 is p + It is electrically connected to the source electrode 44 by being partially connected to the mold region 22 .

[0051] p + The mold region 21 may be in contact with the gate insulating film 17 at the bottom of the trench 16, or may be spaced apart from the bottom of the trench 16. + The width of the mold region 21 is equal to or wider than the width of the trench 16. + By making the width of the mold region 21 wider than the width of the trench 16, p +The mold region 21 also faces the bottom corner portion (boundary between the sidewall and the bottom) of the trench 16 in the depth direction. + The effect of the mold region 21 in alleviating the electric field near the bottom of the trench 16 is further enhanced.

[0052] p + The p-type region 22 is formed between the adjacent trenches 16. + The mold region 21 and the trench 16 are spaced apart. + The p-type region 22 is in contact with the p-type base region 13 on the upper surface. + The type region 22 has an n - The upper portion (n + a portion 24 on the side of the n-type source region 14; - The lower portion (n + The portion 23 on the side of the drain region 11 is adjacent to the p + The impurity concentration in the upper portion 24 of the type region 22 is p + The impurity concentration is equal to or greater than that of the lower portion 23 of the mold region 22 .

[0053] The trench 16 has a depth of n + The n-type current diffusion region 20 (or the n-type current diffusion region 20 if no n-type current diffusion region 20 is provided) penetrates the p-type source region 14 and the p-type base region 13. - The trench 16 extends to the p-type drift region 12. + The trench 16 may terminate inside the mold region 21. The trench 16 extends, for example, in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40, and reaches the outer periphery 1b of the active region 1. A gate electrode 18 is provided inside the trench 16 with a gate insulating film 17 interposed therebetween.

[0054] The peripheral portion 1b of the active region 1 surrounds the periphery of the central portion 1a of the active region 1 in a substantially rectangular shape. +The outer peripheral portion 1b of the active region 1 is the portion from the outermost end of the source region 14 to the boundary between the active region 1 and the edge termination region 2. In the short direction of the trench 16, the outer peripheral portion 1b of the active region 1 is the portion from the outer sidewall of the outermost trench 16 to the boundary between the active region 1 and the edge termination region 2. No MOSFET unit cells are provided in the outer peripheral portion 1b of the active region 1.

[0055] The peripheral portion 1b of the active region 1 is connected to the front surface of the semiconductor substrate 40 and the n - The first outer peripheral region (the outermost p ++ the second outer peripheral region (extension of the p-type base region 13) 13a and the p + In these regions, the outer periphery 1b of the active region 1 is in contact with the front surface of the semiconductor substrate 40 and the n-type region 26. - One p-type outer periphery region (second conductivity type outer periphery region) 25 is formed in the entire area between the first and second conductivity type drift regions 12.

[0056] The p-type peripheral region 25 is connected to the n-type terminal region 2 when the MOSFET (silicon carbide semiconductor device 10) is turned off. - This region is for extracting hole (positive hole) current, which is generated in the drift region 12 and flows toward the active region 1, to the source electrode 44, and is electrically connected to the source electrode 44. When the MOSFET is turned off, the n-type terminal region 2 - The hole current generated in p-type drift region 12 is extracted to source electrode 44 via p-type peripheral region 25, thereby suppressing hole current concentration in edge termination region 2 during avalanche breakdown.

[0057] The p-type peripheral region 25 functions to make uniform the electric field in the surface of the front surface of the semiconductor substrate 40 in the peripheral portion 1b of the active region 1. The first and second peripheral regions 15a and 13a respectively correspond to the p-type peripheral region 25 in the central portion 1a of the active region 1. ++The first peripheral region 15a is a region formed simultaneously with the p-type contact region 15d and the p-type base region 13, and surrounds the periphery of the central portion 1a of the active region 1. The first peripheral region 15a is exposed on the front surface of the semiconductor substrate 40, and contacts the insulating layer (an insulating layer formed by laminating a field oxide film 51 and an interlayer insulating film 19 in this order) on the front surface of the semiconductor substrate 40.

[0058] The second outer peripheral region 13a is connected to the first outer peripheral region 15a by - The first outer peripheral region 15a is provided between the first outer peripheral region 15a and the second outer peripheral region 15b. + The p-type drain region 11 is adjacent to the p-type drain region 11. + The mold region 26 is connected to the second outer peripheral region 13a and n - The p-type drift region 12 is provided between the p-type drift region 12 and in contact with these regions. + The mold region 26 is provided radially outwardly away from the trench 16 and surrounds the central portion 1a of the active region 1. + The type region 26 contains all p + The mold regions 21 and 22 are connected.

[0059] p + The p-type region 26 is formed on the front surface of the semiconductor substrate 40. + At a depth position substantially the same as that of the mold region 22, p + The thickness of the mold region 22 is approximately the same as that of the mold region 22. + The upper and lower surfaces of the mold region 26 are each p + The upper and lower surfaces of the mold region 22 are at the same depth. + The type region 26 has an n - an upper portion (hereinafter referred to as a third outer peripheral region) 28 formed inside the silicon carbide layer 42b; - The third and fourth outer peripheral regions 28, 27 are adjacent to each other, and the lower portion (referred to as a fourth outer peripheral region) 27 is formed inside the silicon carbide layer 42a. The inner ends of the third and fourth outer peripheral regions 28, 27 are located at approximately the same position.

[0060] The third outer peripheral region 28 is p + The second outer peripheral region 13a is provided at substantially the same depth as the upper portion 24 of the mold region 22 and with substantially the same thickness. +The third outer peripheral region 28 is adjacent to the drain region 11. That is, the upper surface and the lower surface of the third outer peripheral region 28 are each formed to have a thickness of p + The third outer peripheral region 28 is located at the same depth as the upper and lower surfaces of the upper portion 24 of the mold region 22. The impurity concentration of the third outer peripheral region 28 is p + The impurity concentration of the third outer peripheral region 28 is lower than that of the upper portion 24 of the type region 22. Specifically, the impurity concentration of the third outer peripheral region 28 is, for example, p + The impurity concentration in the upper portion 24 of the mold region 22 may be in the range of 0.1 to 0.5 times, for example, 1×10 19 / cm 3 It is desirable that the temperature be as low as possible.

[0061] The third outer peripheral region 28 has a lower impurity concentration than the third outer peripheral region 124a of the conventional structure (see FIG. 5). That is, the impurity concentration of the third outer peripheral region 28 is lower than that of the p + The impurity concentration is lower than that of the upper portion 24 of the doped region 22. For example, when a trench gate structure similar to the conventional structure is disposed in the central portion 1a of the active region 1, the p ++ the p-type contact region 15d, the p-type base region 13 and the p + The p-type regions 22 are of the conventional structure. ++ the p-type contact region 115, the p-type base region 113 and the p + The structure is the same as that of the mold region 122. + The upper portion 24 of the mold region 22 and the third peripheral region 28 are each a conventional p + The third outer peripheral region 124a corresponds to the upper portion of the mold region 122 and the third outer peripheral region 124a. + This is because the upper portion of the mold region 122 has the same impurity concentration.

[0062] The impurity concentration of the third outer peripheral region 28 is p + Instead of making the impurity concentration of the first outer peripheral region 15a lower than that of the upper portion 24 of the type region 22, the impurity concentration of the first outer peripheral region 15a is made lower than that of the central portion 1a of the active region 1. ++ In this case, the impurity concentration of the first outer peripheral region 15 may be lower than that of the p-type contact region 15d.++ The impurity concentration of the contact region 15d may be, for example, in the range of 0.1 to 0.5 times, for example, 1×10 19 / cm 3 The impurity concentration of the third outer peripheral region 28 is about p + The impurity concentration of the third outer peripheral region 28 may be the same as that of the upper portion 24 of the mold region 22. In this case, the impurity concentration of the third outer peripheral region 28 may be set to p + The same effect can be obtained as when the impurity concentration is lower than that of the upper portion 24 of the mold region 22. In addition, the impurity concentration of the third outer peripheral region 28 and the impurity concentration of the first outer peripheral region 15a may both be lower than the impurity concentration of the corresponding region in the central portion 1a of the active region 1.

[0063] The fourth outer peripheral region 27 is n of the third outer peripheral region 28. + The fourth peripheral region 27 is adjacent to the n-type drain region 11 side. + The fourth outer peripheral region 27 is disposed on the p-type drain region 11 side. + This is a region formed simultaneously with the lower portion 23 of the mold region 22, and + The fourth outer peripheral region 27 is provided at substantially the same depth as the lower portion 23 of the mold region 22, with substantially the same thickness and substantially the same impurity concentration. + It is at the same depth as the upper and lower surfaces of the lower portion 23 of the mold region 22 .

[0064] The outer ends of the first outer peripheral region 15a, the second outer peripheral region 13a, the third outer peripheral region 28, and the fourth outer peripheral region 27 terminate at different positions. Specifically, the outer end of the first outer peripheral region 15a is located at the boundary between the active region 1 and the edge termination region 2. The outer end of the second outer peripheral region 13a terminates a predetermined width w1 inward from the outer end of the first outer peripheral region 15a. The outer end of the third outer peripheral region 28 terminates a predetermined width w2 inward from the outer end of the second outer peripheral region 13a. The outer end of the fourth outer peripheral region 27 terminates a predetermined width w3 inward from the outer end of the third outer peripheral region 28.

[0065] As a result, of first outer peripheral region 15a, second outer peripheral region 13a, third outer peripheral region 28, and fourth outer peripheral region 27 that make up p-type outer peripheral region 25, first outer peripheral region 15a, which is closest to the front surface of semiconductor substrate 40, is extended to the outermost position. At the outer edge of p-type outer peripheral region 25, multiple steps of the same widths w1, w2, w3 are formed that are gradually recessed inward as they move away from the front surface of semiconductor substrate 40 in the depth direction. The widths w1, w2, w3 of the steps at the outer edge of p-type outer peripheral region 25 are all the same (w1 = w2 = w3).

[0066] The widths w1, w2, and w3 of the steps at the outer end of the p-type outer peripheral region 25 may be, for example, approximately 1 μm or more, and are preferably as wide as possible. Furthermore, the widths w1, w2, and w3 of the steps at the outer end of the p-type outer peripheral region 25 may be, for example, approximately 2 μm or more and 4 μm or less. The widths w1, w2, and w3 of the steps at the outer end of the p-type outer peripheral region 25 are the radial width from the outer end of the first outer peripheral region 15a to the outer end of the second outer peripheral region 13a, the radial width from the outer end of the second outer peripheral region 13a to the outer end of the third outer peripheral region 28, and the radial width from the outer end of the third outer peripheral region 28 to the outer end of the fourth outer peripheral region 27, respectively.

[0067] By forming a step at the outer edge of p-type peripheral region 25 in this manner, outer corner portion 15b of the bottom of first peripheral region 15a becomes a location of electric field concentration when the MOSFET is off, but the electric field concentration at portion 15b is alleviated by breakdown-resistant structure 30 adjacent to the outside of first peripheral region 15a. Also, second peripheral region 13a, third peripheral region 28, and fourth peripheral region 27 each terminate more inward than the outer edge of the p-type region adjacent directly above (on the front surface side of semiconductor substrate 40), thereby suppressing local electric field concentration at the outer corner portion of the bottom.

[0068] Interlayer insulating film 19 is provided over the entire front surface of semiconductor substrate 40, covering gate electrode 18 and gate polysilicon wiring layer 52. A field oxide film 51 is provided between the front surface of semiconductor substrate 40 and interlayer insulating film 19 in peripheral portion 1b of active region 1 and edge termination region 2. Gate polysilicon wiring layer 52 is disposed between field oxide film 51 and interlayer insulating film 19 in peripheral portion 1b of active region 1. Gate polysilicon wiring layer 52 surrounds the periphery of central portion 1a of active region 1.

[0069] A gate metal wiring layer 53 is provided on the gate polysilicon wiring layer 52 via a contact hole in the interlayer insulating film 19. The gate polysilicon wiring layer 52 and the gate metal wiring layer 53 form a gate runner. Gate electrodes 18 are connected to the gate polysilicon wiring layer 52 at the longitudinal ends of the trenches 16. All of the gate electrodes 18 are electrically connected to gate pads (electrode pads: not shown) via the gate polysilicon wiring layer 52 and the gate metal wiring layer 53.

[0070] Directly below the gate runner (n + The gate runner 11 and the n-type drain region 11 side preferably have the same structure. - Only the p-type outer periphery region 25 is disposed between the gate runner and the p-type drift region 12. That is, the entire surface of the gate runner faces all of the first outer periphery region 15a, the second outer periphery region 13a, the third outer periphery region 28, and the fourth outer periphery region 27 in the depth direction, with the field oxide film 51 interposed therebetween. The inner end of the gate runner is located outward from the inner end of the first outer periphery region 15a. The outer end of the gate runner is located inward from the outer end of the fourth outer periphery region 27.

[0071] The ohmic electrodes (first electrodes) 43 are provided on the front surface of the semiconductor substrate 40 on the portions exposed in the contact holes of the interlayer insulating film 19. The ohmic electrodes 43 are n-type electrodes on the front surface of the semiconductor substrate 40. + type source region 14 and p ++Type contact regions 15d, 15c(p ++ When the type contact regions 15d and 15c are not provided, the ohmic electrode 43 is in ohmic contact with the p-type base region 13. The ohmic electrode 43 is, for example, a nickel silicide (NixSiy, where x and y are any integers) film.

[0072] The source electrode (first electrode) 44 is provided on the interlayer insulating film 19 so as to fill each contact hole in the interlayer insulating film 19. The source electrode 44 is provided over substantially the entire central portion 1a of the active region 1 and extends to the peripheral portion 1b of the active region 1 so as not to reach the gate metal wiring layer 53. The source electrode 44 is connected to the n-type ohmic electrode 43 in the central portion 1a of the active region 1. + Type source region 14, p ++ p-type contact region 15d, p-type base region 13, p + It is electrically connected to the mold regions 21 and 22 .

[0073] The source electrode 44 is connected to the p ++ The drain electrode (second electrode) 45 is electrically connected to the n-type contact region 15c, the first outer periphery region 15a, the second outer periphery region 13a, the third outer periphery region 28, and the fourth outer periphery region 27. + The back surface of the starting substrate 41 is provided with n + type drain region 11(n + ohmic contact with the starting substrate 41), + The gate electrode 12 is electrically connected to the drain region 11 .

[0074] The breakdown voltage structure 30 in the edge termination region 2 is, for example, a spatially modulated JTE structure in which the JTE structure is spatially modulated. - A plurality of p-type regions (second conductivity type breakdown voltage regions) 31 and a plurality of p-type regions (second conductivity type breakdown voltage regions) 32 are selectively provided between the p-type drift region 12 and the p-type drift region 13. - The p-type region 31 and the p-type region 32 are connected to each other. - Type region 32 is n -These are diffusion regions formed by ion implantation in the surface region of the silicon carbide layer 42c, and the depth d1 of these regions is all substantially the same, for example, about 0.5 μm from the front surface of the semiconductor substrate 40.

[0075] p-type region 31 and p - The depth position of each bottom of the mold region 32 is shallower than the depth position of the bottom of the first outer peripheral region 15a from the front surface of the semiconductor substrate 40. Therefore, the outer corners of the bottoms of the first outer peripheral region 15a, the second outer peripheral region 13a, the third outer peripheral region 28, and the fourth outer peripheral region 27 are - The p-type region 31 and the p-type drift region 12 are surrounded by the p-type region 31 and the p-type drift region 12. - The mold region 32 contacts the insulating layer (the interlayer insulating film 19 and the field oxide film 51) on the front surface of the semiconductor substrate .

[0076] The multiple p-type regions 31 are concentrically arranged apart from one another around the periphery of the active region 1. The p-type regions 31 arranged further outward have a narrower width (the width in the radial direction from the inside to the outside within the plane of the front surface of the semiconductor substrate 40) and a wider interval between adjacent p-type regions 31 on the inside. The innermost p-type region 31 is arranged outside the first outer peripheral region 15a and adjacent to the first outer peripheral region 15a. In FIGS. 2 and 3, the p-type regions 31 and p - The mold regions 32 are each hatched differently.

[0077] Multiple p - The p-type regions 32 are arranged concentrically around the periphery of the active region 1, spaced apart from one another. - The width (radial width) of the mold region 32 is narrower, and the p - The outermost p - The width of the mold region 32 is - It may be wider than the width of the mold region 32. - Some of the p-type regions 32 are disposed between adjacent p-type regions 31 and are adjacent to the p-type regions 31 on both sides in the radial direction, surrounding the bottom corners of all the p-type regions 31 .

[0078] Innermost p - The inner edge of the p-type region 32 terminates at the same position as the outer edge of the innermost p-type region 31 or further outward than the outer edge of the innermost p-type region 31. - The p-type regions 32 extend inward from the outermost p-type regions 31. - p outside type region 32 - The n-type region 32 is disposed outside the p-type region 31. - The drift region 12 is formed by all adjacent p - The p-type region 32 extends between the p-type region 32 and reaches the front surface of the semiconductor substrate 40. - Adjacent to the mold area 32 .

[0079] All p-type regions 31 and inner p - Some of the die regions 32 are fixed to the potential of the source electrode 44 via the first outer periphery region 15a. The electric field strength in the edge termination region 2 tends to decrease with increasing distance from the active region 1. Therefore, by decreasing the impurity concentration of the JTE regions 30a, 30c the farther they are located from the active region 1 in accordance with the electric field strength distribution tendency in the edge termination region 2, the predetermined breakdown voltage of the edge termination region 2 is stably ensured.

[0080] The innermost p-type region 31 (JTE region 30a) and the p - The double-zone JTE structure is formed by the p-type region 31 other than the JTE region 30a and the inner p-type region 31. - The spatial modulation region 30b between the JTE regions 30a and 30c is formed by some of the mold regions 32. - p outside type region 32 - type region 32 and n - The type drift region 12 and the spatial modulation region 30d are formed adjacent to the outside of the JTE region 30c.

[0081] The spatial modulation region 30b is divided into two small regions (p-type region 31 and p-type region 32) having approximately the same impurity concentration as the regions (JTE regions 30a and 30c) adjacent to both sides of the spatial modulation region 30b. - The spatial modulation region 30d is formed by alternately and repeatedly arranging adjacent regions (JTE regions 30c and n) on both sides of the spatial modulation region 30d. - The two small regions (p - Type region 32 and n - The spatial impurity concentration distribution of the entire spatial modulation regions 30b and 30d is determined by the width and impurity concentration ratio of the two small regions.

[0082] Thus, the breakdown voltage withstanding structure 30 includes the JTE regions 30a and 30c and the spatial modulation regions 30b and 30d. In this case, the breakdown voltage withstanding structure 30 includes the spatial modulation region 30b between the adjacent JTE regions 30a and 30c, which has an impurity concentration distribution spatially equivalent to the intermediate impurity concentration of the two regions. - A spatially modulated JTE structure is formed by disposing a spatially modulated region 30d between the p-type drift region 12 and the p-type semiconductor layer 10, which has an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between the impurity concentrations of these two regions, and by gradually decreasing the overall p-type impurity concentration from the inside to the outside.

[0083] The breakdown voltage structure 30 may be a single-zone JTE structure (not shown) that is composed of only one JTE region. In this case, the breakdown voltage structure 30 is composed of one JTE region and the n-zone JTE region outside the JTE region. - This is a spatially modulated JTE structure in which a spatially modulated region having an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between the p-type drift regions is disposed between the p-type drift regions, and the overall p-type impurity concentration gradually decreases from the inside to the outside. Compared to a general JTE structure that does not have a spatially modulated region, the spatially modulated JTE structure can more stably ensure a predetermined breakdown voltage in the edge termination region 2.

[0084] In addition, the front surface of the semiconductor substrate 40 and the n- Between the n-type drift region 12 and the n-type drift region 13, the n-type drift region 13 is formed outside the breakdown voltage structure 30. + A channel stopper region 33 is optionally provided. + The n-type channel stopper region 33 - The n-type silicon carbide layer 42c is a diffusion region formed by ion implantation in the surface region thereof. + The channel stopper region 33 is provided outside the breakdown withstanding structure 30, spaced apart from the breakdown withstanding structure 30 in the radial direction, and surrounds the breakdown withstanding structure 30. + The channel stopper region 33 contacts the insulating layer on the front surface of the semiconductor substrate 40 .

[0085] n + The channel stopper region 33 is exposed at the edge of the chip. + The channel stopper region 33 and the breakdown voltage structure 30 (the outermost p - Between the type region 32) and n - n-type drift region 12. + The n-type channel stopper region 33 has a floating potential. No field plate (FP) or channel stopper electrode is provided on the front surface of the semiconductor substrate 40 in the edge termination region 2. + Instead of the type channel stopper region 33, + A mold channel stop region may be provided.

[0086] The operation of the silicon carbide semiconductor device 10 according to the embodiment will now be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 18 while a positive voltage (forward voltage) relative to the source electrode 44 is applied to the drain electrode 45, a channel (n-type inversion layer) is formed in the portion of the p-type base region 13 along the trench 16. As a result, the n + Type drain region 11 to n - through the drift region 12 and the channel + A current flows toward the source region 14, and the MOSFET (silicon carbide semiconductor device 10) turns on.

[0087] On the other hand, when a voltage less than the gate threshold voltage is applied to the gate electrode 18 while a forward voltage is applied between the source and drain, the p-type base region 13, p + The p-type regions 21 and 22 and the p-type peripheral region 25, and the n-type current diffusion region 20 and the n - The pn junction (main junction of the active region 1) between the n-type drift region 12 and the n-type drift region 12 is reverse biased, and the MOSFET remains in the off state. - As the depletion layer spreads in the type drift region 12, the electric field applied to the gate insulating film 17 at the bottom of the trench 16 is alleviated.

[0088] When the MOSFET is off, the depletion layer - A predetermined withstand voltage based on the dielectric breakdown field strength of silicon carbide and the depletion layer width (radial width) is ensured by the amount that the p-type drift region 12 extends outward (toward the chip end) within the p-type drift region 12. Furthermore, when the MOSFET is off, of the first to fourth outer peripheral regions 15a, 13a, 28, and 27 that make up the p-type outer peripheral region 25, outer corner 15b at the bottom of first outer peripheral region 15a, which is closest to the front surface of semiconductor substrate 40, becomes an electric field concentration location.

[0089] This suppresses local electric field concentration at the outermost peripheral edge (hereinafter referred to as the main junction edge) of the main junction of active region 1. The main junction edge of active region 1 refers to outer corner portion 25b of the bottom of p-type peripheral region 25 (outer corner portion 27b of the bottom of fourth peripheral region 27, which is the closest to the back surface of semiconductor substrate 40 among first to fourth peripheral regions 15a, 13a, 28, and 27 that make up p-type peripheral region 25). Electric field concentration at outer corner portion 15b of the bottom of first peripheral region 15a is mitigated by breakdown-breakdown structure 30 adjacent to the outside of first peripheral region 15a.

[0090] In addition, a plurality of steps having the same widths w1, w2, and w3 are formed at the outer end of the p-type peripheral region 25, which are recessed inward in a stepwise manner as the distance from the front surface of the semiconductor substrate 40 increases in the depth direction. The impurity concentration of the third peripheral region 28 constituting the p-type peripheral region 25 is adjusted to be equal to the p-type impurity concentration of the central portion 1a of the active region 1. +By making the impurity concentration lower than that of the upper part 24 of the p-type region 22, the electric field applied to the lower part (third and fourth peripheral regions 28, 27) and the outer end part (step part) of the p-type peripheral region 25 when the MOSFET is off can be alleviated, thereby suppressing a decrease in the breakdown voltage in the edge termination region 2.

[0091] Next, a method for manufacturing silicon carbide semiconductor device 10 according to the embodiment will be described. + n-type drain region 11 + Type starting substrate (n + On the front surface of the mold starting wafer 41, n - n type drift region 12 - Next, an n-type silicon carbide layer 42a is epitaxially grown in the central portion 1a of the active region 1 by photolithography and ion implantation of p-type impurities. - The surface region of the silicon carbide layer 42a is + Type region 21 and p + The lower portion 23 of the mold region 22 and the fourth outer peripheral region 27 are selectively formed simultaneously.

[0092] In addition, photolithography and ion implantation of n-type impurities are performed to form n-type impurities in the active region 1. - The lower portion of the n-type current diffusion region 20 is formed in the surface region of the p-type silicon carbide layer 42a. + type region 21, p + The order of forming the lower portion 23 of the n-type region 22, the fourth outer peripheral region 27, and the lower portion of the n-type current diffusion region 20 can be reversed. + Type region 21 and p + It may be formed at a timing different from that of the lower portion 23 of the mold region 22 .

[0093] Next, n - On the silicon carbide layer 42a, - n type drift region 12 - Next, the n-type silicon carbide layer 42b in the central portion 1a of the active region 1 is epitaxially grown by photolithography and ion implantation of p-type impurities. - The silicon carbide layer 42b is +The upper portion 24 of the mold region 22 is selectively formed. + The upper and lower portions 24 and 23 of the mold area 22 are joined together.

[0094] In addition, photolithography and p-type impurity ion implantation are performed to form n-type impurity regions in the peripheral portion 1b of the active region 1. - The silicon carbide layer 42b is + The third outer peripheral region 28 is selectively formed with a lower impurity concentration than the upper portion 24 of the mold region 22. At this time, the third and fourth outer peripheral regions 28 and 27 are connected to each other in the depth direction to form p + A mold region 26 is formed. The outer edge of the third outer peripheral region 28 terminates outside the outer edge of the fourth outer peripheral region 27.

[0095] In addition, photolithography and ion implantation of n-type impurities are performed to form n-type impurities in the active region 1. - The upper portion of the n-type current diffusion region 20 is formed in the silicon carbide layer 42b. At this time, the upper and lower portions of the n-type current diffusion region 20 are connected to each other. + The order of forming the upper portion 24 of the n-type region 22, the third periphery region 28, and the upper portion of the n-type current spreading region 20 can be reversed.

[0096] Next, n - On the silicon carbide layer 42b, - n type drift region 12 - The silicon carbide layer 42c is then epitaxially grown. + n-type regions 21, 22, 26 and n-type current diffusion region 20 - The silicon carbide layer 42 (42a to 42c) is + A semiconductor substrate (semiconductor wafer) 40 having a predetermined thickness is completed by laminating it on a mold starting substrate 41.

[0097] Next, photolithography and ion implantation of p-type impurities are performed to form n - The p-type base region 13 and the second outer peripheral region 13a are simultaneously formed in the silicon carbide layer 42c. +The second outer peripheral region 13a is connected to the upper portion 24 of the mold region 22. The second and third outer peripheral regions 13a, 28 are connected to each other in the depth direction. The outer edge of the second outer peripheral region 13a terminates outside the outer edge of the third outer peripheral region 28.

[0098] In addition, photolithography and ion implantation of n-type impurities are performed to form n-type impurities in the central portion 1a of the active region 1. - The surface region of the silicon carbide layer 42c is + The n-type source region 14 is selectively formed in the active region 1 by photolithography and ion implantation of p-type impurities. - The surface region of the silicon carbide layer 42c is ++ The mold contact regions 15d, 15c and the first outer peripheral region 15a are selectively formed simultaneously.

[0099] At this time, n + type source region 14 and p ++ The p-type contact region 15d is in contact with the p-type base region 13. ++ The p-type contact region 15c is brought into contact with the second outer peripheral region 13a. The first and second outer peripheral regions 15a, 13a are also connected to each other in the depth direction. As a result, the first to fourth outer peripheral regions 15a, 13a, 28, 27 are connected to each other in the depth direction, and a p-type outer peripheral region 25 is formed in the outer periphery 1b of the active region 1.

[0100] The outer edge of the first outer peripheral region 15a terminates more outside than the outer edge of the second outer peripheral region 13a. As a result, the outer edges of the first to fourth outer peripheral regions 15a, 13a, 28, and 27 terminate more inward as they move away from the front surface of the semiconductor substrate 40. The outer edge of the p-type outer peripheral region 25 is - The further away from the surface of the silicon carbide layer 42c, the more stepped inward the recesses are, forming a plurality of steps each having the same widths w1, w2, and w3.

[0101] In addition, photolithography and p-type impurity ion implantation are used to form n-type impurity regions in the edge termination region 2. - The surface region of the silicon carbide layer 42c is provided with a plurality of p-type regions 31 and a plurality of p -The p-type region 31 and the p-type region 32 are selectively formed. - The edge termination region 2 is formed at a timing different from that of the n-type region 32. In addition, the edge termination region 2 is formed at an n-type - The surface region of the silicon carbide layer 42c is + A mold channel stopper region 33 is selectively formed.

[0102] A plurality of p-type regions 31 and a plurality of p - The die region 32 forms a breakdown withstanding structure 30 in the edge termination region 2. - The order in which the diffusion regions are formed in the silicon carbide layer 42c can be changed as appropriate. + The n-type channel stopper region 33 + The source region 14 may be formed at the same time. - The portion of the silicon carbide layer 42 (42a to 42c) that is not ion-implanted and remains at the same impurity concentration as during epitaxial growth is n. - This becomes the type drift region 12.

[0103] Next, n - A heat treatment is performed to activate the impurities ion-implanted into the silicon carbide layer 42. The heat treatment for activating the impurities is performed in the n-type silicon carbide layer 42. - This may be performed each time impurity ions are implanted into each of the silicon carbide layers 42a to 42c. Next, the trench 16, the gate insulating film 17, the gate electrode 18, the field oxide film 51, and the gate polysilicon wiring layer 52 are formed by a general method.

[0104] Next, an interlayer insulating film 19 is formed over the entire front surface of the semiconductor substrate 40. Next, a source electrode 44, a gate pad (not shown), a gate metal wiring layer 53, a passivation film (surface protection film: not shown), and a drain electrode 45 are formed by a general method. The portion of the source electrode 44 exposed in the opening of the passivation film becomes the source pad. Thereafter, the semiconductor wafer is diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10 of FIGS. 1 to 3.

[0105] As described above, according to the embodiment, a step is formed at the outer edge of the p-type peripheral region on the periphery of the active region, recessing inward in stages as the distance from the front surface of the semiconductor substrate increases. As a result, of the first to fourth peripheral regions constituting the p-type peripheral region, the first peripheral region is positioned closest to the front surface of the semiconductor substrate and terminates outermost, and an outer corner of the bottom of the first peripheral region becomes an electric field concentration point when the MOSFET is off, but the electric field concentration at the outer corner of the bottom is alleviated by the breakdown voltage structure adjacent to the outside of the first peripheral region.

[0106] According to the embodiment, the impurity concentration in the third outer peripheral region is set to p for reducing the electric field applied to the gate insulating film at the bottom of the trench in the center of the active region. + The impurity concentration of the third peripheral region is lower than that of the upper part of the p-type peripheral region, and the widths of the multiple steps at the outer edge of the p-type peripheral region are all the same. This makes it possible to optimize the impurity concentration of the third peripheral region and the positions of the outer edges of the first to fourth peripheral regions, thereby mitigating the electric field applied to the lower part of the p-type peripheral region (third and fourth peripheral regions) and the outer edge (step portion).

[0107] By reducing the electric field applied to the lower portion and outer edge of the p-type peripheral region, localized electric field concentration at the main junction edge (outer corner portion of the bottom of the p-type peripheral region) of the active region is suppressed, thereby improving the avalanche breakdown capability at the main junction edge of the active region. This suppresses a decrease in the breakdown voltage of the edge termination region, preventing the breakdown voltage of the edge termination region from becoming lower than the breakdown voltage of the active region. Therefore, the breakdown voltage of the active region can determine the overall breakdown voltage of the silicon carbide semiconductor device, improving reliability.

[0108] Furthermore, according to the embodiment, by appropriately changing the ion implantation mask pattern, a step can be formed at the outer edge of the p-type peripheral region without changing the method for forming the active region's element structure. Furthermore, by forming the third peripheral region at a different timing from each part of the active region, the impurity concentration in the third peripheral region can be appropriately set without changing the method for forming the active region's element structure. Therefore, it is possible to provide a highly reliable silicon carbide semiconductor device that can be easily formed and can stably ensure a predetermined breakdown voltage.

[0109] (Experimental example) The breakdown voltage characteristics of silicon carbide semiconductor device 10 according to the first embodiment described above (hereinafter referred to as an experimental example; see FIGS. 1 to 3) were examined. FIG. 4 is a characteristic diagram showing the results of simulating the breakdown voltage characteristics of the experimental example. The horizontal axis of FIG. 4 represents p + The vertical axis represents the ratio of the impurity concentration in the third outer periphery region 28 to the impurity concentration in the upper portion 24 of the mold region 22 (hereinafter referred to as the impurity concentration ratio of the third outer periphery region 28).

[0110] Figure 4 shows the results of simulations of the breakdown voltage of edge termination region 2 in experimental examples, in which the widths w1, w2, and w3 (width w1 = width w2 = width w3) of the steps at the outer end of p-type periphery region 25 and the impurity concentration of third periphery region 28 were variously changed. Figure 4 shows the simulation results of four experimental examples in which the widths w1, w2, and w3 (width w1 = width w2 = width w3) of the steps at the outer end of p-type periphery region 25 were set to 1 μm, 2 μm, 3 μm, and 4 μm.

[0111] 4 also shows, for comparison, the results of simulating the breakdown voltage of edge termination region 2 of the comparative example, labeled "no step." The comparative example differs from the experimental example in that the outer ends of first to fourth peripheral regions constituting p-type peripheral region 25 terminate at the same position and are on the same plane perpendicular to the front surface of semiconductor substrate 40. In other words, no step is formed at the outer end of p-type peripheral region 25 of the comparative example.

[0112] 4, it was confirmed that in the comparative example, the breakdown voltage of edge termination region 2 is almost constant regardless of the impurity concentration ratio of third periphery region 28, but is significantly lower at 1180 V than the design value (standard breakdown voltage) of the breakdown voltage of active region 1. Here, the design value of the breakdown voltage of active region 1 in the comparative example is a breakdown voltage (horizontal dashed line) slightly higher than 1600 V. Therefore, the comparative example is applicable to MOSFETs with a breakdown voltage class of 1200 V.

[0113] On the other hand, in the experimental example, the outer edge of p-type peripheral region 25 is formed with a step that gradually recesses inward in the depth direction as it moves away from the front surface of semiconductor substrate 40, and it was confirmed that this suppresses a decrease in the breakdown voltage of edge termination region 2, and that the breakdown voltage of edge termination region 2 approaches the design value of the breakdown voltage of active region 1. Here, the design value of the breakdown voltage of active region 1 in the experimental example is also a breakdown voltage (horizontal dashed line) that is slightly higher than 1600V.

[0114] In the experimental example, the widths w1, w2, and w3 of the steps formed at the outer end of the p-type peripheral region 25 were all equal to or greater than 2 μm, and the impurity concentration of the third peripheral region 28 was p + It was confirmed that when the impurity concentration of the upper portion 24 of the die region 22 is within the range of 0.1 times or more and 0.5 times or less than the design value of the breakdown voltage of the active region 1, the breakdown voltage of the edge termination region 2 is equal to or greater than the design value of the breakdown voltage of the active region 1, and the edge termination region 2 can be applied to MOSFETs with a breakdown voltage of 1600V class.

[0115] Furthermore, in the experimental example, it was confirmed that the wider the widths w1, w2, and w3 of the steps at the outer end of p-type periphery region 25 and the lower the impurity concentration of third periphery region 28, the higher the breakdown voltage of edge termination region 2. Specifically, when the widths w1, w2, and w3 of the steps at the outer end of p-type periphery region 25 were set to 4 μm, it was confirmed that the breakdown voltage of edge termination region 2 was up to 82 V higher than the design value of the breakdown voltage of active region 1.

[0116] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the active region structure shown in FIG. 2 is an example, and a planar gate structure, for example, can be used instead of the trench gate structure. That is, a p-type peripheral region is formed on the periphery of the active region, surrounding the periphery of the central portion of the active region, and a plurality of steps are formed at the outer end of the p-type peripheral region, recessed inward in stages as the distance from the front surface of the semiconductor substrate increases in the depth direction. The element structure of the active region can be modified as appropriate.

[0117] Alternatively, instead of the spatially modulated JTE structure, a general JTE structure may be provided in contact with a p-type peripheral region on the periphery of the active region and an insulating layer on the front surface of the semiconductor substrate. A general JTE structure is a structure in which multiple p-type regions (JTE regions) are concentrically arranged around the periphery of the active region, with the JTE regions having lower impurity concentrations as they move away from the center to the outside. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0118] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0119] 1 active area 1a Central part of the active region 1b Outer periphery of the active region 2 Edge Termination Area 10 Silicon carbide semiconductor device 11n + Type drain region 12n - Type Drift Region 13 p-type base region 13a: Second outer peripheral region (extension of p-type base region) 14n + Type Source Area 15,15c,15d p ++ Mold contact area 15a First outer region (outermost p ++ contact area) 15b: outer corner portion of the bottom of the first outer peripheral region 16 Trench 17 Gate insulating film 18 gate electrode 19 Interlayer insulating film 20 n-type current diffusion region 21 P under the trench + type area 22 p between adjacent trenches + type area 23 p between adjacent trenches + Bottom of the mold area 24 p between adjacent trenches + Top of the mold area 25 p-type outer region 25b: outer corner of bottom of p-type peripheral region 26 pages + type area 27 4th outer peripheral area 27b: the outer corner of the bottom of the fourth outer peripheral region 28 Third outer area 30 Pressure-resistant structure 30a,30c JTE area 30b, 30d Spatial modulation area 31 P-type region of the breakdown voltage structure 32 Pressure-resistant structure - type area 33n + Type channel stopper region 40 Semiconductor substrate 41n + Starting substrate 42, 42a, 42b, 42c n - mold silicon carbide layer 43 Ohmic electrode 44 Source electrode 45 Drain electrode 51 Field oxide 52 Gate polysilicon wiring layer 53 Gate metal wiring layer 61,62 n-type channel stopper region d1 Breakdown structure (p-type region and p - Depth of the mold area w1, w2, w3 Width of the step at the outer edge of the p-type peripheral region

Claims

1. a semiconductor substrate made of silicon carbide and having a first main surface that is flat over the entire surface; an active region provided in the semiconductor substrate; a termination region provided in the semiconductor substrate and surrounding the active region; a first semiconductor region of a first conductivity type provided within the semiconductor substrate across the active region and the termination region; a second semiconductor region of a second conductivity type provided between the first major surface and the first semiconductor region in the active region; an element structure including a pn junction between the first semiconductor region and the second semiconductor region, wherein a current flows through the pn junction; a second conductivity type outer periphery region provided between the first main surface and the first semiconductor region, between the element structure and the termination region, and surrounding the periphery of the active region; a breakdown voltage structure including a plurality of second conductivity type breakdown voltage regions spaced apart from one another and concentrically arranged to surround the active region in the termination region between the first main surface and the first semiconductor region; a first electrode provided on the first major surface and electrically connected to the second semiconductor region and the second conductivity type peripheral region; a second electrode provided on a second main surface of the semiconductor substrate and electrically connected to the first semiconductor region; Equipped with The device structure is a third semiconductor region of the first conductivity type selectively provided between the first major surface and the second semiconductor region and electrically connected to the first electrode; a trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region; a gate electrode provided inside the trench via a gate insulating film; a second conductivity type high concentration region having an impurity concentration higher than that of the second semiconductor region, the second conductivity type high concentration region being selectively provided between the first semiconductor region and the second semiconductor region and closer to the second main surface than a bottom surface of the trench, the second conductivity type outer peripheral region has, at an outer end thereof, a plurality of steps of the same width that are recessed inward in a stepwise manner as the region becomes farther away from the first main surface in a depth direction, and is composed of a plurality of outer peripheral regions that terminate more inward as the region becomes farther away from the first main surface according to the steps; The plurality of outer circumferential regions are a first outer peripheral region that is closest to the first main surface and that contacts an inner end of the pressure-resistant structure; a second peripheral region that is a portion of the second semiconductor region outside the element structure and adjacent to the first peripheral region on the second main surface side; a third outer peripheral region adjacent to the second outer peripheral region on the second main surface side; a fourth outer periphery region adjacent to the third outer periphery region on the second main surface side, the fourth outer periphery region having a lower surface at the same depth as a lower surface of the second conductivity type high concentration region.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the impurity concentration of the third outer peripheral region is lower than the impurity concentration of the second conductivity type high concentration region.

3. 3 . The silicon carbide semiconductor device according to claim 2 , wherein the impurity concentration of the third outer peripheral region is within a range of 0.1 to 0.5 times the impurity concentration of the second conductivity type high concentration region.

4. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the impurity concentration of the fourth outer peripheral region is equal to the impurity concentration of the second conductivity type high concentration region.

5. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the width of the step at the outer end of the second conductivity type peripheral region is not less than 1 μm and not more than 4 μm.

6. The second conductivity type high concentration region is a first second conductivity type high concentration region having an impurity concentration higher than that of the second semiconductor region, the first conductivity type high concentration region being selectively provided between the first semiconductor region and the second semiconductor region and facing a bottom surface of the trench; a second second-conductivity-type heavily doped region, having an impurity concentration higher than that of the second semiconductor region, selectively provided between the first semiconductor region and the second semiconductor region, spaced apart from the trench and the first second-conductivity-type heavily doped region and in contact with the second semiconductor region, the second second-conductivity-type heavily doped region reaching a position closer to the second main surface than a bottom surface of the trench; an upper surface of the third outer periphery region is at the same depth as an upper surface of the second second-conductivity-type high-concentration region, and has a lower impurity concentration than a portion of the second second-conductivity-type high-concentration region on the first main surface side; 2. The silicon carbide semiconductor device according to claim 1, wherein a lower surface of the fourth outer peripheral region is at the same depth as a lower surface of the second second conductivity type high concentration region, and has an impurity concentration equal to that of a portion of the second second conductivity type high concentration region on the second main surface side.

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