Monolithic LED arrays and their precursors

Abstract

A monolithic LED array precursor, comprising a plurality of LED structures sharing a first semiconductor layer, the first semiconductor layer defining a plane of the LED array precursor, each LED structure comprising: (i) a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a top surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion, such that the second semiconductor layer has sloping sides; (ii) a third semiconductor layer on the second semiconductor layer, the third semiconductor layer having a top surface portion parallel to the plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion, such that the third semiconductor layer has sloping sides parallel to the sloping sides of the second semiconductor layer; and (iii) a fourth semiconductor layer on the third semiconductor layer, the fourth semiconductor layer having a top surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a third (iv) a fourth semiconductor layer having a regular trapezoidal cross section perpendicular to a top surface portion thereof such that the fourth semiconductor layer has sloping sides parallel to the sloping sides of the fourth semiconductor layer; (iv) primary electrical contacts on the fourth semiconductor layer, the primary electrical contacts being only on the top surface portion of the fourth semiconductor layer that is parallel to the plane of the LED array precursor; (v) electrically insulating, optically transparent spacers on the sloping sides of the fourth semiconductor layer, the electrically insulating, optically transparent spacers having an inner surface facing the sloping side of the fourth semiconductor layer and an opposing outer surface; and (vi) an electrically conductive reflective layer extending over the outer surfaces of the spacers, wherein the third semiconductor layer includes a plurality of quantum well sublayers, the quantum well sublayers having greater thicknesses in portions parallel to the plane of the LED array precursor and reduced thicknesses in portions not parallel to the plane of the LED array precursor.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to monolithic LED arrays, LED devices including monolithic LED arrays, and methods of manufacturing the same. In particular, the present disclosure provides monolithic LED arrays with improved light emission. [Background technology]

[0002] The micro light-emitting diode (LED) array is 100 x 100 μm 2 It can be defined as an array of LEDs having a size of: Micro LED arrays are being developed for several commercial and military applications, such as self-emissive microdisplays and projectors, and can be incorporated into a variety of devices, such as wearable displays, heads-up displays, camcorders, viewfinders, multi-site excitation sources, and picoprojectors.

[0003] III-nitride-based microLEDs are inorganic semiconductor LEDs that contain GaN and its alloys with InN and AlN in the active light-emitting region. III-nitride-based microLEDs have become popular because they can be driven at significantly higher current densities and emit higher optical power densities than conventional large-area LEDs, especially organic light-emitting diodes (OLEDs), whose light-emitting layer is an organic compound. As a result, their optical power density (LED) is measured in candela per square meter (cd / m), which is defined as the amount of light emitted per unit area of ​​the light source in a given direction. 2 Higher luminance (brightness), also measured in nits (nt), makes microLEDs suitable for applications requiring or benefiting from high brightness, such as displays or projections in high-brightness environments.

[0004] Additionally, the high luminous efficacy, expressed in lumens per watt (lm / W), of III-nitride micro-LEDs allows for lower power usage compared to other light sources, making them particularly suitable for portable devices. Furthermore, the unique material properties of III-nitrides enable micro-LEDs to operate in extreme conditions, such as high or low temperatures and high or low humidity, thereby providing performance and reliability advantages in wearable and outdoor applications.

[0005] There are currently two main approaches for producing inorganic micro LED arrays. In the first approach, individual micro LED devices are produced using techniques similar to those for conventional-sized LEDs, and then these are assembled into an array on a substrate using pick-and-place techniques. The substrate can be an active matrix backplane containing driver circuits for addressing the individual micro LEDs. This first approach allows LEDs with different properties, such as different emission wavelengths, fabricated on different growth substrates to be transferred onto the product substrate to achieve full-color displays. In addition, it allows defective devices to be discarded before they become part of the array, potentially improving the final yield of the array. However, the resolution (small pitch) and array size (large number of micro LEDs) required in various applications pose significant challenges to this approach in terms of pick-and-place accuracy and transfer time, respectively affecting the reliability of the process and its throughput.

[0006] The second approach uses monolithic integration to fabricate micro LED arrays on a single growth substrate, thereby enabling higher integration density, smaller LEDs, and smaller pitch (i.e., higher array resolution). This second approach relies on colorization technology to achieve full-color displays. The shaping technology depends on the pitch of the micro-LED array. Conventional phosphor materials for lighting applications are currently only suitable for large-pitch, low-resolution arrays, while quantum dot-based wavelength conversion materials are required for higher-resolution applications. Regardless of the approach used, the perimeter of the active region of each micro-LED in the array is generally formed by an etching process that removes a portion of the light-emitting active region, thereby electrically isolating the individual micro-LEDs for the purpose of enabling independent current injection in each micro-LED and adjusting the amount of radiative recombination within each micro-LED in the array.

[0007] A less commonly employed fabrication process uses selective area growth (SAG) to achieve electrically isolated portions of the active region into which current can be independently injected without the use of an etching step, as disclosed in U.S. Pat. No. 7,087,932. In the selective area growth technique, a mask is patterned on the buffer layer. The material of the mask is such that, under growth conditions, additional material is not grown directly on the mask except only within openings that expose portions of the surface of the underlying buffer layer.

[0008] The brightness of III-nitride LEDs increases with increasing operating current, but the luminous efficacy decreases with increasing current density (A / cm 2 ), which initially rises as current density increases, reaches a maximum, and then declines due to a phenomenon known as "efficiency droop." Many factors contribute to the luminous efficiency of an LED device, including its ability to generate photons internally, called the internal quantum efficiency (IQE). The external quantum efficiency (EQE) is defined as the number of photons emitted in the active region divided by the number of electrons injected. EQE is a function of the IQE and light extraction efficiency (LEE) of the LED device. At low current densities, efficiency is low due to the strong influence of defects or other processes, called nonradiative recombination, in which electrons and holes recombine without generating light. As these defects saturate, radiative recombination dominates and efficiency rises. When the injected current density exceeds a characteristic value for the LED device, "efficiency droop," or a gradual decrease in efficiency, begins.

[0009] Surface recombination is believed to be the primary contributor to non-radiative recombination in micro-LEDs. Defects and dangling bonds around the periphery of the micro-LED active region interrupt the atomic lattice and introduce electronic energy levels inside the semiconductor band gap, which can enhance non-radiative recombination by acting as stepping stones for charge carrier transitions between the conduction and valence bands.

[0010] Surface recombination is particularly important in inorganic microLEDs due to their large perimeter to area ratio and the dry etching techniques commonly used to define the perimeter of the active region. Various techniques are known to those skilled in the art, including surface treatment using wet etchants or high temperature processes, or perimeter coating with a suitable "passivation layer" as disclosed in U.S. Pat. No. 9,601,659, which aims to mitigate damage and reduce dangling bonds around the active light-emitting region.

[0011] However, there remains a need for micro LED arrays and LED array precursors with high packing density, smaller LEDs and smaller pitches, and methods of producing the same, while avoiding problems associated with non-radiative recombination, particularly surface recombination.

[0012] Light emitting diode (LED) devices are further known to provide efficient light sources for a wide range of applications. Increased light generation efficiency and extraction of LEDs, along with the creation of smaller LEDs (with smaller light emitting areas) and the integration of different wavelength LED emitters into arrays, have led to the provision of high quality color arrays with multiple applications, particularly in display technology.

[0013] Several display technologies have been considered and used for microLED displays for use in various applications, including augmented reality, mixed reality, virtual reality, and direct-view displays such as smartwatches and mobile devices. Technologies such as digital micromirror devices (DMDs) and liquid crystal displays (LCoS) are based on reflective technologies, where an external light source is used to generate red, green, and blue photons in a time-sequential manner, and pixels redirect the light through optical elements (DMDs) or absorb light (LCoS) to adjust the brightness of the pixel to form an image. Liquid crystal displays (LCDs) typically use a backlight, an LCD panel on an addressable backplane, and color filters to generate images. The backplane must turn individual pixels on and off and adjust their brightness for each video frame. Emissive display technologies such as organic light-emitting diodes (OLEDs) or active-matrix OLEDs (AMOLEDs), and more recently, microLEDs, are gaining popularity as they offer low power consumption and high image contrast for untethered microdisplay applications. In particular, microLEDs offer higher efficiency and better reliability than microOLED and AMOLED displays.

[0014] Aspects of the invention described in this document relate to methods for creating high efficiency micro LED array bonding techniques that improve internal quantum efficiency (IQE) and light extraction efficiency (LEE) to improve advantageous efficiency and brightness characteristics.

[0015] Structures designed to increase light extraction efficiency are well known in the LED industry, including the use of quasi-parabolic LED structures that direct photons generated in a multiple quantum well (MQW) towards the light emitting surface.

[0016] One technique used to fabricate such quasi-parabolic shapes involves reactive ion etching (RIE) or inductively coupled plasma etching (ICP) of semiconductor materials. In such etching techniques, a high-energy plasma containing RF, high voltage (DC bias), and reactive gases, often including free radicals, is used to selectively etch the semiconductor material. Features are defined using a photolithographic process using a photosensitive material to define the areas that will undergo the etching process and the areas that will remain unetched. The precise shape of the semiconductor material can be controlled by the profile of the photosensitive material used to define the pattern and by the etching pressure, power, gas flow, and gas species.

[0017] This not only complicates the manufacturing process, but as a result of this etching process, the edges of the semiconductor material can be damaged, which affects the IQE of the micro LED.

[0018] As shown in Figure 9, as the DC bias and plasma density increase, more damage is inflicted on the edge of the feature, leading to surface leakage paths formed by crystal damage, nitrogen vacancies, and dangling bonds. Dry etching creates many crystal defects due to high-energy ion bombardment at the surface. The dangling bonds are prone to oxidation, and the crystal damage creates many defect levels in the energy bands that act as carrier recombination centers at the surface, leading to non-radiative recombination.

[0019] The surface recombination velocity (non-radiative recombination velocity) is faster than the radiative recombination velocity in bulk MQWs, and therefore small micro-LEDs are vulnerable to surface recombination and the resulting reduction in IQE.

[0020] A widely reported consequence of damage caused during etching is shown in Figure 10. As seen, there is a decrease in efficiency with smaller micro-LED dimensions. The external quantum efficiency (EQE) is the product of IQE (ratio of the number of generated photons to the number of electrons). The mechanism driving this trend is the ratio of the micro-LED perimeter to the area. As the size of the micro-LED decreases, the area of ​​the sidewalls increases relative to the area of ​​the MQWs. Therefore, the surface leakage path at the edge of the micro-LED causes an increase in non-radiative recombination.

[0021] MicroLED displays used in augmented reality and head-mounted displays have a current rating of 1A / cm 2 ~10A / cm 2 This may imply a 20-fold decrease in efficiency for small LEDs compared to large LEDs.

[0022] The efficiency of micro-LEDs can be significantly increased by repairing the damage caused by etching, as shown in Figure 11. Typically, implementing an optimized damage repair regime can result in a ten-fold improvement in EQE. The peak EQE increases after damage repair, and occurs at a lower current density, resulting in a ten-fold increase in efficiency at typical operating conditions. Such a regime, however, cannot be compared to maintaining a shaped structure optimized for high LEE because the repair process removes semiconductor material damaged by etching, as shown in Figure 12. Therefore, it is desirable to provide an alternative means of achieving such a quasi-parabolic LED structure. Summary of the Invention [Problem to be solved by the invention]

[0023] It is an object of the present invention to provide an improved LED array precursor, or at least to provide a commercially viable alternative thereto, that addresses at least one of the problems associated with prior art arrays. [Means for solving the problem]

[0024] According to a first aspect, the present disclosure provides a method of forming a monolithic LED array precursor, the method comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on a surface of a substrate; (iii) selectively masking the first semiconductor layer by depositing a mask layer on the first semiconductor layer, the mask layer including a plurality of openings; (iv) growing a second semiconductor layer on the unmasked portions of the first semiconductor layer through the openings in the mask layer to form a plurality of pillars, each pillar having a regular trapezoidal cross section perpendicular to the substrate with sloping sidewalls and a substantially flat top portion; (v) forming a third semiconductor layer overlying the second semiconductor layer, the third semiconductor layer including one or more quantum well sublayers and having a sloped sidewall and a substantially flat top surface portion; (vi) forming a fourth semiconductor layer overlying the third semiconductor layer, whereby the fourth semiconductor layer has an inclined side surface and a substantially flat top surface portion; (vii) forming a primary electrical contact on a substantially planar upper surface portion of the fourth semiconductor layer, the first to fourth semiconductor layers including a Group III nitride; (viii) forming an electrically insulating, optically transparent spacer on the inclined side surface of the fourth semiconductor layer, the spacer having an inner surface facing the inclined side surface of the fourth semiconductor layer and an opposing outer surface; (ix) depositing a reflective conductive layer on the outer surface of the spacer; Includes.

[0025] Further aspects of the invention will become apparent from the description, drawings, and appended claims. .

[0026] The present invention will now be further described. In the following text, different aspects of the invention are defined in more detail. Each aspect so defined may be combined with any other aspect, unless expressly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature indicated as being preferred or advantageous.

[0027] The present disclosure provides methods for forming monolithic LED array precursors so that electrically isolated LED structures can be produced exhibiting improved light emitting characteristics and reduced non-radiative recombination. The inventors have discovered that by growing the specific structures disclosed and providing electrical contacts only on specific regions of the LED structure, LED array precursors can be formed that provide LED devices with improved properties.

[0028] FIELD OF THE INVENTION The present invention relates to a method for forming a monolithic LED array precursor. LED is well known in the art and refers to a light emitting diode.

[0029] Monolithic array refers to the provision of multiple LED structures formed as a single piece. Array means that the LEDs are intentionally spaced across the monolithic structure, typically forming a regular array such as a hexagonally close-packed array or a square-packed array of LEDs.

[0030] It should be noted that by the term "precursor," the described LED array does not have the counter electrical contacts or associated circuitry required for each LED to enable light emission, etc. The described array is therefore a precursor to a monolithic LED array that will be formed once necessary further steps are performed, including counter electrodes and any light extraction surfaces, as may be achieved by removing the substrate.

[0031] The method involves several numbered steps, which it will be understood that to the extent possible, these steps may be performed simultaneously or in parallel.

[0032] The first step involves providing a substrate having a surface. Suitable substrates include sapphire, SiC, and silicon. Other suitable substrates are known in the art.

[0033] The second step involves forming a continuous first semiconductor layer on the surface of the substrate. The first semiconductor layer may function as a buffer layer. The first semiconductor layer, and indeed any further semiconductor layers, comprise a Group III nitride. Preferably, the Group III nitride comprises one or more of AllnGaN, AlGaN, InGaN, and GaN.

[0034] As used herein, any reference to a species by its constituent elements includes all available stoichiometries thereof. Thus, for example, AlGaN refers to Al x Ga 1-x N, where x is not equal to 1 or 0. The preferred stoichiometry will vary depending on the function of the particular layer.

[0035] The third step involves selectively masking the first semiconductor layer by depositing a mask layer containing a plurality of openings on the first semiconductor layer. Preferably, the mask layer is made of SiO2 and / or SiN. x Contains SiO2 and / or SiN x The mask layer can be deposited ex-situ using standard deposition techniques such as plasma enhanced chemical vapor deposition. Alternatively, in-situ SiN x The mask layer may be deposited in a reaction chamber, and suitable reaction chambers, such as MOCVD reactors, are well known in the art.

[0036] Optionally, the plurality of apertures form a regularly spaced array, which may resemble any arrangement for close packing of circles, such as a square packing or a hexagonal packing.

[0037] A preferred way to accomplish the third step is to By (a) depositing a continuous mask layer, and (b) selectively removing portions of the mask layer to provide a plurality of openings.

[0038] Optionally, selectively removing portions of the mask layer comprises selectively removing corresponding portions of the first semiconductor layer, meaning that a second, optionally discontinuous, layer is then formed in the wells of the first semiconductor layer.

[0039] A fourth step involves growing an optionally discontinuous second semiconductor layer through the openings in the mask layer and on the unmasked portions of the first semiconductor layer to form a plurality of pillars, each having a trapezoidal cross section perpendicular to the substrate and a substantially flat top portion, the flat top portion lying in a plane parallel to the plane of the substrate surface on which the layer is formed.

[0040] By "regular trapezoidal cross section," it is meant that the top of the pillar is narrower than the bottom and has generally flat, parallel top and bottom surfaces with sloping, straight sides. This may result in a truncated cone shape, or more likely a pyramidal trapezoid shape with three or more sides, typically six. The phrase "regular trapezoidal cross section" refers to a portion of the second semiconductor layer that extends above the first semiconductor layer. The bottom portion of the second semiconductor layer is within an opening defined by the first semiconductor layer, and therefore the bottom portion typically has a constant cross section rather than a tapered cross section. The tapered side of the pillar is referred to herein as a side or facet. If the second layer is continuous, the trapezoidal cross section is a discontinuous portion of the second semiconductor layer that extends above a continuous, planar portion of the second semiconductor layer.

[0041] Preferably, the side surface of the columnar portion has a substantially constant angle (α) with respect to a plane parallel to the first semiconductor layer. That is, the angle between the side surface of the columnar portion and the plane parallel to the first semiconductor layer does not change significantly. Preferably, the angle α is 50° to 70°, more preferably 58° to 64°, and most preferably about 62°.

[0042] Preferably, each of the plurality of pillars of the second semiconductor layer has a truncated hexagonal pyramid shape.

[0043] A fifth step involves forming an optionally discontinuous third semiconductor layer overlying the optionally discontinuous second semiconductor layer, the third semiconductor layer including one or more quantum well sublayers and having a substantially flat top portion and sloping side surfaces that conform to the shape of the underlying second semiconductor layer.

[0044] By "substantially planar upper surface portion" it is understood to mean that the top of a particular semiconductor layer is generally parallel to the first semiconductor layer (ie, provides a plane that is parallel to the plane of the substrate).

[0045] The inventors have discovered that deposition of the third semiconductor layer material on the second semiconductor layer occurs with a thicker top surface but a significantly thinner layer deposited on the facets, which occurs automatically due to growth rates in different directions relative to the crystalline structure.

[0046] The layers deposited on the inclined surfaces around the mask openings are generally thinner than the layers deposited on the c-plane oriented surfaces. In particular, the InGaN multiple quantum well (MQW) deposited between the n-doped and p-doped layers of the p-n junction in the LED is thinner on the inclined surfaces than on the c-plane oriented surfaces.

[0047] It is known to those skilled in the art that light emission from tilted GaN faces can provide a means of improving the efficiency of lighting devices due to the reduced polarization fields of semipolar faces. In addition, the presence of different MQW thicknesses on the tilted faces compared to the flat facets can also enable phosphor-free multi-wavelength emission from a single device for color tuning purposes.

[0048] In contrast, one objective of the present invention is to confine light generation to the generally flat surface region, preventing carrier injection and / or diffusion into the tilted surfaces and potential non-radiative recombination around the active region where the periodic arrangement of atoms in the crystal terminates. Carrier confinement in the upper flat region is achieved by restricting the formation of electrical contact regions to portions of the upper flat surface away from the tilted surfaces.

[0049] Additionally, the difference in MQW thickness between the portion of the MQW oriented along the c-plane and the portion of the MQW on the tilted facet corresponds to a bandgap difference between the two MQW portions, effectively preventing carrier diffusion from the flat MQW portion to the tilted MQW portion. This is a mechanism similar to that occurring around threading dislocations in III-nitride LEDs, where injected carriers are confined away from the threading dislocation core, preventing the possibility of non-radiative recombination. Concomitantly, the MQW composition in the region deposited on the facet can also differ from that of the thick top MQW, such that carrier confinement at the thick top surface still occurs. As a result, a uniform and relatively narrow emission wavelength is expected.

[0050] A sixth step involves forming an optionally discontinuous fourth semiconductor layer overlying the optionally discontinuous third semiconductor layer, whereby the fourth semiconductor layer has a substantially flat top portion and sloping side surfaces that conform to the shape of the underlying third and second semiconductor layers. Again, deposition of the fourth semiconductor layer material on the third semiconductor layer occurs with a thicker layer on the top surface but a much thinner layer deposited on the facets.

[0051] Preferably, the fourth semiconductor layer is doped with magnesium. Optionally, to further aid in confining carrier injection to the thick top surface of the third semiconductor layer, the Mg doping density is higher in the thick top surface but much lower in the layer deposited on the facet.

[0052] Preferably, the second, third, and fourth semiconductor layers are discontinuous. Preferably, the mask method of the first aspect produces discontinuous layers, but in some embodiments with particularly dense pitch, the third, fourth, and fifth semiconductor layers may merge, such that these layers form a continuous or partially continuous portion shared by several LED structures.

[0053] The first semiconductor may have a thickness of 100 nm to 8 μm, preferably 3 μm to 5 μm.

[0054] The columnar portion of the second semiconductor layer may have a thickness of 500 nm to 4 μm, preferably 1 μm to 2 μm.

[0055] The substantially flat upper surface portion of the third semiconductor layer may have a thickness of 30 nm to 150 nm, preferably 40 nm to 60 nm. In addition, the mask opening / pyramid width may be 1 μm to 8 μm.

[0056] The substantially flat upper surface portion of the fourth semiconductor layer may have a thickness of 50 nm to 300 nm, preferably 100 nm to 150 nm.

[0057] The portions of the semiconductor layer that are not aligned with the openings in the mask may range from 0 nm up to those mentioned above. The masked areas have thicknesses up to the minimum of each layer, and are less favorable to the growth of subsequent semiconductor layers, but may not completely prevent them.

[0058] The seventh step involves forming a primary electrical contact on the substantially planar top surface portion of the optionally discontinuous fourth semiconductor layer. Any conventional electrode material may be used, which may be applied by conventional techniques such as thermal evaporation or electron beam evaporation.

[0059] Optionally, the primary electrical contact is formed by depositing a transparent conductive oxide, such as indium tin oxide, to form a lens-like structure on the flat top surface portion of the fourth semiconductor layer, the outer surface of the transparent conductive oxide being generally convex or particularly circular or parabolic in shape.

[0060] The eighth step involves forming an electrically insulating, optically transparent spacer on the inclined side of the fourth semiconductor layer, the spacer having an inner surface facing the inclined side of the fourth semiconductor layer and an opposing outer surface. Preferably, the outer surface of the spacer is angled relative to the inner surface, and more preferably, the outer surface of the spacer has a quasi-parabolic profile. The parabolic shape acts to direct emitted photons toward the light-emitting surface of the device so that the emitted photons are incident on the surface at an angle of incidence less than the critical angle, thereby allowing the photons to be extracted into air with high efficiency.

[0061] Preferably, the outer surface of the spacer has a profile that approximates a Bezier curve having two control points with a Bezier coefficient of 0.5, which has been found to provide maximum light extraction. In one embodiment, the spacer is formed from silicon nitride, silicon oxide, or tin oxide.

[0062] Optionally, a second electrically insulating, optically transparent material on the outer surface of each spacer has a different refractive index than the first electrically insulating, optically transparent material. This allows for the use of materials with graded refractive indices so that emitted photons can be more easily extracted. In further embodiments, additional spacer layers may be used with reduced refractive indices away from the sloped side of the fourth semiconductor layer.

[0063] The ninth step involves forming a reflective conductive layer on the outer surface of the spacer. In one embodiment, the reflective conductive layer is formed from aluminum, although one skilled in the art will recognize that any suitable material may be used. In one embodiment, the interface between the spacer and the reflective conductive layer has a surface roughness of Ra<50 nm, most preferably Ra<10 nm, to prevent light diffusion, which reduces light extraction efficiency.

[0064] Each of the above-mentioned layers may be formed from one or more sublayers. For example, the first semiconductor layer may be Al x Ga 1-xIt can be formed from a N compositionally graded layer.

[0065] Optionally, the first semiconductor layer includes a sublayer proximate the second semiconductor layer, the sublayer including silicon-doped GaN. Preferably, the first semiconductor layer is substantially undoped except for the silicon-doped sublayer. In one embodiment, the first semiconductor layer includes a plurality of undoped (Al)GaN sublayers and a silicon-doped sublayer. The silicon-doped Al x Ga 1-x The N sublayer may have a thickness of 100 nm to 1 μm, preferably 300 nm to 500 nm. Preferably, the Al composition is x=0 to 0.2, more preferably 0.05 to 0.1. Preferably, the doping level is 1×10 18 at / cm3~1×10 21 at / cm3, more preferably 1×10 20 at / cm 3 ~2×10 20 at / cm 3 is.

[0066] Preferably, when the first semiconductor layer includes a silicon-doped sublayer, the second semiconductor layer The silicon-doped sublayer is partially removed when forming the plurality of openings so that the (Al)GaN:Si sublayer is formed directly on the undoped portion of the first semiconductor layer. Advantageously, this structure allows for the use of a highly silicon-doped layer for beneficial current spreading without degrading material quality, since the (Al)GaN:Si sublayer is removed where the second semiconductor is grown.

[0067] All of the above deposition steps can be performed using conventional semiconductor deposition systems. The deposition of semiconductor layers for LED production is well known in the art, such as MOCVD.

[0068] As will be appreciated, each of the pillars of the second semiconductor layer provides a base for an individual LED structure formed from the associated layer in the final monolithic LED array precursor.

[0069] A further aspect of the invention provides a similar method, but with an alternative approach for forming the second semiconductor layer. All aspects of the first aspect described above may be freely combined with this embodiment.

[0070] In this further embodiment, the first semiconductor layer is treated to provide a pattern of amorphous material that is less favorable for subsequent layer growth. This means that the second semiconductor layer will preferentially form over the crystalline untreated areas, resulting in columnar sections. This layer can be continuous or discontinuous, depending on the relative growth achieved in the treated and untreated areas. The trapezoidal cross section is a discontinuous portion of the second semiconductor layer that extends above a continuous, planar portion of the second semiconductor layer.

[0071] Specifically, this further aspect provides a method of forming a monolithic LED array precursor, the method comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on a surface of a substrate; (iii) selectively treating the first semiconductor layer to form an amorphous surface region, the amorphous surface region defining a plurality of untreated portions of the first semiconductor layer; (iv) growing a second semiconductor layer on the untreated portion of the first semiconductor layer to form a plurality of pillars, each pillar having a trapezoidal cross section perpendicular to the substrate and a substantially flat top surface portion; (v) forming a third semiconductor layer overlying the second semiconductor layer, the third semiconductor layer including one or more quantum well sublayers and having a substantially planar top surface portion; (vi) forming a fourth semiconductor layer overlying the third semiconductor layer, whereby the fourth semiconductor layer has a substantially flat upper surface portion; and (vii) forming a primary electrical contact on the substantially flat upper surface portion of the fourth semiconductor layer, where the first to fourth semiconductor layers include a Group III nitride.

[0072] Optionally, the first semiconductor layer includes a sublayer proximate the second semiconductor layer, the sublayer including silicon-doped GaN. Preferably, the first semiconductor layer is substantially undoped except for the silicon-doped sublayer. That is, preferably, the first semiconductor layer includes a plurality of undoped (Al)GaN sublayers and a silicon-doped sublayer.

[0073] Preferably, selectively treating the first semiconductor layer comprises amorphizing a surface portion of the first semiconductor layer by ion implantation. Preferably, selectively treating comprises a lithographic patterning and etching step followed by ion implantation. Suitable ions for implantation may be selected from N+, H+ and Ar+. Advantageously, lithographic patterning and etching with a suitable mask pattern prevents ion damage to etched remaining areas of the first semiconductor layer.

[0074] Optionally, in the method of the second aspect, step (iii) comprises: (a) depositing a continuous mask layer comprising a mask layer material on a continuous first semiconductor layer; (b) selectively removing mask layer material to provide a plurality of mask regions of the first semiconductor layer; (c) treating the first semiconductor layer with ion implantation to form amorphous material in the first semiconductor layer except for the masked areas; and (b) removing the remaining mask layer material and, optionally, removing a plurality of corresponding portions of the first semiconductor layer to provide a plurality of untreated portions of the first semiconductor layer.

[0075] Preferably, if the first semiconductor layer includes a silicon-doped sublayer, the silicon-doped sublayer is partially removed when forming the plurality of openings, such that the second semiconductor layer is formed directly on the undoped portion of the first semiconductor layer. Advantageously, this structure allows for the use of a highly silicon-doped layer for beneficial current spreading without degrading material quality, since the AlGaN:Si sublayer is removed where the second semiconductor layer was grown.

[0076] Preferably, in the method of the second aspect, the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer are discontinuous.

[0077] The following disclosure relates to preferred features that are equally applicable to both of the above-mentioned aspects.

[0078] Preferably, the second semiconductor layer is n-type doped. Preferably, the second semiconductor layer is n-type doped with silicon or germanium, preferably silicon.

[0079] Preferably, the third semiconductor layer is undoped.

[0080] Preferably, the fourth semiconductor layer is p-type doped, and preferably the fourth semiconductor layer is doped with magnesium.

[0081] Advantageously, the above layer compositions provide an LED active region with good light generation and emission properties.

[0082] Preferably, the first semiconductor layer has a wurtzite-type crystal structure with a (0001) plane, and the substantially flat top surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer. Similarly, each of the flat top surfaces of the second and third semiconductor layers should be parallel to the (0001) plane of the first semiconductor layer.

[0083] Preferably, the method further includes removing the substrate to facilitate light extraction from the bottom of the fabricated device (which is flipped over when used). Alternately, at least a portion of the substrate is removed corresponding to each of the individual LED structures described above to expose a portion of the first semiconductor layer for light extraction from the array precursor. Preferably, the substrate is completely removed, and optionally, a roughened layer is applied to the exposed first semiconductor layer. The substrate, also known as a growth substrate, provides a surface on which the LED array is grown, but generally does not form part of the final device. Preferably, the substrate is substantially completely removed to minimize absorption in the case of a non-transparent substrate such as Si, or to minimize crosstalk between LED structures in the array in the case of a transparent substrate such as SiC or sapphire.

[0084] Optionally, the substrate is selectively removed to form a plurality of collimating channels, each of the collimating channels being formed on a substantially planar top surface portion of the fourth semiconductor layer. The next point is aligned.

[0085] Optionally, the method further includes providing the steps of at least partially removing the substrate and at least partially removing the first semiconductor layer to form a plurality of dome or lens structures corresponding to and aligned with each of the plurality of pillars in the second semiconductor layer. Preferably, the method includes completely removing the substrate and partially removing the first semiconductor layer to provide a plurality of convex domes distal to the second semiconductor layer, each dome aligned with one of the plurality of LED structures in the array.

[0086] Advantageously, the dome structure improves light extraction and collimation of the LED structure without the need for additional materials. Preferably, the dome structures can be coated with a dielectric coating or a clear epoxy layer to minimize reflections on the surface of the dome.

[0087] Preferably, the method may further comprise providing one or more transparent insulating layers followed by a reflective layer on at least a portion of the fourth semiconductor layer distal to the third semiconductor layer where the primary electrical contact is not provided. Preferably, the insulating layers are made of SiO2 and / or SiN x Advantageously, such coating layers may improve light extraction from the LED structure by reducing light losses within the array and improve collimation of the extracted light.

[0088] Optionally, the method further includes forming one or more secondary electrical contacts in electrical communication with the primary electrical contact across the quantum well sublayer to form a monolithic LED array. The provision of the secondary electrical contacts provides all the necessary features for the LED array to function: applying a potential difference across the primary and secondary contacts causes the LED structure to produce light.

[0089] Preferably, one or more secondary electrical contacts are formed on the first semiconductor layer, and even more preferably, the secondary electrical contacts are provided by a transparent conductive oxide layer in contact with the first semiconductor layer.

[0090] The formed monolithic LED array precursor preferably includes at least four LED structures, each LED structure corresponding to a separate second semiconductor layer portion, a corresponding third semiconductor layer portion formed thereon, a corresponding fourth semiconductor layer portion formed thereon, and a corresponding primary electrical contact formed thereon. The LED array precursor is preferably a micro LED array.

[0091] Preferably, the monolithic LED array precursor includes at least a first sub-array and a second sub-array of LED structures, each sub-array capable of emitting light at a different dominant wavelength.

[0092] In a further aspect, the present disclosure provides a monolithic LED array precursor, preferably obtainable by one of the methods described in the above aspects. Accordingly, all aspects described in relation to structures formed by the above methods apply equally to the precursor described herein.

[0093] In a further aspect, the present disclosure provides a monolithic LED array precursor comprising: a plurality of LED structures sharing a first semiconductor layer, the first semiconductor layer defining a plane of the LED array precursor, each LED structure comprising: (i) a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a top surface portion parallel to a plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the second semiconductor layer has sloped sides; (ii) a third semiconductor layer on the second semiconductor layer, the third semiconductor layer having a top surface portion parallel to a plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the third semiconductor layer has sloped sides parallel to the sloped sides of the second semiconductor layer; (iii) a fourth semiconductor layer on the third semiconductor layer, the fourth semiconductor layer having a top surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the fourth semiconductor layer has sloping sides parallel to the sloping sides of the third semiconductor layer; (iv) a primary electrical contact on the fourth semiconductor layer, the primary electrical contact being on only a top surface portion of the fourth semiconductor layer that is parallel to the plane of the LED array precursor; A monolithic LED array precursor is provided, wherein the third semiconductor layer includes a plurality of quantum well sublayers, the quantum well sublayers having a greater thickness in portions parallel to the plane of the LED array precursor and a reduced thickness in portions not parallel to the plane of the LED array precursor.

[0094] In one embodiment, the fourth semiconductor layer is made of pGaN. In an alternative embodiment, the fourth semiconductor layer is made of p-AlGaN to further insulate the sidewalls. In this embodiment, the Al content of the sidewall region is higher than the planar region, further insulating the sidewalls so that current injection occurs only through the planar region.

[0095] Preferably, the LED array precursor includes a mask portion at the interface between the first semiconductor layer and the second semiconductor layer. The mask portion of the LED precursor may be the same as that described with respect to the first embodiment above. Alternatively, the LED array precursor may have an amorphized portion of the first semiconductor layer created by ion implantation.

[0096] Preferably, the distance from the inclined side surface of the second semiconductor layer to the inclined side surface of the third semiconductor layer is smaller than the distance from the top surface portion of the second semiconductor layer to the top surface portion of the third semiconductor layer.

[0097] Preferably, the distance from the inclined side surface of the third semiconductor layer to the inclined side surface of the fourth semiconductor layer is smaller than the distance from the top surface portion of the third semiconductor layer to the top surface portion of the fourth semiconductor layer.

[0098] Optionally, the second, third and fourth semiconductor layers are shared among the LED structures in the array, as may occur when the precursor is fabricated using the second embodiment described above, which has an amorphous substrate pattern that prevents subsequent overlay growth.

[0099] Preferably, the plurality of LED structures form a regularly spaced array. Preferably, the second to fourth layers of LED structures are in the shape of a truncated hexagonal pyramid.

[0100] Advantageously, the above layer compositions provide an LED active region with good light generation and extraction properties.

[0101] Preferably, the first semiconductor layer has a wurtzite crystal structure with a (0001) plane, and the substantially flat top surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer.

[0102] Preferably, the LED structures of the LED array precursor include a shared light extraction layer on the first semiconductor layer on a surface distal from the second semiconductor layer. In one embodiment, the shared light extraction layer includes a plurality of collimating channels, each collimating channel aligned with a primary contact. Alternatively, the first semiconductor layer corresponds to a plurality of LED structures on a surface distal from the second semiconductor layer. and forming a plurality of dome or lens structures aligned with the plurality of LED structures.

[0103] In a further aspect, the present disclosure provides a monolithic LED array comprising the monolithic LED array precursor described herein, further comprising one or more secondary electrical contacts in electrical communication with the primary electrical contact across the quantum well sublayer. The array is based on the precursor as described above, and preferably obtained from the method described herein. Accordingly, all features described in those aspects apply equally to this further aspect.

[0104] Preferably, the monolithic LED array includes at least four LED structures. The LED array is preferably a micro LED array. Preferably, the monolithic LED array includes at least first and second sub-arrays of LED structures, each capable of emitting light at a different dominant wavelength. Preferably, the light generating layer in each sub-array emits light in a narrow wavelength bandwidth, preferably in the range of 370 nm to 680 nm, more preferably 440 nm to 550 nm.

[0105] In a further aspect, the present disclosure provides a display device comprising the monolithic LED array disclosed herein. Preferably, the methods of the present disclosure are suitable for producing the LED array precursors and LED arrays disclosed herein.

[0106] The present invention will now be described in connection with the following non-limiting drawings. Further advantages of the present disclosure will become apparent by reference to the detailed description when considered in conjunction with the drawings. The drawings are not to scale to more clearly show details. Like reference numerals refer to like elements throughout the several views. [Brief explanation of the drawings]

[0107] [Figure 1A] Figure 1 shows an LED array precursor according to a first embodiment: Figure 1a shows a plan view of the LED array precursor; [Figure 1B] 1 shows a cross section of an LED array precursor. [Figure 2] 1 shows a cross section of a portion of an LED array precursor according to a second embodiment. [Figure 3] 1 shows a cross section through an embodiment of an LED array precursor, where the first semiconductor layer includes a silicon-doped surface layer. [Figure 4A] 1 shows further details of the LED structure of the LED array precursor according to the first embodiment. [Figure 4B] 1 shows further details of the LED structure of the LED array precursor according to the first embodiment. [Figure 4C] 1 shows further details of the LED structure of the LED array precursor according to the first embodiment. [Figure 4D] 1 shows further details of the LED structure of the LED array precursor according to the first embodiment. [Figure 4E] 1 shows further details of the LED structure of the LED array precursor according to the first embodiment. [Figure 5A] 1 shows simulated light extraction efficiency values ​​and full width half maximum beam angles for LEDs of the present disclosure. [Figure 5B] 1 shows simulated light extraction efficiency values ​​and full width half maximum beam angles for LEDs of the present disclosure. [Figure 5C] 1 shows simulated light extraction efficiency values ​​and full width half maximum beam angles for LEDs of the present disclosure. [Figure 6A]1 shows scanning electron microscope (SEM) images and atomic force microscope (AFM) measurements for micro-LEDs of the present disclosure. [Figure 6B] 1 shows scanning electron microscope (SEM) images and atomic force microscope (AFM) measurements for micro-LEDs of the present disclosure. [Figure 6C] 6d-6e show scanning electron microscope (SEM) images and atomic force microscope (AFM) measurements for a micro LED of the present disclosure, and illustrate the light path within a micro LED of the present disclosure with and without a convex dome. [Figure 7] 1 shows an LED array of the present disclosure. [Figure 8] 1 shows an image of an LED array of the present disclosure. [Figure 9] [Figure 10] [Figure 11] [Figure 12] [Figure 13] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 14A] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 14B] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 15A] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 15B] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 16A] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 16B] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 17] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 18A] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 18B] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 19A] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 19B] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 20A] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 20B] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 20C] 1 illustrates an LED structure and its manufacturing process according to a further embodiment of the present disclosure. [Figure 21A] 1 shows an LED structure according to a further embodiment of the present disclosure. [Figure 21B] 1 shows an LED structure according to a further embodiment of the present disclosure. [Figure 22A] 1 shows the simulated light coupling efficiency and angular distribution of light emitted from an LED structure of the present disclosure. [Figure 22B] 1 shows the simulated light coupling efficiency and angular distribution of light emitted from an LED structure of the present disclosure. [Figure 23A] 1 shows the simulated light coupling efficiency and angular distribution of light emitted from an LED structure of the present disclosure. [Figure 23B] 1 shows the simulated light coupling efficiency and angular distribution of light emitted from an LED structure of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0108] Figure 1a shows a plan view of a portion of an LED array precursor according to a first embodiment of the present disclosure, and Figure 1b shows a vertical cross section along line S1.

[0109] The LED array precursor 1 of FIG. 1 includes a growth substrate (100), a first semiconductor layer (110), a mask layer (120), a discontinuous second semiconductor layer (130) including a plurality of pillars, a discontinuous third semiconductor layer (140) including a plurality of quantum well sublayers (141), a discontinuous fourth semiconductor layer (150), and a primary electrical contact (160) on a substantially planar top surface portion of the discontinuous fourth semiconductor layer (150).

[0110] The trapezoidal cross section of the second semiconductor layer 130 can be seen in cross section. In the illustrated embodiment, the sloped portions of the third and fourth semiconductor layers 140 and 150 are thinner than the portions parallel to the substantially flat top surface portion. Similarly, the sloped portions of the quantum well sublayer 141 are thinner than the portions parallel to the substantially flat top surface portion of the second semiconductor layer 130.

[0111] In the plan view of Figure 1b, the hexagonal shape of the posts can be seen as the top surface of the fourth semiconductor layer (150), with primary electrical contacts (160) isolated in the middle of each post, and the area between the posts is the top surface of the mask layer (120).

[0112] The LED array precursor of Figure 2 includes a growth substrate (100), a first semiconductor layer (110), an amorphous surface region (121) of the first semiconductor layer, a second semiconductor layer (130) including a plurality of pillars, a third semiconductor layer (140) including a plurality of quantum well sublayers (not shown), a fourth semiconductor layer (150), and a primary electrical contact (160) on a substantially planar top surface portion of the discontinuous fourth semiconductor layer (150).

[0113] In the embodiment of FIG. 2, the second semiconductor layer (130), the third semiconductor layer (140) and the fourth semiconductor layer (150) are continuous.

[0114] 3 shows a cross section of a single LED structure of an inventive LED array precursor, in which the first semiconductor layer (110) includes a silicon-doped sublayer (190) on a surface proximal to the second semiconductor layer (130). Additionally, during formation of the mask layer (120), the first semiconductor layer is partially removed below the opening in the mask layer such that the second semiconductor layer (130) penetrates into the first semiconductor layer (110) through the silicon-doped sublayer (190).

[0115] Figure 4a shows a single LED structure of a first embodiment of an LED array precursor, in which the growth substrate has been completely removed and the first semiconductor layer (110) has been shaped into a dome aligned with the LED structure. In the LED structure of Figure 4b, the surface of the dome is coated with a dielectric coating or clear epoxy layer (115) to minimize reflections at the surface of the convex dome. In Figure 4c, the dome is coated as in Figure 4b, and the surface of the posts is coated with SiO2 and / or SiN x The fourth semiconductor layer (150) is coated with a transparent layer and a reflective layer (170). Specifically, the exposed surfaces of the sloped portions of the fourth semiconductor layer (150) are coated. Advantageously, these features (dome, dome coating, and coating on the side of the posts) improve light extraction and collimation.

[0116] The inventors have discovered that adding a dome-shaped region aligned with the pyramid base enhances light extraction from the pyramid, as shown in Figures 4a-4c. Advantageously, this complements the collimation effect achieved by total internal reflection at the pyramid sidewalls. Preferably, the dome-shaped region has a radius of curvature that matches the size of the base of the pyramid. That is, the base of the dome-shaped region and the base of the pyramid are preferably approximately They are the same size.

[0117] Figures 4d and 4e show exemplary light paths within a micro LED in accordance with the present invention. Comparing Figure 4d with Figure 4e, the addition of a convex dome aligned with the pyramid base reduces the amount of light reflected inside the micro LED at the light extraction surface (the surface where light escapes from the LED), thereby further improving light extraction efficiency.

[0118] 5a-5c show simulated light extraction efficiency values ​​and full-width half-maximum beam angles for three model LEDs of the present disclosure. Specifically, FIG. 5a corresponds to an LED with uncoated post sides, FIG. 5b with SiO2-coated sides, and FIG. 5c with Ag / Si3N4-coated sides.

[0119] In comparison to known structures aimed at improving light extraction from conventional LEDs, in which pyramids are etched on the surface distal from a flat and infinite light-generating region, the light-generating region in the disclosed invention is entirely contained within a pyramidal structure, thereby substantially preventing light propagation in the lateral direction (parallel to the LED layers).

[0120] Compared to yet another class of known similar structures in which the light-generating region is entirely contained within inclined surfaces obtained by dry etching for the purpose of improving light extraction (see, for example, U.S. Pat. No. 7,518,149), the inclined facets obtained by the selective area growth process are superior in terms of light extraction because they are smoother than the surfaces obtained by dry etching, thereby promoting total internal reflection at the inclined sidewalls and collimating a higher proportion of the generated light towards the light-extraction surface that intersects them at an angle close to perpendicular.

[0121] Figure 6a shows an SEM image and Figure 6b shows an AFM measurement of a micro LED according to the present disclosure. Figure 6c is a cross section of the AFM measurement in Figure 6b showing in more detail the topography of the micro LED corresponding to the sidewall. The images demonstrate that the method disclosed in this invention produces smooth micro LED sidewalls.

[0122] The differential growth rate on different crystal planes compared to anisotropic dry etching results in more consistent and reproducible sidewall slopes, generally with angles close to 62° (α in Figure 4a) with the base of the pyramid, as shown by the AFM cross section in Figure 6c.

[0123] It will be understood by those skilled in the art that the improvement in light extraction obtained by the presence of sloped sidewalls surrounding the light-generating region is attributable to the effect of total internal reflection, while the enhanced light extraction obtained by adding a dome-shaped region results from a reduction in total internal reflection at the light extraction surface, since most of the light is already partially collimated by the sloped facets and therefore intersects the internal dome surface at an angle close to perpendicular. Therefore, obtaining the dome by dry etching does not constitute a detriment to the working principle disclosed herein, given that light extraction from the dome-shaped surface does not rely on total internal reflection.

[0124] Figure 7 shows a cross section through an LED array of the present disclosure. The LED array of Figure 7 includes the LED array precursor of Figure 1. The array precursor is flipped over and attached to a backplane including a backplane substrate (200) and backplane contact pads (202). The growth substrate of the LED array precursor is removed, and a roughened layer (112) is laminated onto the exposed surface of the first semiconductor layer (110). In addition, a secondary electrical contact (180) is attached to the first semiconductor layer. The primary and secondary electrical contacts are in electrical contact with each other through the LED structure.

[0125] It should be understood that the various embodiments described above and below may be combined into a single LED device. As will be understood by those skilled in the art, for example, the dome, dome coating 115, and coated side surfaces of the posts (170) as shown in Figure 4 can be combined with the silicon doped sublayer (190) of Figure 3.

[0126] FIG. 13 illustrates an LED structure according to a further aspect of the present disclosure. The LED structure is as described above in connection with FIGS. 1-4, with the additional feature of spacers 300 located on the inclined surfaces of the fourth semiconductor layer 150. The spacers 300 are formed from silicon dioxide, having a refractive index of n1. In alternative embodiments, the spacers are formed from silicon nitride or titanium oxide. While the outer surfaces of the spacers have a quasi-parabolic profile in the illustrated embodiment, they may have any suitable profile described by a range of Bézier curves having two control points and a coefficient B, where B is one of 0.1, 0.5, 0.2, and 0.05. In a preferred embodiment, the Bézier coefficient is 0.5, resulting in spacers with substantially straight sides that angle outward from the sidewalls.

[0127] In one embodiment, the spacer 300 is formed from an inner portion and an outer portion having refractive indices n1 and n2, respectively. In a preferred embodiment, n1>n2, which may be achieved by using silicon nitride as the inner spacer material and aluminum oxide as the second spacer material. In a further embodiment, an additional spacer layer is formed on the fourth semiconductor layer 150 (i.e., n1>n2>n N ) can be used with a decreasing refractive index away from the sidewalls. Although depicted as two separate spacers in the schematic of Figure 13, the spacer may actually be formed as a continuous layer surrounding the light-emitting structure.

[0128] Also shown is a reflective conductive layer 310 extending over the outer surface of the spacer 300. In one embodiment, the reflective conductive layer 310 is formed from aluminum or silver and has a surface roughness of Ra=50 nm. In a preferred embodiment, the surface roughness is Ra<10 nm to prevent light diffusion, which would reduce the light extraction efficiency of the device. In addition to covering the outer surface of the spacer 300, the reflective conductive layer 310 may also extend over any portion of the fourth semiconductor layer 150 that is not covered by the spacer 310 or the primary electrical contact 160 to act as a current spreading layer.

[0129] 14-16 illustrate the fabrication process for an LED array corresponding to the structure shown in FIG. 13. Starting with the structure shown in FIG. 1b, spacers are deposited on the inclined surfaces of the fourth semiconductor layer 150 (FIG. 14b). In one embodiment, the inclined surfaces are first sidewall passivated by applying a layer of silicon dioxide, aluminum oxide, or cubic aluminum nitride before a conformal film of silicon dioxide, silicon nitride, or tin oxide is deposited. This is then subjected to a global etch-back process to form the desired spacer shape. Optionally, the surface roughness of the underlying inclined surfaces can be adjusted by either dry etching or using a photolithographic resist with an appropriate resist profile. Advantageously, roughened sidewalls have been found to improve luminance uniformity and enhance light extraction from the LED structure, while after the addition of the spacers 300, the profile of the LED structure can be shaped as desired.

[0130] A reflective conductive material 310 is then deposited on the spacers 300 and / or exposed portions of the fourth semiconductor layer 150 to further enhance light extraction efficiency (FIG. 15a).

[0131] The growth substrate and LED structures are then flipped over by known processes and aligned and bonded to a CMOS backplane wafer (Figure 15b). The backplane wafer includes a backplane substrate (200) and backplane contact pads (202). The growth substrate of the LED array precursor is then removed (Figure 16a) and a transparent conductive oxide layer 330 is applied to the exposed surface of the first semiconductor (110). In one embodiment, layer 330 is formed from indium tin oxide (ITO) and electrically connects the primary contacts to the respective LED structures. In a further embodiment, layer 330 may be patterned or shaped to provide light extraction features (such as lenticular structures) above each LED structure.

[0132] To further increase light extraction efficiency, the refractive index of the transparent conductive oxide layer 330 can be varied through varying the porosity of the transparent conductive oxide. One known method for varying the porosity of transparent conductive oxides such as ITO is oblique deposition using electron beam evaporation. By varying the angle of the deposition plane relative to the full vapor deposition, the amount of shadow cast by the as-deposited material can be controlled, thereby controlling the porosity of the as-formed layer. Further discussion of oblique deposition for ITO can be found in at least one publication, "Light-Extraction Enhancement of GaInN Light Emitting Diodes," in by Graded-Refractive-Index Indium Tin Oxide Anti-Reflection Contact”, Jong Kyu Kim et.al., Advanced Materials, vol.20, no.4 pp. 801-804 (2008).

[0133] In use, a current is applied across the LED structure. Light emitted by the quantum wells is directed towards the emitting light either directly or by i) reflection and / or refraction at the interface with the spacer 300, ii) by the reflective conductive layer 310, or iii) by multiple reflections within the structure including a combination of the above. The LED structure is therefore positioned to increase the proportion of light incident on the light-emitting surface within a critical angle range to allow light transmission.

[0134] 17 shows a further embodiment in which the primary electrical contact is formed using a transparent conductive oxide 320 having a generally convex outer surface over which a reflective conductive layer 310 extends, allowing the p-contact 160 to function as an extended reflector that acts to narrow the emission angle of light emitted from the LED structure.

[0135] 18-20 illustrate the fabrication process for an LED array corresponding to the structure shown in FIG. 17. Starting with the structure shown in FIG. 1b (but before the formation of the primary electrical contacts 160), spacers are formed on the inclined surfaces of the fourth semiconductor layer 150 (FIG. 18b). A transparent conductive oxide 320 is then deposited on the exposed surfaces of the fourth semiconductor layer (FIG. 19a) and shaped by known chemical or mechanical means to provide a convex outer surface. A reflective conductive material is then deposited on the spacers 300, the transparent conductive oxide 320, and / or the exposed portions of the fourth semiconductor layer 150 to further enhance light extraction efficiency (FIG. 19b).

[0136] The growth substrate and LED structures are then flipped over by known processes and aligned and bonded to a CMOS backplane wafer (FIG. 20a), with the backplane contact pads (202) forming electrical contacts to the LED structures via a reflective conductive layer 310. The growth substrate of the LED array precursor is then removed (FIG. 20b), and a further transparent conductive oxide layer 330 is applied to the exposed surface of the first semiconductor layer (110). As described above, layer 330 may be formed from indium tin oxide (ITO) and serves as a common secondary electrical contact that electrically connects with the primary contacts through each LED structure. Layer 330 may be patterned or shaped to provide light extraction features (such as lenticular structures) above each LED structure. The refractive index of layer 330 may also be varied, as described with respect to FIG. 16b.

[0137] 21 shows a further embodiment in which a transparent conductive oxide 320 (such as indium tin oxide) is used as both the primary contact 160 and the spacer material 300. This results in a lower contrast in the refractive index experienced by light traveling through the LED structure. In the above embodiment, light passes through the silicon dioxide mask layer 120 (n=1.5), through layer 320 (where ITO has n=2.0), and finally reaches the GaN semiconductor layer (n=2.4). 21(b), the spacer 300 is formed from indium tin oxide, and an insulating (undoped) AlGaN layer 125 (with a higher refractive index, n=2.4) is provided between the transparent conductive oxide 320 and the first semiconductor layer 110. Thus, the probability of Fresnel reflection is reduced when the silicon dioxide mask layer 120 is removed, while the undoped AlGaN layer 125 prevents short circuits between the primary electrical contact 320 and the first semiconductor layer 110.

[0138] 22-23 show simulations of the device shown in FIG.

[0139] Figure 22b shows the simulated coupling efficiency gain versus acceptance angle of the optical system coupled to the display, where the acceptance angle θ is shown in Figure 22a. The coupling gain is defined as the ratio of the coupling efficiency of the collimated beam of the present invention to that of a Lambertian emitter. Thus, for a projection / relay lens F / 2, the acceptance angle is about 14 degrees, which results in a coupling gain of about 2x. This means that twice as much light is coupled into the F / 2 lens when compared to a conventional Lambertian display.

[0140] Figures 23a and 23b show the angular and polar distributions of light emitted from the simulated device, with Figure 23a showing a full width half maximum of 40°.

[0141] Thus, LED array precursors, LED arrays and methods for manufacturing them are provided that offer advantages in increased internal quantum efficiency while maintaining high light extraction efficiency to affect significant improvements in external quantum efficiency over the prior art, reduced number of mask layers and narrower angular emission distributions that enable the fabrication of smaller micro LEDs with higher pixels per inch (PPI).

[0142] While preferred embodiments of the invention have been described in detail herein, it will be understood by those skilled in the art that variations can be made thereto without departing from the scope of the invention or the appended claims.

[0143] Numbered Description 1. A method for forming a monolithic LED array precursor, comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on a surface of a substrate; (iii) selectively masking the first semiconductor layer by depositing a mask layer on the first semiconductor layer, the mask layer including a plurality of openings; (iv) growing a second semiconductor layer through the openings in the mask layer on the unmasked portions of the first semiconductor layer to form a plurality of pillars, each pillar having a trapezoidal cross section perpendicular to the substrate and a substantially flat top surface portion; (v) forming a third semiconductor layer overlying the second semiconductor layer, the third semiconductor layer including one or more quantum well sublayers and having a substantially planar top surface portion; (vi) forming a fourth semiconductor layer overlying the third semiconductor layer, the fourth semiconductor layer having a substantially planar upper surface portion; (vii) forming a primary electrical contact on the substantially planar upper surface portion of the fourth semiconductor layer, whereby the first to fourth semiconductor layers comprise a Group III nitride; A method comprising:

[0144] 2. The method of numbered statement 1, wherein the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are discontinuous.

[0145] 3. Step (iii) comprises (a) depositing a succession of mask layers; and (b) forming a plurality of and selectively removing a plurality of portions of the mask layer to provide an opening, and optionally, selectively removing a plurality of portions of the mask layer includes selectively removing a plurality of corresponding portions of the first semiconductor layer.

[0146] 4. A method of forming a monolithic LED array precursor, comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on a surface of a substrate; (iii) selectively treating the first semiconductor layer to form an amorphous surface pattern, the amorphous surface pattern defining a plurality of untreated portions of the first semiconductor layer; (iv) growing a second semiconductor layer on the untreated portion of the first semiconductor layer to form a plurality of pillars, each pillar having a trapezoidal cross section perpendicular to the substrate and a substantially flat top surface portion; (v) forming a third semiconductor layer overlying the second semiconductor layer, the third semiconductor layer including one or more quantum well sublayers and having a substantially planar top surface portion; (vi) forming a fourth semiconductor layer overlying the third semiconductor layer, whereby the fourth semiconductor layer has a substantially planar upper surface portion; (vii) forming a primary electrical contact on a substantially planar upper surface portion of the fourth semiconductor layer, the first to fourth semiconductor layers including a Group III nitride; A method comprising:

[0147] 5. The method of any one of numbered statements 1-4, wherein the plurality of apertures form a regularly spaced array.

[0148] 6. The method of any one of numbered statements 1 to 5, wherein the first semiconductor layer has a wurtzite-type crystal structure with a (0001) plane, and the substantially flat top surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer.

[0149] 7. The method of any one of numbered statements 1-6, further comprising forming one or more secondary electrical contacts in electrical communication with the primary electrical contact across the quantum well sublayer to form a monolithic LED array, preferably the one or more secondary electrical contacts are formed on the first semiconductor layer.

[0150] 8. The method of any one of numbered statements 1-7, wherein the monolithic LED array precursor includes at least a first subarray and a second subarray of LED structures, each subarray capable of emitting light at a different dominant wavelength.

[0151] 9. A method according to any one of numbered statements 1 to 8, further comprising at least partially removing the substrate and at least partially removing the first semiconductor layer to form a plurality of dome or lens structures corresponding to and aligned with each of the plurality of pillars of the second semiconductor layer.

[0152] 10. A method according to any one of numbered statements 1 to 9, wherein the substrate is selectively removed to form a plurality of collimating channels, each of the collimating channels being aligned with a primary contact formed on a substantially planar top surface portion of the fourth semiconductor layer.

[0153] 11. A monolithic LED array precursor or LED array obtained by the method according to any one of the numbered statements 1 to 10.

[0154] 12. A monolithic LED array precursor, comprising: a plurality of LED structures sharing a first semiconductor layer, the first semiconductor layer defining a plane of the LED array precursor, each LED structure comprising: (i) a second semiconductor layer on the first semiconductor layer having a top surface portion parallel to a plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the second semiconductor layer has sloped sides; (ii) a third semiconductor layer on the second semiconductor layer, the third semiconductor layer having a top surface portion parallel to a plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the third semiconductor layer has sloped sides parallel to the sloped sides of the second semiconductor layer; (iii) a fourth semiconductor layer on the third semiconductor layer having a top surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the fourth semiconductor layer has sloping sides parallel to the sloping sides of the third semiconductor layer; and (iv) primary electrical contacts on the fourth semiconductor layer, the primary electrical contacts being only on the top surface portion of the fourth semiconductor layer that is parallel to the plane of the LED array precursor. wherein the third semiconductor layer comprises a plurality of quantum well sublayers, the quantum well sublayers having a greater thickness in portions parallel to a plane of the LED array precursor and a reduced thickness in portions non-parallel to the plane of the LED array precursor.

[0155] 13. A monolithic LED array precursor as described in numbered statement 12, wherein the distance from the sloping side of the second semiconductor layer to the sloping side of the third semiconductor layer is smaller than the distance from the top surface portion of the second semiconductor layer to the top surface portion of the third semiconductor layer, and / or the distance from the sloping side of the third semiconductor layer to the sloping side of the fourth semiconductor layer is smaller than the distance from the top surface portion of the third semiconductor layer to the top surface portion of the fourth semiconductor layer.

[0156] 14. The monolithic LED array precursor of numbered statement 12 or numbered statement 13, wherein the angled surfaces of each layer form a plurality of planar facets.

[0157] 15. A monolithic LED array precursor according to any one of numbered statements 12-14, wherein the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are shared between LED structures.

[0158] 16. A monolithic LED array precursor according to any one of numbered statements 12 to 15, wherein the first semiconductor layer has a wurtzite-type crystal structure with a (0001) plane, and the substantially flat top surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer.

[0159] 17. A monolithic LED array precursor according to any one of numbered statements 12-15, wherein the first semiconductor layer includes a plurality of lens structures corresponding to and aligned with the plurality of LED structures.

[0160] 18. A monolithic LED array comprising the monolithic LED array precursor of any one of numbered statements 12-17, and further comprising one or more secondary electrical contacts in electrical communication with the primary electrical contact across the quantum well sublayer.

[0161] 19. The monolithic LED array of numbered statement 18, wherein the monolithic LED array includes at least a first subarray and a second subarray of LED structures, each subarray capable of emitting light at a different dominant wavelength.

[0162] 20. A display device comprising a monolithic LED array according to numbered statement 18 or 19.

Claims

1. 1. A method of forming a monolithic LED array precursor, comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on the surface of the substrate; (iii) selectively masking the first semiconductor layer by depositing a mask layer on the first semiconductor layer, the mask layer including a plurality of openings; (iv) growing a second semiconductor layer through the openings in the mask layer and on the unmasked portions of the first semiconductor layer to form a plurality of pillars, each pillar having a regular trapezoidal cross section perpendicular to the substrate with sloping sidewalls and a substantially flat top portion; (v) forming a third semiconductor layer covering the substantially flat top surface portion and the inclined side surface of the second semiconductor layer, the third semiconductor layer including one or more quantum well sublayers and having an inclined side surface and a substantially flat top surface portion conforming to the shape of the underlying second semiconductor layer; (vi) forming a fourth semiconductor layer covering the substantially flat upper surface portion and the inclined side surface of the third semiconductor layer, whereby the fourth semiconductor layer has an inclined side surface and a substantially flat upper surface portion that follow the shapes of the underlying second semiconductor layer and the third semiconductor layer; (vii) forming a primary electrical contact on the substantially planar upper surface portion of the fourth semiconductor layer, wherein the first through fourth semiconductor layers comprise a Group III nitride; (viii) forming an electrically insulating, optically transparent spacer on the inclined side surface of the fourth semiconductor layer, the electrically insulating, optically transparent spacer having an inner surface facing the inclined side surface of the fourth semiconductor layer and an opposing outer surface, the electrically insulating, optically transparent spacer having a parabolic profile; (ix) depositing a reflective conductive layer on the outer surface of the electrically insulating, optically transparent spacer; A method comprising:

2. Step (iii) comprises (a) depositing a continuous mask layer; and (b) selectively removing portions of the mask layer to provide a plurality of openings, and optionally, selectively removing portions of the mask layer comprises removing a plurality of openings in the first semiconductor layer.

10. The method of claim 1, comprising selectively removing corresponding portions of

3. 1. A method of forming a monolithic LED array precursor, comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on the surface of the substrate; (iii) selectively treating the first semiconductor layer to form an amorphous surface pattern, the amorphous surface pattern defining a plurality of untreated portions of the first semiconductor layer; and (iv) growing a second semiconductor layer on the untreated portion of the first semiconductor layer to form a plurality of pillars, each pillar having a regular trapezoidal cross section perpendicular to the substrate with sloping sidewalls and a substantially flat top portion; (v) forming a third semiconductor layer covering the substantially flat top surface portion and the inclined side surface of the second semiconductor layer, the third semiconductor layer including one or more quantum well sublayers and having an inclined side surface and a substantially flat top surface portion conforming to the shape of the underlying second semiconductor layer; (vi) forming a fourth semiconductor layer covering the substantially flat upper surface portion and the inclined side surface of the third semiconductor layer, whereby the fourth semiconductor layer has an inclined side surface and a substantially flat upper surface portion that follow the shapes of the underlying second semiconductor layer and the third semiconductor layer; (vii) forming a primary electrical contact on the substantially planar upper surface portion of the fourth semiconductor layer, wherein the first through fourth semiconductor layers comprise a Group III nitride; (viii) forming an electrically insulating, optically transparent spacer on the inclined side surface of the fourth semiconductor layer, the electrically insulating, optically transparent spacer having an inner surface facing the inclined side surface of the fourth semiconductor layer and an opposing outer surface, the electrically insulating, optically transparent spacer having a parabolic profile; (ix) depositing a reflective conductive layer on the outer surface of the electrically insulating, optically transparent spacer; A method comprising:

4. forming the primary electrical contact includes depositing a transparent conductive oxide having an inner surface and a convex outer surface in contact with the substantially planar top surface portion of the fourth semiconductor layer; The method of any one of claims 1 to 3, further comprising depositing a reflective conductive layer on the convex outer surface of the transparent conductive oxide.

5. The method of any one of claims 1 to 4, wherein the electrically insulating, optically transparent spacer is formed from one of silicon dioxide, silicon nitride, or titanium oxide.

6. 6. The method of claim 1, wherein the inner surface of the electrically insulating, optically transparent spacer is formed from a first material and the outer surface of the electrically insulating, optically transparent spacer is formed from a second material, the first material having a higher refractive index than the second material.

7. 7. The method of claim 1, further comprising forming one or more secondary electrical contacts across the quantum well sublayer in electrical communication with the primary electrical contact to form a monolithic LED array.

8. 8. The method of claim 1, further comprising at least partially removing the substrate and at least partially removing the first semiconductor layer to form a plurality of dome or lens structures corresponding to and aligned with each of the plurality of pillars of the second semiconductor layer.

9. 9. The method of claim 1, wherein the substrate is selectively removed to form a plurality of collimating channels, each of the collimating channels aligned with a primary contact formed on the substantially planar top surface portion of the fourth semiconductor layer.

10. 1. A monolithic LED array precursor, comprising a plurality of LED structures sharing a first semiconductor layer, the first semiconductor layer defining a plane of the monolithic LED array precursor, each LED structure comprising: (i) a second semiconductor layer on the first semiconductor layer having a top surface portion parallel to the plane of the monolithic LED array precursor, the second semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the second semiconductor layer has sloped sides; (ii) a third semiconductor layer on the top surface portion and the inclined side surfaces of the second semiconductor layer, the third semiconductor layer having a top surface portion parallel to the plane of the monolithic LED array precursor, the third semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the third semiconductor layer has inclined side surfaces parallel to the inclined side surfaces of the second semiconductor layer; (iii) a fourth semiconductor layer on the top surface portion and the inclined side surfaces of the third semiconductor layer, the fourth semiconductor layer having a top surface portion parallel to the plane of the monolithic LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross section perpendicular to the top surface portion such that the fourth semiconductor layer has inclined side surfaces parallel to the inclined side surfaces of the third semiconductor layer; (iv) a primary electrical contact on the fourth semiconductor layer, the primary electrical contact being on only the top surface portion of the fourth semiconductor layer that is parallel to the plane of the monolithic LED array precursor; (v) an electrically insulating, optically transparent spacer on the inclined side surface of the fourth semiconductor layer, the electrically insulating, optically transparent spacer having an inner surface facing the inclined side surface of the fourth semiconductor layer and an opposing outer surface, the electrically insulating, optically transparent spacer having a parabolic profile; (vi) an electrically conductive reflective layer extending over the outer surface of the electrically insulating, optically transparent spacer; and the third semiconductor layer comprises a plurality of quantum well sublayers, the quantum well sublayers having a greater thickness in portions parallel to the plane of the monolithic LED array precursor and a reduced thickness in portions non-parallel to the plane of the monolithic LED array precursor.

11. 11. The monolithic LED array precursor of claim 10, wherein the primary electrical contact comprises a transparent conductive oxide having an inner surface in contact with the top surface portion of the fourth semiconductor layer and a convex outer surface.

12. 12. The monolithic LED array precursor of claim 11, wherein the reflective conductive layer extends over the convex outer surface of the transparent conductive oxide.

13. The monolithic LED array precursor of any one of claims 10 to 12, wherein the electrically insulating, optically transparent spacer is formed from one of silicon dioxide, silicon nitride, or titanium oxide.

14. 14. A monolithic LED array precursor as described in any one of claims 10 to 13, wherein the inner surface of the electrically insulating, optically transparent spacer is formed from a first material and the outer surface of the electrically insulating, optically transparent spacer is formed from a second material, the first material having a higher refractive index than the second material.

15. The distance between the inclined side surface of the second semiconductor layer and the inclined side surface of the third semiconductor layer is , the spacing of the inclined side surface of the fourth semiconductor layer from the inclined side surface of the third semiconductor layer is smaller than the spacing of the inclined side surface of the second semiconductor layer from the inclined side surface of the third semiconductor layer, and / or the spacing of the inclined side surface of the fourth semiconductor layer from the inclined side surface of the third semiconductor layer is smaller than the spacing of the inclined side surface of the fourth semiconductor layer from the inclined side surface of the third semiconductor layer.

16. 16. A monolithic LED array precursor according to any one of claims 10 to 15, wherein the first semiconductor layer includes a plurality of lens structures corresponding to and aligned with the plurality of LED structures.

17. 17. A monolithic LED array comprising the monolithic LED array precursor of any one of claims 10 to 16, and further comprising one or more secondary electrical contacts in electrical communication with the primary electrical contact across the quantum well sublayer.

18. 20. The monolithic LED array of claim 17, wherein the secondary electrical contact is provided by a transparent conductive oxide layer in contact with the first semiconductor layer.

19. A display device comprising a monolithic LED array according to any one of claims 10 to 18.

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