Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suitably suppressing unnecessary wetting and spreading of solder when solder-joining a semiconductor substrate, and a manufacturing method thereof.SOLUTION: A semiconductor device 10 comprises a semiconductor substrate 12 and a metal layer 20 provided on a surface of the semiconductor substrate. The metal layer comprises a first metal layer (a nickel layer 24 and a titanium layer 22) and a second metal layer (a metal layer 26) covering a surface of the first metal layer and having higher solder wettability than the first metal layer. The second metal layer is exposed on a principal surface of the metal layer. The first metal layer is exposed on a side surface of the metal layer. A principal surface 20a of the metal layer is provided with a protrusion 30. The protrusion extends so as to make a circuit along an outer peripheral edge of the principal surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate having a metal layer formed on the back surface thereof, which is solder-bonded to a package substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-241623 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, metals with high solder wettability are used as materials for metal layers used when soldering semiconductor substrates. Therefore, with the technology of Patent Document 1, when soldering a metal layer to a package substrate, the solder spreads onto the side surfaces (i.e., the outer peripheral surfaces) of the metal layer, and may reach the side surfaces of the semiconductor substrate. As a result, variations occur in the characteristics of the semiconductor device. This specification proposes a technology that can effectively suppress unwanted spreading of solder when soldering semiconductor substrates. [Means for solving the problem]

[0005] The semiconductor device (10) disclosed in this specification comprises a semiconductor substrate (12) and a metal layer (20) provided on a surface (12a) of the semiconductor substrate. The metal layer has a first metal layer (24) and a second metal layer (26) covering the surface of the first metal layer and having higher solder wettability than the first metal layer. The second metal layer is exposed on a main surface (20a) of the metal layer. The first metal layer is exposed on a side surface (20b) of the metal layer. A protrusion (30) is provided on the main surface of the metal layer. The protrusion extends in a circular pattern along the outer periphery of the main surface.

[0006] In this semiconductor device, the second metal layer, which has high solder wettability, is exposed on the main surface of the metal layer. Therefore, when the metal layer is solder-bonded to a target component, the solder spreads smoothly over the main surface of the metal layer. Meanwhile, the main surface of the metal layer is provided with a protrusion that runs around the outer periphery of the metal layer. Therefore, when the metal layer is solder-bonded to a target component, the protrusion blocks the solder, preventing it from spreading beyond the metal layer. Furthermore, in this semiconductor device, the first metal layer is exposed on the side surface of the metal layer. Therefore, even if the solder overflows the protrusion, the first metal layer, which has low solder wettability, is exposed on the side surface of the metal layer, making it difficult for the solder to spread over the side surface of the metal layer and preventing the solder from reaching the side surface of the semiconductor substrate. As described above, this semiconductor device can ensure the solder's wettability while preventing unwanted spreading of the solder.

[0007] This specification also discloses a method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device includes the steps of: pressing a pressing member (60) against a main surface (20a) of a metal layer (20) formed on a first surface (2a) of a semiconductor wafer (2) along a planned dividing line (4), thereby deforming the metal layer along the planned dividing line, thereby forming grooves extending along the planned dividing line and protrusions (30) extending adjacent to the grooves, and forming cracks (5) in the semiconductor wafer along the planned dividing line and in the thickness direction of the semiconductor wafer, wherein the metal layer has a first metal layer (22, 24) and a second metal layer (26) having higher solder wettability than the first metal layer, covering the surface of the first metal layer, and exposed at the main surface of the metal layer; and, after the step of forming the cracks, pressing a dividing member (62) against a second surface (2b) of the semiconductor wafer opposite the first surface along the planned dividing line, thereby dividing the semiconductor wafer along the planned dividing line.

[0008] In this manufacturing method, a pressing member is pressed against the main surface of a metal layer formed on the first surface of a semiconductor wafer along a planned dividing line. By pressing the pressing member, a crack is formed on the first surface side. Furthermore, by pressing the pressing member, the metal layer is plastically deformed to form a groove, and the metal layer is pushed out into an area adjacent to the planned dividing line by the amount that the pressing member bites into the metal layer. This forms a protrusion extending adjacent to the groove. Then, a dividing member is pressed against the semiconductor wafer from the second surface side along the planned dividing line. This applies a force in a direction that splits the crack and separates adjacent regions through the crack. As a result, the crack extends in the thickness direction of the semiconductor wafer. This divides the semiconductor wafer along the planned dividing line. Furthermore, a force is applied to the metal layer across the crack in a direction that separates adjacent regions, and the metal layer is also divided.

[0009] Thus, in the above-described manufacturing method, when cracks are formed, protrusions extending adjacent to the planned dividing line (groove) are formed. Therefore, when the semiconductor wafer and the metal layer are divided along the planned dividing line, the main surface of the divided metal layer is provided with protrusions extending around its outer periphery. Therefore, in a semiconductor device manufactured by this manufacturing method, when the metal layer is soldered to a target component, the protrusions block the solder, preventing it from spreading beyond the metal layer to the outer periphery. Furthermore, since the metal layer includes two layers, a first metal layer and a second metal layer, the first metal layer, which has low solder wettability, is exposed on the side of the divided metal layer. Therefore, in a semiconductor device manufactured by this manufacturing method, even if the solder crosses the protrusions, the solder is less likely to spread along the side of the metal layer, preventing it from reaching the side of the semiconductor substrate. As described above, a semiconductor device manufactured by this manufacturing method can ensure wettability while preventing unwanted spreading of the solder.

[0010] In this specification, the term "solder" has a comprehensive meaning that includes, for example, a bonding material that utilizes the melting point (melting and solidification) of a metal whose main component is tin or other metals, as well as a conductive bonding agent that utilizes the dispersion and precipitation of metal microparticles in a dispersion medium (organic solvent, etc.). [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a bottom view of the semiconductor device according to the embodiment. [Figure 3] FIG. 2 is an enlarged view of the periphery of a protrusion of a metal layer of the semiconductor device according to the embodiment. [Figure 4] 1A and 1B are diagrams for explaining a state in which the semiconductor device according to the embodiment is soldered; [Figure 5] 10A to 10C are diagrams for explaining another state in which the semiconductor device of the embodiment is soldered; [Figure 6] FIG. 1 is a plan view of a semiconductor wafer. [Figure 7] 5A to 5C are diagrams illustrating a metal layer forming step. [Figure 8] FIG. 10 is a diagram illustrating a crack formation process. [Figure 9] 10A to 10C are diagrams illustrating protrusions formed in a crack forming step. [Figure 10] FIG. [Figure 11] FIG. 1 is a diagram showing a plurality of individual semiconductor devices. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the semiconductor device disclosed in the present specification as an example, the first metal layer may be exposed at an outer peripheral edge of the protruding portion with a width of 1 μm or more.

[0013] In this configuration, even if the solder exceeds the protruding portion when the metal layers are soldered together, the first metal layer can more effectively prevent the solder from wetting and spreading.

[0014] In the semiconductor device disclosed in the present specification as an example, the height of the protrusion may be equal to or greater than half the thickness of the metal layer.

[0015] In this configuration, when the metal layers are soldered together, it is possible to more effectively prevent the solder from wetting and spreading beyond the protruding portions.

[0016] In the semiconductor device disclosed in the present specification, the side surface of the semiconductor substrate may be a cleavage plane.

[0017] In one example of the semiconductor device disclosed herein, the first metal layer may be a nickel layer and / or a titanium layer, and the second metal layer may be a gold layer.

[0018] The gold layer has a relatively high solder wettability, while the nickel layer and titanium layer have a low solder wettability. Therefore, with this configuration, the solder wettability can be ensured while effectively suppressing unwanted spreading of the solder.

[0019] In the semiconductor device disclosed in the present specification, the protrusion may have an undulation along an outer periphery of the main surface, or the protrusion may be formed intermittently along the outer periphery of the main surface.

[0020] In one example manufacturing method disclosed in this specification, the pressing member may be a scribing wheel, and pressing the pressing member may be rolling the scribing wheel, and in the step of forming the crack, a scribe line accompanied by the crack extending in the thickness direction of the semiconductor wafer along the planned dividing line may be formed on the first surface.

[0021] In such a configuration, by rotatably supporting the scribing wheel in a disk (annular) shape, cracks can be easily formed along the planned dividing lines by rolling the scribing wheel.

[0022] In one example manufacturing method disclosed herein, the first metal layer may be a nickel layer and / or a titanium layer, and the second metal layer may be a gold layer.

[0023] (Example) A semiconductor device 10 according to an embodiment will be described below with reference to the drawings. The semiconductor device 10 according to the embodiment includes a semiconductor substrate 12 and a metal layer 20. The semiconductor substrate 12 has a first main surface 12a, a second main surface 12b located on the opposite side of the first main surface 12a, and a side surface 12c connecting the first main surface 12a and the second main surface 12b. Although not shown, semiconductor elements having functions such as transistors and diodes are formed on the semiconductor substrate 12. The semiconductor substrate 12 is made of SiC (silicon carbide). The semiconductor substrate 12 may also be made of other semiconductor materials such as Si (silicon) and GaN (gallium nitride). The side surface 12c of the semiconductor substrate 12 is a cleavage plane.

[0024] The metal layer 20 is provided on the first main surface 12a of the semiconductor substrate 12. The metal layer 20 has a titanium layer 22, a nickel layer 24, and a gold layer 26. The titanium layer 22 covers the first main surface 12a of the semiconductor substrate 12. The nickel layer 24 covers the surface of the titanium layer 22. The gold layer 26 covers the surface of the nickel layer 24. The gold layer 26 is made of gold (i.e., Au). The gold layer 26 is exposed on the main surface 20a of the metal layer 20. The titanium layer 22 and the nickel layer 24 are exposed on the side surface 20b of the metal layer 20. That is, the titanium layer 22 and the nickel layer 24 are not covered by the gold layer 26 on the side surface 20b of the metal layer 20. The titanium layer 22 has a thickness of approximately 200 nm, the nickel layer 24 has a thickness of approximately 1000 nm, and the gold layer 26 has a thickness of approximately 50 nm. The nickel layer 24 and the titanium layer 22 are an example of a “first metal layer,” and the gold layer 26 is an example of a “second metal layer.” In addition to gold, silver can also be used as a metal constituting the second metal layer.

[0025] The gold layer 26 has higher solder wettability than the nickel layer 24. The solder wettability of a metal can be evaluated, for example, by the solder spreading rate. The spreading rate can be calculated by placing solder on the surface of a certain metal, melting it, and measuring the shape after melting (after spreading). Specifically, when the height of the solder after spreading is H and the diameter is D, the spreading rate can be calculated by 100 × (DH) / D. The spreading rate of the gold layer 26 is approximately 95%, and the spreading rate of the nickel layer 24 is approximately 50%.

[0026] The metal layer 20 has protrusions 30. As shown by dotted hatching in FIG. 2, the protrusions 30 go around the outer periphery of the main surface 20a of the metal layer 20. As shown in FIG. 3, the height h of the protrusions 30 (height from the main surface 20a of the metal layer 20) is at least half the thickness t of the metal layer 20 (thickness from the first main surface 12a of the semiconductor substrate 12 to the main surface 20a). The thickness t and height h are not particularly limited, but for example, the thickness t of the metal layer 20 is about 200 to 5000 nm, and the height h of the protrusions 30 is about 100 to 3000 nm. The protrusions 30 may have undulations along the outer peripheral edge of the main surface 20a, and may be formed intermittently along the outer peripheral edge of the main surface 20a. However, it is preferable that the proportion of the portion that is 1 / 2 or more of the thickness t of the metal layer 20 is, for example, 1 / 3 or more, particularly 1 / 2 or more, relative to the entire length of the outer peripheral edge of the main surface 20a.

[0027] 3, the nickel layer 24 and the titanium layer 22 are exposed even in a portion 30a of the outer circumferential edge of the protrusion 30. That is, in this portion 30a, the nickel layer 24 and the titanium layer 22 are not covered with the gold layer 26. The width w of this portion 30a when viewing the semiconductor substrate 12 from below (see also FIG. 2) is approximately 2 μm.

[0028] The semiconductor device 10 of this embodiment is solder-bonded to a conductive plate 40, such as a heat sink. FIGS. 4 and 5 show the semiconductor device 10 bonded to the conductive plate 40 via the metal layer 20 using solder 50. As shown in FIG. 4 , the metal layer 20 of the semiconductor device 10 has a gold layer 26, which has high solder wettability, exposed on its main surface 20a. Therefore, when the metal layer 20 is solder-bonded to the conductive plate 40, the solder 50 spreads smoothly over the main surface 20a of the metal layer 20. Meanwhile, the main surface 20a of the metal layer 20 is provided with protrusions 30 that run along the outer periphery thereof. Therefore, when the metal layer 20 is solder-bonded to the conductive plate 40, the protrusions 30 block the solder 50, preventing the solder 50 from spreading beyond the metal layer 20. Furthermore, even if the protrusions 30 have undulations along the outer periphery of the main surface 20a or are formed intermittently, the surface tension of the solder 50 and other factors can also act to prevent the solder 50 from wetting and spreading to the outer periphery.

[0029] Furthermore, in this semiconductor device 10, the nickel layer 24 and the titanium layer 22 are exposed on a portion 30a of the protrusion 30 and on the side surface 20b of the metal layer 20. Therefore, even if the solder 50 overflows the protrusion 30, as shown in Fig. 5, the nickel layer 24 and the titanium layer 22, which have low solder wettability, are exposed, making it difficult for the solder 50 to spread from the gold layer 26 to the nickel layer 24 and the titanium layer 22, and preventing the solder 50 from reaching the side surface 12c of the semiconductor substrate 12. As described above, in this semiconductor device, the wettability of the solder to the main surface 20a of the metal layer 20 is ensured while unnecessary spreading of the solder is prevented.

[0030] Next, a method for manufacturing the semiconductor device 10 will be described. First, a semiconductor wafer 2 shown in FIG. 6 is prepared. A plurality of element regions 3 are formed in a matrix on the semiconductor wafer 2. In FIG. 6, each element region 3 is schematically indicated by a solid line. For ease of explanation, the boundaries between adjacent element regions 3, which are the dividing lines along which the semiconductor wafer 2 is later divided into individual element regions 3, will be referred to as planned dividing lines 4. The planned dividing lines 4 are imaginary lines rather than lines actually drawn on the semiconductor wafer 2. The planned dividing lines 4 may also be lines or grooves actually drawn on the semiconductor wafer 2 for visual confirmation. Each element region 3 has a semiconductor element formed therein, which functions as a transistor, a diode, or the like. The semiconductor wafer 2 is made of silicon carbide (SiC). Note that the semiconductor wafer 2 may also be made of other semiconductor materials, such as silicon (Si) or gallium nitride (GaN). As shown in FIG. 7 and other figures, the semiconductor wafer 2 has a first surface 2a and a second surface 2b located behind the first surface 2a.

[0031] (Metal layer formation process) The semiconductor wafer 2 shown in FIG. 6 is subjected to a metal layer formation process shown in FIG. 7. In the metal layer formation process, a metal layer 20 is formed on the first surface 2a of the semiconductor wafer 2. The metal layer 20 has a titanium layer 22, a nickel layer 24, and a gold layer 26 (a layer made of gold (Au)). The titanium layer 22, the nickel layer 24, and the gold layer 26 are deposited in this order on the first surface 2a of the semiconductor wafer 2. The metal layer 20 is formed so as to cover substantially the entire first surface 2a. In other words, the metal layer 20 is formed on the first surface 2a so as to span multiple element regions 3. The metal layer 20 functions as an electrode of the completed semiconductor device. The titanium layer 22 has a thickness of approximately 200 nm, the nickel layer 24 has a thickness of approximately 1000 nm, and the gold layer 26 has a thickness of approximately 50 nm.

[0032] (Crack formation process) Next, a crack formation step shown in FIG. 8 is performed. In the crack formation step, a scribing wheel 60 is pressed against the main surface 20a of the metal layer 20 from the first surface 2a side of the semiconductor wafer 2, thereby forming a scribe line 61 with a crack 5 on the semiconductor wafer 2. The scribing wheel 60 is a disk-shaped (annular) member and rotatably supported by a support device (not shown). Here, the scribing wheel 60 is moved (scanned) along the planned division lines 4 while being pressed against the main surface 20a of the metal layer 20. As the scribing wheel 60 moves along the planned division lines 4, it rolls (rolls) on the main surface 20a of the metal layer 20 like a tire rolling on a road surface. The scribing wheel 60 has a sharp ridge on its periphery, and forms a line (scribe line 61) on the main surface 20a of the metal layer 20 along the planned division lines 4. The scribing wheel 60 may be a scribing wheel with a continuous ridge formed on its periphery, or a scribing wheel with notches (grooves) formed on its periphery and discontinuous ridges. When the main surface 20a is pressed by the scribing wheel 60, compressive stress is generated in the surface region of the first surface 2a inside the semiconductor wafer 2. Scribe lines 61 (i.e., grooves) are formed at the locations pressed by the scribing wheel 60, while tensile stress is generated inside the semiconductor wafer 2 directly below the area where compressive stress is generated. The first surface 2a of the semiconductor wafer 2 is exposed at the bottom of the grooves that form the scribe lines 61, and the first surface 2a of the semiconductor wafer 2 is directly pressed by the scribing wheel 61. Tensile stress is generated along the first surface 2a of the semiconductor wafer 2 in a direction away from the planned dividing line 4 directly below the area where compressive stress is generated. This tensile stress forms cracks 5 extending from the first surface 2a of the semiconductor wafer 2 to the interior in the thickness direction of the semiconductor wafer 2. Here, by pressing the scribing wheel 60 against the main surface 20a and moving it along the planned dividing line 4, the metal layer 20 is divided by the scribe line 61 along the boundary between adjacent element regions 3, and cracks 5 are formed extending in the thickness direction of the semiconductor wafer 2.Crack 5 is formed near the surface layer of first surface 2a of semiconductor wafer 2. Scribing wheel 60 is an example of a "pressing member." Generally, compressive stress suppresses the formation and extension of cracks, so crack 5 is formed so as to extend from outside the region where compressive stress occurs at the point pressed by scribing wheel 60 on first surface 2a of semiconductor wafer 2 to the region where tensile stress occurs immediately below the region where compressive stress occurs. Furthermore, even when first surface 2a of semiconductor wafer 2 is not exposed at the bottom of the groove forming scribe line 61 (i.e., when first surface 2a of semiconductor wafer 2 is pressed via metal layer 20 (e.g., titanium layer 22)), crack 5 can be formed by controlling the pressing load of scribing wheel 60.

[0033] As described above, the metal layer 20 is plastically deformed by the scribing wheel 60 being pressed against it. At this time, the metal layer 20 is pushed out into the area adjacent to the planned dividing lines 4 by an amount corresponding to the amount of penetration of the scribing wheel 60 into the main surface 20a (the volume of the scribe lines 61 to be formed), and the entire or most of the metal layer 20 is divided. As a result, protrusions 30 extending adjacent to both sides of the planned dividing lines 4 are formed on the main surface 20a of the metal layer 20. Here, the thickness of the gold layer 26 is extremely thin compared to the nickel layer 24 and the titanium layer 22. Therefore, as shown in FIG. 9 , at the sidewall portions of the scribe lines 61, the gold layer 26 is pushed out laterally by the scribing wheel 60, and the exposed nickel layer 24 is also pushed out laterally, and further the exposed titanium layer 22 is also pushed out laterally, so that the first surface 2a of the semiconductor wafer 2 is exposed at the bottom of the scribe lines 61. For example, by using a scribing wheel 60 having notches (grooves) formed on the periphery and having discontinuous ridges, it is possible to form undulating protrusions 30 or discontinuous continuous protrusions 30.

[0034] (splitting process) Next, the dividing step shown in FIG. 10 is carried out. Note that in FIG. 10, the semiconductor wafer 2 is depicted with the second surface 2b facing up. In the dividing step, a break plate 62 is pressed along the planned dividing lines 4 (cracks 5 formed in the crack forming step), and the semiconductor wafer 2 is divided along the planned dividing lines 4 (along the boundaries of the element regions 3). Here, the break plate 62 is pressed against the second surface 2b of the semiconductor wafer 2. The break plate 62 is a plate-like member, and its lower end (the edge that is pressed against the second surface 2b) has a ridge-like shape (sharp blade-like), but it simply presses against the semiconductor wafer 2 without cutting it.

[0035] When the break plate 62 is pressed against the second surface 2b, the semiconductor wafer 2 bends. Here, the crack 5 is formed on the first surface 2a side of the semiconductor wafer 2. Therefore, when the break plate 62 is pressed against the semiconductor wafer 2 from the second surface 2b side, the semiconductor wafer 2 bends around the pressed portion (line) as an axis, and a force is applied on the first surface 2a side to the crack 5 in a direction that separates the two element regions 3 adjacent to the dividing position. Also, as described above, tensile stress is applied around the crack 5. Therefore, when the break plate 62 is pressed against the second surface 2b, the crack 5 extends in the thickness direction of the semiconductor wafer 2, and the semiconductor wafer 2 is divided along the planned dividing line 4. At this time, the semiconductor wafer 2 is cleaved starting from the crack 5. That is, the dividing surface of the semiconductor wafer 2 (side surface 12c shown in FIG. 1) becomes the cleavage surface. Furthermore, since the metal layer 20 is divided along the scribe line 61, dividing the semiconductor wafer 2 allows the individual semiconductor devices 10 to be obtained. Furthermore, even if the metal layer 20 is not completely divided when the scribe line 61 is formed (the first surface 2a of the semiconductor wafer 2 is not exposed), the undivided metal layer 20 is formed on the first surface 2a of the semiconductor wafer 2 and is exposed at the bottom of the scribe line 61, so when the break plate 61 is pressed against the second surface 2b, a force is also applied to the metal layer 20 in a direction that separates the two element regions 3 adjacent to the dividing position, and the metal layer 20 deforms so as to be separated and divided along the scribe line 61. The break plate 62 is an example of a "dividing member".

[0036] In the dividing step, the above-described step of pressing the break plate 62 against the second surface 2b is repeatedly performed along each planned dividing line 4. This allows the semiconductor wafer 2 and the metal layer 20 (if the metal layer 20 is not completely divided) to be divided along the boundaries of each element region 3. As a result, the semiconductor wafer 2 is divided into a plurality of semiconductor devices 10, as shown in FIG. 11 . This completes a plurality of semiconductor devices 10 each having a metal layer 20 (electrode) formed on its surface. As described above, on the sidewalls of the scribe lines 61, the gold layer 26 is extruded near the surface of the semiconductor device 10, exposing the nickel layer 24 and the titanium layer 22 near the bottom of the scribe lines 61. Furthermore, the nickel layer 24 and the titanium layer 22 are also exposed on the dividing surfaces of the metal layer 20 after dividing. Therefore, the metal layer 20 of each divided semiconductor device 10 has the nickel layer 24 and the titanium layer 22 exposed at its outer periphery.

[0037] In this manufacturing method, a metal layer 20 having a titanium layer 22, a nickel layer 24, and a gold layer 26 is formed on the first surface 2a of a semiconductor wafer 2. Then, a scribing wheel 60 is pressed against the main surface 20a of the metal layer 20 from the first surface 2a side along the planned dividing line 4. By pressing the scribing wheel 60, the entire or most of the metal layer 20 is divided, forming cracks 5 on the first surface 2a side of the semiconductor wafer 2. Furthermore, by pressing the scribing wheel 60, the metal layer 20 is plastically deformed. The metal layer 20 is pushed out into a region adjacent to the planned dividing line 4 by the amount that the scribing wheel 60 penetrates the metal layer 20, dividing the metal layer 20. This forms a protrusion 30 extending adjacent to the planned dividing line 4. Then, a break plate 62 is pressed against the semiconductor wafer 2 from the second surface 2b side along the planned dividing line 4. This widens the crack 5, applying a force in a direction that separates adjacent regions via the crack 5. As a result, the crack 5 extends in the thickness direction of the semiconductor wafer 2. This causes the semiconductor wafer 2 to be divided along the planned dividing lines 4. Furthermore, if the metal layer 20 is not completely divided, a force is also applied to the metal layer 20 across the crack 5 in a direction that separates the adjacent regions, and the metal layer 20 is also divided.

[0038] As described above, in the manufacturing method described above, when the cracks 5 are formed, the protrusions 30 extending adjacent to the planned dividing lines 4 are formed. Therefore, when the semiconductor wafer 2 (and the remaining metal layer 20) is divided along the planned dividing lines 4, the main surface 20a of the divided metal layer 20 is provided with the protrusions 30 extending all the way around its outer periphery. Therefore, in the semiconductor device 10 manufactured by this manufacturing method, when the metal layer 20 is solder-bonded to a target member (such as the conductor plate 40 in FIGS. 4 and 5), the protrusions 30 block the solder and prevent the solder from spreading beyond the metal layer 20 to the outer periphery. Furthermore, since the metal layer 20 includes the nickel layer 24 (and the titanium layer 22) and the gold layer 26, the nickel layer 24 (and the titanium layer 22), which has low solder wettability, is exposed on the side surfaces of the divided metal layer 20. Therefore, in the semiconductor device 10 manufactured by this manufacturing method, even if the solder exceeds the protrusion 30, the solder is less likely to spread over the side surfaces of the metal layer 20 (nickel layer 24 and titanium layer 22), and the solder is prevented from reaching the side surfaces of the semiconductor substrate. As described above, the semiconductor device manufactured by this manufacturing method can prevent unnecessary spreading of the solder while ensuring wettability.

[0039] In the above-described embodiment, the metal layer 20 was composed of the titanium layer 22, the nickel layer 24, and the gold layer 26. However, the type of metal constituting the metal layer 20 is not particularly limited, as long as the solder wettability of the metal exposed on the main surface 20a of the metal layer 20 is higher than the solder wettability of the metal located in the layer below the exposed metal.

[0040] In the above-described embodiment, the nickel layer 24 may not be exposed at a portion 30a of the outer peripheral edge of the protrusion 30. The height h of the protrusion 30 may be less than half the thickness t of the metal layer 20. Even with this configuration, unwanted wetting and spreading of the solder can be suppressed.

[0041] The configurations disclosed in this specification are listed below. (Configuration 1) A semiconductor substrate (12); a metal layer (20) provided on the surface (12a) of the semiconductor substrate; Equipped with The metal layer is a first metal layer (24); a second metal layer (26) covering the surface of the first metal layer and having higher solder wettability than the first metal layer; It has the second metal layer is exposed on a main surface (20a) of the metal layer, the first metal layer is exposed on a side surface (20b) of the metal layer, a protrusion (30) is provided on the main surface of the metal layer, The protrusion extends around the outer periphery of the main surface. A semiconductor device (10). (Configuration 2) 2. The semiconductor device according to claim 1, wherein the first metal layer is exposed at the outer peripheral edge of the protrusion with a width of 1 μm or more. (Configuration 3) 3. The semiconductor device according to claim 1, wherein the height (h) of the protrusion is equal to or greater than half the thickness (t) of the metal layer. (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein the side surface (12c) of the semiconductor substrate is a cleavage plane. (Configuration 5) the first metal layer is a nickel layer and / or a titanium layer; 5. The semiconductor device according to any one of configurations 1 to 4, wherein the second metal layer is a gold layer. (Configuration 6) 6. The semiconductor device according to any one of configurations 1 to 5, wherein the protrusion has undulations along the outer periphery of the main surface. (Configuration 7) 6. The semiconductor device according to any one of configurations 1 to 5, wherein the protrusions are formed discontinuously along the outer periphery of the main surface. (Configuration 8) A method for manufacturing a semiconductor device, comprising: a step of pressing a pressing member (60) against a main surface (20a) of a metal layer (20) formed on a first surface (2a) of a semiconductor wafer (2) along a planned dividing line (4) to deform the metal layer along the planned dividing line, thereby forming grooves extending along the planned dividing line and protrusions (30) extending adjacent to the grooves, and also forming cracks (5) in the semiconductor wafer along the planned dividing line and in a thickness direction of the semiconductor wafer, the metal layer having a first metal layer (22, 24) and a second metal layer (26) having higher solder wettability than the first metal layer, covering the surface of the first metal layer, and exposed at the main surface of the metal layer; a step of dividing the semiconductor wafer along the planned dividing lines by pressing a dividing member (62) against a second surface (2b) of the semiconductor wafer located opposite to the first surface (2b) after the step of forming the cracks; A manufacturing method comprising: (Configuration 9) the pressing member is a scribing wheel, The pressing of the pressing member is performed by rolling a scribing wheel, 9. The manufacturing method according to claim 8, wherein in the step of forming the cracks, scribe lines accompanied by the cracks are formed on the first surface along the planned dividing lines, the scribe lines extending in the thickness direction of the semiconductor wafer. (Configuration 10) the first metal layer is a gold layer; 10. The method according to claim 8, wherein the second metal layer is a nickel layer and / or a titanium layer.

[0042] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0043] 2: Semiconductor wafer 5: Crack 10: Semiconductor device 12: Semiconductor substrate 20: Metal layer 22: Titanium layer 24: Nickel layer 26: Gold layer 30:Protrusion

Claims

1. a semiconductor substrate (12); a metal layer (20) provided on the surface (12a) of the semiconductor substrate; Equipped with The metal layer is a first metal layer (22, 24); a second metal layer (26) covering the surface of the first metal layer and having higher solder wettability than the first metal layer; It has the second metal layer is exposed on a main surface (20a) of the metal layer; the first metal layer is exposed on a side surface (20b) of the metal layer, A protrusion (30) is provided on the main surface of the metal layer, the protrusion extends around the outer periphery of the main surface, The side surface (12c) of the semiconductor substrate is a cleavage plane. A semiconductor device (10).

2. 2. The semiconductor device according to claim 1, wherein the first metal layer is exposed at the outer peripheral edge of the protrusion with a width of 1 [mu]m or more.

3. 2. The semiconductor device according to claim 1, wherein the height (h) of said protrusion is equal to or greater than half the thickness (t) of said metal layer.

4. the first metal layer is a nickel layer and / or a titanium layer; 2. The semiconductor device according to claim 1, wherein the second metal layer is a gold layer.

5. 2. The semiconductor device according to claim 1, wherein said protrusion has undulations along the outer periphery of said main surface.

6. 2. The semiconductor device according to claim 1, wherein said protrusions are formed discontinuously along the outer periphery of said main surface.

7. A method for manufacturing a semiconductor device, comprising: a step of pressing a pressing member (60) against a main surface (20a) of a metal layer (20) formed on a first surface (2a) of a semiconductor wafer (2) along a planned dividing line (4) to deform the metal layer along the planned dividing line, thereby forming grooves extending along the planned dividing line and protrusions (30) extending adjacent to the grooves, and forming cracks (5) in the semiconductor wafer along the planned dividing line and in the thickness direction of the semiconductor wafer, the metal layer having a first metal layer (22, 24) and a second metal layer (26) having higher solder wettability than the first metal layer, covering the surface of the first metal layer, and exposed at the main surface of the metal layer; a step of dividing the semiconductor wafer along the planned dividing lines by pressing a dividing member (62) against a second surface (2b) of the semiconductor wafer located opposite to the first surface (2b) after the step of forming the cracks; A manufacturing method comprising:

8. the pressing member is a scribing wheel, The pressing of the pressing member is performed by rolling a scribing wheel, The manufacturing method according to claim 7 , wherein in the step of forming the cracks, scribe lines accompanied by the cracks are formed on the first surface along the planned dividing lines, the scribe lines extending in the thickness direction of the semiconductor wafer.

9. the first metal layer is a nickel layer and / or a titanium layer; The method of claim 7, wherein the second metal layer is a gold layer.

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