Semiconductor Devices

Abstract

This semiconductor device includes: a semiconductor layer; a first-electroconductivity-type first region formed on a surface layer part of a first main surface of the semiconductor layer; a cell structure having a second-electroconductivity-type second region formed on a surface layer part of the first region, a first-electroconductivity-type third region formed on the surface layer part of the first region so as to be in contact with the second region, and a control electrode that forms a current path in the second region and that faces the second region via an interposed first insulating film adjacent to the second region; a first electrode layer that is formed so as to cover the cell structure on the first main surface of the semiconductor layer and that is electrically connected to the third region; a second electrode layer that is formed apart from the first electrode layer on the first main surface of the semiconductor layer and that is electrically connected to the control electrode; a first recess that is formed in the surface layer part of the first main surface of the semiconductor layer so as to face the second electrode layer; a second insulating film that covers the first recess; and an auxiliary electrode that is implanted in the first recess with the second insulating film interposed therebetween and that is electrically connected to the second electrode layer.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate having an active region, and a source pad and a gate pad provided on the front surface of the active region via an interlayer insulating film. The source pad and the gate pad are embedded in a first contact hole in the interlayer insulating film in a portion of the active region excluding the gate pad region and the gate resistor region. A unit cell (a constituent unit of an element) is arranged in a portion of the active region facing the source pad in the depth direction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-150179 Summary of the Invention [Means for solving the problem]

[0004] a second insulating film covering the first recess; an auxiliary electrode embedded in the first recess via the second insulating film; and an auxiliary electrode electrically connected to the second electrode layer. The semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having a first main surface and a second main surface opposite the first main surface; a cell structure including a first region of a first conductivity type formed in a surface portion of the first main surface of the semiconductor layer; a second region of a second conductivity type formed in a surface portion of the first region so as to contact the second region; and a control electrode facing the second region via a first insulating film adjacent to the second region and forming a current path in the second region. The semiconductor layer includes a first electrode layer formed on the first main surface of the semiconductor layer so as to cover the cell structure and electrically connected to the third region; a second electrode layer formed on the first main surface of the semiconductor layer at a distance from the first electrode layer and electrically connected to the control electrode; a first recess formed in a surface portion of the first main surface of the semiconductor layer so as to face the second electrode layer; a second insulating film covering the first recess; and an auxiliary electrode embedded in the first recess via the second insulating film and electrically connected to the second electrode layer. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic overhead view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic plan view of a semiconductor element in one embodiment of the semiconductor device of FIG. [Figure 3] FIG. 3 is a diagram schematically showing a cross section taken along line III-III in FIG. [Figure 4] FIG. 4 is a diagram schematically showing a cross section taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a diagram showing a part of a manufacturing process for one embodiment of the semiconductor device of FIG. [Figure 6] FIG. 6 is a diagram showing the next step of FIG. [Figure 7] FIG. 7 is a diagram showing the next step of FIG. [Figure 8] FIG. 8 is a diagram showing the next step of FIG. [Figure 9] FIG. 9 is a diagram showing the next step of FIG. [Figure 10]FIG. 10 is a diagram showing the next step of FIG. [Figure 11] FIG. 11 is a circuit diagram showing the electrical structure of the semiconductor device. [Figure 12] FIG. 12 is a schematic cross-sectional view of a semiconductor element according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic cross-sectional view of a semiconductor element according to a third embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] <Embodiments of the present disclosure> First, embodiments of the present disclosure will be listed and described.

[0007] a second electrode layer formed on the first main surface of the semiconductor layer and spaced apart from the first electrode layer and electrically connected to the control electrode; a first recess formed on the surface of the first main surface of the semiconductor layer and facing the second electrode layer; an auxiliary electrode embedded in the first recess through a second insulating film and electrically connected to the first electrode layer;

[0008] According to this configuration, the auxiliary electrode is electrically connected to the control electrode via the second electrode layer. Because the auxiliary electrode is embedded in the first recess, the capacitance between the auxiliary electrode and the semiconductor layer, which face each other via the second insulating film, can be increased compared to when the auxiliary electrode is formed in a layer along the first main surface of the semiconductor layer. This increases the parasitic capacitance between the first electrode layer and the second electrode layer. As a result, a semiconductor device with excellent electrostatic breakdown resistance characteristics can be provided.

[0009] Furthermore, the auxiliary electrodes are formed away from the cell structure, so that even if the auxiliary electrodes are formed, the effects of layout changes or the like on the cell structure can be suppressed, and the characteristics of the semiconductor device, such as the on-resistance, can be maintained.

[0010] A semiconductor device according to one embodiment of the present disclosure may include a fourth region of a second conductivity type formed in a surface layer portion of the first region so as to face the second electrode layer, and the first recess may be formed within the fourth region.

[0011] In the semiconductor device according to the embodiment of the present disclosure, a part of the fourth region may be interposed between a bottom of the first recess and the first region in a thickness direction of the semiconductor layer.

[0012] As a result, the bottom of the first recess is covered with the fourth region, and therefore it is possible to prevent the electric field from concentrating on the bottom of the first recess.

[0013] In the semiconductor device according to the embodiment of the present disclosure, the portion of the fourth region may have a thickness of 1 μm or more.

[0014] In one embodiment of the semiconductor device of the present disclosure, the fourth region may have a first depth from the first main surface of 7 μm or more and 10 μm or less, and the first recess may have a second depth from the first main surface of 6 μm or less.

[0015] In a semiconductor device according to one embodiment of the present disclosure, the cell structure may include a trench cell structure having a second recess formed in a surface layer portion of the first main surface of the semiconductor layer, the control electrode embedded in the second recess via the first insulating film, and the third region and the second region formed on the side surface of the second recess in that order from the first main surface toward the second main surface.

[0016] In the semiconductor device according to the embodiment of the present disclosure, the first recess and the second recess may have approximately the same depth.

[0017] In the semiconductor device according to the embodiment of the present disclosure, the depth of the first recess may be smaller than the depth of the second recess.

[0018] In the semiconductor device according to the embodiment of the present disclosure, the first recess and the second recess may both be formed in a stripe shape extending in a first direction.

[0019] A semiconductor device according to one embodiment of the present disclosure may include a collector region of a second conductivity type formed in a surface layer portion of the second main surface of the semiconductor layer, and the cell structure may include an IGBT cell structure having a base region consisting of the second region, an emitter region consisting of the third region, and a gate electrode consisting of the control electrode.

[0020] A semiconductor device according to one embodiment of the present disclosure may include a semiconductor layer having a first main surface and a second main surface opposite thereto, an active region formed on a surface portion of the first main surface of the semiconductor layer, the active region having a cell structure in which a current path is formed by voltage control of the control electrode, a first electrode layer formed on the active region and connected to the current path, a second electrode layer formed on the first main surface of the semiconductor layer in a region outside the active region and electrically connected to the control electrode, a first recess formed on a surface portion of the first main surface of the semiconductor layer so as to face the second electrode layer, and an auxiliary electrode embedded in the first recess via a second insulating film and electrically connected to the second electrode layer.

[0021] According to this configuration, the auxiliary electrode is electrically connected to the control electrode via the second electrode layer. Because the auxiliary electrode is embedded in the first recess, the capacitance between the auxiliary electrode and the semiconductor layer, which face each other via the second insulating film, can be increased compared to when the auxiliary electrode is formed in a layer along the first main surface of the semiconductor layer. This increases the parasitic capacitance between the first electrode layer and the second electrode layer. As a result, a semiconductor device with excellent electrostatic breakdown resistance characteristics can be provided.

[0022] Furthermore, the auxiliary electrodes are formed in an area outside the active area, so that even if the auxiliary electrodes are formed, the effects of layout changes and the like on the cell structure can be suppressed, and the characteristics of the semiconductor device, such as the on-resistance, can be maintained.

[0023] In the semiconductor device according to the embodiment of the present disclosure, the second insulating film may have a thickness of 100 nm or more and 120 nm or less.

[0024] In a semiconductor device according to one embodiment of the present disclosure, the auxiliary electrode may include a first portion embedded in the first recess and a second portion integrally formed with the first portion and formed on the first main surface of the semiconductor layer, and may also include a third insulating film formed between the second portion of the auxiliary electrode and the second electrode layer and having a contact hole for connecting the auxiliary electrode to the second electrode layer, and a conductive member connected to the second electrode layer in a region avoiding the contact hole in a planar view.

[0025] For example, a step occurs between the surface of the third insulating film and the bottom surface of the contact hole (the surface of the second portion of the auxiliary electrode). Due to this step, the portion of the second electrode layer filled in the contact hole may be recessed compared to other regions of the second electrode layer. Therefore, by connecting the conductive member to the second electrode layer in a region that avoids the contact hole, poor connection of the conductive member can be prevented.

[0026] In the semiconductor device according to the embodiment of the present disclosure, the second electrode layer may include a pad electrode layer to which the conductive member is connected. Detailed Description of Embodiments of the Present Disclosure Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following detailed description, there are a plurality of components with names each having an ordinal number, but the ordinal numbers do not necessarily match the ordinal numbers of the components described in the claims. [First embodiment] 1 is a schematic overhead view of a semiconductor device 1 according to a first embodiment of the present disclosure. For clarity, in FIG. 1, a package 4 is shown by an imaginary line (broken line), and other components are shown by solid lines.

[0027] The semiconductor device 1 includes a lead frame 2 , a conductive member 3 , a package 4 , and a semiconductor element 5 .

[0028] The lead frame 2 is a metal member formed into a plate shape. The lead frame 2 is formed by punching, cutting, bending, etc. from a thin metal plate made of Cu or the like that is rectangular in plan view. Therefore, the main component of the material of the lead frame 2 is Cu. However, the material of the lead frame 2 is not limited to this.

[0029] The lead frame 2 may include a die pad portion 21, a first lead portion 22, a second lead portion 23, and a third lead portion 24. In this embodiment, the first lead portion 22, the second lead portion 23, and the third lead portion 24 may be referred to as a gate lead portion, a collector lead portion, and an emitter lead portion, respectively. Furthermore, the first lead portion 22, the second lead portion 23, and the third lead portion 24 are partially exposed from the package 4 and have portions connected to an external circuit of the semiconductor device 1, so they may also be referred to as a first terminal (gate terminal), a second terminal (collector terminal), and a third terminal (emitter terminal). Furthermore, a portion of the die pad portion 21 is also exposed from the package 4.

[0030] In a plan view, the die pad portion 21 has a rectangular shape having a pair of first sides 211A, 211B extending in a first direction X and a pair of second sides 212A, 212B extending in a direction intersecting the first direction X (in this embodiment, a direction perpendicular to the first direction X, that is, a second direction Y). A hole 25 is formed in the die pad portion 21. The hole 25 is exposed from the package 4 and is used, for example, as a screw hole when fixing the semiconductor device 1 to a mounting board (not shown) or a cooling housing (not shown).

[0031] The first lead portion 22, the second lead portion 23 and the third lead portion 24 are disposed adjacent to one first side 211A of the die pad portion 21.

[0032] The first lead portion 22 is formed apart from the die pad portion 21. The first lead portion 22 may include a first pad portion 221 and a first lead 222. In a plan view, the first pad portion 221 is formed in a generally rectangular shape extending along the first side 211A of the die pad portion 21. The first lead 222 is formed integrally with the first pad portion 221, and extends from the first pad portion 221 in a direction intersecting the longitudinal direction of the first pad portion 221.

[0033] The second lead portion 23 is formed integrally with the die pad portion 21. The second lead portion 23 extends in the second direction Y from the die pad portion 21.

[0034] The third lead portion 24 is formed apart from the die pad portion 21. The third lead portion 24 may include a third pad portion 241 and a third lead 242. In a plan view, the third pad portion 241 is formed in a generally rectangular shape extending along the first side 211A of the die pad portion 21. The third lead 242 is formed integrally with the third pad portion 241, and extends from the third pad portion 241 in a direction intersecting the longitudinal direction of the third pad portion 241.

[0035] The conductive member 3 is a member for connecting the lead frame 2 to the semiconductor element 5. In this embodiment, the conductive member 3 is made of a metal wire. The conductive member 3 is not limited to a wire, and may be a clip or the like. The conductive member 3 is made of a conductive material containing, for example, Au, Cu, or Al. The conductive member 3 includes a first wire 31 connecting the first lead portion 22 to the semiconductor element 5, and a second wire 32 connecting the third lead portion 24 to the semiconductor element 5. A plurality of first wires 31 may be connected to the first lead portion 22 and the semiconductor element 5. A plurality of second wires 32 may be connected to the third lead portion 24 and the semiconductor element 5.

[0036] The package 4 covers the lead frame 2, the conductive member 3, and a portion of the semiconductor element 5, and may also be called a sealing resin. The package 4 is made of an insulating material. In this embodiment, the package 4 is made of, for example, black epoxy resin.

[0037] The semiconductor element 5 is disposed on the die pad portion 21 of the lead frame 2 and is supported by the die pad portion 21. In a plan view, the semiconductor element 5 has a rectangular shape that is smaller than the die pad portion 21 and has a pair of first sides 51A, 51B and a pair of second sides 52A, 52B. In this embodiment, the semiconductor element 5 is disposed on the die pad portion 21 so that the first sides 51A, 51B are parallel to the first sides 211A, 211B of the die pad portion 21 and the second sides 52A, 52B are parallel to the second sides 212A, 212B of the die pad portion 21.

[0038] Fig. 2 is a schematic plan view of a semiconductor element 5 in one embodiment of the semiconductor device 1 of Fig. 1. Fig. 3 is a schematic view of a cross section taken along line III-III in Fig. 2. Fig. 4 is a schematic view of a cross section taken along line IV-IV in Fig. 2. Note that Figs. 3 and 4 do not show the cross section of Fig. 2 at the same scale.

[0039] The semiconductor element 5 includes a semiconductor chip 6, an insulating film 7, a control electrode 8, an auxiliary electrode 82, an interlayer insulating film 9, a surface electrode film 10, and a collector electrode film 11.

[0040] The semiconductor chip 6 is, for example, a structure in which a single-crystal semiconductor material is formed into a chip shape (rectangular parallelepiped shape). The semiconductor chip 6 is formed of a semiconductor material such as Si or SiC. The semiconductor chip 6 has a first main surface 61A and a second main surface 62B opposite to the first main surface 61A. The first main surface 61A is a device surface on which functional devices are formed. The second main surface 61B is a non-device surface on which no functional devices are formed. In this embodiment, a cell structure of an IGBT (Insulated Gate Bipolar Transistor) device is formed on the first main surface 61A. The device structure formed on the semiconductor chip is not limited to this and may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor chip 6 may also be referred to as a semiconductor layer.

[0041] The semiconductor chip 6 is formed with a first region 621 (n drift) of a first conductivity type, a second region 622 (p base of the IGBT, p body of the MOSFET) of a second conductivity type, a third region 623 (n emitter of the IGBT, n source of the MOSFET) of a first conductivity type, a fourth region 624 (p well) of a second conductivity type, a fifth region 625 (p+ contact) of a second conductivity type, a sixth region 626 (collector) of a second conductivity type, a field limit region 628 of the second conductivity type, a channel stop region 629 of the first conductivity type, a first recess 631, and a second recess 632.

[0042] The first region 621 is formed over the entire surface layer of the first main surface 61A of the semiconductor chip 6. In this embodiment, the first region 621 may be formed of an epitaxial layer. The n-type impurity concentration of the first region 621 is 1.0×10 13 cm -3 Over 1.0 x 10 15 cm -3 The first region 621 may be referred to as a drift region.

[0043] The second region 622 is a p-type impurity region formed in the surface layer portion of the first main surface 61A in the first region 621. The p-type impurity concentration of the second region 622 is 1.0×10 17 cm -3 Over 1.0 x 10 18 cm -3 The second regions 622 may be arranged in a planar pattern such as a stripe pattern or a matrix pattern.

[0044] The third region 623 is an n-type region selectively formed in a surface layer portion of the first main surface 61A in each second region 622. At least one third region 623 is formed in each second region 622. The third region 623 is in contact with the second region 622, and at least a portion of the third region 623 is exposed from the first main surface 61A. The n-type impurity concentration of the third region 623 is higher than the n-type impurity concentration of the first region 621, and is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The third region 623 may be referred to as an emitter region.

[0045] The fourth region 624 is a p-type impurity region selectively formed in the surface layer portion of the first main surface 61A in the first region 621. The fourth region 624 is formed in a region of the surface layer portion of the first main surface 61A where the third region 623 and the fifth region 625 are not formed. The fourth region 624 may be physically separated from the second region 622 and surround the second region 622. The fourth region 624 is formed deeper than the second region 622. A depth D1 of the fourth region 624 from the first main surface 61A may be, for example, 7 μm or more and 10 μm or less. The p-type impurity concentration of the fourth region 624 is 1.0×10 16 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0046] The fifth region 625 is a p-type impurity region formed in the surface layer portion of the first main surface 61A in the second region 622. The fifth region 625 extends from the first main surface 61A through the third region 623 to the second region 622. The p-type impurity concentration of the fifth region 625 is higher than the p-type impurity concentration of the second region 622. The p-type impurity concentration of the fifth region 625 is 1.0×10 19 cm -3 Over 1.0 x 10 21 cm -3 The fifth region 625 may be referred to as a contact region.

[0047] The sixth region 626 is a p-type impurity region formed in a surface layer portion of the second main surface 61B of the semiconductor chip 6. The sixth region 626 is exposed from the second main surface 61B of the semiconductor chip 6. The sixth region 626 may be formed over the entire semiconductor chip 6. The sixth region 626 may be formed partially in the semiconductor chip 6. For example, a portion of the sixth region 626 in FIGS. 3 and 4 may be formed as an n-type region, and the collector electrode film 11 may be connected to this n-type region. As a result, the semiconductor element 5 may be a reverse conducting IGBT (RC-IGBT). In this embodiment, the sixth region 626 may be formed of a semiconductor substrate. The p-type impurity concentration of the sixth region 626 is higher than the p-type impurity concentration of the second region 622. The p-type impurity concentration of the sixth region 626 is 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 The sixth region 626 may be referred to as the collector region.

[0048] The field limit region 628 is a p-type impurity region selectively formed in a surface layer portion of the first main surface 61A in the first region 621. The field limit region 628 has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the fourth region 624. The field limit region 628 has a depth that is approximately equal to the depth D1 of the fourth region 624.

[0049] The field limit region 628 is formed as a field limit region group including a plurality of (four in this embodiment) field limit regions 628A, 628B, 628C, and 628D. The field limit regions 628A to 628D are formed in this order at intervals along a direction away from the fourth region 624. The field limit regions 628A to 628D may be physically separated from the fourth region 624 and may surround the fourth region 624. The field limit regions 628A to 628D extend in a band shape along the periphery of the fourth region 624 in a plan view. More specifically, the field limit regions 628A to 628D are formed in an endless shape (quadratic ring shape) surrounding the fourth region 624 in a plan view. The field limit regions 628A to 628D may also be referred to as FLR (Field Limiting Ring) regions.

[0050] The field limit regions 628A to 628D may be formed at equal intervals, or may not be spaced at regular intervals as shown in Fig. 4. In Fig. 4, the interval between the outermost field limit region 628D and the field limit region 628C immediately inside it is wider than the intervals between the other field limit regions 628A to 628C.

[0051] The channel stop region 629 is an n-type impurity region selectively formed in the surface layer portion of the first main surface 61A in the first region 621. The n-type impurity concentration of the channel stop region 629 is higher than the n-type impurity concentration of the first region 621, and is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 It may be the following:

[0052] The channel stop region 629 may be physically separated from the field limit region 628 and surround the field limit region 628. The channel stop region 629 extends in a strip shape along the periphery of the field limit region 628 in a plan view. More specifically, the channel stop region 629 is formed in an endless shape (a square ring shape) surrounding the fourth region 624 in a plan view.

[0053] The region surrounded by the fourth region 624 may be referred to as the active region 64, and the region outside the active region 64 may be referred to as the inactive region 65. The inactive region 65 may also be referred to as the peripheral region. The active region 64 is a region in which a cell structure 66 is formed, in which a current path is formed by voltage control of the control electrode 8. In the active region 64, a cell structure 66 (trench cell structure) including a second recess 632, the control electrode 8, the second region 622, the third region 623, and the fifth region 625 is formed.

[0054] The first recess 631 is a groove formed in a surface layer portion of the first main surface 61A. The first recess 631 is formed in a region of the semiconductor chip 6 where the fourth region 624 is formed. A depth D2 of the first recess 631 from the first main surface 61A is shallower than a depth D1 of the fourth region 624. That is, a part 6241 of the fourth region 624 is interposed between a bottom 633 of the first recess 631 and the first region 621 in the thickness direction of the semiconductor chip 6. Because the depth D2 of the first recess 631 from the first main surface 61A is shallower than the depth D1 of the fourth region 624, the bottom 633 of the first recess 631 is covered with the fourth region 624, thereby preventing an electric field from concentrating at the bottom 633 of the first recess 631. The depth D2 of the first recess 631 from the first main surface 61A may be, for example, 6 μm or less. It is preferable that a part 6241 of the fourth region 624 between the bottom 633 of the first recess 631 and the first region 621 has a thickness of 1 μm or more. A plurality of first recesses 631 may be formed. The first recesses 631 are formed in a stripe shape extending in the second direction Y.

[0055] The second recesses 632 are grooves formed in the surface layer of the first main surface 61A. The second recesses 632 are formed in a regular planar pattern and define cell structures 66 in the semiconductor chip 6. A plurality of second recesses 632 may be formed. For example, a plurality of second recesses 632 may be formed in a stripe shape extending in the second direction Y. As a result, the cell structure 66 (second region 622) may be formed between adjacent second recesses 632. The active region 64 may be defined as a region inside the outermost second recesses 632 of the stripe-shaped second recesses 632. When the second recesses 632 are formed in a lattice shape, the active region 64 may be defined as a region inside the ring-shaped second recesses 632 that form the outer periphery of the lattice. The second recesses 632 may also be referred to as a gate trench.

[0056] The second recess 632 penetrates the second region 622, the third region 623, and the fifth region 625, and reaches the first region 621. The second recess 632 has a depth D3 from the first main surface 61A that is substantially the same as that of the first recess 631.

[0057] The insulating film 7 is formed on the first major surface 61A. The insulating film 7 may be referred to as a gate insulating film. The insulating film 7 may include a first insulating film 71 and a second insulating film 72.

[0058] The first insulating film 71 is formed in the active region 64. The first insulating film 71 is formed so as to cover the second recess 632. The first insulating film 71 covers a part of the first main surface 61A and the inner wall 635 and bottom 636 of the second recess 632. The first insulating film 71 has an opening 711 through which the first main surface 61A is exposed. The first insulating film 71 is in contact with the second region 622 and the third region 623. The first insulating film 71 is made of an insulating material containing, for example, SiO2, SiN, or the like. The first insulating film 71 has a thickness of 100 nm or more and 120 nm or less.

[0059] The second insulating film 72 is formed to cover the first recess 631. The second insulating film 72 covers a part of the first main surface 61A, an inner wall 634 of the first recess 631, and a bottom 633 of the first recess 631. The second insulating film 72 is in contact with the fourth region 624. The second insulating film 72 is made of an insulating material containing, for example, SiO2, SiN, or the like. The second insulating film 72 has a thickness of 100 nm or more and 120 nm or less. The first insulating film 71 and the second insulating film 72 are integrally formed.

[0060] The control electrode 8 is accommodated in the second recess 632. The control electrode 8 is in contact with the first insulating film 71. The control electrode 8 faces the second region 622 via the first insulating film 71. When a voltage is applied to the control electrode 8, a current path (channel) is formed in the second region 622 on the inner wall 635 of the second recess 632. This structure enables miniaturization and a reduction in on-voltage compared to a planar structure. The control electrode 8 is made of a conductive material containing polysilicon or the like. The control electrode 8 may also be referred to as a gate electrode or a first gate electrode.

[0061] The auxiliary electrode 82 is in contact with the second insulating film 72. The auxiliary electrode 82 includes a first portion 821 embedded in the first recess 631 and a second portion 822 formed integrally with the first portion 821 and formed on the first main surface 61A. The first portion 821 protrudes from the second portion 822 toward the inside of the semiconductor chip 6. The auxiliary electrode 82 is made of a conductive material containing polysilicon or the like. As will be described later, the auxiliary electrode 82 is defined as an auxiliary electrode because it assists in increasing the parasitic capacitance between the first electrode film 101 and the second electrode film 102, but it may also be called a second gate electrode or a buried electrode.

[0062] The interlayer insulating film 9 is formed on the first main surface 61A. The interlayer insulating film 9 covers the insulating film 7, the control electrode 8, and the auxiliary electrode 82. The interlayer insulating film 9 is made of an insulating material containing SiO2, SiN, or the like.

[0063] A first through hole 91 and a second through hole 92 are formed in the interlayer insulating film 9. The first through hole 91 is formed above the active region 64. The first through hole 91 is formed so as to overlap an opening 711 formed in the first insulating film 71 in a plan view. The second through hole 92 is formed above the auxiliary electrode 82. The second through hole 92 is formed in a ring shape in a plan view.

[0064] The surface electrode film 10 includes a first electrode film 101 , a second electrode film 102 , a field electrode film 103 , and an EQR electrode film 104 .

[0065] The first electrode film 101 is formed on the interlayer insulating film 9 and is connected to the third region 623 and the fifth region 625 via a first through-hole 91 formed in the interlayer insulating film 9. The first electrode film 101 is an electrode that inputs a reference potential that serves as a basis for transistor operation. The first electrode film 101 is formed at least on the active region 64. A portion of the first electrode film 101 may be formed in a position facing the end 8211 of the first portion 821 in a planar view. The first electrode film 101 may also be referred to as an emitter electrode. The first electrode film 101 is made of a conductive material such as Al or Cu. The first electrode film 101 may include a plating layer of Ni, Au, or the like formed on such a conductive material. The first electrode film 101 may also be referred to as a first electrode layer.

[0066] The first electrode film 101 includes a first pad portion 1014 and a first lead portion 1012 .

[0067] The first pad portion 1014 is formed in an island shape, and one end of the first wire 31 is connected to the first wire connecting portion 1011. The first pad portion 1014 may also be called an emitter pad portion.

[0068] The first lead portion 1012 is led out from the first pad portion 1014. The first lead portion 1012 extends in a strip shape along the outer periphery of the first pad portion 1014 and is formed in an endless shape (quadratic ring shape) surrounding the first pad portion 1014. The first lead portion 1012 is connected to the fourth region 624 via a third through-hole 93 provided in the interlayer insulating film 9. The connection position between the first lead portion 1012 and the fourth region 624 (the position of the third through-hole 93) may be outside the first recess 631. The first lead portion 1012 may also be referred to as an emitter lead-out portion.

[0069] The second electrode film 102 is formed on the interlayer insulating film 9 and is connected to the second portion 822 of the auxiliary electrode 82 via a second through-hole 92 provided in the interlayer insulating film 9. The second electrode film 102 is an electrode that inputs a control signal for the semiconductor element 5. The second electrode film 102 covers the auxiliary electrode 82 in a plan view. In other words, the second electrode film 102 may face the second portion 822 of the auxiliary electrode 82 over the entire area from one end 1024 to the other end 1025 in the direction along the first main surface 61A in the cross-sectional view shown in FIG. 3 .

[0070] The second electrode film 102 is electrically connected to the control electrode 8 and the auxiliary electrode 82. This configuration allows for an increase in the insulating film 7 connected to the second electrode film 102, thereby increasing the parasitic capacitance between the first electrode film 101 and the second electrode film 102. As a result, a semiconductor device 1 with excellent electrostatic discharge resistance characteristics can be provided. The second electrode film 102 is made of a conductive material such as Al or Cu. The second electrode film 102 may include a plating layer of Ni, Au, or the like formed on such a conductive material. The second electrode film 102 may also be referred to as a second electrode layer.

[0071] The second electrode film 102 includes a second pad portion 1023 and a second lead portion 1022 .

[0072] The second pad portion 1023 is formed in an island shape, and one end of the second wire 32 is connected to the second wire connecting portion 1021. The second wire connecting portion 1021 is formed at a position that does not overlap the second through-hole 92 in a plan view. That is, one end of the second wire 32 is connected to the second electrode film 102 (second pad portion 1023) in a region that avoids the second through-hole 92 in a plan view. For example, a step is generated between the surface 94 of the interlayer insulating film 9 and the bottom surface 921 of the second through-hole 92 (the surface of the auxiliary electrode 82). Due to this step, the portion of the second electrode film 102 that is embedded in the second through-hole 92 may be recessed compared to other regions of the second electrode film 102. Therefore, by connecting the second wire 32 to the second electrode film 102 in a region that avoids the second through-hole 92, poor connection of the second wire 32 can be prevented.

[0073] The second lead portion 1022 is led out from the second pad portion 1023. The second lead portion 1022 extends in a strip shape along the outer periphery of the first electrode film 101, surrounds the first electrode film 101, and has a pair of open ends that open on one side of the first main surface 61A. The second lead portion 1022 may be formed in a gap 1013 between the first electrode film 101 and the first lead portion 1012. The second lead portion 1022 is made of a conductive material such as Al or Cu. The second lead portion 1022 may include a plating layer of Ni, Au, or the like formed on such a conductive material. The second lead portion 1022 may also be referred to as a gate finger.

[0074] The field electrode film 103 is formed to surround the first electrode film 101 and the second electrode film 102 in a planar view. The field electrode film 103 is formed as a field electrode film group including a plurality (four in this embodiment) of field electrode films 103A, 103B, 103C, and 103D. The field electrode films 103A to 103D are formed in this order at intervals along a direction away from the center of the semiconductor chip 6 in a planar view. The field electrode films 103A to 103D are electrically floating. In this embodiment, the field electrode films 103A to 103D are formed in an endless shape (a square ring shape) surrounding the first electrode film 101 and the second electrode film 102. At least one field electrode film 103 may be formed with ends. The field electrode film 103 is made of a conductive material, such as Al or Cu. The field electrode film 103 may include a plating layer of Ni, Au, or the like formed on such a conductive material. The field electrode films 103A to 103D are connected to the field limit regions 628A to 628D through the interlayer insulating film 9 and the insulating film 7, respectively.

[0075] The EQR (EQui-potential Ring) electrode film 104 is routed in a strip shape along the field electrode film 103 at an interval from the field electrode film 103D in a direction away from the center of the semiconductor chip 6. In this embodiment, the EQR electrode film 104 is formed in an endless shape (quadratic ring shape) surrounding the field electrode film 103. The EQR electrode film 104 is an electrode for maintaining the outer periphery of the semiconductor chip 6 at a constant potential. The EQR electrode film 104 is connected to the channel stop region 629 through the interlayer insulating film 9 and the insulating film 7.

[0076] A collector electrode film 11 is formed on the second main surface 61B. The collector electrode film 11 may be formed over the entire second main surface 61B. The collector electrode film 11 is in contact with the sixth region 626. The collector electrode film 11 is made of a conductive material containing, for example, Al, Ni, Ag, Au, or the like. In the collector electrode film 11, Ni and Au may be plated layers formed by plating.

[0077] The semiconductor element 5 may include a protective film 12. The protective film 12 covers at least a portion of each of the first electrode film 101, the second electrode film 102, the field electrode film 103, and the EQR electrode film 104. The protective film 12 has a first opening 121 that exposes a portion of the first electrode film 101 and a second opening 122 that exposes a portion of the second electrode film 102. The first opening 121 exposes at least the first wire connection portion 1011. The second opening 122 exposes at least the second wire connection portion 1021. The protective film 12 is made of a material including polyimide, etc.

[0078] Next, a method for manufacturing the semiconductor element 5 will be described with reference to Figures 5 to 10. Figures 5 to 10 are vertical cross-sectional views showing some of the manufacturing steps of the semiconductor device 1 in the order of steps.

[0079] 5, in manufacturing the semiconductor device 5, first, a semiconductor wafer 67 to be divided into semiconductor chips 6 is prepared. Next, a p-type sixth region 626 and an n-type first region 621 are formed in the semiconductor wafer 67 in this order from the second main surface 62B toward the first main surface 61A. A p-type fourth region 624, a p-type field limit region 628, and an n-type channel stop region 629 are selectively formed on the first main surface 61A side of the first region 621. The seventh region may be a semiconductor substrate.

[0080] 6, for example, by etching via photoresist (not shown), a first recess 631 is formed in a region of first main surface 61A where fourth region 624 is exposed, and a second recess 632 is formed in a region of first main surface 61A where first region 621 is exposed. Because first recess 631 and second recess 632 are formed simultaneously in the same process, the depths of first recess 631 and second recess 632 from first main surface 61A are approximately the same.

[0081] 7, a second region 622, a third region 623, and a fifth region 625 are formed in the region where the second recess 632 is formed. The fifth region 625 is formed closer to the first main surface 61A than the bottom 633 of the second recess 632. The second region 622 is formed closer to the first main surface 61A than the fifth region 625. The third region 623 is formed closer to the first main surface 61A than the second region 622, and is exposed from the first main surface 61A.

[0082] 8, for example, by thermal oxidation, an insulating film 7 is formed on the first main surface 61A so as to cover the first recess 631 and the second recess 632. The insulating film 7 includes a second insulating film 72 covering the first recess 631 and a first insulating film 71 covering the second recess 632. Next, for example, by CVD, a control electrode 8 is formed on the first insulating film 71, and an auxiliary electrode 82 is formed on the second insulating film 72.

[0083] 9, an interlayer insulating film 9 is formed on the first main surface 61A by, for example, a CVD method so as to cover the control electrode 8 and the auxiliary electrode 82. Next, a first through-hole 91 exposing the third region 623 and the fifth region 625, a second through-hole 92 selectively exposing a portion of the auxiliary electrode 82, and a third through-hole 93 exposing the fourth region 624 are formed by, for example, etching via a photoresist (not shown).

[0084] 10, a surface electrode film 10 is formed on the interlayer insulating film 9 by, for example, sputtering. Next, the surface electrode film 10 is patterned to divide it into a first electrode film 101, a second electrode film 102, a field electrode film 103, and an EQR electrode film 104. The first electrode film 101 is connected to the third region 623 and the fifth region 625 via the first through hole 91, and to the fourth region 624 via the third through hole 93. The second electrode film 102 is connected to the auxiliary electrode 82 via the second through hole 92. Next, a collector electrode film 11 is formed on the second main surface 61B by, for example, sputtering.

[0085] Thereafter, the semiconductor wafer 67 is divided into individual semiconductor chips 6, thereby manufacturing the semiconductor elements 5.

[0086] FIG. 11 is a circuit diagram showing the electrical structure of the semiconductor device 1. As shown in FIG.

[0087] The electrical configuration of the semiconductor element 5 can be represented schematically by a circuit diagram in which a capacitor 13 is connected between the gate and emitter of a conventional IGBT device, as shown in Fig. 11. In other words, the configuration of the semiconductor element 5 reduces the parasitic capacitance C ge is increasing.

[0088] In an IGBT device, the gate electrode is insulated by an insulating film, so there is parasitic capacitance between the gate, collector, and emitter terminals. The electrostatic breakdown resistance characteristics of an IGBT device are determined by the parasitic capacitance C ge and the parasitic capacitance C between the gate and collector gc The input capacitance C is the sum of ies =C ge +C gc Therefore, the parasitic capacitance C between the gate and emitter ge By increasing the capacitance, a semiconductor device having good electrostatic breakdown resistance characteristics can be provided.

[0089] Therefore, in this semiconductor element 5, the auxiliary electrode 82 is electrically connected to the control electrode 8 via the second electrode film 102. Since the auxiliary electrode 82 is embedded in the first recess 631, the parasitic capacitance C between the auxiliary electrode 82 and the fourth region 624, which face each other via the second insulating film 72, is reduced compared to when, for example, only the layer-like second portion 822 is formed along the first main surface 61A. ge This allows the gate-emitter parasitic capacitance C ge As a result, it is possible to provide a semiconductor device 1 having good electrostatic breakdown resistance characteristics.

[0090] Furthermore, according to the configuration of the semiconductor element 5, the collector-emitter parasitic capacitance Cge and the parasitic capacitance C between the gate and collector gc The output capacitance C is the sum of oes =C ce +C gc To prevent this, the output is turned off. oes This prevents the current caused by the current flowing and adversely affects characteristics such as the turn-off time, which is the time required for the output to be completely turned off.

[0091] Furthermore, auxiliary electrode 82 is formed in inactive region 65 outside active region 64. Therefore, even if auxiliary electrode 82 is formed, it is possible to suppress the influence of layout changes and the like on cell structure 66, and therefore it is possible to maintain the characteristics of semiconductor device 1, such as on-resistance. [Second embodiment] The cross-sectional structure of a semiconductor element 5 according to the second embodiment of the present disclosure will be described with reference to FIG.

[0092] In this embodiment, the first recess 631 is formed in a region that avoids an area below the second wire 32 connected to the second electrode film 102. A plurality of first recesses 631 may be formed. With this configuration, it is possible to suppress unevenness on the surface of the second wire connecting portion 1021 of the second electrode film 102, and therefore it is possible to satisfactorily bond the second wire 32 to the second electrode film 102. As the other configurations are the same as those of the first embodiment, a description thereof will be omitted. [Third embodiment] The cross-sectional structure of a semiconductor element 5 according to a third embodiment of the present disclosure will be described with reference to FIG.

[0093] In this embodiment, the first recess 631 is formed so that a depth D2 from the first main surface 61A is shallower than a depth D3 from the first main surface 61A of the second recess 632. In this case, the first recess 631 and the second recess 632 may be formed in separate steps. This configuration can prevent the electric field from concentrating at the bottom of the first recess 631. A plurality of first recesses 631 may be formed. The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0094] Although one embodiment of the present disclosure has been described above, the present disclosure can be embodied in other forms.

[0095] For example, a configuration may be adopted in which the conductivity types of the semiconductor portions of the semiconductor element 5 are reversed. For example, in the semiconductor element 5, the p-type portions may be n-type, and the n-type portions may be p-type.

[0096] In addition, various design modifications can be made within the scope of the claims.

[0097] This application corresponds to Patent Application No. 2021-003065 filed with the Japan Patent Office on January 12, 2021, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0098] 1: Semiconductor device 2: Lead frame 21: Die pad section 22: First lead part 221: First pad section 222: 1st lead 23: Second lead part 24: Third lead part 241: Third pad section 242: Third lead 25: Hole 3: Conductive material 31: First wire 32: Second wire 4: Package 5: Semiconductor elements 6: Semiconductor chip 61A: First main surface 61B: Second main surface 621: 1st area 622:Second area 623: Third area 624: 4th area 625: 5th area 626: 6th area 628: Field limit area 629: Channel stop region 631: First recess 632: Second recess 633: Bottom 634 :Inner wall 635 :Inner wall 636: Bottom wall 64: Active area 65: Inactive area 66: Cell structure 67: Semiconductor wafer 7: Insulating film 71: First insulating film 711 :Aperture 72: Second insulating film 8: Control electrode 82:Auxiliary electrode 821 :1st part 8211: End 822 :Second part 9: Interlayer insulating film 91: First through hole 92: Second through hole 921: Bottom 93: Third through hole 94 :Surface 10: Surface electrode film 101:First electrode film 1011: First wire connection 1012: First drawer 1013: Gap 1014: First pad section 102:Second electrode film 1021: Second wire connection 1022: Second drawer 1023: Second pad section 1024: One end 1025: Other end 103: Field electrode film 104 :EQR electrode membrane 11: Collector electrode film 12:Protective film 121: First opening 122: Second opening 13: Capacitor D1: Depth D2: Depth D3: Depth

Claims

1. a semiconductor layer having a first major surface and a second major surface opposite to the first major surface; a first region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer; a cell structure including: a second region of a second conductivity type formed on a surface layer portion of the first region; a third region of a first conductivity type formed on a surface layer portion of the first region so as to be in contact with the second region; and a control electrode facing the second region via a first insulating film adjacent to the second region and forming a current path in the second region; a first electrode layer formed on the first main surface of the semiconductor layer so as to cover the cell structure and electrically connected to the third region; a second electrode layer formed on the first main surface of the semiconductor layer, spaced apart from the first electrode layer, and electrically connected to the control electrode; a first recess formed in a surface layer portion of the first main surface of the semiconductor layer so as to face the second electrode layer; a second insulating film covering the first recess; an auxiliary electrode embedded in the first recess with the second insulating film interposed therebetween and electrically connected to the second electrode layer; the auxiliary electrode includes a first portion embedded in the first recess and a second portion formed integrally with the first portion and on the first main surface of the semiconductor layer; a semiconductor device, wherein the second electrode layer has one end and the other end when viewed from a direction perpendicular to the thickness direction of the semiconductor layer, the second portion has one end and the other end, and the one end and the other end of the second electrode layer are disposed between the one end and the other end of the second portion.

2. a fourth region of the second conductivity type formed on a surface layer portion of the first region so as to face the second electrode layer; The semiconductor device according to claim 1 , wherein said first recess is formed in said fourth region.

3. 3. The semiconductor device according to claim 2, wherein a part of said fourth region is interposed between a bottom of said first recess and said first region in a thickness direction of said semiconductor layer.

4. The semiconductor device according to claim 3 , wherein said portion of said fourth region has a thickness of 1 μm or more.

5. a first depth of the fourth region from the first main surface is equal to or greater than 7 μm and equal to or less than 10 μm; 5. The semiconductor device according to claim 2, wherein a second depth of said first recess from said first main surface is 6 μm or less.

6. The semiconductor device according to any one of claims 1 to 5, wherein the cell structure includes a trench cell structure having a second recess formed in a surface layer portion of the first main surface of the semiconductor layer, the control electrode embedded in the second recess via the first insulating film, and the third region and the second region formed on the side surface of the second recess in that order from the first main surface toward the second main surface.

7. 7. The semiconductor device according to claim 6, wherein said first recess and said second recess have substantially the same depth.

8. The semiconductor device according to claim 6 , wherein the depth of said first recess is smaller than the depth of said second recess.

9. 9. The semiconductor device according to claim 6, wherein the first recess and the second recess are both formed in a stripe shape extending in a first direction.

10. a collector region of a second conductivity type formed in a surface layer portion of the second main surface of the semiconductor layer, 10. The semiconductor device according to claim 1, wherein the cell structure includes an IGBT cell structure having a base region made of the second region, an emitter region made of the third region, and a gate electrode made of the control electrode.

11. a semiconductor layer having a first major surface and a second major surface opposite to the first major surface; an active region formed in a surface layer portion of the first main surface of the semiconductor layer, the active region having a control electrode formed on a first insulating film in contact with the semiconductor layer, and a cell structure in which a current path is formed by voltage control of the control electrode; a first electrode layer formed on the active region and connected to the current path; a second electrode layer formed on the first main surface of the semiconductor layer in a region outside the active region and electrically connected to the control electrode; a first recess formed in a surface layer portion of the first main surface of the semiconductor layer so as to face the second electrode layer; a second insulating film covering the first recess; an auxiliary electrode embedded in the first recess with the second insulating film interposed therebetween and electrically connected to the second electrode layer; the auxiliary electrode includes a first portion embedded in the first recess and a second portion formed integrally with the first portion and on the first main surface of the semiconductor layer; a semiconductor device, wherein the second electrode layer has one end and the other end when viewed from a direction perpendicular to the thickness direction of the semiconductor layer, the second portion has one end and the other end, and the one end and the other end of the second electrode layer are disposed between the one end and the other end of the second portion.

12. 12. The semiconductor device according to claim 1, wherein the second insulating film has a thickness of 100 nm or more and 120 nm or less.

13. A third insulating film formed between the second portion of the auxiliary electrode and the second electrode layer, the third insulating film having a contact hole for connecting the auxiliary electrode and the second electrode layer; 13. The semiconductor device according to claim 1, further comprising: a conductive member connected to said second electrode layer in a region avoiding said contact hole in a plan view.

14. The semiconductor device according to claim 13 , wherein the second electrode layer includes a pad electrode layer to which the conductive member is connected.

15. A semiconductor device as described in claim 1, comprising an interlayer insulating film arranged between the second electrode layer and the auxiliary electrode, and a through hole formed in the interlayer insulating film.

16. A semiconductor device as described in Claim 15, wherein a wire is connected to the second electrode layer in an area that avoids the through hole when viewed in a plane.

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