Lead frame and semiconductor device using the same

Abstract

To provide a lead frame capable of uniformly performing plasma surface treatment of a die pad even in a structure in which the position of the die pad is lower than a lead.SOLUTION: A lead frame 100 includes a die pad 101 on which a semiconductor chip 110 is fixed, and a plurality of leads 102 arranged around the die pad 101 and provided at a position higher than the die pad 101, and in a lead tip portion 102a, the width Wab of a lower surface 102ab is narrower than the width Waa of an upper surface 102aa.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a lead frame and a semiconductor device using the same. [Background technology]

[0002] In the manufacturing process of a resin-encapsulated semiconductor device, which is called a "post-process," a lead frame on which a die pad and leads are formed is often used first.

[0003] The specific manufacturing process involves fixing a semiconductor chip to the top surface of the die pad and electrically connecting the semiconductor chip to the leads with bonding wires. Next, the lead frame is sandwiched between two molds, and resin is injected into the molds, solidified, and sealed, and then the molds are separated into individual pieces to produce multiple semiconductor devices.

[0004] In such manufacturing processes, plasma surface treatment is often performed before fixing the semiconductor chip to the die pad, before wire bonding, before injecting resin, etc., in order to remove particles, oxides, unnecessary resin, etc. remaining on the surfaces of the lead frame, semiconductor chip, etc. It is known that this plasma surface treatment improves the bonding strength of the bonding wire and the adhesion between the lead frame and the encapsulating resin.

[0005] In such resin-sealed semiconductor devices, as the semiconductor chip fixed to the die pad becomes more functional, power consumption increases, so structures have been proposed that make it easier to dissipate heat generated by the semiconductor chip to the outside. For example, a structure has been proposed in which a downset process is performed on a lead frame to make the die pad lower than the leads, thereby exposing the lower surface of the die pad from the sealing resin (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-165777 Summary of the Invention [Problem to be solved by the invention]

[0007] Therefore, one aspect of the present invention aims to provide a lead frame that allows uniform plasma surface treatment of the die pad even when the die pad is located lower than the leads. [Means for solving the problem]

[0008] The lead frame in one embodiment of the present invention comprises: a die pad on which a semiconductor chip is fixed; a plurality of leads arranged around the die pad and positioned higher than the die pad; and The tip of the lead is characterized in that the width of the lower surface is narrower than the width of the upper surface. [Effects of the Invention]

[0009] According to one aspect of the present invention, it is possible to provide a lead frame in which the die pad can be uniformly plasma surface treated even if the die pad is located lower than the leads. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic top view showing a lead frame in this embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing a lead frame in this embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view showing a state after a semiconductor chip has been mounted on the lead frame in this embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing the state after the lead frame and the semiconductor chip have been connected by wire bonding in this embodiment. [Figure 5] FIG. 5 is a schematic side view showing a semiconductor device using the lead frame of this embodiment. [Figure 6] FIG. 6 is a schematic top view showing a lead frame according to a modified example of this embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a lead frame according to a modified example of this embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a state after the lead frame and the semiconductor chip have been connected by wire bonding in a modified example of this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present invention is based on the finding that in the lead frame of a semiconductor device as shown in FIG. 3 of Patent Document 1, the die pad is positioned lower than the leads, making it difficult to perform uniform plasma surface treatment of the die pad. Specifically, the greater the difference in height between the leads and the die pad, the more likely it is that the plasma surface treatment of the die pad will be insufficient. This phenomenon is called the shadow effect of plasma surface treatment, and is likely to occur when a shielding structure is present on the target object. As a result, even if plasma surface treatment is performed on the die pad, the shadow effect may occur, and particles, unnecessary resin, oxides, etc. may remain on the die pad, which is located lower than the leads. In such a case, when a semiconductor chip is mounted on the die pad, particles, etc. may become trapped, causing the semiconductor chip to be mounted at an angle, which may cause problems with the wire bonding connection and reduce the reliability of the semiconductor device.

[0012] Therefore, in one embodiment of the present invention, the lead frame has a die pad on whose upper surface a semiconductor chip is fixed, and a plurality of leads arranged around the die pad and positioned higher than the die pad, and the tip portions of these leads have a width on the lower surface that is narrower than the width on the upper surface. As a result, even if this lead frame has a structure in which the die pad is positioned lower than the leads, the volume of the underside of the lead tip portion located near the die pad is reduced to ensure space near the die pad, making it less likely to be shielded and allowing uniform plasma surface treatment of the die pad.

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, identical components are denoted by the same reference numerals, and redundant explanations may be omitted. Furthermore, in the drawings, the X, Y, and Z directions are perpendicular to one another. The direction including the X direction and the opposite direction of the X direction (-X direction) is referred to as the "X-axis direction," the direction including the Y direction and the opposite direction of the Y direction (-Y direction) is referred to as the "Y-axis direction," and the direction including the Z direction and the opposite direction of the Z direction (-Z direction) is referred to as the "Z-axis direction" (height direction, thickness direction). In this regard, in the following embodiments, the surface of each film facing the Z direction may be referred to as the "surface." The drawings are schematic, and the ratios of width, length, depth, etc. are not as shown in the drawings.

[0014] (Example of embodiment) FIG. 1 is a schematic top view showing a lead frame in this embodiment. As shown in FIG. 1, a lead frame 100 includes a die pad 101 and a plurality of leads 102. The die pad 101 is connected to a tie bar 104 via a suspension lead 103. The leads 102 are connected directly to the tie bar 104. Furthermore, the lead frame 100 is formed with a plurality of combinations of a die pad 101, a plurality of leads 102, and a suspension lead 103, and FIG. 1 shows one combination that forms one semiconductor device.

[0015] This lead frame 100 is made of a copper alloy and serves as the base of the semiconductor device. As will be described in detail later, a semiconductor chip is fixed to a die pad 101, and a plurality of leads 102 are electrically connected to the electrode pads of the semiconductor chip with bonding wires (see FIG. 3). After that, the lead frame 100 is sandwiched between two molds, and a sealing resin is injected into the molds and allowed to harden. At this time, portions of the leads 102 are exposed so that they function as external terminals, and the lead frame 100 is divided into individual pieces to manufacture a plurality of semiconductor devices.

[0016] A plurality of leads 102 are arranged around the die pad 101. Each lead 102 has a lead tip 102a located on the side adjacent to the die pad 101 and a lead body 102b connected to a tie bar 104.

[0017] Width W of lead tip 102a aa is the width W of the lead body 102b b In this embodiment, the width W of the lead tip 102a is narrower than aa is the width W of the lead body 102b b It is narrowed to about half of the original width. This reduces the area of ​​the lead tip 102a located near the die pad 101 and reduces obstructions near the die pad 101, making it less likely that a shadow effect will occur even if plasma surface treatment is performed on the die pad 101.

[0018] Furthermore, the lead tip portions 102a of adjacent pairs of leads 102 among the plurality of leads 102 are spaced apart from each other. That is, the adjacent pairs of leads 102 are spaced apart from each other by a distance G between the lead tip portions 102a. aa The distance G between the lead body portions 102b is b The lead tips 102a are spaced apart so that the lead width is wider than the width of the lead tip 102a. This ensures a wide area near the die pad 101 where no obstructions exist.

[0019] In this embodiment, the lead tip 102a is plated with silver and is electrically connected to an electrode pad provided on the upper surface of the semiconductor chip by a bonding wire.

[0020] FIG. 2 is a schematic cross-sectional view showing a lead frame in this embodiment. As shown in FIG. 2, in the lead frame 100, the suspension leads 103 are downset, so that the position of the die pad 102 is lower than the positions of the leads 102 and the tie bars 104.

[0021] The lead tip 102a has a width W of the tip top surface 102aa. aa The width W of the lead body 102b is b (See FIG. 1), and the width W ab The width W of the top surface 102aa of the tip aa That is, the lead tip 102a has a notch 102ac extending from its side surface to the tip bottom surface 102ab. This reduces the volume of the lead tip 102a located near the die pad 101 and reduces the amount of obstruction near the die pad 101, making it less likely that a shadow effect will occur even if plasma surface treatment is performed on the die pad 101.

[0022] The method for providing the notch 102ac in the lead tip 102a can be selected appropriately, and examples thereof include methods such as press working and etching. Specifically, first, a press working is performed to form a recess on the lower surface of the lead 102 to a depth of about half the thickness of the lead 102. The width of this recess on the lower surface of the lead 102 is set to the distance G between the lower surface 102ab of the tip portion. ab Next, the distance G between the top surface 102aa of the tip end portion is adjusted to match the position of the recess. aaBy performing a press process to shear the lead 102 at a width of 102a, the notched portion 102ac can be provided at the lead tip 102a. Alternatively, the recessed portion may be formed by etching.

[0023] Furthermore, the lead tip portions 102a of the pair of adjacent leads 102 among the plurality of leads 102 are spaced apart by a distance G between the top surfaces 102aa of the tip portions. aa Distance G between the tip end undersurface 102ab and the ab That is, in the adjacent pair of leads 102, notches 102ac are provided on the opposing side surfaces. This ensures a large space near the die pad 101 where no obstructions exist.

[0024] In this way, even if the lead frame 100 has a structure in which the die pad 101 is positioned lower than the lead 102, the volume of the lower surface 102ab of the tip of the lead 102 located close to the die pad 101 is reduced to ensure space near the die pad 101, making it less likely to be shielded and allowing uniform plasma surface treatment of the die pad 101.

[0025] Next, a method for manufacturing a resin-sealed semiconductor device using the lead frame 100 will be described with reference to FIGS.

[0026] In a method for manufacturing a resin-encapsulated semiconductor device, first, plasma surface treatment is performed on the lead frame 100 to remove particles, unnecessary resin, oxides, etc. from the upper surface of the lead frame 100 including the die pad 101. Although the die pad 101 is positioned lower than the leads 102, as described above, the shape of the lead tips 102a ensures space near the die pad 101, so that the plasma surface treatment can be performed uniformly even on the upper surface of the die pad 101.

[0027] Next, as shown in Fig. 3, the semiconductor chip 110 is fixed to the upper surface of the die pad 101 with a conductive adhesive 120. At this time, the conductive adhesive 120 is heated and hardened, which may cause particles or unnecessary resin to adhere or generate oxides. Therefore, after performing plasma surface treatment again to remove these, multiple electrode pads (not shown) formed on the upper surface of the semiconductor chip 110 are electrically connected to the tip upper surfaces 102aa of the multiple leads 102 with bonding wires 130, as shown in Fig. 4.

[0028] Next, the lead frame 100 is sandwiched between two molds (not shown), and a sealing resin is injected into the molds and solidified to seal them, and then the molds are separated into individual pieces, thereby manufacturing the semiconductor device 10 as shown in Fig. 5. As shown in Fig. 5, all or part of the lead body 102b is exposed from the sealing resin 140, and is separated from the tie bar 104 shown in Fig. 1 and deformed to function as an outer lead. In addition, in order to improve the heat dissipation of the semiconductor chip 110, it is preferable that the underside of the die pad 101 is also exposed from the sealing resin 140.

[0029] Thus, the semiconductor device 10 in this embodiment includes, in addition to the lead frame 100, a semiconductor chip 110 fixed to the upper surface of the die pad 101 and having a plurality of electrode pads each electrically connected to the lead tip portion 102a by a bonding wire 130, and a sealing resin 140 covering at least the semiconductor chip 110 and the bonding wire 130. As a result, when the lead frame 100 is subjected to plasma surface treatment during the manufacture of the semiconductor device 10, the plasma surface treatment can be performed uniformly also on the upper surface of the die pad 101, making it difficult for particles to remain. This reduces the likelihood of wire bonding problems occurring when the semiconductor chip 110 is mounted at an angle, thereby improving the reliability of the semiconductor device 10.

[0030] (Modification of this embodiment) FIG. 6 is a schematic top view showing a lead frame according to a modified example of this embodiment. 6, the modified example of this embodiment is the same as this embodiment except that the lead tip 102a of the lead 102 of this embodiment is replaced with a lead 105 having a lead tip 105a with a different shape. Therefore, since the configuration is the same except for the lead tip 105a, the same components are denoted by the same reference numerals and their description will be omitted.

[0031] Width W of lead tip 105a aa is the width W of the lead body 105b b is equivalent to This prevents the area of ​​the tip portion upper surface 105aa from becoming smaller, making it possible to connect a plurality of bonding wires to the tip portion upper surface 105aa or to connect a bonding wire with a large diameter.

[0032] Furthermore, the lead tip portions 105a of adjacent pairs of leads 105 among the plurality of leads 105 are spaced apart from each other. That is, the adjacent pairs of leads 105 are spaced apart from each other by a distance G between the lead tip portions 105a. aa The distance G between the lead bodies 105b is b The lead tips 105a are spaced apart so that the lead width is wider than the width of the lead tip 105a. This ensures a wide area near the die pad 101 where no obstructions exist.

[0033] FIG. 7 is a schematic cross-sectional view showing a lead frame according to a modified example of this embodiment. The lead tip 105a has a width W of the tip lower surface 105ab, similar to the lead tip 102a. ab The width W of the top surface 105aa of the tip aa That is, the lead tip 105a has a notch 105ac extending from its side surface to the tip bottom surface 105ab. This reduces the volume of the lead tip 105a located near the die pad 101 and reduces the amount of obstruction near the die pad 101, making it less likely that a shadow effect will occur even if plasma surface treatment is performed on the die pad 101.

[0034] Furthermore, as described above, the area of ​​the tip portion upper surface 105aa of the modified example is not smaller than the tip portion upper surface 102aa, so that an area can be secured to connect multiple bonding wires or a bonding wire with a large diameter to the tip portion upper surface 105aa, as shown in FIG. 8.

[0035] As described above, the lead frame in one embodiment of the present invention has a die pad to which a semiconductor chip is fixed on its upper surface, and a plurality of leads arranged around the die pad and positioned higher than the die pad, and the tips of the leads are narrower on the lower surface than on the upper surface. As a result, even if this lead frame has a structure in which the die pad is positioned lower than the leads, the volume of the underside of the lead tip portion located near the die pad is reduced to ensure space near the die pad, making it less likely to be shielded and allowing uniform plasma surface treatment of the die pad.

[0036] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to this embodiment, and includes designs within the scope of the invention that do not deviate from the gist of the invention. For example, in this embodiment, the lead tip 102a is silver plated, but it does not have to be silver plated. [Explanation of symbols]

[0037] 10 Semiconductor devices 100 lead frames 101 die pad 102, 105 leads 102a, 105a Lead tip 102aa, 105aa Tip top surface 102ab, 105ab Bottom surface of tip 102ac, 105ac Notched part 102b, 105b Lead body 103 Hanging Lead 104 Tie Bar 110 Semiconductor Chips 120 Conductive adhesive 130 Bonding Wire 140 Sealing resin G aa Spacing (above the lead tips) G ab Spacing (underneath lead tips) G b Spacing (of lead body) W aa Width (top of lead tip) W ab Width (under the lead tip) W b Width (of lead body)

Claims

1. a die pad on which a semiconductor chip is fixed; a plurality of leads arranged around the die pad and positioned higher than the die pad; and The lead has a tip portion having a width narrower than a body portion, In the adjacent pairs of leads among the plurality of leads, The structure is symmetrical both in plan view and cross-sectional view, In a plan view, the width of the tip portion only on the adjacent side is narrower than the width of the main body portion so that the tip portions are spaced apart more from each other than the main body portion, A lead frame characterized in that, in a cross-sectional view, the width of each of the tip ends narrows from the upper surface to the lower surface so that the width is narrowest at the lower surface, and the spacing between the lower surfaces is wider than the spacing between the upper surfaces.

2. A lead frame as described in Claim 1, wherein the tip of the lead has an upper surface that is silver-plated.

3. A lead frame according to claim 1 or 2, the semiconductor chip having a plurality of electrode pads fixed to an upper surface of the die pad of the lead frame and electrically connected to the tip ends of the leads by bonding wires, respectively; a sealing resin that covers at least the semiconductor chip and the bonding wires; A semiconductor device comprising:

4. A semiconductor device as described in claim 3, wherein the underside of the die pad is exposed.

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