Imaging device

Abstract

To provide an imaging device of low power consumption.SOLUTION: In a pixel, a first circuit and a second circuit are provided. The first circuit can generate imaging data, and can keep differential data from data acquired in an initial frame. In the second circuit, a circuit that compares the differential data with the voltage range that is optionally set is provided. The second circuit supplies a readout signal according to the comparison result to the first circuit. With this structure, readout is not performed from the pixel when it is determined that the differential data is within the set voltage range and readout is performed from the pixel only when it is determined that the differential data is not within the voltage range.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, memory devices, imaging devices, and operation methods thereof or manufacturing methods thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a pixel circuit that uses a transistor that includes an oxide semiconductor and has extremely low off-state current. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 Summary of the Invention [Problem to be solved by the invention]

[0006] When capturing moving images using a CMOS image sensor, data acquired from all pixels is read out for each frame. In this operation, data that can be considered identical may be acquired from the same pixel in multiple consecutive frames.

[0007] For example, a still subject outdoors is subject to changes in the brightness of natural light over time, but at short intervals of 1 / 10 seconds or less, which corresponds to the frame rate of moving images, there is almost no change that can be discerned by humans. In other words, it can be said that data that can be considered identical is acquired across multiple frames.

[0008] The data is read out for each frame, consuming power. If the data can be considered identical, power consumption can be reduced by omitting the read operation.

[0009] Therefore, an object of one embodiment of the present invention is to provide an imaging device with low power consumption. Another object is to provide an imaging device that can detect a change in a subject. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for operating the imaging device. Another object is to provide a novel semiconductor device or the like.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention relates to an imaging device having a circuit that compares data between adjacent frames and determines which pixels to read.

[0012] One embodiment of the present invention is an imaging device including a pixel having a first circuit and a second circuit, wherein the first circuit includes a first node, a second node, and a first switch. The first node has a function of holding first image data generated in a first frame period. The first node has a function of holding second image data generated in an nth frame period (n is a natural number equal to or greater than 2). The second node has a function of holding differential data that is a difference between the first image data and the second image data. The first switch has a function of controlling output of the first image data and the second image data. The second circuit includes a comparison circuit and an output circuit. The comparison circuit has a function of determining whether the differential data is within a predetermined voltage range. The output circuit has a function of outputting a voltage that turns off the first switch when the differential data is within the voltage range and a voltage that turns on the first switch when the differential data is not within the voltage range.

[0013] The first circuit may include a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor, wherein one electrode of the photoelectric conversion device is electrically connected to one of a source or a drain of the first transistor, the other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, a gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor, one of the source or the drain of the third transistor is electrically connected to one of a source or a drain of the fourth transistor, the other of the source or the drain of the third transistor is electrically connected to one of a source or a drain of the fifth transistor, and the other electrode of the second capacitor is electrically connected to one of a source or a drain of the sixth transistor. The fifth transistor may operate as a first switch.

[0014] The first circuit may further include a seventh transistor, one of the source or drain of which is electrically connected to the other of the source or drain of the first transistor and one of the source or drain of the second transistor, and the other of the source or drain of the seventh transistor is electrically connected to the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor.

[0015] The first to seventh transistors preferably have a metal oxide in a channel formation region, which can include In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0016] The comparison circuit may have a first sense amplifier and a second sense amplifier, the first sense amplifier having a third node, the second sense amplifier having a fourth node, the output circuit having a fifth node, the first sense amplifier having a first input section for inputting a voltage at the lower end of a voltage range, the second sense amplifier having a second input section for inputting a voltage at the upper end of the voltage range, the first sense amplifier and the second sense amplifier each having a third input section to which the second node is electrically connected, the third node and the fourth node being electrically connected to the output circuit, and the fifth node being electrically connected to the first switch.

[0017] The third input section may be electrically connected to the second node of one pixel, and the fifth node may be electrically connected to the first switches of a plurality of pixels.

[0018] The second circuit may further include an inverter circuit, and the transistors included in the inverter circuit, the first sense amplifier, the second sense amplifier, and the output circuit may have silicon in their channel formation regions.

[0019] Alternatively, the first and second sense amplifiers may each have a first power switch and a second power switch, the first power switch having a p-channel transistor, and the second power switch having an n-channel transistor, the n-channel transistor having a metal oxide in a channel formation region. The metal oxide preferably includes In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0020] The first circuit and the second circuit may have an overlapping region, or multiple first circuits and one second circuit may have an overlapping region.

[0021] Another aspect of the present invention is a method of operating an imaging device, which sets a first voltage and a second voltage (first voltage<second voltage) in a pixel, acquires first image data in a first frame period, acquires second image data in an nth frame period (n is a natural number greater than or equal to 2), calculates a third voltage which is the difference between the first image data and the second image data, compares the first voltage, the second voltage, and the third voltage, and does not read out the second data from the pixel when the third voltage is greater than the first voltage and less than the second voltage, and reads out the second data from the pixel when the third voltage is less than the first voltage or when the third voltage is greater than the second voltage. [Effects of the Invention]

[0022] By using one embodiment of the present invention, an imaging device with low power consumption can be provided. Alternatively, an imaging device capable of detecting a change in a subject can be provided. Alternatively, an imaging device with high reliability can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a method for operating the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief explanation of the drawings]

[0023] [Figure 1]FIG. 1 is a diagram illustrating a pixel. [Figure 2] 2A and 2B are circuit diagrams illustrating the circuit 10. FIG. [Figure 3] FIG. 3 is a circuit diagram illustrating the circuit 11. As shown in FIG. [Figure 4] FIG. 4 is a timing chart illustrating the operation of the pixel. [Figure 5] FIG. 5 is a diagram illustrating the operation of the circuit 11. [Figure 6] FIG. 6 is a timing chart illustrating the operation of the pixel. [Figure 7] FIG. 7 is a diagram illustrating the operation of the circuit 11. [Figure 8] FIG. 8 is a diagram illustrating the operation of the circuit 11. [Figure 9] FIG. 9 is a timing chart illustrating the operation of the pixel. [Figure 10] FIG. 10 is a diagram illustrating the operation of the circuit 11. [Figure 11] FIG. 11 is a timing chart illustrating the operation of the pixel. [Figure 12] FIG. 12 is a diagram illustrating the operation of the circuit 11. [Figure 13] FIG. 13 is a timing chart illustrating the operation of the pixel. [Figure 14] FIG. 14 is a block diagram illustrating the imaging device. [Figure 15] 15A to 15D are diagrams illustrating the configuration of a pixel. [Figure 16] FIG. 16 is a block diagram illustrating the configuration of a pixel. [Figure 17] FIG. 17 is a block diagram illustrating the configuration of a pixel. [Figure 18] 18A and 18B are circuit diagrams illustrating the circuit 10. FIG. [Figure 19] 19A to 19E are circuit diagrams illustrating a portion of the circuit 10. FIG. [Figure 20] 20A and 20B are circuit diagrams illustrating the circuit 10. FIG. [Figure 21] 21A to 21D are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 22] 22A to 22C are diagrams illustrating the configuration of a photoelectric conversion device. [Figure 23] FIG. 23 is a cross-sectional view illustrating a pixel. [Figure 24] 24A to 24C are diagrams illustrating a Si transistor. [Figure 25] FIG. 25 is a cross-sectional view illustrating a pixel. [Figure 26] FIG. 26 is a cross-sectional view illustrating a pixel. [Figure 27] 27A to 27D illustrate an OS transistor. [Figure 28] FIG. 28 is a cross-sectional view illustrating a pixel. [Figure 29] FIG. 29 is a cross-sectional view illustrating a pixel. [Figure 30] FIG. 30 is a cross-sectional view illustrating a pixel. [Figure 31] 31A to 31C are perspective views (cross-sectional views) illustrating pixels. [Figure 32] 32A1 to 32A3 and 32B1 to 32B3 are perspective views of a package and a module that house an imaging device. [Figure 33] 33A to 33F are diagrams illustrating an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0025] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0026] Furthermore, a single conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0027] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0028] One embodiment of the present invention has a function of comparing data between frames and determining whether or not to perform readout based on the result of the comparison. Whether or not to perform readout can be controlled on a pixel-by-pixel basis.

[0029] Each pixel is provided with a first circuit and a second circuit. The first circuit generates image data and stores differential data, which is the difference between the image data and the initial frame data. The second circuit is provided with a circuit that compares the differential data with an arbitrarily set voltage range. The second circuit supplies a readout signal to the first circuit based on the comparison result.

[0030] By using this configuration, for example, if it is determined that the differential data is within a set voltage range, no reading is performed from the pixel, and if it is determined that the differential data is not within the voltage range, reading is performed from the pixel.

[0031] Therefore, if data that can be considered the same as the initial frame data is acquired, the read operation can be omitted, thereby reducing power consumption. Note that when this operation is performed, frame data can be generated by rewriting only the data of the pixels that have been read based on the initial frame data.

[0032] <Pixel circuit> FIG. 1 is a circuit diagram of a pixel included in an imaging device according to one embodiment of the present invention. The pixel includes a circuit 10 and a circuit 11. The circuit 10 has a function of generating and storing imaging data. The circuit 10 can also store differential data, which is the difference between data acquired during a first frame (initial frame) and data acquired during an nth frame (target frame) (n is a natural number greater than or equal to 2). The circuit 11 is a determination circuit that can determine whether the differential data is large or small and determine whether to read the data from the circuit 10.

[0033] <Circuit 10> The circuit 10 includes a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a transistor 106, a transistor 107, a capacitor 108, and a capacitor 109. Note that the capacitor 108 may be omitted.

[0034] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109. One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105. The other of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 106. The other electrode of the capacitor 109 is electrically connected to one of the source or drain of the transistor 107.

[0035] A gate of the transistor 106 is electrically connected to the circuit 11 through a wiring 242. The other electrode of the capacitor 109 is electrically connected to the circuit 11 through a wiring 241.

[0036] Here, the point (wiring) where the other of the source or drain of transistor 102, one of the source or drain of transistor 103, the gate of transistor 104, one electrode of capacitor 108, and one electrode of capacitor 109 are connected is referred to as node FD1. Also, the point (wiring) where the other electrode of capacitor 109, one of the source or drain of transistor 107, and wiring 241 are connected is referred to as node FD2. Node FD1 can hold data acquired in each frame period. Node FD2 can hold data of the initial frame or differential data that is the difference between the data of the initial frame and the data of the target frame.

[0037] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 121. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 122. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 125. The other of the source and the drain of the transistor 106 is electrically connected to a wiring 123. The other of the source and the drain of the transistor 107 is electrically connected to a wiring 124.

[0038] A gate of the transistor 102 is electrically connected to a wiring 231. A gate of the transistor 103 is electrically connected to a wiring 232. A gate of the transistor 105 is electrically connected to a wiring 234. A gate of the transistor 107 is electrically connected to a wiring 233. Note that the wiring 234 is also electrically connected to the circuit 11.

[0039] The wirings 121 to 124 can function as power supply lines. For example, the wiring 121 can be a low-potential power supply line, and the wirings 122, 123, and 124 can be high-potential power supply lines. Note that in the configuration shown in FIG. 1, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102, and therefore the power supply lines are as described above. On the other hand, as shown in FIG. 2A, a configuration in which the anode side of the photoelectric conversion device 101 is electrically connected to the transistor 102 may also be used. In this case, the wiring 122 can be a low-potential power supply line, and the wirings 121, 123, and 124 can be high-potential power supply lines.

[0040] The wirings 231 to 234 can function as signal lines that control the conduction of each transistor. The wiring 125 can function as an output line and is electrically connected to, for example, an interlayer double sampling circuit (CDS circuit) or a readout circuit that includes an A / D conversion circuit.

[0041] The transistor 102 has a function of controlling the potential of the node FD1. The transistor 103 has a function of resetting the potential of the node FD1. The transistor 104 functions as an element of a source follower circuit. The transistors 105 and 106 have a function of selecting an output of the pixel. The transistor 107 has a function of resetting the potential of the node FD2.

[0042] The transistors included in the circuit 10 are preferably transistors having a metal oxide in a channel formation region (hereinafter referred to as OS transistors). OS transistors have extremely low off-state current. In particular, it is preferable to use transistors with low off-state current as the transistors 102, 103, and 107. By using these transistors as OS transistors, the period during which charge can be held at the nodes FD1 and FD2 can be significantly extended, and image data can be read with little degradation.

[0043] Alternatively, transistors having silicon in a channel formation region (hereinafter referred to as Si transistors) can be used as the transistors 102 to 107. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single-crystal silicon). Si transistors have high mobility and are suitable for high-speed operation.

[0044] Note that when the transistors 102 and 103 are Si transistors, a transistor 111 is preferably further provided as shown in Figure 2B. Here, the transistor 111 is an OS transistor.

[0045] The other of the source and the drain of the transistor 111 is electrically connected to the other of the source and the drain of the transistor 102 and the other of the source and the drain of the transistor 103. The other of the source and the drain of the transistor 111 is electrically connected to the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109.

[0046] A gate of the transistor 111 is electrically connected to a wiring 235. The wiring 235 can function as a signal line that controls conduction of the transistor 111.

[0047] In the configuration of FIG. 2B, the point (wiring) where the other of the source or drain of the transistor 111, the gate of the transistor 104, one electrode of the capacitor 108, and one electrode of the capacitor 109 are connected is the node FD1.

[0048] Since the transistor 111 is an OS transistor with low off-state current, the charge retention function of the nodes FD1 and FD2 can be improved. Furthermore, since the photoelectric conversion device 101 can be a buried photodiode formed on a silicon substrate, a pixel circuit with low noise can be formed.

[0049] <Circuit 11> FIG. 3 shows a circuit diagram of circuit 11. Circuit 11 has sense amplifiers 11A and 11B as comparison circuits. It also has an output circuit 11C. Inverters 171 and 172 are connected to a portion of the signal lines connecting sense amplifiers 11A and 11B and output circuit 11C. Note that the connection relationships of the elements constituting circuit 11 are shown in FIG. 3, and detailed description thereof will be omitted.

[0050] The sense amplifier 11A has a configuration in which an inverter latch circuit (transistors 141, 142, 143, 144) is electrically connected to a power switch (transistors 131, 133) connected to a high-potential power line (wiring 127), and the inverter latch circuit is electrically connected to a power switch (transistors 135, 137) connected to a low-potential power line (wiring 128) via transistors 145 and 146.

[0051] A gate of the transistor 145 is electrically connected to a node FD2 of the circuit 10 through a wiring 241. A gate of the transistor 146 is electrically connected to a wiring 238. The wiring 238 is a wiring to which a constant potential determined for a specific purpose is supplied.

[0052] A transistor 147 is electrically connected to a node LATNB of the inverter latch circuit, and a transistor 148 is electrically connected to a node LATN. The transistor 147 has a function of precharging the node LATNB to the potential of a wiring 129. The transistor 148 has a function of precharging the node LATN to the potential of a wiring 129. The potential of the wiring 129 can be set to, for example, an intermediate potential between the potential of the wiring 127 and the potential of the wiring 128.

[0053] The sense amplifier 11B has a configuration in which an inverter latch circuit (transistors 151, 152, 153, 154) is electrically connected to a power switch (transistors 132, 134) connected to a high-potential power line (wiring 127), and the inverter latch circuit is electrically connected to a power switch (transistors 136, 138) connected to a low-potential power line (wiring 128) via transistors 155 and 156.

[0054] A gate of the transistor 155 is electrically connected to a node FD2 of the circuit 10 through a wiring 241. A gate of the transistor 156 is electrically connected to a wiring 239. The wiring 239 is a wiring to which a constant potential determined for a specific purpose is supplied.

[0055] A transistor 157 is electrically connected to a node LATPB of the inverter latch circuit, and a transistor 158 is electrically connected to the node LATP. The transistor 157 has a function of precharging the node LATPB to the potential of the wiring 129. The transistor 158 has a function of precharging the node LATP to the potential of the wiring 129.

[0056] The output circuit 11C has power switches (transistors 161 and 162) connected to the high-potential power line (wiring 127), power switches (transistors 167 and 168) connected to the low-potential power line (wiring 128), and transistors 163, 164, 165, 166, and 169. Each transistor is electrically connected to an output node PCTR.

[0057] The gates of the transistors 164 and 165 are electrically connected to the node LATN. The gates of the transistors 163 and 166 are electrically connected to the node LATPB. The gate of the transistor 169 is electrically connected to a wiring 236 via an inverter 172. The output node PCTR is electrically connected to the gate of the transistor 106 included in the circuit 10 via a wiring 242.

[0058] Wirings 236, 234, and 237 are electrically connected to the circuit 11. The wirings 236, 234, and 237 are signal lines for controlling the conduction of transistors.

[0059] When a high potential ("H") is supplied to the wiring 236, the potential of the node PCTR is forced to become a high potential ("H"), and the transistor 106 in the circuit 10 is turned on. That is, the transistor 106, which is one of the two selection transistors included in the circuit 10, can be forced to be turned on.

[0060] The wiring 236 can be electrically connected to the gates of the transistors 131, 131, and 161. The wiring 236 can also be electrically connected to the gates of the transistors 135, 136, 167, and 169 via the inverter 172.

[0061] The wiring 234 can be electrically connected to the gates of the transistors 133, 134, and 162 via the inverter 171. The wiring 234 can also be electrically connected to the gates of the transistors 137, 138, and 168. When a low potential ("L") is supplied to the wiring 236 and a high potential ("H") is supplied to the wiring 234, each power switch can be turned on.

[0062] The wiring 237 can be electrically connected to the gates of the transistors 147, 148, 157, and 158. When a high potential (“H”) is supplied to the wiring 237, the transistors 147, 148, 157, and 158 are turned on, and the nodes LATNB, LATN, LATPB, and LATP can be precharged.

[0063] The circuit 11 includes p-channel transistors (transistors 131, 132, 133, 134, 141, 143, 151, 153, 161, 162, 164, and 169) and n-channel transistors (transistors 135, 136, 137, 138, 142, 144, 145, 146, 147, 148, 152, 154, 155, 156, 157, 158, 165, 166, 167, and 168).

[0064] These transistors are preferably Si transistors. Alternatively, OS transistors may be used as n-channel transistors. In particular, by using OS transistors as the transistors 135, 136, 137, and 138 that constitute the power switch, unnecessary leakage current between power lines that occurs when the power switch is not operating can be suppressed, thereby reducing power consumption.

[0065] <Operations of Circuit 10 and Circuit 11> Next, the operations of circuits 10 and 11 will be described. The operations include imaging and readout of the initial frame, normal imaging, difference calculation, and determination, and will be described in order. In the following description, a high-potential signal that makes an n-channel transistor conductive and a high-potential signal that makes a p-channel transistor non-conductive will be represented by "H," and a low-potential signal that makes an n-channel transistor non-conductive and a low-potential signal that makes a p-channel transistor conductive will be represented by "L."

[0066] In the circuit 11, a potential VN is supplied to the wiring 238, and a potential VP is supplied to the wiring 239. The potential VN is the lower end voltage of the voltage range used for the determination, and the potential VP is the upper end voltage. This voltage range corresponds to the range in which the data of the initial frame and the data of the target frame are considered to be the same.

[0067] <Initial frame imaging operation> 4 is a timing chart illustrating the imaging operation (period T1) and the readout operation (period T2) of the initial frame. Note that [0] to [n] (n is a natural number) in the figure represent row numbers. In the following explanation, only row number [0] will be described.

[0068] During the period T1, when the potential of the wiring 231 is set to "H", the potential of the wiring 232 is set to "H", the potential of the wiring 233 is set to "H", the potential of the wiring 236 is set to "L", the potential of the wiring 237 is set to "L", and the potential of the wiring 234[0:n] is set to "L", in the circuit 10, the transistors 102, 103, and 107 are turned on, and the potentials of the cathode of the photoelectric conversion device 101 and the node FD1 are reset to the potential "VRES1" of the wiring 122. Also, the potential of the node FD2 is reset to the potential "VRES2" of the wiring 124.

[0069] Next, when the potential of the wiring 231 is set to "L", charge is accumulated in the cathode in response to the operation of the photoelectric conversion device 101. Furthermore, the potential of the wiring 232 is set to "L", the transistor 103 is turned off, and the potential of the node FD1 is held at "VRES1".

[0070] Next, when the potential of the wiring 231 is set to "H" after a predetermined exposure time has elapsed, the charge accumulated in the cathode of the photoelectric conversion device 101 is transferred to the node FD1. At this time, the potential of the node FD1 drops by an amount corresponding to the amount of transferred charge ("Vref"), and becomes "VRES1-Vref." At this time, "VRES2" is supplied to the node FD2.

[0071] Next, the potential of the wiring 231 is set to "L", the potential of the wiring 233 is set to "L", the transistors 102 and 107 are turned off, and the potential of the node FD1 is held at "VRES1-Vref". The potential of the node FD2 is held at "VRES2". Here, "VRES2" can also be said to be a value obtained by replacing the data of the initial frame. This concludes the description of the imaging operation of the initial frame.

[0072] <Reading out the initial frame>

[0073] In the period T2, when the potential of the wiring 231 is set to "L", the potential of the wiring 232 is set to "L", the potential of the wiring 233 is set to "L", the potential of the wiring 236 is set to "H", the potential of the wiring 237 is set to "L", and the potential of the wiring 234[0:n] is set to "L", as shown in FIG. 5, in the circuit 11, all the power switches are turned off and the transistor 169 is turned on. Therefore, the potential of the output node PCTR becomes "H", and in the circuit 10, the transistor 106 is turned on, and the potential of the wiring 123 (power supply potential) is supplied to the other of the source and drain of the transistor 104. Note that in the figure, ◯ indicates that a transistor is on, and × indicates that a transistor is off.

[0074] Next, when the potential of the wiring 234[0] is set to "H", the transistor 105 is turned on, and data corresponding to the potential of the node FD1 is output to the wiring 125. This completes the description of the read operation of the initial frame. The data read here can be stored in a frame memory, for example.

[0075] <Normal imaging operation and difference calculation operation> FIG. 6 is a timing chart illustrating the normal imaging operation and difference calculation operation (period T3) and the difference determination operation and readout operation (period T4) following the readout operation of the initial frame (period T2 in FIG. 4).

[0076] In period T3, when the potential of wiring 231 is set to "H", the potential of wiring 232 is set to "H", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "L", and the potential of wiring 234[0:n] is set to "L", transistors 102 and 103 become conductive, and the potentials of the cathode of photoelectric conversion device 101 and node FD1 are reset to the potential "VRES1" of wiring 122.

[0077] At this time, since node FD2 is in a floating state, the change in the potential of node FD1 is added to the potential of node FD2 due to the capacitive coupling of capacitor 109. Since the change in the potential of node FD1 is "+Vref", the potential of node FD2 becomes "VRES2+Vref".

[0078] Next, when the potential of the wiring 231 is set to "L", charge is accumulated in the cathode in response to the operation of the photoelectric conversion device 101. Furthermore, the potential of the wiring 232 is set to "L", the transistor 103 is turned off, and the potential of the node FD1 is held at "VRES1".

[0079] Next, when the potential of the wiring 231 is set to "H" after a predetermined exposure time has elapsed, the charge accumulated in the cathode of the photoelectric conversion device 101 is transferred to the node FD1. At this time, the potential of the node FD1 drops by an amount corresponding to the amount of transferred charge ("Vtar1"), and becomes "VRES1-Vtar1". Furthermore, due to the capacitive coupling of the capacitor 109, the change in the potential of the node FD1 is added to the potential of the node FD2. Since the change in the potential of the node FD1 is "-Vtar1", the potential of the node FD2 becomes "VRES2+Vref-Vtar1".

[0080] Next, the potential of the wiring 231 is set to "L" to turn off the transistor 102, and the potential of the node FD1 is held at "VRES1-Vtar1." Also, the potential of the node FD2 is held at "VRES2+Vref-Vtar1."

[0081] The above is the normal imaging operation and the difference calculation operation. As a result of the normal imaging operation, "VRES1-Vtar1" is held at node FD1. Furthermore, as a result of the difference calculation operation, "VRES2+Vref-Vtar1" is held at node FD2. "VRES2" is the reset potential, but can be considered to be 0. Therefore, "+Vref-Vtar1" is the difference between the data of the initial frame and the data acquired in the normal imaging operation.

[0082] <Difference determination operation, read operation (no excess difference)>

[0083] In period T4, when the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "H", and the potential of wiring 234[0:n] is set to "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 are turned on, and nodes LATNB, LATN, LATPB, and LATP are precharged to the potential of wiring 129.

[0084] Next, when the potential of the wiring 237 is set to "L" and the potential of the wiring 234[0] is set to "H", all the power switches are turned on and current begins to flow to the sense amplifier, as shown in Figure 8. Here, the potential of the node FD2, "VRES2+Vref-Vtar1", is supplied to the gate of the transistor 145 and the gate of the transistor 155, the potential "VN" is supplied to the wiring 238, and the potential "VP" is supplied to the wiring 239.

[0085] 6, if "VN"<"VRES2+Vref-Vtar1"<"VP", the channel resistance of transistor 145 is lower than the channel resistance of transistor 146, and therefore the precharge potential of node LATNB decreases preferentially before the precharge potential of node LATN. Therefore, transistors 142 and 143 are turned on, power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATNB and LATN are determined.

[0086] Furthermore, since the channel resistance of the transistor 156 is lower than the channel resistance of the transistor 155, the precharge potential of the node LATP is lowered preferentially than that of the node LATPB. Therefore, the transistors 151 and 154 are turned on, and the power supply voltage is supplied from the wirings 127 and 128, so that the potentials of the nodes LATP and LATPB are determined.

[0087] At this time, the potential of node LATN is "H", and the potential of node LATPB is "H", so that transistors 165 and 166 are turned on, transistors 163 and 164 are turned off, and the potential of output node PCTR is "L". Therefore, in circuit 10, transistor 106 is not turned on and power is not supplied to transistor 104, so that even if transistor 105 is turned on, data at node FD1 is not output to wiring 125. In other words, if "VN"<"VRES2+Vref-Vtar1"<"VP", no data is output from circuit 10.

[0088] Here, since a source follower bias transistor (not shown) is connected to the wiring 125, the potential of the wiring 125 becomes 0 V unless the transistor 104 outputs data. When reading data, a steady current flows through the bias transistor. Therefore, if a read operation is not performed, power consumption equivalent to the steady current can be reduced.

[0089] <Difference determination operation, read operation (positive difference exceeded)> Using the timing chart in Figure 9, we will explain what happens when the difference exceeds the set voltage range. Note that period T5 is the same as period T3 in that it is a normal imaging operation and difference calculation operation, so its explanation will be omitted. However, the potential of node FD1 during normal imaging operation is "VRES1-Vtar2" (Vtar1>Vtar2), and the potential of node FD2 is "VRES1+Vref-Vtar2", so "VP"<"VRES1+Vref-Vtar2".

[0090] In period T6, when the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "H", and the potential of wiring 234[0:n] is set to "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 are turned on, and nodes LATNB, LATN, LATPB, and LATP are precharged to the potential of wiring 129.

[0091] Next, when the potential of the wiring 237 is set to "L" and the potential of the wiring 234[0] is set to "H", all the power switches are turned on and current begins to flow to the sense amplifier, as shown in Fig. 10. Here, the potential of the node FD2, "VRES2+Vref-Vtar2", is supplied to the gate of the transistor 145 and the gate of the transistor 155, the potential "VN" is supplied to the wiring 238, and the potential "VP" is supplied to the wiring 239.

[0092] 9, if "VN"<"VP"<"VRES2+Vref-Vtar2", the channel resistance of transistor 145 is lower than the channel resistance of transistor 146, and therefore the precharge potential of node LATNB decreases preferentially before the precharge potential of node LATN. Therefore, transistors 142 and 143 are turned on, power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATNB and LATN are determined.

[0093] Furthermore, the precharge potential of the node LATPB is lowered with priority over the node LATP because the channel resistance of the transistor 155 is lower than the channel resistance of the transistor 156. Therefore, the transistors 152 and 153 are turned on, and the power supply voltage is supplied from the wirings 127 and 128, so that the potentials of the nodes LATPB and LATP are determined.

[0094] At this time, the potential of node LATN becomes "H" and the potential of node LATPB becomes "L", so that transistors 163 and 165 are turned on and transistors 164 and 166 are turned off, and the potential of output node PCTR becomes "H". Therefore, in circuit 10, transistor 106 is turned on and power is supplied to transistor 104, so that transistor 105 becomes conductive, causing data at node FD1 to be output to wiring 125. In other words, if "VN"<"VP"<"VRES2+Vref-Vtar2", data is output from circuit 10.

[0095] The data output from the circuit 10 is stored in the frame memory where the image data of the initial frame is stored, at an address corresponding to that circuit 10. In other words, data is rewritten only at the address of the circuit 10 from which it was read. This operation reduces the write power compared to when data in all circuits 10 is rewritten.

[0096] Even when no read operation is performed, the A / D conversion circuit generates digital data corresponding to analog data of 0 V. When this digital data is generated, control is performed so that no write operation to the frame memory is performed.

[0097] <Difference determination operation, read operation (negative difference exceeded)> Using the timing chart in Figure 11, we will explain what happens when the difference exceeds the set voltage range on the lower side. Note that period T7 is the same normal imaging operation and difference calculation operation as period T3, so its explanation will be omitted. However, the potential of node FD1 during normal imaging operation is "VRES1-Vtar3" ("Vtar3" > "Vtar1"), and the potential of node FD2 is "VRES1+Vref-Vtar3", where "VRES1+Vref-Vtar3" < "VN" < "VP".

[0098] In period T8, when the potential of wiring 231 is set to "L", the potential of wiring 232 is set to "L", the potential of wiring 233 is set to "L", the potential of wiring 236 is set to "L", the potential of wiring 237 is set to "H", and the potential of wiring 234[0:n] is set to "L", as shown in FIG. 7, in circuit 11, transistors 147, 148, 157, and 158 are turned on, and nodes LATNB, LATN, LATPB, and LATP are precharged to the potential of wiring 129.

[0099] Next, when the potential of the wiring 237 is set to "L" and the potential of the wiring 234[0] is set to "H," all the power switches are turned on and current begins to flow through the sense amplifier, as shown in Fig. 12. Here, the potential of the node FD2, "VRES2+Vref-Vtar3," is supplied to the gate of the transistor 145 and the gate of the transistor 155, the potential "VN" is supplied to the wiring 238, and the potential "VP" is supplied to the wiring 239.

[0100] 11, if "VRES2+Vref-Vtar3"<"VN"<"VP", the channel resistance of transistor 146 is lower than the channel resistance of transistor 145, and therefore the precharge potential of node LATN decreases preferentially before the precharge potential of node LATNB. Therefore, transistors 141 and 144 are turned on, power supply voltage is supplied from wirings 127 and 128, and the potentials of nodes LATN and LATNB are determined.

[0101] Furthermore, since the channel resistance of the transistor 154 is lower than the channel resistance of the transistor 155, the precharge potential of the node LATP is lowered preferentially than that of the node LATPB. Therefore, the transistors 151 and 154 are turned on, and the power supply voltage is supplied from the wirings 127 and 128, so that the potentials of the nodes LATP and LATPB are determined.

[0102] At this time, the potential of node LATN becomes "L" and the potential of node LATPB becomes "H", so that transistor 164 is turned on, transistors 163 and 165 are turned off, and the potential of output node PCTR becomes "H". Therefore, in circuit 10, transistor 106 is turned on and power is supplied to transistor 104, so that transistor 105 becomes conductive, causing data at node FD1 to be output to wiring 125. In other words, if "VRES2+Vref-Vtar3"<"VN"<"VP", data is output from circuit 10.

[0103] As explained above, the output of circuit 10 can be controlled by the operation of circuit 11. Note that as time passes, the data of the initial frame and the data of the target frame become increasingly different from each other, so it is preferable to update the data of the initial frame at regular intervals or for a certain number of frames. Note that the data of the initial frame may also be updated every other frame.

[0104] 4, 6, 9, and 11 show the operation of the circuit 10 shown in Fig. 1, but in the case of the configuration of Fig. 2B, a potential supply operation to the wiring 235 may be added as shown in Fig. 13. Note that Fig. 13 shows the imaging operation of the initial frame (period T1), but the same applies to the normal imaging operation (period T3, etc.).

[0105] <Configuration of imaging device> 14 is a block diagram illustrating an imaging device of one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels (circuits 10 and 11) arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, a circuit 23 having a function of reading data from the circuit 10, and a circuit 28 that supplies a power supply potential. Note that the number of wirings connecting the respective elements is simplified in FIG. 14. The circuits 22, 23, and 28 may be multiple.

[0106] The circuit 23 may include a circuit 24 (CDS circuit) for performing correlated double sampling on the output data of the circuit 10, a circuit 25 (A / D conversion circuit or the like) having the function of converting the analog data output from the circuit 24 into digital data, and a circuit 26 (column driver) having the function of selecting a column from which data is to be output. The circuit 10 and the circuit 23 are electrically connected via wiring 125.

[0107] 14 illustrates an overlapping region between the circuit 10 and the circuit 11. As will be described in detail later, forming the circuit 10 and the circuit 11 into a stacked structure facilitates reducing the pixel area and improves the resolution. Furthermore, by forming the circuit 11 using a Si transistor and forming the circuit 10 on top of it using an OS transistor, a stacked structure can be formed without performing a process such as bonding.

[0108] Note that the configuration is not limited to one circuit 10 overlapping one circuit 11. For example, as shown in FIG. 15A, two circuits 10 arranged horizontally (in the direction in which the gate lines extend) may overlap one circuit 11. Alternatively, as shown in FIG. 15B, two circuits 10 arranged vertically (in the direction in which the source lines extend) may overlap one circuit 11. Alternatively, as shown in FIG. 15C, two circuits 10 arranged horizontally and vertically may overlap one circuit 11. Alternatively, as shown in FIG. 15D, three circuits 10 arranged horizontally and vertically may overlap one circuit 11. Alternatively, the number of circuits 10 overlapping one circuit 11 may be more than three.

[0109] In this way, in a configuration in which multiple circuits 10 are connected to one circuit 11, the difference data of any one of the circuits 10 can be acquired, and the other circuits 10 can perform the same operation depending on the result of the acquisition. An example of this is described below.

[0110] FIG. 16 is a diagram illustrating the connection configuration of 3×3 circuits 10 (circuits 10[0,0] to [2,2]) and one circuit 11. Since the three signal lines (wirings 231, 232, and 233) in each row are electrically connected to each other, operations other than read operations are performed simultaneously in the 3×3 circuits 10. The selection signal line (wirings 234[0:2]) of each row is electrically connected to the circuit 11 via the OR circuit 112. Therefore, the circuit 11 can be operated in accordance with the selection operation of each row.

[0111] Here, the node FD2 of any one of the circuits 10 is electrically connected to the circuit 11. While FIG. 16 shows an example in which the node FD2 of the circuit 10[0,1] is connected to the circuit 11, the circuit 11 may be connected to the node FD2 of the other circuits 10. Furthermore, the output node PCTR of the circuit 11 is electrically connected to all the circuits 10. Therefore, whether or not to read from all the circuits 10 is determined depending on the value of the node FD2 of one circuit 10. With this configuration, the number of circuits 11 can be reduced, thereby reducing the power required for precharging the sense amplifiers of the circuits 11.

[0112] 17 shows a configuration in which a transistor 113 is added to the configuration in FIG. 16 and the OR circuit 112 is omitted. The transistor 113 is provided between the output node PCTR of the circuit 11 and a wiring 242. In the configuration in FIG. 17, the node FD2 of the circuit 10 in the row to be read first is connected to the circuit 11. The gate of the transistor 113 is connected to a wiring 234 that connects to the circuit 10 in that row.

[0113] In the read operation of the first row, the potential of the output node PCTR is determined in the circuit 11, the transistor 113 is turned on, and the potential is output to each circuit 10. When the next row is read, the transistor 113 is turned off, and the potential of the wiring 242 is maintained. Therefore, the same operation (read or not read) can be performed in all the circuits 10.

[0114] In this configuration, the potential generated at the output node PCTR of the circuit 11 in the selection operation of the first row can be maintained. Therefore, it is not necessary to generate a potential at the output node PCTR in the selection operation of other rows, so that the number of operations of the circuit 11 can be reduced, and power consumption can be reduced.

[0115] In one embodiment of the present invention, a transistor may have a back gate as illustrated in FIG. 18A. In FIG. 18A, the back gate is electrically connected to the front gate, which has the effect of increasing the on-state current. Alternatively, a constant potential may be supplied to the back gate as illustrated in FIG. 18B. In this configuration, the threshold voltage of the transistor can be controlled. Furthermore, the configurations illustrated in FIG. 18A and FIG. 18B may be mixed in one circuit. Alternatively, a transistor without a back gate may be provided.

[0116] In the circuit 10, the transistors 104, 105, and 106 connected in series to the wiring 123 and the wiring 125 may be arranged in the order shown in FIGS. 19A to 19E instead of the order shown in FIG.

[0117] 2B, one of the source and the drain of the transistor 103 may be electrically connected to the other of the source and the drain of the transistor 111, one electrode of the capacitor 108, and the gate of the transistor 104, as shown in Fig. 20A. Alternatively, the gates of the transistors 102 and 111 may be electrically connected to a wiring 231, and the wiring 235 may be omitted, as shown in Fig. 20B.

[0118] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0119] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0120] <Structure example> FIG. 21A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0121] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 22A. Note that the term "layer" may be replaced with "region" in some cases.

[0122] 22A is a pn junction photodiode, and for example, a p-type semiconductor may be used for the layer 565a and an n-type semiconductor may be used for the layer 565b. Alternatively, an n-type semiconductor may be used for the layer 565a and a p-type semiconductor may be used for the layer 565b.

[0123] The pn junction photodiode can be typically formed using single crystal silicon.

[0124] 22B, the photoelectric conversion device 101 included in the layer 561 may be a stack of layers 566a, 566b, 566c, and 566d. The photoelectric conversion device 101 shown in FIG. 22B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0125] The layer 566a is preferably a low-resistance metal layer, such as aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0126] The layer 566d is preferably a conductive layer that has a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0127] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material, which is a p-type semiconductor, and the layer 566c is made of an n-type semiconductor such as gallium oxide.

[0128] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In these photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. Furthermore, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production, such as the ability to fabricate thin-film photoelectric conversion layers. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering.

[0129] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0130] The n-type semiconductor is preferably formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer and can reduce dark current.

[0131] 22C, the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e. The photoelectric conversion device 101 shown in FIG. 22C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0132] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0133] For example, molybdenum oxide can be used as the hole transport layer. For example, C 60 , C 70 or derivatives thereof can be used.

[0134] The photoelectric conversion layer may be a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor.

[0135] 21A can be, for example, a silicon substrate. The silicon substrate has Si transistors and the like. Pixel circuits can be formed using the Si transistors. Furthermore, circuits for driving the pixel circuits, readout circuits for the pixel circuits, image processing circuits, neural networks, communication circuits, and the like can be formed.

[0136] In addition, a memory circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (Micro Controller Unit), etc. may be formed. In this embodiment, the circuits 10 and 11 described in the first embodiment are called pixel circuits, and the other circuits are called functional circuits.

[0137] For example, some or all of the transistors included in the circuit 10, the circuit 11, and the functional circuits (circuits 22, 23, 28, etc.) can be provided in the layer 563.

[0138] Furthermore, the layer 563 may be a laminate of multiple layers as shown in FIG. 21B. Although FIG. 21B illustrates three layers, 563a, 563b, and 563c, two layers may be used. Alternatively, the layer 563 may be a laminate of four or more layers. These layers can be laminated using, for example, a bonding process. With this configuration, the pixel circuits and functional circuits can be distributed across multiple layers and stacked on top of each other, making it possible to manufacture a compact, highly functional imaging device.

[0139] Alternatively, the pixel may have a stacked structure of layers 561, 562, and 563 as shown in FIG. 21C.

[0140] The layer 562 can include OS transistors. For example, the circuit 10 can be formed in the layer 562, and the circuit 11 can be formed in the layer 563. One or more of the functional circuits described above can be formed using OS transistors. Alternatively, one or more of the functional circuits can be formed using Si transistors included in the layer 563 and OS transistors included in the layer 562. Alternatively, the layer 563 can be used as a support substrate such as a glass substrate, and pixel circuits and functional circuits can be formed using OS transistors included in the layer 562.

[0141] For example, a normally-off CPU (also referred to as an "Noff-CPU") can be realized using OS transistors and Si transistors. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are off (off) even when the gate voltage is 0 V.

[0142] The Noff-CPU can stop the power supply to circuits within the Noff-CPU that are not in operation, putting those circuits into a standby state. When the power supply is stopped and the circuit is in a standby state, no power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, it is possible to quickly return from the standby state. In this way, the Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0143] Furthermore, layer 562 may be a laminate of multiple layers as shown in FIG. 21D. While FIG. 21D illustrates two layers, layer 562a and layer 562b, layer 562 may be a laminate of three or more layers. These layers may be formed by stacking them on layer 563, for example. Alternatively, layer 562 may be formed by bonding a layer formed on layer 563 with a layer formed on layer 561.

[0144] The semiconductor material used for an OS transistor can be a metal oxide with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. A typical example is an oxide semiconductor containing indium, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors that prioritize reliability. Furthermore, CAC-OS exhibits high mobility, making it suitable for transistors that operate at high speed.

[0145] Because of the large energy gap of the semiconductor layer, OS transistors exhibit extremely low off-state currents of a few yA / μm (current value per 1 μm of channel width). Furthermore, unlike Si transistors, OS transistors have characteristics such as the absence of impact ionization, avalanche breakdown, and short-channel effects, making them suitable for the formation of high-voltage, highly reliable circuits. Furthermore, OS transistors are less susceptible to variations in electrical characteristics due to non-uniformity in crystallinity, which is a problem with Si transistors.

[0146] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (one or more metals selected from aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, hafnium, etc.). The In-M-Zn oxide can be formed by, for example, a sputtering method, an atomic layer deposition (ALD) method, or a metal organic chemical vapor deposition (MOCVD) method.

[0147] When forming an In-M-Zn oxide film by sputtering, the atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M and Zn≧M. The atomic ratios of the metal elements in such sputtering targets are preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=10:1:3, etc. The atomic ratios of the semiconductor layer to be formed can vary within ±40% of the atomic ratios of the metal elements contained in the sputtering target.

[0148] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm3 Less than 1 × 10 15 / cm 3 or less, more preferably 1 × 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 or less, more preferably 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above-described oxide semiconductors can be used. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. Such oxide semiconductors have a low density of defect states and stable characteristics.

[0149] Note that the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0150] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase, resulting in n-type conductivity. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0151] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, it may generate carriers, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16atoms / cm 3 Do the following:

[0152] Furthermore, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons acting as carriers are generated, increasing the carrier density and making the semiconductor layer more likely to be n-type. As a result, transistors using oxide semiconductors that contain nitrogen tend to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0153] Furthermore, if hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons that serve as carriers. Furthermore, some of the hydrogen may bond with oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0154] A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, oxide semiconductors are sometimes evaluated using carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration."

[0155] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×1020 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0156] The semiconductor layer may also have a non-single-crystal structure. Examples of the non-single-crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0157] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain any crystalline components, or an amorphous oxide film has, for example, a completely amorphous structure and does not contain any crystalline parts.

[0158] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single-crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0159] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single-crystal semiconductor layer.

[0160] CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0161] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0162] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into mosaics, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0163] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0164] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0165] The crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals are connected together with their c-axis orientation and no orientation in the ab plane.

[0166] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. CAC-OS is a material structure containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, the crystal structure is a secondary element in CAC-OS.

[0167] Note that CAC-OS does not include a stacked structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0168] In addition, GaO X3The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary between the region where the main component is the chromatic aberration and the region where the chromatic aberration is the main component may not be observed.

[0169] When one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained instead of gallium, the CAC-OS has a structure in which some regions observed to be nanoparticles containing the metal element as the main component and some regions observed to be nanoparticles containing In as the main component are randomly dispersed in a mosaic pattern.

[0170] The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the better. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0171] CAC-OS has the characteristic that no clear peaks are observed when measured using the θ / 2θ scan by the out-of-plane X-ray diffraction (XRD) method, which indicates that the ab-plane and c-axis orientations of the measured region are not observed.

[0172] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nanobeam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern indicates that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0173] For example, in the case of CAC-OS made of In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 It can be seen that the region where the main component is the crystalline silicon is unevenly distributed and mixed.

[0174] CAC-OS has a different structure from IGZO compounds, in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The structure is such that the regions are separated into a mosaic of regions each containing one of the elements as the main component and a region each containing one of the elements as the main component.

[0175] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is exhibited.X2 Zn Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud-like shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0176] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing the above as a main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0177] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation due to X2 Zn Y2 O Z2 , or InO X1 The conductivity due to the gate insulating layer and the gate insulating layer work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ) can be achieved.

[0178] Furthermore, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0179] <Laminated structure 1> Next, the layered structure of the imaging device will be described using cross-sectional views. Note that the elements such as the insulating layer and conductive layer shown below are examples, and other elements may be included. Alternatively, some of the elements shown below may be omitted. Furthermore, the layered structure shown below can be formed using a bonding process, a polishing process, or the like, as necessary.

[0180] FIG. 23 is an example of a cross-sectional view of a laminate having layers 560, 561, and a layer 563, with a bonding surface between layers 563a and 563b that constitute layer 563.

[0181] <layer 563b> The layer 563b includes elements of the circuit 11 provided on the silicon substrate 610. Here, the transistors 203 and 204 included in the inverter 172, and the transistor 169 are shown as some of the elements of the circuit 11.

[0182] The layer 563b includes a silicon substrate 610 and insulating layers 611, 612, 613, 614, 615, 616, 617, and 618. A conductive layer 619 is also provided. The insulating layer 611 functions as a protective film. The insulating layers 612, 613, 614, 615, 616, and 617 function as an interlayer insulating film and a planarizing film. The insulating layer 618 and the conductive layer 619 function as a bonding layer. The conductive layer 619 is electrically connected to the transistor 169.

[0183] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin. The dielectric layer of the capacitor may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The lamination layer will be described later.

[0184] Conductors that can be used as wiring, electrodes, and plugs for electrical connection between devices may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may also be made of multiple layers composed of different materials.

[0185] <Layer 563a> The layer 563a includes elements of the circuit 10. Here, the transistor 102 and the transistor 106 are shown as some of the elements of the circuit 10. In the cross-sectional view shown in FIG. 23, the electrical connection between them is not shown.

[0186] The layer 563a is provided with a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638, and conductive layers 636 and 639.

[0187] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as interlayer insulating films and planarizing films. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 from the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. Alternatively, the insulating layer 638 may be formed of the same material as the insulating layer 631.

[0188] The conductive layer 639 is electrically connected to the gate of the transistor 106 and the conductive layer 619. The conductive layer 636 is electrically connected to the wiring 121 (see FIG. 1).

[0189] The Si transistor shown in Fig. 23 is a fin type having a channel formation region in a silicon substrate (silicon substrates 610 and 632). A cross section in the channel width direction (a cross section taken along A1-A2 in layer 563a in Fig. 23) is shown in Fig. 24A. The Si transistor may also be a planar type, as shown in Fig. 24B.

[0190] 24C, the transistor may have a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single-crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 632.

[0191] <layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Fig. 23 shows a configuration in which the organic photoconductive film shown in Fig. 22C is used as the photoelectric conversion layer for the photoelectric conversion device 101. Here, the layer 567a is the cathode, and the layer 567e is the anode.

[0192] Layer 561 is provided with insulating layers 651, 652, 653, 654 and a conductive layer 655.

[0193] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101 and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. An organic insulating film or the like is preferably used as the element isolation layer.

[0194] The layer 567a, which corresponds to the cathode of the photoelectric conversion device 101, is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e, which corresponds to the anode of the photoelectric conversion device 101, is electrically connected to the conductive layer 636 included in the layer 563a via the conductive layer 655.

[0195] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0196] The light-shielding layer 671 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. The metal layer may also be stacked with a dielectric film that functions as an anti-reflection film.

[0197] A color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning colors such as (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filters for each pixel. For example, as shown in the perspective view (including cross section) of FIG. 31A, a color filter 672R (red), a color filter 672G (green), and a color filter 672B (blue) can be assigned to each different pixel.

[0198] Furthermore, if a wavelength cut filter is used in the optical conversion layer 672, an imaging device that can obtain images in various wavelength regions can be obtained.

[0199] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths shorter than visible light in the optical conversion layer 672. Alternatively, a far-infrared imaging device can be formed by using a filter that blocks light with wavelengths shorter than near-infrared light in the optical conversion layer 672. Alternatively, an ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths longer than visible light in the optical conversion layer 672.

[0200] Note that a plurality of different optical conversion layers may be arranged within a single imaging device. For example, as shown in FIG. 31B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR may be assigned to different pixels. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0201] 31C, color filter 672R (red), color filter 672G (green), color filter 672B (blue), and ultraviolet filter 672UV can be assigned to different pixels, respectively. In this configuration, visible light images and ultraviolet light images can be acquired simultaneously.

[0202] Furthermore, if a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation, such as for use in an X-ray imaging device. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting this light with the photoelectric conversion device 101. An imaging device having such a configuration may also be used as a radiation detector, etc.

[0203] Scintillators contain a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with such radiation. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, or the like dispersed in resin or ceramics can be used.

[0204] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, thereby enabling efficient photoelectric conversion. The microlens array 673 is preferably formed from a resin or glass that is highly translucent to light of the wavelength of the object to be imaged.

[0205] <Laminating> Next, the bonding of the layer 563b and the layer 563a will be described.

[0206] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that they are at the same height.

[0207] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that they are at the same height.

[0208] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component. The insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0209] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. Cu, Al, W, or Au is preferred for ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 618 and 631.

[0210] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded together at the boundary between them.

[0211] The conductive layers 619 and 639 may have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0212] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Furthermore, it is possible to obtain connection between the insulating layer 618 and the insulating layer 631 with sufficient mechanical strength.

[0213] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods create bonds at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0214] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or other methods, then surfaces that have been hydrophilically treated with oxygen plasma or other methods are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0215] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0216] For example, a method can be used in which the surface is polished, cleaned, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0217] By the above-described bonding, the elements of the layer 563b and the elements of the layer 563a can be electrically connected to each other.

[0218] <Modification of laminate structure 1> FIG. 25 shows a modified example of the stacked structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 563a are different, and there is also a bonding surface between the layer 561 and the layer 563a.

[0219] Layer 561 includes photovoltaic device 101, insulating layers 661, 662, 664, 665 and conductive layers 685, 686.

[0220] The photoelectric conversion device 101 is a pn junction photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. The photoelectric conversion device 101 is a buried photodiode, and a thin p-type region (part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a can suppress dark current and reduce noise.

[0221] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer. The insulating layer 665 functions to suppress the outflow of carriers.

[0222] Grooves that separate pixels are provided in the silicon substrate, and an insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. The insulating layer 665 can prevent carriers generated in the photoelectric conversion device 101 from flowing into adjacent pixels. The insulating layer 665 also has the function of preventing stray light from entering. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0223] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, the insulating layer 665 may be an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic. The insulating layer 665 may have a multi-layer structure. It is also possible to employ a structure without an element isolation layer.

[0224] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions buried in the insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that they are at the same height.

[0225] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. A conductive layer 683 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0226] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have regions buried in the insulating layer 638. The surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0227] Here, the conductive layers 683, 684, 685, and 686 are bonding layers similar to the above-described conductive layers 619 and 639. The insulating layers 638 and 661 are bonding layers similar to the above-described insulating layers 618 and 631.

[0228] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to either the source or the drain of the transistor 102. Also, by bonding the conductive layer 684 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 121 (see FIG. 1). Also, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 and the layer 563a.

[0229] <Laminated structure 2> 26 is an example cross-sectional view of a stack having layers 560, 561, 562, and 563 and no bonding surface. A Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Note that the structures of the layers 563, 561, and 560 are the same as those shown in FIG. 23, and therefore will not be described here.

[0230] <layer 562> Layer 562 is formed on layer 563. Layer 562 includes OS transistors. Transistors 102 and 106 are shown here as part of circuit 10. The cross-sectional view shown in FIG. 26 does not show the electrical connection between them.

[0231] Insulating layers 621, 622, 623, 624, 625, 626, and 628 are provided over the layer 562. A conductive layer 627 is also provided. The conductive layer 627 can be electrically connected to the wiring 121 (see FIG. 1).

[0232] The insulating layer 621 functions as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 function as an interlayer insulating film and a planarizing film. The insulating layer 624 functions as a protective film.

[0233] The blocking layer is preferably a film that has a function of preventing hydrogen diffusion. In Si devices, hydrogen is required to terminate dangling bonds. However, hydrogen near an OS transistor can generate carriers in the oxide semiconductor layer, reducing reliability. Therefore, a hydrogen blocking film is preferably provided between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0234] The blocking film may be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0235] The gate of the transistor 106 is electrically connected to the transistor 169 via a plug.

[0236] One of the source and the drain of the transistor 102 is electrically connected to a layer 567a of the photoelectric conversion device 101 included in the layer 561. The conductive layer 627 is electrically connected to a layer 567e of the photoelectric conversion device 101 included in the layer 561.

[0237] 27A shows the details of an OS transistor. The OS transistor shown in FIG. 27A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0238] The OS transistor can have a structure including a channel formation region, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0239] As shown in FIG. 27B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0240] Alternatively, as shown in FIG. 27C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0241] Although the OS transistor has a back gate 535, it may not necessarily have a back gate. The back gate 535 may be electrically connected to the front gate of a transistor located opposite the back gate, as shown in the cross-sectional view of the transistor in the channel width direction in FIG. 27D. Note that FIG. 27D illustrates the cross section of the transistor taken along line B1-B2 in FIG. 27A as an example, but the same applies to transistors with other structures. Furthermore, the back gate 535 may be supplied with a fixed potential different from that of the front gate.

[0242] <Modification 1 of Laminated Structure 2> 28 is a modified example of the stacked structure shown in FIG. 26, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 562 are different, and a bonding surface is provided between the layer 561 and the layer 562.

[0243] The photoelectric conversion device 101 included in the layer 561 is a pn junction photodiode formed on a silicon substrate, and has the same configuration as that shown in FIG.

[0244] In the layer 562, an insulating layer 648 is formed over the insulating layer 626. Furthermore, a conductive layer 688 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0245] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have regions buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 688 and 689 are flattened so that they are at the same height.

[0246] Here, the conductive layers 688 and 689 are bonding layers similar to the above-described conductive layers 619 and 639. The insulating layer 648 is a bonding layer similar to the above-described insulating layers 618 and 631.

[0247] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to either the source or the drain of the transistor 102. Also, by bonding the conductive layer 689 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 121 (see FIG. 1). Also, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 and the layer 562a.

[0248] When stacking multiple Si devices, multiple polishing and bonding processes are required. This poses challenges such as a large number of steps, the need for specialized equipment, low yields, and high manufacturing costs. OS transistors can be formed by stacking them on a silicon substrate on which devices are already formed, eliminating the need for bonding processes.

[0249] <Modification 2 of Laminated Structure 2> FIG. 29 shows a modified example of the laminated structure shown in FIG. 28, in which the configuration of layer 561 and a portion of the configuration of layer 562 are different, and a bonding surface is provided between layer 561 and layer 562.

[0250] In this modified example, the transistor 102 included in the circuit 10 is provided in a layer 561. In the layer 561, the transistor 102 is formed of a Si transistor. One of the source or the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source or the drain acts as a node FD1.

[0251] In this case, the layer 562 includes all the transistors included in the circuit 10 except for at least the transistor 102. FIG. 29 illustrates an example in which the transistor 104 and the transistor 106 are provided.

[0252] <Laminated structure 3> 25 to 29 illustrate examples of a stacked structure for the circuit 10 illustrated in FIG. 1, but the circuit 10 illustrated in FIG. 2B can have a structure illustrated in FIG. 30. FIG. 30 illustrates a structure in which Si transistors 102, 103, 104, 105, and 106 (transistor 105 is not illustrated) are provided in a layer 561, and a transistor 111, which is an OS transistor, is provided in the layer 561. Note that while FIG. 30 illustrates an example in which the layer 562 and the layer 563 are bonded to each other, the layer 561 and the layer 562 may be bonded to each other, as in FIG. 29.

[0253] <Package, Module> 32A1 is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see FIG. 32A3), a cover glass 420, and an adhesive 430 for bonding the two together.

[0254] 32A2 is a perspective view of the underside of the package. The underside of the package has a BGA (Ball Grid Array) with solder balls as bumps 440. The package is not limited to a BGA, and may have an LGA (Land Grid Array) or a PGA (Pin Grid Array), etc.

[0255] 32A3 is a perspective view of the package, with the cover glass 420 and part of the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and bumps 440 are electrically connected via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0256] 32B1 is a perspective view of the top surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 that fixes an image sensor chip 451 (see FIG. 32B3), a lens cover 421, and a lens 435. An IC chip 490 (see FIG. 32B3) having functions such as a drive circuit and a signal conversion circuit for the imaging device is also provided between the package substrate 411 and the image sensor chip 451, forming a SiP (System in Package) configuration.

[0257] 32B2 is a perspective view of the appearance of the bottom side of the camera module. The bottom and side surfaces of package substrate 411 have a QFN (quad flat no-lead package) configuration with mounting lands 441 provided. Note that this configuration is just one example, and a QFP (quad flat package) or the aforementioned BGA may also be provided.

[0258] 32B3 is a perspective view of the module, omitting a portion of lens cover 421 and lens 435. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0259] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0260] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0261] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS.

[0262] 33A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the mobile phone, thereby reducing power consumption.

[0263] 33B shows a portable data terminal including a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919 and output as voice through the speaker 913. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal, thereby reducing power consumption.

[0264] FIG. 33C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling, enabling imaging of the entire periphery. The imaging device and its operating method according to one embodiment of the present invention can be applied to elements for acquiring images in the camera unit, thereby reducing power consumption. Note that the term "surveillance camera" is a common name and is not intended to limit the application. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0265] 33D shows a video camera including a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display portion 973 is provided in the second housing 972. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this video camera, thereby reducing power consumption.

[0266] 33E shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the digital camera, thereby reducing power consumption.

[0267] 33F shows a wristwatch-type information terminal including a display portion 932, a housing / wristband 933, a camera 939, and the like. The display portion 932 includes a touch panel for operating the information terminal. The display portion 932 and the housing / wristband 933 are flexible and easy to wear on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal, thereby reducing power consumption.

[0268] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. [Explanation of symbols]

[0269] 10: Circuit, 11: Circuit, 11A: Sense amplifier, 11B: Sense amplifier, 11C: Output circuit, 21: Pixel array, 22: Circuit, 23: Circuit, 24: Circuit, 25: Circuit, 26: Circuit, 28: Circuit, 101: Photoelectric conversion device, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Transistor, 107: Transistor, 108: Capacitor, 109: Capacitor, 111: Transistor, 112: OR circuit, 113: Transistor, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125 : Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 131: Transistor, 132: Transistor, 133: Transistor, 134: Transistor, 135: Transistor, 136: Transistor, 137: Transistor, 138: Transistor, 141: Transistor, 142: Transistor, 143: Transistor, 144: Transistor, 145: Transistor, 146: Transistor, 147: Transistor, 148: Transistor, 151: Transistor, 152: Transistor, 153: Transistor, 154: Transistor, 155: Transistor, 156: Transistor, 157: Transistor, 158: Transistor, 161: Transistor, 162: Transistor, 163: Transistor, 164: Transistor, 165: Transistor, 166: Transistor, 167: Transistor, 168: Transistor, 169: Transistor, 171: Inverter, 172: Inverter, 203: Transistor, 204: Transistor, 231: Wiring, 232: Wiring, 233: Wiring, 234: Wiring, 235: Wiring, 236: Wiring, 237: Wiring, 238: Wiring, 239: Wiring, 241: Wiring Line, 242: wiring, 410: package substrate, 411: package substrate, 420: cover glass, 421: lens cover, 430: adhesive, 435: lens, 440: bump, 441: land, 450: image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 470: wire, 471: wire, 490: IC chip, 535: back gate, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 562b: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer,565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 610: silicon substrate, 611: insulating layer, 612: insulating layer, 613: insulating layer, 614: insulating layer, 615: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer ,626: Insulating layer, 627: Conductive layer, 628: Insulating layer, 631: Insulating layer, 632: Silicon substrate, 633: Insulating layer, 634: Insulating layer, 635: Insulating layer, 636: Conductive layer, 637: Insulating layer, 638: Insulating layer, 639: Conductive layer, 648: Insulating layer, 651: Insulating layer, 652: Insulating layer, 653: Insulating layer, 654: Insulating layer, 655: Conductive layer, 661: Insulating layer, 662: Insulating layer, 664: Insulating layer, 665: Insulating layer, 671: Light-shielding layer, 672: Optical conversion layer, 6 73: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing / wristband, 939: camera, 951: Support stand, 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light emitting unit, 971: Housing, 972: Housing, 973: Display unit, 974: Operation keys, 975: Lens, 976: Connection unit, 977: Speaker, 978: Microphone, 981: Housing, 982: Display unit, 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

1. An imaging device having a pixel including a first circuit and a second circuit, the first circuit includes a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor; one electrode of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and one electrode of the second capacitor; the other of the source and the drain of the second transistor is electrically connected to a first power supply line; one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to the one of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to a second power supply line; the other electrode of the second capacitor is electrically connected to one of the source and the drain of the sixth transistor; the other of the source and the drain of the sixth transistor is electrically connected to a third power supply line; a potential higher than that of the other electrode of the photoelectric conversion device is applied to each of the first power supply line, the second power supply line, and the third power supply line; the first circuit has a function of holding first image data generated in a first frame period at a gate of the third transistor of the first circuit; the first circuit has a function of holding second image data generated in an n-th frame period (n is a natural number equal to or greater than 2) at the gate of the third transistor; the first circuit has a function of holding, at one of a source and a drain of the sixth transistor of the first circuit, difference data that is a difference between the first image data and the second image data; the fifth transistor has a function of controlling output of the first image data and the second image data, the second circuit includes a comparison circuit and an output circuit; the comparator circuit has a function of determining whether the difference data is within an arbitrarily set voltage range, the output circuit has a function of outputting a voltage that turns off the fifth transistor when the difference data is within the voltage range, and outputting a voltage that turns on the fifth transistor when the difference data is not within the voltage range. Imaging device.

2. In claim 1, each of the first to sixth transistors has a metal oxide in a channel formation region; Imaging device.

3. In claim 2, The metal oxide contains at least In. Imaging device.

Images