Passive elements and electronic devices

Abstract

A passive element comprising: a semiconductor substrate; a first insulating film; a first metal pad; a first conductor; and a first conductive film. The semiconductor substrate is of p-type or n-type conductivity, and has a main surface and a back surface. The first insulating film is provided over a first region on the main surface of the semiconductor substrate. The first metal pad is provided on the first insulating film. The first conductor extends from the first metal pad in a first direction. The first conductive film is provided over a second region adjacent to the first region in the first direction on the main surface of the semiconductor substrate. The first conductive film is ohmically connected to the main surface of the semiconductor substrate, and has an electric resistivity smaller than the electric resistivity of the semiconductor substrate.

Description

[Technical Field]

[0001] This disclosure relates to passive elements and electronic devices. This application claims priority to Japanese Application No. 2021-098158, filed on June 11, 2021, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0002] Patent Document 1 discloses the configuration of a semiconductor device and its package. The semiconductor device includes a semiconductor chip and a circuit board. The semiconductor chip and circuit board are housed in a package. The circuit board is made of ceramic or the like. On the circuit board, a circuit for distributing and combining power, a circuit for matching input / output impedance of transistors, and surface wiring for interconnecting the circuit for distributing and combining power and the circuit for matching input / output impedance are formed. The package has input leads and input wiring pads. The circuit board is connected to the input wiring pads by bonding wires. The circuit board is connected to the semiconductor chip by another bonding wire. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-294401 Summary of the Invention [Problem to be solved by the invention]

[0004] Passive elements such as capacitors are often used in electronic devices, such as amplifiers. For example, in electronic devices that input and output high-frequency signals with frequencies of 100 MHz or higher, capacitors are used to match the input and output impedances of semiconductor elements built into the electronic device. For example, as described in Patent Document 1, a component having a ceramic substrate and a metal pad on the ceramic substrate can be placed on a conductive base to obtain capacitance between the metal pad and the base. In this case, the base is set to a constant potential, such as a ground potential common to the semiconductor element, and the metal pad is connected to the signal input or output terminal of the semiconductor element by a wire or the like.

[0005] Consider using a semiconductor substrate with an insulating film formed on it instead of a ceramic substrate. For example, a silicon substrate with a silicon oxide film formed on it and a metal pad on top of that is called a MOS capacitor. When a capacitor with an insulating film on a semiconductor substrate and a metal pad on top of that is used in a high-frequency electronic device, the following problem arises: When a signal propagates through the metal pad, a return current flows through the conductive base on which the capacitor is mounted. When the signal frequency is relatively low, this return current flows mainly inside the base and very little flows through the semiconductor substrate. In contrast, when the signal frequency is relatively high, for example, 100 MHz or higher, the return current flows mainly near the top surface of the semiconductor substrate due to the so-called skin effect. In this case, the return current is affected by the electrical resistance of the semiconductor substrate, resulting in attenuation of the high-frequency signal.

[0006] The present disclosure aims to suppress attenuation of high-frequency signals in a passive element having an insulating film on a semiconductor substrate and a metal pad on the insulating film. [Means for solving the problem]

[0007] A first passive element according to the present disclosure includes a semiconductor substrate, a first insulating film, a first metal pad, a first conductor, and a first conductive film. The semiconductor substrate has p-type or n-type conductivity and has a main surface and a back surface. The first insulating film is provided on a first region on the main surface of the semiconductor substrate. The first metal pad is a metal pad provided on the first insulating film. The first conductor extends in a first direction from the first metal pad. The first conductive film is provided on a second region on the main surface of the semiconductor substrate that is adjacent to the first region in the first direction. The first conductive film is in ohmic contact with the main surface of the semiconductor substrate and has an electrical resistivity lower than that of the semiconductor substrate.

[0008] A second passive element according to the present disclosure includes a semiconductor substrate, a conductive film, a first insulating film, a first metal pad, and a first conductor. The semiconductor substrate has p-type or n-type conductivity and has a main surface and a back surface. The conductive film is provided on the main surface of the semiconductor substrate over a region including a first region and a second region adjacent to the first region in a first direction. The conductive film is in ohmic contact with the main surface of the semiconductor substrate and has an electrical resistivity lower than that of the semiconductor substrate. The first insulating film is provided on the conductive film over the first region. The first metal pad is a metal pad provided on the first insulating film. The first conductor extends in a first direction from the first metal pad.

[0009] The electronic device according to the present disclosure includes a housing, a semiconductor element, a passive element, a second conductor, and a third conductor. The housing has a signal terminal and a conductive base. The semiconductor element has a signal electrode and a ground electrode conductively connected to the base and is mounted on the base. The passive element has a semiconductor substrate, a first insulating film, a first metal pad, a first conductor, a first conductive film, a second insulating film, and a second metal pad. The semiconductor substrate is mounted on the base, has p-type or n-type conductivity, and has a main surface and a back surface. The first insulating film is provided on a first region on the main surface of the semiconductor substrate. The first metal pad is provided on the first insulating film. The first conductor is connected to the first metal pad and extends in a first direction from the first metal pad. The first conductive film is provided on the second region. The second region is adjacent to the first region in a first direction on the main surface of the semiconductor substrate and is located below the first conductor. The first conductive film is in ohmic contact with the main surface of the semiconductor substrate and has an electrical resistivity lower than that of the semiconductor substrate. The second insulating film is provided on a third region adjacent to the second region in the first direction. The second metal pad is connected to the first conductor and is provided on the second insulating film. The second conductor electrically connects the first metal pad of the passive element to the signal terminal. The third conductor electrically connects the second metal pad of the passive element to the signal electrode of the semiconductor element. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to suppress attenuation of high frequency signals in a passive element having an insulating film on a semiconductor substrate and a metal pad on the insulating film. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view showing the structure of the capacitor according to the first embodiment. [Figure 2] FIG. 2 is a plan view of the capacitor according to the first embodiment. [Figure 3] FIG. 3 is a schematic diagram showing an example of the configuration of a conductive film when the semiconductor substrate is a silicon substrate. [Figure 4] FIG. 4 is a schematic diagram showing an example of the configuration of a conductive film when the semiconductor substrate is a silicon substrate. [Figure 5] 5A to 5C are cross-sectional views showing steps in a method for manufacturing a capacitor. [Figure 6] 6A to 6C are cross-sectional views showing steps in a method for manufacturing a capacitor. [Figure 7] 7A to 7C are cross-sectional views showing steps in a method for manufacturing a capacitor. [Figure 8] FIG. 8 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 9] FIG. 9 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 10] 10A to 10C are cross-sectional views showing steps in a method for manufacturing a capacitor. [Figure 11] FIG. 11 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 12] 12A to 12C are cross-sectional views showing steps in a method for manufacturing a capacitor. [Figure 13] 13A to 13C are cross-sectional views showing steps in a method for manufacturing a capacitor. [Figure 14] 14A to 14C are cross-sectional views showing steps in a method for manufacturing a capacitor. [Figure 15] FIG. 15 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 16] FIG. 16 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 17] FIG. 17 is a cross-sectional view showing a step in a method of manufacturing a capacitor. [Figure 18] FIG. 18 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 19] FIG. 19 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 20] FIG. 20 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 21]FIG. 21 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 22] FIG. 22 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 23] FIG. 23 is a cross-sectional view showing a step in a method for manufacturing a capacitor. [Figure 24] FIG. 24 is a cross-sectional view showing the structure of a ceramic capacitor. [Figure 25] FIG. 25 is a cross-sectional view showing a capacitor having an insulating film on a semiconductor substrate. [Figure 26] FIG. 26 is a diagram showing the path of the return current. [Figure 27] FIG. 27 is a graph showing the relationship between the skin depth and the signal frequency when the semiconductor substrate is made of silicon. [Figure 28] FIG. 28 is a diagram showing an example in which two capacitors having the configuration shown in FIG. 25 are arranged side by side. [Figure 29] FIG. 29 is a diagram showing a configuration in which the thickness of the insulating film is reduced and the width of the semiconductor substrate is also reduced. [Figure 30] FIG. 30 is a diagram showing a configuration in which two capacitors share a common semiconductor substrate. [Figure 31] FIG. 31 is a diagram showing a path of a return current in the capacitor of the first embodiment. [Figure 32] FIG. 32 is a graph showing the S21 transmission characteristics of an RF amplifier. [Figure 33] FIG. 33 is a cross-sectional view showing the structure of a capacitor according to a first modification. [Figure 34] FIG. 34 is a plan view of a capacitor according to a first modification. [Figure 35] FIG. 35 is a plan view showing a capacitor according to a second modification. [Figure 36] FIG. 36 is a plan view showing a state in which wires are connected to metal pads of a capacitor according to a second modification. [Figure 37] FIG. 37 is a plan view showing a state in which wires are connected to metal pads of a capacitor according to a second modification. [Figure 38] FIG. 38 is a cross-sectional view showing the structure of a capacitor according to a third modification. [Figure 39] FIG. 39 is a plan view of a capacitor according to a third modification. [Figure 40] FIG. 40 is a plan view showing the configuration of the electronic device according to the second embodiment. [Figure 41] FIG. 41 is a cross-sectional view taken along line XXXXI-XXXXI in FIG. [Figure 42] FIG. 42 is a plan view showing the configuration of the electronic device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] [Description of the embodiments of the present disclosure] A first passive element according to one embodiment includes a semiconductor substrate, a first insulating film, a first metal pad, a first conductor, and a first conductive film. The semiconductor substrate has p-type or n-type conductivity and has a main surface and a back surface. The first insulating film is provided on a first region on the main surface of the semiconductor substrate. The first metal pad is a metal pad provided on the first insulating film. The first conductor extends in a first direction from the first metal pad. The first conductive film is provided on a second region on the main surface of the semiconductor substrate that is adjacent to the first region in the first direction. The first conductive film is in ohmic contact with the main surface of the semiconductor substrate and has an electrical resistivity lower than that of the semiconductor substrate.

[0013] When this first passive element is mounted on a conductive base, the semiconductor substrate is electrically connected to the base and has the same potential as the base, resulting in a capacitance between the semiconductor substrate and the first metal pad. This capacitance depends on the area of ​​the first metal pad and the distance from the first metal pad to the semiconductor substrate, which typically depends on the thickness of the first insulating film. Therefore, when the first metal pad is connected to a signal terminal of a semiconductor element by a bonding wire, the input impedance or output impedance of the signal terminal can be matched by appropriately determining the area of ​​the first metal pad and the distance from the first metal pad to the semiconductor substrate.

[0014] Let us now consider a case where the first conductive film does not exist. As mentioned above, when the signal frequency is relatively high, the return current flows mainly near the upper surface, i.e., the main surface, of the semiconductor substrate due to the so-called skin effect. The return current is then affected by the electrical resistance of the semiconductor substrate, resulting in attenuation of the high-frequency signal. To reduce the degree of attenuation of this high-frequency signal, it is effective to minimize the width of the semiconductor substrate in the direction of the return current, in other words, to minimize the path of the return current within the semiconductor substrate. However, the smaller the width of the semiconductor substrate, the more likely it is that cracks will occur in the semiconductor substrate and that rotational misalignment will occur during assembly of the electronic device, making it difficult to handle passive elements.

[0015] To address this problem, the first passive element includes a first conductive film on the main surface of the semiconductor substrate in addition to a first insulating film and a first metal pad for obtaining capacitance. The first conductive film is provided alongside the first insulating film and the first metal pad and is ohmically connected to the main surface of the semiconductor substrate. In the first region, the high-frequency return current mainly flows near the main surface of the semiconductor substrate, but in the second region, it mainly flows within the first conductive film that is ohmically connected to the main surface of the semiconductor substrate. This allows the path of the return current within the semiconductor substrate to be shortened while ensuring a sufficient width of the semiconductor substrate. Therefore, the first passive element can suppress attenuation of high-frequency signals.

[0016] The first passive element may further include a second insulating film provided on a third region aligned with the second region on the principal surface of the semiconductor substrate, and a second metal pad provided on the second insulating film. The second region may be located between the first region and the third region. In this case, by connecting the first metal pad and the second metal pad with a wire, a matching circuit having two stages of capacitor portions and inductance therebetween can be realized by a single capacitor element.

[0017] The first metal pad may have a first protrusion protruding toward the second metal pad. The first conductive film may have a first recess surrounding the first protrusion on three sides. In this case, one end of a wire connecting the first metal pad and the second metal pad can be bonded to the first protrusion, thereby expanding the adjustable range of the wire length. In addition, the width of the first region in the direction of current flow can be kept narrow in the first region except for the portion directly below the first protrusion. This allows the width of the second region, i.e., the width of the first conductive film, to be kept wide. Therefore, the attenuation of high-frequency signals can be effectively reduced while increasing the degree of freedom in the wire length, i.e., the magnitude of inductance.

[0018] The second metal pad may have a second protrusion protruding toward the first protrusion. The first conductive film may further have a second recess surrounding the second protrusion on three sides. In this case, the other end of the wire connecting the first metal pad and the second metal pad can be bonded to the second protrusion, further expanding the adjustable range of the wire length. In addition, the width of the third region in the direction of current flow can be kept narrow in the third region except for the portion directly below the second protrusion. This allows the width of the second region, i.e., the width of the first conductive film, to be kept wide. Therefore, the degree of freedom in the wire length, i.e., the magnitude of inductance, can be further increased, while effectively reducing the attenuation of high-frequency signals.

[0019] The first passive element may further include a second conductive film, a third insulating film, and a third metal pad. The second conductive film is provided on a fourth region on the main surface of the semiconductor substrate. The second conductive film is in ohmic contact with the main surface of the semiconductor substrate and has an electrical resistivity lower than that of the semiconductor substrate. The third insulating film is provided on a fifth region on the main surface of the semiconductor substrate. The third metal pad is a metal pad provided on the third insulating film. The first region, the second region, the third region, the fourth region, and the fifth region may be arranged in this order along the first direction. In this case, by connecting the first metal pad and the second metal pad with a wire and connecting the second metal pad and the third metal pad with another wire, a matching circuit having three stages of capacitor portions and inductances between them can be realized with a single capacitor element.

[0020] The width of the first conductive film in the first direction may be larger than the width of the first metal pad in the same direction. By narrowing the width of the first metal pad and widening the width of the first conductive film, the portion of the return current path within the semiconductor substrate can be shortened and the portion within the first conductive film can be lengthened. Therefore, the attenuation of high-frequency signals can be effectively reduced while ensuring a sufficient width of the semiconductor substrate.

[0021] The first conductive film may be made of metal, in which case the first conductive film can be easily formed to have an electrical resistivity lower than that of the semiconductor substrate.

[0022] The semiconductor substrate may be a silicon substrate, and the first conductive film may include a Ti film in contact with the silicon substrate and an Au film provided on the Ti film. In this case, the semiconductor substrate and the first conductive film are firmly bonded, thereby improving the reliability of the passive elements. The semiconductor substrate may also be a gallium arsenide (GaAs) substrate.

[0023] A second passive element according to one embodiment includes a semiconductor substrate, a conductive film, a first insulating film, a first metal pad, and a first conductor. The semiconductor substrate has p-type or n-type conductivity and has a main surface and a back surface. The conductive film is provided on the main surface of the semiconductor substrate over a region including a first region and a second region adjacent to the first region in a first direction. The conductive film is in ohmic contact with the main surface of the semiconductor substrate and has an electrical resistivity lower than that of the semiconductor substrate. The first insulating film is provided on the conductive film over the first region. The first metal pad is a metal pad provided on the first insulating film. The first conductor extends in the first direction from the first metal pad.

[0024] When this second passive element is mounted on a conductive base, the conductive film is electrically connected to the base via the semiconductor substrate and has the same potential as the base, resulting in a capacitance between the conductive film and the first metal pad. This capacitance depends on the area of ​​the first metal pad and the distance from the first metal pad to the conductive film, which is typically the thickness of the first insulating film. Therefore, when the first metal pad is connected to a signal terminal of a semiconductor element by a bonding wire, the input impedance or output impedance of the signal terminal can be matched by appropriately determining the area of ​​the first metal pad and the distance from the first metal pad to the conductive film.

[0025] In this second passive element, a conductive film in contact with the main surface of the semiconductor substrate is provided from a first region, where a first insulating film and a first metal pad for obtaining capacitance are provided, to a second region. Therefore, the high-frequency return current mainly flows within the conductive film in both the first region and the second region. This allows the path of the return current within the semiconductor substrate to be shortened while ensuring a sufficient width of the semiconductor substrate. Therefore, the second passive element can suppress attenuation of high-frequency signals.

[0026] The second passive element may further include a second insulating film provided on the conductive film in a third region adjacent to the second region in the first direction on the main surface of the semiconductor substrate, and a second metal pad provided on the second insulating film. The second region may be located between the first region and the third region. In this case, by connecting the first metal pad and the second metal pad with a wire, a matching circuit having two stages of capacitor portions and inductance therebetween can be realized by a single capacitor element.

[0027] The first passive element and the second passive element may further include a backside metal film provided on the backside of the semiconductor substrate and in contact with the semiconductor substrate, in which case the backside metal film and the base can be easily and firmly bonded together using a conductive paste or the like.

[0028] The electrical resistivity of the semiconductor substrate is 1.0×10 -4 The electrical resistivity may be Ω·cm or more and 1 Ω·cm or less. The first passive element and the second passive element are particularly effective when using a semiconductor substrate having such an electrical resistivity.

[0029] The first metal pad may extend along a second direction intersecting the first direction, and the length of the first metal pad in the second direction may be greater than the width of the first metal pad in the first direction. By having the first metal pad have a planar shape that is elongated in the second direction intersecting the first direction, i.e., the direction of current flow, the current density of the signal current and the return current is suppressed, allowing the first metal pad to be used in high-power electronic devices. In this case, the length of the first metal pad in the second direction may be 10 times or more the width of the first metal pad in the first direction.

[0030] A first electronic device according to one embodiment includes a housing, a semiconductor element, and any one of the passive elements described above. The housing has a signal terminal and a conductive base. The semiconductor element has a signal electrode and a ground electrode conductively bonded to the base, and is mounted on the base. The passive element is mounted on the base. A first metal pad of the passive element is electrically connected to the signal terminal by a first wire, and is electrically connected to the signal electrode of the semiconductor element by a second wire. The semiconductor substrate of the passive element is conductively bonded to the base. This electronic device, including any of the passive elements described above, can suppress attenuation of high-frequency signals.

[0031] A second electronic device according to one embodiment includes a housing, a semiconductor element, a passive element, a second conductor, and a third conductor. The housing has a signal terminal and a conductive base. The semiconductor element has a signal electrode and a ground electrode conductively connected to the base and is mounted on the base. The passive element has a semiconductor substrate, a first insulating film, a first metal pad, a first conductor, a first conductive film, a second insulating film, and a second metal pad. The semiconductor substrate is mounted on the base, has p-type or n-type conductivity, and has a main surface and a back surface. The first insulating film is provided on a first region on the main surface of the semiconductor substrate. The first metal pad is provided on the first insulating film. The first conductor is connected to the first metal pad and extends in a first direction from the first metal pad. The first conductive film is provided on the second region. The second region is adjacent to the first region in a first direction on the main surface of the semiconductor substrate and is located below the first conductor. The first conductive film is in ohmic contact with the main surface of the semiconductor substrate and has an electrical resistivity lower than that of the semiconductor substrate. The second insulating film is provided on a third region adjacent to the second region in the first direction. The second metal pad is connected to the first conductor and is provided on the second insulating film. The second conductor electrically connects the first metal pad of the passive element to the signal terminal. The third conductor electrically connects the second metal pad of the passive element to the signal electrode of the semiconductor element. This electronic device can suppress attenuation of high-frequency signals. [Details of the embodiment of the present invention]

[0032] Specific examples of passive elements and electronic devices according to the present disclosure will be described below with reference to the drawings. The present invention is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. In the following description, the same elements in the drawings will be designated by the same reference numerals, and duplicate explanations will be omitted. (First embodiment)

[0033] FIG. 1 is a cross-sectional view showing the structure of a capacitor 1 as a passive element according to a first embodiment. FIG. 2 is a plan view of the capacitor 1. The capacitor 1 is used to match one or both of the input impedance and the output impedance of a semiconductor element in an electronic device such as an amplifier. The capacitor 1 is mounted on a conductive base 60 provided in the electronic device. The capacitor 1 includes a semiconductor substrate 10, a conductive film 21 (first conductive film), an insulating film 31 (first insulating film), an insulating film 32 (second insulating film), a metal pad 41 (first metal pad), a metal pad 42 (second metal pad), and a backside metal film 51. The base 60 is made of, for example, metal and primarily contains copper (Cu) in one example. The base 60 has a flat mounting surface 61. The base 60 is larger than the capacitor 1 in a plan view (in other words, when viewed from the normal direction of the mounting surface 61).

[0034] The semiconductor substrate 10 is a substantially rectangular parallelepiped member. The semiconductor substrate 10 has a p-type or n-type conductivity. In one example, the semiconductor substrate 10 is a p-type or n-type silicon (Si) substrate. Alternatively, the semiconductor substrate 10 may be a p-type or n-type GaAs substrate. The electrical resistivity of the semiconductor substrate 10 is, for example, 1.0×10 -4 When the semiconductor substrate 10 is a silicon substrate, the electrical resistivity is determined by adjusting the n-type or p-type impurity concentration to, for example, 10 15 cm -3 Over 10 21 cm -3 This can be achieved by:

[0035] The semiconductor substrate 10 has a main surface 11, a back surface 12 facing away from the main surface 11, and a pair of side surfaces 13 and 14. The normal direction of the main surface 11 coincides with the normal direction of the mounting surface 61 and the thickness direction of the semiconductor substrate 10. The back surface 12 is parallel to the main surface 11. The pair of side surfaces 13 and 14 face each other in a direction D1 (first direction) along the mounting surface 61. The pair of side surfaces 13 and 14 are parallel to each other and perpendicular to the main surface 11 and the back surface 12.

[0036] The thickness Ta of the semiconductor substrate 10 is, for example, 50 μm or more and 500 μm or less, and in one embodiment, is 200 μm. The width Wa of the semiconductor substrate 10 in the direction D1 is, for example, 400 μm or more and 2500 μm or less, and in one embodiment, is 1500 μm. The height-to-width ratio (Ta / Wa) of the semiconductor substrate 10 is, for example, 0.02 or more and 1.25 or less, and in one embodiment, is 0.13. The length La of the semiconductor substrate 10 in the direction D2 (second direction) perpendicular to the direction D1 along the mounting surface 61 is, for example, 1000 μm or more and 8000 μm or less, and in one embodiment, is 6200 μm. The width-to-length ratio (Wa / La) of the semiconductor substrate 10 is, for example, 0.05 or more and 2.5 or less, and in one embodiment, is 0.24. Thus, the length La of the semiconductor substrate 10 is greater than the width Wa of the semiconductor substrate 10.

[0037] As shown in FIG. 1 , the main surface 11 includes a first region 111, a second region 112, and a third region 113. The first region 111, the second region 112, and the third region 113 are spaced apart from one another and arranged side by side in this order in the direction D1. That is, in the direction D1, the second region 112 is located between the first region 111 and the third region 113. The second region 112 is adjacent to the first region 111 in the direction D1. The third region 113 is adjacent to the second region 112 in the direction D1. The first region 111 is provided along a side surface 13 of the semiconductor substrate 10. The third region 113 is provided along a side surface 14 of the semiconductor substrate 10.

[0038] The insulating film 31 is provided on the first region 111 of the main surface 11. The insulating film 32 is provided on the third region 113 of the main surface 11. The insulating films 31 and 32 are, for example, inorganic insulating films, and one example is a silicon oxide film (SiO2 film). When the semiconductor substrate 10 is a silicon substrate, the silicon oxide film may be a film formed by oxidizing the surface of the silicon substrate. The insulating films 31 and 32 have a thickness Tb of, for example, 0.1 μm or more and 5 μm or less, and in one embodiment, is 1 μm. The insulating film 31 is provided along the side surface 13 of the semiconductor substrate 10. The insulating film 32 is provided along the side surface 14 of the semiconductor substrate 10.

[0039] The metal pads 41 and 42 are metal pads for wire bonding. The metal pad 41 is provided on the insulating film 31 and is provided along the side surface 13 of the semiconductor substrate 10. That is, the insulating film 31 is interposed between the metal pad 41 and the semiconductor substrate 10. The metal pad 42 is provided on the insulating film 32 and is provided along the side surface 14 of the semiconductor substrate 10. That is, the insulating film 32 is interposed between the metal pad 42 and the semiconductor substrate 10. The metal pads 41 and 42 are made of a metal material such as Au, Pt, or Ti.

[0040] When the capacitor 1 is in use, one end of a conductive wire 71 (first conductor) is bonded to the upper surface of the metal pad 41, and the other end of the wire 71 is bonded to the upper surface of the metal pad 42. The wire 71 extends from the metal pad 41 in direction D1. This electrically connects the metal pad 41 and the metal pad 42 to each other via the wire 71. The length of the wire 71 is, for example, not less than 200 μm and not more than 2000 μm, and in one embodiment, is 1600 μm.

[0041] One end of another conductive wire 72 (third conductor) is bonded to the metal pad 41. The other end of the wire 72 is bonded to, for example, a signal electrode of a semiconductor element (not shown), i.e., a signal input terminal or a signal output terminal. As a result, the metal pad 41 is electrically connected to the signal input terminal or signal output terminal of the semiconductor element by the wire 72. One end of yet another conductive wire 73 (second conductor) is bonded to the metal pad 42. The other end of the wire 73 is bonded to, for example, a signal input terminal or a signal output terminal of a housing (not shown). As a result, the metal pad 42 is electrically connected to the signal input terminal or signal output terminal of the housing by the wire 73.

[0042] The metal pads 41 and 42 extend along the direction D2. The length Lc of the metal pads 41 and 42 in the direction D2 is greater than the width Wc of the metal pads 41 and 42 in the direction D1. The length Lc of the metal pads 41 and 42 may be 10 times or more the width Wc of the metal pads 41 and 42, or may be 30 times or more the width Wc. The length Lc of the metal pads 41 and 42 may be the same as the length La of the semiconductor substrate 10, or may be shorter than the length La.

[0043] The thickness Tc of the metal pads 41 and 42 is, for example, 0.5 μm or more and 10 μm or less, and in one embodiment, 5 μm. The width Wc of the metal pads 41 and 42 in the direction D1 is, for example, 100 μm or more and 1000 μm or less, and in one embodiment, 200 μm. The ratio (Wc / Wa) of the width Wc of each of the metal pads 41 and 42 to the width Wa of the semiconductor substrate 10 is, for example, 0.05 or more and 0.66 or less, and in one embodiment, 0.13. The length Lc of the metal pads 41 and 42 is, for example, 1000 μm or more and 8000 μm or less, and in one embodiment, 6000 μm. The width-to-length ratio (Wc / Lc) of the metal pads 41 and 42 is, for example, 0.01 or more and 0.5 or less, and in one embodiment, 0.033.

[0044] The conductive film 21 is provided on the second region 112 of the main surface 11 and is in ohmic contact with the main surface 11. The conductive film 21 has an electrical resistivity smaller than that of the semiconductor substrate 10. The conductive film 21 is made of, for example, a metal. In the direction D1, the conductive film 21 is disposed between the metal pad 41 and the metal pad 42. A gap is provided between the conductive film 21 and the metal pad 41, and the conductive film 21 and the metal pad 41 are insulated from each other. A gap is provided between the conductive film 21 and the metal pad 42, and the conductive film 21 and the metal pad 42 are insulated from each other.

[0045] 3 and 4 are schematic diagrams showing examples of the configuration of the conductive film 21 when the semiconductor substrate 10 is a silicon substrate. The conductive film 21A shown in Fig. 3 includes a Ti film 211 in contact with the silicon substrate and an Au film 212 provided on the Ti film 211. The conductive film 21B shown in Fig. 4 includes, in addition to the Ti film 211 and the Au film 212, a Pt film 213 provided between the Ti film 211 and the Au film 212.

[0046] 1 and 2 again. The thickness Td of the conductive film 21 is, for example, 0.5 μm or more and 10 μm or less, and in one embodiment, 5 μm. The width Wd of the conductive film 21 in the direction D1 is, for example, 200 μm or more and 2000 μm or less, and in one embodiment, 1000 μm. The length Ld of the conductive film 21 in the direction D2 is, for example, 1000 μm or more 8000The conductive film 21 has a width Ld of 0.025 or less and a width Wd of 0.17 or less, and in one embodiment, the width Ld is 6000 μm. In the illustrated example, the length Ld of the conductive film 21 is equal to the length Lc of the metal pads 41 and 42, but the conductive film 21 may be longer than the length Lc of the metal pads 41 and 42. In other words, one end of the conductive film 21 may extend beyond the imaginary line connecting one end of the metal pad 41 and one end of the metal pad 42. The ratio of the width to the length of the conductive film 21 (Wd / Ld) is, for example, 0.025 or more and 2.3 or less, and in one embodiment, it is 0.17. Thus, the length Ld of the conductive film 21 is greater than the width Wd of the conductive film 21. The width Wd of the conductive film 21 is greater than the width Wc of the metal pads 41 and 42. The ratio (Wc / Wd) of the width Wc of the metal pads 41 and 42 to the width Wd of the conductive film 21 is, for example, 0.01 or more and 1.0 or less, and in one embodiment, it is 0.20. The gap Ga between the conductive film 21 and the metal pads 41, 42 is, for example, 5 μm or more and 200 μm or less, and in one embodiment is 50 μm. Gaps are also provided between the conductive film 21 and the insulating films 31, 32, and the main surface 11 of the semiconductor substrate 10 is exposed from these gaps. The conductive film 21 may be in contact with the insulating films 31, 32, in which case the main surface 11 of the semiconductor substrate 10 is not exposed.

[0047] The rear surface metal film 51 is a metal film provided on the entire rear surface 12 of the semiconductor substrate 10. The rear surface metal film 51 is in contact with the semiconductor substrate 10. The rear surface metal film 51 is made of a metal material such as Au, Pt, or Ti. The thickness Te of the rear surface metal film 51 is, for example, 0.1 μm or more and 10 μm or less, and is 3 μm in one embodiment. The rear surface metal film 51 is conductively bonded to the mounting surface 61 of the base 60 by a conductive paste 74. The conductive paste 74 is, for example, an AuSn paste or an Ag paste.

[0048] When the capacitor 1 is mounted on the conductive base 60, the semiconductor substrate 10 is electrically connected to the base 60 and has the same potential as the base 60, so that capacitance is obtained between the semiconductor substrate 10 and the metal pads 41, 42. This capacitance depends on the area of ​​the metal pads 41, 42 and the distance from the metal pads 41, 42 to the semiconductor substrate 10, which typically depends on the thickness of the insulating films 31, 32. Therefore, when the metal pads 41, 42 are connected to signal terminals of a semiconductor element by wires 71, 72, it is possible to match the input impedance or output impedance at the signal terminals.

[0049] Here, a method for manufacturing the capacitor 1 will be described. FIGS. 5 to 23 are cross-sectional views showing the steps in the method for manufacturing the capacitor 1. Here, a silicon substrate is used as the semiconductor substrate 10. First, in the steps shown in FIGS. 5 to 10, a mask made of an inorganic material is formed on the main surface 11 of the semiconductor substrate 10. Below, an example will be given in which the mask is made of SiN, but the mask material is not limited to this.

[0050] First, as shown in FIG. 5, a SiN film 81 is formed on the entire main surface 11 of the semiconductor substrate 10. The SiN film 81 is formed by, for example, chemical vapor deposition (CVD). Next, as shown in FIG. 6, a resist 82 is applied to the entire surface of the SiN film 81. In the following description, a case where the resist 82 is negative is exemplified, but the resist 82 may also be positive. Next, as shown in FIG. 7, a portion of the resist 82 above the second region 112 is exposed to light to form a photosensitive portion 821. Then, as shown in FIG. 8, the portions of the resist 82 other than the photosensitive portion 821, i.e., the portions above the first region 111 and the third region 113, are removed by development. Then, as shown in FIG. 9, the portions of the SiN film 81 exposed by the resist 82, i.e., the portions above the first region 111 and the third region 113, are removed by etching. Thereafter, as shown in FIG. 10, all of the resist 82 is peeled off and removed. Through the above steps, a SiN mask 83 is formed having openings 831 and 832 respectively on the first region 111 and the third region 113. The first region 111 and the third region 113 of the semiconductor substrate 10 are exposed through the openings 831 and 832.

[0051] Next, as shown in FIG. 11 , an insulating film 31 is formed in the first region 111 of the semiconductor substrate 10 exposed through the opening 831 of the SiN mask 83. At the same time, an insulating film 32 is formed in the third region 113 of the semiconductor substrate 10 exposed through the opening 832 of the SiN mask 83. The insulating films 31 and 32 can be formed using, for example, CVD. Alternatively, a silicon oxide film may be formed as the insulating films 31 and 32 by thermally oxidizing the exposed surface of the semiconductor substrate 10, which is a silicon substrate. Thereafter, the SiN mask 83 is removed using a remover. The remover is, for example, a liquid mainly containing phosphoric acid. As a result, as shown in FIG. 12 , the insulating film 31 can be selectively formed on the first region 111 of the semiconductor substrate 10 and the insulating film 32 can be selectively formed on the third region 113 of the semiconductor substrate 10.

[0052] 13 to 17, the conductive film 21 is formed on the second region 112 using a lift-off method. First, as shown in FIG. 13, a resist 84 is applied to the entire surface of the main surface 11. In the following description, a case where the resist 84 is negative is exemplified, but the resist 84 may also be positive. Next, as shown in FIG. 14, the portions of the resist 84 on the first region 111 and the third region 113 are exposed to light to form exposed portions 841 and 842. Then, as shown in FIG. 15, the portions of the resist 84 other than the exposed portions 841 and 842, i.e., the portion on the second region 112, are removed by development.

[0053] Next, as shown in FIG. 16, a film 23 made of the material of the conductive film 21 is deposited over the entire surface of the main surface 11, for example, by vapor deposition. At this time, the film 23 is deposited on the second region 112 exposed from the resist 84, as well as on the resist 84 in the first region 111 and the third region 113. In one embodiment, a Ti film is formed first, and then an Au film is formed. Alternatively, a Ti film may be formed first, then a Pt film, and then an Au film. Thereafter, as shown in FIG. 17, the resist 84 is peeled off and removed, leaving only the film 23 on the second region 112, i.e., the conductive film 21.

[0054] 18 to 22, metal pads 41 and 42 are formed on the insulating films 31 and 32, respectively, using a lift-off method. First, as shown in FIG. 18, a resist 85 is applied to the entire surface of the main surface 11. In the following description, a case in which the resist 85 is negative is exemplified, but the resist 85 may also be positive. Next, as shown in FIG. 19, the portion of the resist 85 on the conductive film 21 is exposed to light to form a photoexposed portion 851. Then, as shown in FIG. 20, the portions of the resist 85 other than the photoexposed portion 851, i.e., the portions on the insulating films 31 and 32, are removed by development.

[0055] 21, a film 44 made of the material of the metal pads 41, 42 is deposited over the entire main surface 11 by, for example, vapor deposition. At this time, the film 44 is deposited on the insulating films 31, 32 exposed from the resist 85 and on the exposed portions 851 of the resist 85. Thereafter, as shown in FIG. 22, the resist 85 is peeled off and removed, leaving only the film 44 on the insulating films 31, 32, i.e., the metal pads 41, 42. Thereafter, as shown in FIG. 23, a back surface metal film 51 is formed on the back surface 12 of the semiconductor substrate 10 by, for example, vapor deposition. Through the above steps, the capacitor 1 of this embodiment is fabricated.

[0056] The effects and advantages obtained by the capacitor 1 of this embodiment having the above configuration will be described below, along with the problems that conventional capacitors have.

[0057] For example, in electronic devices that input and output high-frequency signals with frequencies of 100 MHz or higher, capacitors are used to match the input and output impedances of semiconductor devices built into the electronic devices. As an example, as shown in FIG. 24, a component having a ceramic substrate 91 and a metal pad 92 provided on the ceramic substrate 91 is placed on a conductive base 60. This allows capacitance to be obtained between the metal pad 92 and the base 60. In this case, the base 60 is set to a constant potential, such as the ground potential common to the semiconductor device. The metal pad 92 is connected to a signal input or output terminal of the semiconductor device by a wire 72 and to a signal input or output terminal of a housing that houses the semiconductor device by a wire 73. When a signal current Js propagates through the metal pad 92, a return current Jr flows through the base 60.

[0058] Here, as shown in FIG. 25, consider using a semiconductor substrate 95 with an insulating film 96 formed thereon instead of the ceramic substrate 91 of FIG. 24. For example, a capacitor having a silicon oxide film formed on a silicon substrate and a metal pad thereon is called a MOS capacitor. When a capacitor 90 having an insulating film 96 on a semiconductor substrate 95 and a metal pad 92 thereon is used in a high-frequency electronic device, the following problem arises. When the signal frequency is relatively low, the return current Jr flows mainly inside the base 60 and very little flows into the semiconductor substrate 95. In contrast, when the signal frequency is relatively high, for example, 100 MHz or higher, the return current Jr flows mainly through a region 951 near the top surface of the semiconductor substrate 95 due to the so-called skin effect, as shown in FIG. 26.

[0059] 27 is a graph showing the relationship between the thickness of the region 951, or the so-called skin depth, and the signal frequency when the semiconductor substrate 95 is made of silicon. The electrical resistivity of silicon is 2.0×10 -5 27, the vertical axis represents the skin depth (μm) and the horizontal axis represents the frequency (GHz). As is clear from FIG. 27, the higher the signal frequency, the smaller the skin depth becomes, and above 700 MHz the skin depth becomes smaller than 100 μm. In order to reduce cracks, it is desirable for the semiconductor substrate 95 to have a thickness of 100 μm or more, and therefore the region 951 due to the skin effect is biased toward the upper surface of the semiconductor substrate 95.

[0060] When the return current Jr flows inside the semiconductor substrate 95, the return current Jr is affected by the electrical resistance of the semiconductor substrate 95, and the high frequency signal is attenuated.

[0061] FIG. 28 shows an example in which two capacitors 90 having the configuration shown in FIG. 25 are arranged in series. In this case, the metal pad 92 of one capacitor 90 is connected to a signal input terminal or a signal output terminal of a semiconductor device via a wire 72. The metal pad 92 of the other capacitor 90 is connected to a signal input terminal or a signal output terminal of a housing that accommodates the semiconductor device via a wire 73. The metal pad 92 of one capacitor 90 and the metal pad 92 of the other capacitor 90 are interconnected via a wire 71. With this configuration, an internal matching circuit is formed by combining the capacitance of the two capacitors 90 with the inductance of the three wires 71, 72, and 73, further improving the matching of the input impedance or output impedance of the semiconductor device. Even with this configuration, the return current Jr flows near the top surface of the semiconductor substrate 95 of each capacitor 90 due to the skin effect.

[0062] 29, it is effective to reduce the thickness of the insulating film 96 and to make the width of the semiconductor substrate 95 in the direction of travel of the return current Jr as small as possible. This makes it possible to shorten the path of the return current Jr within the semiconductor substrate 95 while ensuring the necessary capacitance of each capacitor 90. However, the smaller the width of the semiconductor substrate 95, the more likely it is that cracks will occur in the semiconductor substrate 95, and the more difficult it is to handle the capacitors 90, for example, causing rotation errors in the capacitors 90 when assembling an electronic device.

[0063] As shown in FIG. 30, if the two capacitors 90 share a common semiconductor substrate 95 while maintaining the relationship between the two metal pads 92 and the three wires 71, 72, and 73, the problems of cracking and difficulty in handling the capacitors 90 are solved, but the problem of attenuation of high-frequency signals due to the skin effect still remains.

[0064] To address the above-described problem, the capacitor 1 of this embodiment includes a conductive film 21 on the main surface 11 of the semiconductor substrate 10, in addition to the insulating films 31 and 32 and the metal pads 41 and 42 for capacitance. The conductive film 21 is disposed alongside the insulating films 31 and 32 and the metal pads 41 and 42 and is in ohmic contact with the main surface 11 of the semiconductor substrate 10. Therefore, as shown in FIG. 31 , the high-frequency return current Jr mainly flows near the main surface 11 of the semiconductor substrate 10 in the first region 111 and the third region 113, but mainly flows within the conductive film 21 that is in ohmic contact with the main surface 11 of the semiconductor substrate 10 in the second region 112. This ensures a sufficient width Wa of the semiconductor substrate 10, thereby solving problems such as cracking and difficulty in handling the capacitor 90, while shortening the path of the return current Jr within the semiconductor substrate 10. Therefore, the capacitor 1 of this embodiment can suppress attenuation of high-frequency signals.

[0065] Curve G1 in FIG. 32 shows the S21 transmission characteristics of Case A, in which the capacitor 1 of this embodiment is applied to the input matching circuit of an RF amplifier in which the semiconductor element is a transistor. For comparison, curves G2 and G3 are also shown in FIG. 32. Curve G2 shows the S21 transmission characteristics of Case B, in which a ceramic substrate 91 is used instead of a semiconductor substrate (see FIG. 24). Curve G3 shows the S21 transmission characteristics of Case C, in which no conductive film 21 is provided on the semiconductor substrate (see FIG. 30). In FIG. 32, the vertical axis shows the gain (dB) and the horizontal axis shows the signal frequency (GHz). Table 1 below shows the maximum gains at 2.2 GHz in Cases A, B, and C. [Table 1] As shown in FIG. 32 and Table 1, the capacitor 1 of this embodiment causes a larger attenuation in the gain of the RF amplifier compared to when the ceramic substrate 91 is used, but the attenuation in the gain of the RF amplifier can be reduced compared to when the conductive film 21 is not provided on the semiconductor substrate.

[0066] As in this embodiment, the capacitor 1 may include an insulating film 32 and a metal pad 42 provided on the third region 113, in addition to the insulating film 31 and the metal pad 41 provided on the first region 111. The conductive film 21 on the second region 112 may be located between the set of the insulating film 31 and the metal pad 41 and the set of the insulating film 32 and the metal pad 42. In this case, by connecting the metal pad 41 and the metal pad 42 with a wire 71, a matching circuit having two stages of capacitor portions and an inductance therebetween can be realized by a single capacitor element.

[0067] As described above, the width Wd of the conductive film 21 in the direction D1 may be larger than the width Wc of the metal pads 41, 42 in the same direction. By reducing the width Wc of the metal pad 41 and increasing the width Wd of the conductive film 21 in this way, the portion of the path of the return current Jr that is within the semiconductor substrate 10 can be shortened and the portion that is within the conductive film 21 can be lengthened. Therefore, the attenuation of high-frequency signals can be effectively reduced while ensuring a sufficient width Wa of the semiconductor substrate 10.

[0068] As in this embodiment, the conductive film 21 may be made of metal. In this case, the conductive film 21 having an electrical resistivity lower than that of the semiconductor substrate 10 can be easily formed.

[0069] 3, when the semiconductor substrate 10 is a silicon substrate, the conductive film 21 may include a Ti film 211 in contact with the silicon substrate and an Au film 212 provided on the Ti film 211. In this case, the semiconductor substrate 10 and the conductive film 21 can be firmly bonded to each other, thereby improving the reliability of the capacitor 1. As shown in FIG. 4, a Pt film 213 may be provided between the Ti film 211 and the Au film 212.

[0070] As in the present embodiment, the capacitor 1 may include a back surface metal film 51 provided on the back surface 12 of the semiconductor substrate 10 and in contact with the semiconductor substrate 10. In this case, the back surface metal film 51 and the base 60 can be easily and firmly conductively bonded together using a conductive paste 74 or the like.

[0071] As mentioned above, the electrical resistivity of the semiconductor substrate 10 is 1.0×10 -4 The electrical resistivity may be Ω·cm or more and 1 Ω·cm or less. The capacitor 1 of this embodiment is particularly effective when using a semiconductor substrate 10, typically a silicon substrate, having such an electrical resistivity.

[0072] As in this embodiment, the metal pads 41, 42 extend along the direction D2, and the length Lc of the metal pads 41, 42 in the direction D2 may be greater than the width Wc of the metal pads 41, 42 in the direction D1. In this way, the metal pad 41 has a long planar shape in the direction D2 that intersects with the direction D1 in which the current flows, thereby suppressing the current densities of the signal current Js and the return current Jr, and therefore can be used in high-power electronic devices.

[0073] The method for manufacturing the capacitor 1 described above includes the steps of forming a SiN mask 83, forming a silicon oxide film, forming a conductive film 21, and forming metal pads 41 and 42. In the step of forming the SiN mask 83, the SiN mask 83 having openings 831 and 832 in a first region 111 and a third region 113 is formed on the main surface 11 of a silicon substrate serving as a semiconductor substrate 10. In the step of forming the silicon oxide film, silicon oxide films serving as insulating films 31 and 32 are formed in the first region 111 and the third region 113 of the main surface 11. In the step of forming the conductive film 21, the SiN mask 83 is removed, and then the conductive film 21 is formed so as to form an ohmic connection with the main surface 11 of the semiconductor substrate 10. In the step of forming the conductive film 21, the conductive film 21 is formed in the second region 112 of the main surface 11 of the semiconductor substrate 10 using a lift-off method. In the step of forming the metal pads 41 and 42, the metal pads 41 and 42 for wire bonding are formed on the silicon oxide film by using a lift-off method.

[0074] When a silicon substrate is used as the semiconductor substrate 10, a silicon oxide film can be easily formed by thermal oxidation of the silicon substrate surface. In this case, the silicon substrate is placed in an oxygen atmosphere and heated to a temperature between 700°C and 1100°C, thereby forming a silicon oxide film on the surface of the silicon substrate. To prevent the conductive film 21 from melting due to heating, it is desirable to thermally oxidize the surface of the silicon substrate before the conductive film 21 is formed on the silicon substrate. Therefore, in this embodiment, a SiN mask 83 is formed as an oxidation prevention mask, and a silicon oxide film is selectively formed using the SiN mask 83 in the region where the capacitor is to be formed. This method allows the capacitor 1 of this embodiment to be easily fabricated. (First Modification)

[0075] Fig. 33 is a cross-sectional view showing the structure of capacitor 2 as a passive element according to a first modification of the above embodiment. Fig. 34 is a plan view of capacitor 2. Capacitor 2 of this modification differs from capacitor 1 of the above embodiment in the following respects, but is the same in other respects.

[0076] The main surface 11 of the semiconductor substrate 10 of the capacitor 2 further includes a fourth region 114 and a fifth region 115 in addition to a first region 111, a second region 112, and a third region 113. The first region 111, the second region 112, the third region 113, the fourth region 114, and the fifth region 115 are arranged in this order along the direction D1. That is, the fourth region 114 is disposed between the third region 113 and the fifth region 115. The capacitor 2 further includes a conductive film 22 (second conductive film), an insulating film 33 (third insulating film), and a metal pad 43 (third metal pad).

[0077] The conductive film 22 is provided on the fourth region 114 of the main surface 11 of the semiconductor substrate 10. The conductive film 22 is in ohmic contact with the main surface 11 of the semiconductor substrate 10 and has an electrical resistivity lower than that of the semiconductor substrate 10. The planar shape of the conductive film 22 may be the same as that of the conductive film 21. The constituent material of the conductive film 22 is selected from, for example, the constituent materials of the conductive film 21. In one embodiment, the constituent material of the conductive film 22 is the same as that of the conductive film 21. The thickness, width in the direction D1, and length in the direction D2 of the conductive film 22 are, for example, within the numerical ranges exemplified for the thickness Td, width Wd, and length Ld of the conductive film 21. In one embodiment, the thickness, width in the direction D1, and length in the direction D2 of the conductive film 22 are equal to the thickness Td, width Wd, and length Ld of the conductive film 21, respectively.

[0078] The insulating film 33 is provided on the fifth region 115 of the main surface 11 of the semiconductor substrate 10. The planar shape of the insulating film 33 may be the same as the planar shapes of the insulating films 31 and 32. The constituent material of the insulating film 33 is selected from, for example, the exemplified constituent materials of the insulating films 31 and 32. In one embodiment, the constituent material of the insulating film 33 is the same as the constituent material of the insulating films 31 and 32. The thickness of the insulating film 33 is, for example, within the numerical range exemplified for the thickness Tb of the insulating films 31 and 32. In one embodiment, the thickness of the insulating film 33 is equal to the thickness Tb of the insulating films 31 and 32.

[0079] The metal pad 43 is a metal pad for wire bonding and is provided on the insulating film 33. The planar shape of the metal pad 43 may be the same as the planar shapes of the metal pads 41 and 42. The material of the metal pad 43 is selected from, for example, the materials exemplified as the materials of the metal pads 41 and 42. In one embodiment, the material of the metal pad 43 is the same as the material of the metal pads 41 and 42. The thickness, width in the direction D1, and length in the direction D2 of the metal pad 43 are, for example, within the numerical ranges exemplified for the thickness Tc, width Wc, and length Lc of the metal pads 41 and 42, respectively. In one embodiment, the thickness, width in the direction D1, and length in the direction D2 of the metal pad 43 are equal to the thickness Tc, width Wc, and length Lc of the metal pads 41 and 42, respectively.

[0080] One end of a conductive wire 75 is bonded to the metal pad 42 instead of the wire 73. The other end of the wire 75 is bonded to the metal pad 43. As a result, the metal pads 42 and 43 are electrically connected by the wire 75. One end of the wire 73 is bonded to the metal pad 43. The other end of the wire 73 is bonded to, for example, a signal input terminal or a signal output terminal of a housing (not shown). As a result, the metal pad 43 is electrically connected to the signal input terminal or the signal output terminal of the housing by the wire 73.

[0081] According to this modification, similar to the above embodiment, it is possible to reduce the attenuation of high-frequency signals. In addition, according to this modification, a matching circuit having three stages of capacitor parts and inductances between them can be realized by a single capacitor element. (Second Modification)

[0082] 35 is a plan view showing a capacitor 3 as a passive element according to a second modification of the above embodiment. Capacitor 3 of this modification differs from capacitor 1 of the above embodiment in the following respects, but is the same in other respects.

[0083] The capacitor 3 includes a metal pad 45 instead of the metal pad 41 of the above embodiment. The capacitor 3 includes a metal pad 46 instead of the metal pad 42 of the above embodiment. The capacitor 3 includes a conductive film 25 instead of the conductive film 21 of the above embodiment. The arrangement and materials of the metal pads 45 and 46 and the conductive film 25 are similar to the arrangement and materials of the metal pads 41 and 42 and the conductive film 21 of the above embodiment. In the figure, the metal pads 45 and 46 and the conductive film 25 are hatched for ease of understanding.

[0084] The metal pad 45 has one or more convex portions 451 (first convex portions) protruding from a side facing the metal pad 46 toward the metal pad 46. Four convex portions 451 are illustrated in the figure. The conductive film 25 has recesses 251 (first recesses) on the side facing the metal pad 45, surrounding each convex portion 451 from three sides, and the same number of recesses 251 as the convex portions 451. The metal pad 46 has one or more convex portions 461 (second convex portions) protruding from the side facing the metal pad 45 toward the convex portion 451. Four convex portions 461 are illustrated in the figure. The conductive film 25 has recesses 252 (second recesses) on the side facing the metal pad 46, surrounding each convex portion 461 from three sides, and the same number of recesses as the convex portions 461. The width Wf of the convex portions 451, 461 in the direction D2 is, for example, 40 μm or more and 100 μm or less. The protrusion length Lf of the convex portions 451, 461 in the direction D1 is, for example, 500 μm. The width Wg of the gap between the convex portions 451, 461 and the concave portions 251, 252 in the direction D1 is, for example, 5 μm or more and 200 μm or less. The width Wh of the gap between the convex portions 451, 461 and the concave portions 251, 252 in the direction D2 is, for example, 5 μm or more and 50 μm or less.

[0085] In this modification, the planar shapes of the insulating film 31 and the first region 111 (see FIG. 1) match the planar shape of the metal pad 45. The planar shapes of the insulating film 32 and the third region 113 (see FIG. 1) match the planar shape of the metal pad 46. The planar shape of the second region 112 (see FIG. 1) matches the planar shape of the conductive film 25.

[0086] 36 and 37 are plan views showing a state in which a wire 71 is connected to the metal pads 45 and 46. FIG. 36 shows a case in which one end of the wire 71 is bonded near the tip of the protrusion 451 and the other end of the wire 71 is bonded near the tip of the protrusion 461. In this case, the length of the wire 71 can be shortened. FIG. 37 shows a case in which one end of the wire 71 is bonded near the base of the protrusion 451 and the other end of the wire 71 is bonded near the base of the protrusion 461. In this case, the length of the wire 71 can be lengthened. As described above, according to this modification, the end of the wire 71 connecting the metal pads 45 and 46 can be bonded to the protrusions 451 and 461, thereby expanding the adjustable range of the length of the wire 71. In the first region 111 except for the portion directly below the protrusion 451, the width of the first region 111 in the direction of the return current Jr (see FIG. 31 ) can be kept narrow. This allows the width of the second region 112, i.e., the width Wd of the conductive film 25, to be kept wide. Furthermore, in the third region 113, the width in the direction of travel of the return current Jr can be kept narrow in other parts except for the part directly below the protrusion 461. This allows the width of the second region 112, i.e., the width Wd of the conductive film 25, to be kept even wider. Therefore, it is possible to effectively reduce the attenuation of high-frequency signals while increasing the degree of freedom in the length of the wire 71, i.e., the magnitude of inductance.

[0087] In this modification, only one of the convex portion 451 of the metal pad 45 and the convex portion 461 of the metal pad 46 may be provided. That is, the metal pad 45 (or the metal pad 46) of this modification and the metal pad 42 (or the metal pad 41) of the above embodiment may be combined with each other. In that case, only one of the concave portions 251 and 252 is provided in the conductive film 25 as well. (Third Modification)

[0088] Fig. 38 is a cross-sectional view showing the structure of capacitor 4 as a passive element according to a third modification of the above embodiment. Fig. 39 is a plan view of capacitor 4. Capacitor 4 of this modification differs from capacitor 1 of the above embodiment in the following respects, but is the same in other respects.

[0089] The capacitor 4 includes a conductive film 24 instead of the conductive film 21 of the above embodiment. The conductive film 24 is provided on a region of the main surface 11 of the semiconductor substrate 10, including the first region 111, the second region 112, and the third region 113. In the illustrated example, the conductive film 24 is provided over the entire main surface 11 of the semiconductor substrate 10. The conductive film 24 is in ohmic contact with the main surface 11 of the semiconductor substrate 10. The conductive film 24 has an electrical resistivity lower than that of the semiconductor substrate 10. The constituent material of the conductive film 24 is selected from, for example, the materials exemplified as the constituent materials of the conductive film 21. The thickness of the conductive film 24 falls within, for example, the numerical range exemplified for the thickness Td of the conductive film 21.

[0090] In this modification, the insulating film 31 is provided on the first region 111 and on the conductive film 24. The insulating film 32 is provided on the third region 113 and on the conductive film 24. The upper surface of the conductive film 24 in the second region 112 is exposed from the insulating films 31 and 32.

[0091] When the capacitor 4 of this modification is mounted on the conductive base 60, the conductive film 24 is electrically connected to the base 60 via the semiconductor substrate 10 and has the same potential as the base 60, resulting in capacitance between the conductive film 24 and the metal pads 41, 42. This capacitance depends on the area of ​​the metal pads 41, 42 and the distance from the metal pads 41, 42 to the conductive film 24, typically the thickness of the insulating films 31, 32. Therefore, when the metal pads 41, 42 are connected to signal terminals of a semiconductor element by wires 71, 72, it is possible to match the input impedance or output impedance at the signal terminals.

[0092] In this modification, the conductive film 24 in contact with the main surface 11 of the semiconductor substrate 10 is provided from the first region 111 through the second region 112 to the third region 113. Therefore, the high-frequency return current Jr (see FIG. 31) mainly flows within the conductive film 24 in all of the first region 111, the second region 112, and the third region 113. This makes it possible to shorten the path of the return current Jr within the semiconductor substrate 10 while ensuring a sufficient width Wa (see FIG. 2) of the semiconductor substrate 10. Therefore, according to this modification, it is possible to suppress attenuation of high-frequency signals.

[0093] As in this modification, the capacitor 4 may include an insulating film 32 and a metal pad 42 provided on the third region 113, in addition to the insulating film 31 and the metal pad 41 provided on the first region 111. The second region 112 may be located between the first region 111 and the third region 113. In this case, by connecting the metal pad 41 and the metal pad 42 with a wire 71, a matching circuit having two stages of capacitor portions and an inductance therebetween can be realized by a single capacitor element. (Second embodiment)

[0094] FIG. 40 is a plan view showing the configuration of an electronic device 5 according to a second embodiment. FIG. 41 is a cross-sectional view taken along line XXXXI-XXXXI in FIG. 40. The electronic device 5 according to this embodiment receives a high-frequency signal having a fundamental frequency of, for example, 100 MHz or higher, amplifies the high-frequency signal, and outputs the amplified signal. The electronic device 5 includes a housing 63, an input matching circuit 101, a transistor element 102, and an output matching circuit 103. The housing 63 includes a base 60, end walls 64 and 65, side walls 66 and 67, and a lid 68 (see FIG. 41). The end walls 64 and 65 and the side walls 66 and 67 are made of an insulating material such as a multilayer ceramic material and are provided on the base 60. The base 60 has a substantially rectangular planar shape and mounts the input matching circuit 101, the transistor element 102, and the output matching circuit 103. The end walls 64 and 65 are aligned in direction D1 and extend along direction D2. The side walls 66, 67 are aligned in the direction D2 and extend along the direction D1. The housing 63 further has a signal input terminal 631 for inputting a high-frequency signal and a signal output terminal 632 for outputting the amplified high-frequency signal. The signal input terminal 631 is provided on the end wall 64, and the signal output terminal 632 is provided on the end wall 65.

[0095] The input matching circuit 101, the transistor element 102, and the output matching circuit 103 are arranged in this order in the direction D1. The input matching circuit 101, the transistor element 102, and the output matching circuit 103 are disposed between the end wall 64 and the end wall 65 in the direction D1, and between the side wall 66 and the side wall 67 in the direction D2. The input matching circuit 101, the transistor element 102, and the output matching circuit 103 are surrounded by the end walls 64, 65 and the side walls 66, 67. The lid 68 is disposed on the upper surfaces of the end walls 64, 65 and the side walls 66, 67, and hermetically seals the space accommodating the input matching circuit 101, the transistor element 102, and the output matching circuit 103. The lid 68 is made of, for example, ceramic or metal.

[0096] The transistor element 102 is an example of a semiconductor element in this embodiment, and is, for example, a field effect transistor (FET). The transistor element 102 is arranged between the input matching circuit 101 and the output matching circuit 103 in the direction D1. The transistor element 102 includes, for example, a plurality of transistors for high-frequency amplification. The transistor element 102 has a semiconductor substrate 1020, a plurality of signal input electrodes 1021 and a plurality of signal output electrodes 1022 that are signal electrodes, and a ground electrode 1023 (see FIG. 41 ). The plurality of signal input electrodes 1021 are arranged along the direction D2 at an edge of the principal surface of the semiconductor substrate 1020 that is closer to the input matching circuit 101. The plurality of signal output electrodes 1022 are arranged along the direction D2 at an edge of the principal surface of the semiconductor substrate 1020 that is closer to the output matching circuit 103. The ground electrode 1023 is provided on the rear surface of the semiconductor substrate 1020. In one example, the signal input electrode 1021 is connected to the control terminal (gate) of a transistor, the signal output electrode 1022 is connected to one current terminal (drain) of the transistor, and the ground electrode 1023 is connected to the other current terminal (source) of the transistor. The ground electrode 1023 is conductively bonded to the mounting surface 61 of the base 60 by a conductive paste (not shown).

[0097] The input matching circuit 101 includes the capacitor 1 of the first embodiment, a plurality of wires 71 (first wires), a plurality of wires 72 (second wires), and a plurality of wires 73. The metal pads 41 and 42 of the capacitor 1 are electrically connected to each other by the plurality of wires 71. The metal pad 41 of the capacitor 1 is electrically connected to a plurality of signal input electrodes 1021 of the transistor element 102 by the plurality of wires 72. The metal pad 42 of the capacitor 1 is electrically connected to a signal input terminal 631 of the housing 63 by the plurality of wires 73. The rear surface metal film 51 of the capacitor 1 is conductively bonded to the mounting surface 61 of the base 60 by a conductive paste (not shown). The input impedance of the transistor element 102 is matched by the capacitance of the metal pads 41 and 42 and the inductance of the wires 71, 72, and 73. The input matching circuit 101 may include the capacitor 2 of the first modified example, the capacitor 3 of the second modified example, or the 3 A modified capacitor 4 may also be provided.

[0098] The output matching circuit 103 has a capacitor 90 shown in FIG. 25, a plurality of wires 76, and a plurality of wires 77. A metal pad 92 of the output matching circuit 103 is electrically connected to a signal output electrode 1022 of the transistor element 102 by the plurality of wires 76, and is also electrically connected to a signal output terminal 632 of the housing 63 by the plurality of wires 77. A rear surface metal film 97 of the capacitor 90 is conductively bonded to the mounting surface 61 of the base 60 by a conductive paste (not shown). The output impedance of the transistor element 102 is matched by the capacitance of the metal pad 92 and the inductance of the wires 76 and 77. The output matching circuit 103 may use, instead of the capacitor 90, a ceramic capacitor shown in FIG. 24, the capacitor 1 of the first embodiment, the capacitor 2 of the first modified example, the capacitor 3 of the second modified example, or the like. 3 A modified capacitor 4 may also be provided.

[0099] According to the electronic device 5 of this embodiment, the input matching circuit 101 is the capacitor 1 of the first embodiment, the capacitor 2 of the first modified example, the capacitor 3 of the second modified example, or the capacitor 4 of the third modified example. 3 By including the capacitor 4 of the modified example, it is possible to suppress attenuation of high frequency signals. 3 When the modified capacitor 4 is provided, the attenuation of high frequency signals can be further suppressed.

[0100] FIG. 42 is a plan view showing the configuration of an electronic device 6 according to a third embodiment. In FIG. 42, the package lid is omitted for ease of understanding. The electronic device 6 according to this embodiment receives a high-frequency signal, amplifies the high-frequency signal, and outputs the amplified signal. As shown in FIG. 42, the electronic device 6 includes a housing 63, two transistor elements 102, branch circuit boards 106 and 107, two input matching circuits 101, two output matching circuits 103, and multiplexing circuit boards 108 and 109. The configurations and arrangements of the housing 63, the input matching circuits 101, the transistor elements 102, and the output matching circuits 103 are the same as those of the second embodiment.

[0101] Branch circuit boards 106 and 107 are aligned with each other in direction D1 and are disposed between signal input terminal 631 and input matching circuit 101 in direction D1. Branch circuit board 106 is located on the signal input terminal 631 side, and branch circuit board 107 is located on the input matching circuit 101 side. Branch circuit board 106 has a ceramic substrate 1061 and a branch circuit 1062 provided on the main surface of substrate 1061. Similarly, branch circuit board 107 has a ceramic substrate 1071 and a branch circuit 1072 provided on the main surface of substrate 1071. Metal films (not shown) are fixed to the back surfaces of substrates 1061 and 1071, and the metal films are joined to base 60 with metal paste.

[0102] The branch circuits 1062 and 1072 are branch circuits for the input matching circuit 101. The branch circuit 1062 includes a wiring pattern 1063 provided on the main surface of the substrate 1061. The wiring pattern 1063 is electrically connected to the signal input terminal 631 by a wire 701. The wiring pattern 1063 branches in two directions from the connection point with the wire 701. The branch circuit 1072 includes two wiring patterns 1073 provided on the main surface of the substrate 1071. Each wiring pattern 1073 is electrically connected to each of the two branched ends of the wiring pattern 1063 via a wire 702. Each wiring pattern 1073 repeatedly branches from the connection point with the wire 702 and ultimately reaches four metal pads 1070. Adjacent metal pads 1070 are connected to each other via a film resistor 1074, forming a Wilkinson coupler. The metal pad 1070 is electrically connected to the metal pad 42 of the input matching circuit 101 by a wire 73 .

[0103] Multiplexing circuit boards 108 and 109 are aligned with each other in direction D1 and are disposed between output matching circuit 103 and signal output terminal 632 in direction D1. Multiplexing circuit board 108 is located on the output matching circuit 103 side, and multiplexing circuit board 109 is located on the signal output terminal 632 side. Multiplexing circuit board 108 has a ceramic substrate 1081 and a multiplexing circuit 1082 provided on the main surface of substrate 1081. Similarly, multiplexing circuit board 109 has a ceramic substrate 1091 and a multiplexing circuit 1092 provided on the main surface of substrate 1091. Metal films (not shown) are fixed to the back surfaces of substrates 1081 and 1091, and the metal films are joined to base 60 with metal paste.

[0104] The multiplexing circuits 1082 and 1092 are multiplexing circuits for the output matching circuit 103. The multiplexing circuit 1082 includes two wiring patterns 1083 provided on the main surface of the substrate 1081. Each wiring pattern 1083 includes four metal pads 1080. Adjacent metal pads 1080 are connected to each other via film resistors 1084, forming a Wilkinson coupler. Each metal pad 1080 is electrically connected to a metal pad 92 of the output matching circuit 103 via a wire 77. Each wiring pattern 1083 is repeatedly coupled from the four metal pads 1080 and ultimately reaches a connection point with a wire 703. Each wiring pattern 1083 is electrically connected to two ends of a wiring pattern 1093 of the multiplexing circuit 1092 via the wire 703. The center of the wiring pattern 1093 is electrically connected to the signal output terminal 632 via a wire 704.

[0105] According to the electronic device 6 of this embodiment, as in the second embodiment, the input matching circuit 101 is configured to use the capacitor 1 of the first embodiment, the capacitor 2 of the first modified example, the capacitor 3 of the second modified example, or the capacitor 4 of the third modified example. 3 By providing the modified capacitor 4, it is possible to suppress the attenuation of high frequency signals.

[0106] The passive elements and electronic devices according to the present disclosure are not limited to the above-described embodiments, and various other modifications are possible. For example, the above-described embodiments and modifications may be combined with each other depending on the required purpose and effect. The third region 113, the insulating film 32, the metal pad 42, and the wire 71 may be omitted as necessary. In this case, one end of the wire 73 is bonded to the metal pad 41. [Explanation of symbols]

[0107] 1, 2, 3, 4... Capacitors (passive elements) 5,6…Electronic equipment 10...Semiconductor substrate 11...Main surface 12...Back side 13,14...Side 21,22,21A,21B,24,25...Conductive film 23...Membrane 31, 32, 33...Insulating film 41, 42, 43, 45, 46...Metal pads 44...Membrane 51...Back metal film 60...base 61...Mounting surface 63...Housing 64,65...End walls 66,67…Side wall 68...Lid 71, 72, 73, 75, 76, 77...Wires 74...Conductive paste 81...SiN film 82, 84, 85...Resist 83...SiN mask 90...Capacitor 91...Ceramic substrate 92...Metal pad 95...Semiconductor substrate 96...insulating film 97...Back metal film 101...Input matching circuit 102...Transistor element 103...Output matching circuit 106, 107...Branch circuit board 108,109...Multiplex circuit board 111...First Area 112...Second Region 113...Third Realm 114...The Fourth Realm 115...The Fifth Realm 211...Ti film 212…Au film 213...Pt film 251, 252...recesses 451,461...Convex part 631...Signal input terminal 632...Signal output terminal 701, 702, 703, 704...Wires 821,841,842,851…Photosensitive part 831,832…Aperture 951...area 1020...Semiconductor substrate 1021...Signal input electrode 1022...Signal output electrode 1023...Ground electrode 1061, 1071, 1081, 1091... PCB 1062, 1072...Branch circuits 1063,1073...Wiring pattern 1070,1080...Metal pad 1074, 1084...Membrane resistance 1082,1092…Multiplex circuit 1083,1093...wiring pattern D1,D2…direction G1,G2,G3…Curve Ga...gap Jr...Return current Js…Signal current

Claims

1. a semiconductor substrate having a p-type or n-type conductivity and having a main surface and a back surface; a backside metal film provided on the backside of the semiconductor substrate; a first insulating film provided on a first region on the main surface of the semiconductor substrate; a first metal pad provided on the first insulating film; a first conductor extending in a first direction from the first metal pad; a first conductive film provided adjacent to the first metal pad in the first direction on the main surface of the semiconductor substrate, provided on a second region adjacent to the first region in the first direction, provided in ohmic contact with the main surface of the semiconductor substrate, having an electrical resistivity smaller than that of the semiconductor substrate, and electrically connected to the semiconductor substrate; a second insulating film provided on a third region adjacent to the second region in the first direction on the main surface of the semiconductor substrate; a second metal pad provided on the second insulating film; Equipped with The second region is located between the first region and the third region.

2. the first metal pad has a first protrusion protruding toward the second metal pad; 2. The passive element according to claim 1, wherein said first conductive film has a first recess surrounding said first protrusion on three sides.

3. the second metal pad has a second protrusion protruding toward the first protrusion, 3. The passive element according to claim 2, wherein said first conductive film further has a second recess surrounding said second protrusion on three sides.

4. a second conductive film provided on a fourth region of the main surface of the semiconductor substrate, in contact with the main surface of the semiconductor substrate, and having an electrical resistivity lower than that of the semiconductor substrate; a third insulating film provided on a fifth region on the main surface of the semiconductor substrate; a third metal pad provided on the third insulating film; Further provided with 4. The passive element according to claim 1, wherein the first to fifth regions are arranged in this order along the first direction of the first and second regions.

5. 4. The passive element according to claim 1, wherein a width of the first conductive film in the first direction in the first and second regions is greater than a width of the first metal pad in the same direction.

6. The electrical resistivity of the semiconductor substrate is 1.0×10 －４ 2. The passive element according to claim 1, having a resistivity of Ω·cm or more and 1 Ω·cm or less.

7. the first metal pad extends along a second direction intersecting the first direction; The passive element according to claim 1 , wherein the length of the first metal pad in the second direction is greater than the width of the first metal pad in the first direction.

8. a housing having a signal terminal and a conductive base; a semiconductor element mounted on the base, the semiconductor element having a signal electrode and a ground electrode conductively connected to the base; and the passive element according to any one of claims 1 to 3 mounted on the base, the first metal pad of the passive element is electrically connected to the signal terminal by a second conductor; The semiconductor substrate of the passive element is in conductive contact with the base.

9. a housing having a signal terminal and a conductive base; a semiconductor element mounted on the base, the semiconductor element having a signal electrode and a ground electrode conductively connected to the base; a semiconductor substrate mounted on the base, the semiconductor substrate having a p-type or n-type conductivity and a main surface and a back surface; a back surface metal film provided on the back surface of the semiconductor substrate; a first insulating film provided on a first region on the main surface of the semiconductor substrate; a first metal pad provided on the first insulating film; a first conductor connected to the first metal pad and extending in a first direction from the first metal pad; a first conductive film provided on a second region on the main surface of the semiconductor substrate adjacent to the first region in the first direction and located below the first conductor, the first conductive film making an ohmic connection with the main surface of the semiconductor substrate and having an electrical resistivity lower than that of the semiconductor substrate; a second insulating film provided on a third region adjacent to the second region in the first direction; and a second metal pad connected to the first conductor and provided on the second insulating film; a second conductor electrically connecting the first metal pad of the passive element and the signal terminal; a third conductor electrically connecting the second metal pad of the passive element and the signal electrode of the semiconductor element; An electronic device comprising:

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