Semiconductor Devices

Abstract

To provide a technology which can stabilize a potential of an electric field relaxation region, and can also reduce a contact resistance of a source region.SOLUTION: A semiconductor device includes: a semiconductor substrate; a plurality of trenches that extend in a first direction and are arrayed at intervals in a second direction which intersects the first direction; a gate insulating film; and a gate electrode. The semiconductor substrate includes a source region, a body region, a drift region, a plurality of bottom regions, a plurality of electric field relaxation regions, and a plurality of contact regions. When the semiconductor substrate is viewed in a plan view from above, there are a plurality of overlapping ranges in which each inter-trench semiconductor region and each electric field relaxation region overlap; the plurality of overlapping ranges include a plurality of contact overlapping ranges in which the contact regions are provided, and a plurality of non-contact overlapping ranges in which the contact regions are not provided; and the contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application is a related application of Japanese Patent Application No. 2021-206356 filed on December 20, 2021, and claims priority based on this Japanese patent application, the entire contents of which are incorporated herein by reference.

[0002] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0003] U.S. Pat. No. 10,586,845 discloses a semiconductor device including a semiconductor substrate, a plurality of trenches arranged at intervals on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of each trench, and a gate electrode disposed in each trench. The semiconductor substrate has a plurality of n-type source regions, a p-type body region, a plurality of p-type contact regions, a p-type field relaxation region, and an n-type drift region. Each source region is exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film. Each body region is in contact with the gate insulating film below the source region. Each contact region is exposed on the upper surface of the semiconductor substrate and in contact with the source region and the gate insulating film. Each field relaxation region is in contact with the gate insulating film below the contact region. The drift region is in contact with the body region and the field relaxation region from below. In the semiconductor device of U.S. Pat. No. 10,586,845, the source regions and the contact regions are alternately arranged along the extension direction of the trenches.

[0004] When the semiconductor device of U.S. Patent No. 10,586,845 is turned off, a depletion layer extends from the body region and the field relaxation region into the drift region. In this semiconductor device, contact regions are provided above each of the multiple field relaxation regions. Therefore, when the semiconductor device is turned off, holes rapidly flow from the field relaxation region to the contact region, and a high reverse voltage is applied to the pn junction at the interface between the field relaxation region and the drift region. As a result, the depletion layer rapidly expands in the drift region, suppressing electric field concentration near the bottom of the trench. Summary of the Invention

[0005] In the semiconductor device disclosed in U.S. Pat. No. 10,586,845, many contact regions are arranged, which narrows the area of ​​the source region exposed on the upper surface of the semiconductor substrate. As a result, the contact resistance of the source region increases. This specification provides a technology that can stabilize the potential of the electric field relaxation region and reduce the contact resistance of the source region.

[0006] The semiconductor device disclosed in this specification includes a semiconductor substrate, a plurality of trenches provided on an upper surface of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction intersecting the first direction on the upper surface, a gate insulating film covering the inner surface of each of the trenches, and a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has a source region, a body region, a drift region, a plurality of bottom regions, a plurality of electric field reduction regions, and a plurality of contact regions. The source region is an n-type region exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches. The body region is a p-type region below the source region and in contact with the gate insulating film in each of the trenches. The drift region is an n-type region below the body region and in contact with the gate insulating film in each of the trenches and separated from the source region by the body region. The bottom regions are p-type regions extending in the first direction to contact the gate insulating film at the bottom surface of the corresponding trench and contacting the drift region. The electric field relief regions are p-type regions disposed below the body region, connected to the body region, extending in the second direction, contacting the bottom region, and spaced apart in the first direction. The contact regions are p-type regions exposed on the top surface of the semiconductor substrate and contacting the body region. The semiconductor regions located between the trenches are inter-trench semiconductor regions, and when the semiconductor substrate is viewed from above, there are multiple overlapping ranges where the inter-trench semiconductor regions and the electric field relief regions overlap, and the multiple overlapping ranges include multiple contact overlapping ranges where the contact regions are provided and multiple non-contact overlapping ranges where the contact regions are not provided, and the contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the first direction.

[0007] The semiconductor device has multiple overlapping areas where the inter-trench semiconductor region and the electric field relaxation region overlap when the semiconductor substrate is viewed from above. The multiple overlapping areas include multiple contact overlapping areas and multiple non-contact overlapping areas. The contact overlapping area is the area where the contact region and the electric field relaxation region overlap. That is, in this semiconductor device, each of the multiple contact regions is disposed directly above the electric field relaxation region. Therefore, when the semiconductor device is turned off, in the contact overlapping area, holes flow from the bottom region to the contact region through the electric field relaxation region, maintaining the bottom region at a low potential. Furthermore, the contact overlapping area and the non-contact overlapping area are alternately disposed in the first direction in which the trench extends. Because the contact overlapping area is disposed in a dispersed manner, the potential of the entire bottom region is stabilized at a low potential, and a depletion layer spreads from each bottom region into the drift region in a balanced manner. Therefore, electric field concentration near the bottom end of the trench can be suppressed in a balanced manner. Furthermore, in the non-contact overlapping area, the source region can be exposed on the upper surface of the semiconductor substrate, thereby ensuring the area of ​​the source region. Since the contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the first direction in which the trench extends, it is possible to ensure a wide non-contact overlapping range (i.e., the area of ​​the source region on the upper surface of the semiconductor substrate), thereby reducing the contact resistance of the source region. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 5] 5 is a cross-sectional view taken along line VV in FIG. 4. [Figure 6] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6. [Figure 9] FIG. 7 is a cross-sectional view taken along line IX-IX in FIG. 6. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment, corresponding to FIG. 2; [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment, corresponding to FIG. 2. [Figure 12] FIG. 3 is a cross-sectional view of the semiconductor device of the reference example, corresponding to FIG. 2. DETAILED DESCRIPTION OF THE INVENTION

[0009] The technical elements disclosed in this specification are listed below. Note that each of the following technical elements is independently useful.

[0010] In an embodiment disclosed herein, the contact overlapping areas and the non-contact overlapping areas may be alternately arranged in the second direction. This configuration can more balancedly suppress electric field concentration near the bottom end of the trench and more uniformly reduce the contact resistance of the source region.

[0011] In one embodiment disclosed herein, an n-type upper drift region may be provided between each of the electric field buffer regions and the body region, the upper drift region contacting the gate insulating film in each of the trenches below the body region. In this configuration, the upper drift region functions as a current path even in the area where the electric field buffer regions are provided. That is, the channel formed in the body region located above the electric field buffer regions can be effectively utilized. This reduces channel resistance.

[0012] In one embodiment disclosed in the present specification, the electric field relief region may be a first electric field relief region, the overlapping range may be a first overlapping range, the contact overlapping range may be a first contact overlapping range, and the non-contact overlapping range may be a first non-contact overlapping range. The semiconductor substrate may further include a plurality of p-type second electric field relief regions. Each of the plurality of second electric field relief regions may be disposed below the body region, connected to the body region, extend in a third direction intersecting the first direction and the second direction, and contact each of the bottom regions. The plurality of second electric field relief regions may be disposed at intervals in a direction intersecting the third direction. When the semiconductor substrate is viewed in a plan view from above, there may be a plurality of second overlapping ranges in which each of the inter-trench semiconductor regions and each of the second electric field relief regions overlap. The plurality of second overlapping ranges may include a plurality of second contact overlapping ranges in which the contact region is provided and a plurality of second non-contact overlapping ranges in which the contact region is not provided. The second contact overlapping ranges and the second non-contact overlapping ranges may be arranged alternately in the first direction.

[0013] In the above configuration, the plurality of first electric field buffer regions and the plurality of second electric field buffer regions are provided so as to extend in different directions. Therefore, even if the spacing between the first electric field buffer regions and the spacing between the second electric field buffer regions are widened, the breakdown voltage of the semiconductor device can be ensured. Furthermore, since the spacing between the electric field buffer regions can be widened, the drift region can be disposed over a wide area in the inter-trench semiconductor region, thereby reducing the on-resistance.

[0014] In one embodiment disclosed herein, the semiconductor device may further include an interlayer insulating film covering the upper surface of the gate electrode and having a contact hole above the upper surface of the semiconductor substrate; and an upper electrode covering an area spanning the upper surface of the interlayer insulating film and the inner surface of the contact hole, contacting the upper surface of the semiconductor substrate within the contact hole, and insulated from the gate electrode by the interlayer insulating film. The upper electrode may also include a tungsten-containing layer disposed within the contact hole, and an aluminum-containing layer covering the upper surface of the interlayer insulating film and the upper surface of the tungsten-containing layer. In this configuration, by disposing the tungsten-containing layer within the contact hole, unevenness of the upper electrode (aluminum-containing layer) due to the contact hole can be reduced. Furthermore, the tungsten-containing layer can densely fill narrow contact holes, thereby enabling semiconductor devices to be miniaturized.

[0015] Example 1 1 to 3 show a semiconductor device 10 according to a first embodiment. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). As shown in FIGS. 2 and 3, the semiconductor device 10 includes a semiconductor substrate 12, an upper electrode 14, and a lower electrode 16. Note that FIG. 1 does not illustrate the electrode layer and insulating layer on the upper surface 12a of the semiconductor substrate 12. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the material of the semiconductor substrate 12 is not particularly limited, and may be other semiconductor materials such as silicon (Si) or gallium nitride (GaN). Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the semiconductor substrate 12 and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction.

[0016] As shown in FIG. 1, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends longitudinally along the y direction. Each trench 22 extends parallel to one another. Each trench 22 is arranged at intervals in the x direction. As shown in FIGS. 2 and 3, a gate insulating film 24 and a gate electrode 26 are disposed in each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is disposed inside each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.

[0017] 2 and 3, the upper surface of the gate electrode 26 and the upper surface 12a of the semiconductor substrate 12 are covered with an interlayer insulating film 28. A plurality of contact holes 28a are formed in the interlayer insulating film 28. Each of the contact holes 28a is provided in a range between two adjacent trenches 22. In other words, the contact holes 28a are arranged in a range in the x direction where no gate electrode 26 is provided. Each of the contact holes 28a penetrates the interlayer insulating film 28 from the upper surface to the lower surface.

[0018] The upper electrode 14 covers an area spanning the upper surface of the interlayer insulating film 28 and the inner surface of the contact hole 28a. The upper electrode 14 has a tungsten-containing layer 14a and an aluminum-containing layer 14b. The tungsten-containing layer 14a is disposed inside the contact hole 28a. The tungsten-containing layer 14a contacts the upper surface 12a of the semiconductor substrate 12 at the bottom of the contact hole 28a. The tungsten-containing layer 14a is formed so that its upper surface is substantially flat with the upper surface of the interlayer insulating film 28. The tungsten-containing layer 14a is insulated from the gate electrode 26 by the interlayer insulating film 28. The aluminum-containing layer 14b covers substantially the entire upper surface of the interlayer insulating film 28 and the upper surface of the tungsten-containing layer 14a. In this embodiment, the tungsten-containing layer 14a is made of tungsten, and the aluminum-containing layer 14b is made of an alloy of aluminum and silicon. However, the tungsten-containing layer 14a may be any metal layer containing tungsten as a main component, and the aluminum-containing layer 14b may be any metal layer containing aluminum as a main component (including elemental aluminum).

[0019] The lower electrode 16 is provided on the lower surface 12b of the semiconductor substrate 12. The lower electrode 16 contacts substantially the entire area of ​​the lower surface 12b of the semiconductor substrate 12.

[0020] Within the semiconductor substrate 12, a source region 30, a plurality of contact regions 31, a body region 32, a drift region , a drain region 35, a plurality of bottom regions , and a plurality of electric field reduction regions are provided.

[0021] The source regions 30 are n-type regions. As shown in FIGS. 1 to 3, the source regions 30 are provided in each of the semiconductor regions (hereinafter referred to as inter-trench semiconductor regions) located between adjacent trenches 22. The source regions 30 are provided at positions exposed on the upper surface 12a of the semiconductor substrate 12, and are in ohmic contact with the upper electrode 14 (tungsten-containing layer 14a). Each source region 30 contacts the gate insulating films 24 in the two trenches 22 located on both sides of the inter-trench semiconductor region.

[0022] The body region 32 is a p-type region. As shown in FIGS. 2 and 3, the body region 32 is disposed below the source region 30 and a contact region 31, which will be described later. The body region 32 contacts the source region 30 and the contact region 31 from below. The body region 32 contacts the gate insulating film 24 in each trench 22 below the source region 30.

[0023] The drift region 34 is an n-type region. As shown in FIGS. 2 and 3, the drift region 34 is disposed below the body region 32 and an electric field relaxation region 38, which will be described later. The drift region 34 contacts the body region 32 and the electric field relaxation region 38 from below. As shown in FIG. 3, the drift region 34 contacts the gate insulating film in each trench 22 below the body region 32 in an area where the electric field relaxation region 38 is not provided. The drift region 34 is distributed from each inter-trench semiconductor region to the region below each trench 22. The drift region 34 is separated from the source region 30 by the body region 32.

[0024] (Drawing needs to be revised) A drain region 35 is provided below the drift region 34. The drain region 35 is an n-type region having a higher n-type impurity concentration than the drift region 34. The drain region 35 contacts the drift region 34 from below. The drain region 35 is in ohmic contact with the lower electrode 16 on the lower surface 12b of the semiconductor substrate 12.

[0025] Each bottom region 36 is a p-type region. Each bottom region 36 contacts the gate insulating film 24 in the corresponding trench 22 at the bottom surface of the corresponding trench 22. Each bottom region 36 extends long in the y direction along the bottom surface of the corresponding trench 22. The bottom region 36 contacts the drift region 34.

[0026] Each electric field relaxation region 38 is a p-type region. As shown in FIG. 2, each electric field relaxation region 38 contacts the body region 32 from below. In FIG. 1, each electric field relaxation region 38 is indicated by gray hatching. As shown in FIG. 1, each electric field relaxation region 38 extends elongatedly in a direction intersecting each trench 22 (x direction). Each electric field relaxation region 38 is arranged at intervals in the direction in which each trench 22 extends (y direction). That is, as shown in FIG. 1, when the semiconductor substrate 12 is viewed from above in a plan view, each trench 22 and each electric field relaxation region 38 are arranged in a lattice pattern. As shown in FIG. 2, each electric field relaxation region 38 extends below the lower end of the trench 22 and contacts the side surface of the bottom region 36. Each bottom region 36 extends below each electric field relaxation region 38. The side surface and bottom surface of each electric field relaxation region 38 are surrounded by the drift region 34.

[0027] Each contact region 31 is a p-type region. Each contact region 31 has a higher p-type impurity concentration than the body region 32. As shown in FIGS. 1 and 2, each contact region 31 is provided in an inter-trench semiconductor region. A plurality of contact regions 31 are provided in each inter-trench semiconductor region. Each contact region 31 is exposed on the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 14. As shown in FIG. 1, the side surfaces of each contact region 31 are surrounded by the source region 30. As shown in FIG. 2, each contact region 31 is in contact with the body region 32 at its lower surface.

[0028] As described above, the upper end of each electric field relaxation region 38 is connected to the body region 32. Therefore, each bottom region 36 is connected to the body region 32 via the electric field relaxation region 38. Therefore, each bottom region 36 is connected to the upper electrode 14 via the electric field relaxation region 38, the body region 32, and the contact region 31. Therefore, the potential of each bottom region 36 is approximately equal to the potential of the upper electrode 14.

[0029] As shown in FIG. 1 , in the semiconductor device 10, when the semiconductor substrate 12 is viewed from above, there are multiple overlapping areas 40 (i.e., gray-hatched areas) where the inter-trench semiconductor region and each electric field relaxation region 38 overlap. Hereinafter, among the multiple overlapping areas 40, the overlapping area 40 where the contact region 31 is provided is referred to as the contact overlapping area 40a, and the overlapping area 40 where the contact region 31 is not provided is referred to as the non-contact overlapping area 40b. In the contact overlapping area 40a, the contact region 31 is arranged to overlap with the electric field relaxation region 38. In the non-contact overlapping area 40b, the contact region 31 is not arranged, and above the electric field relaxation region 38, the source region 30 is exposed on the upper surface 12a of the semiconductor substrate 12. In the semiconductor device 10, the contact overlapping area 40a and the non-contact overlapping area 40b are arranged alternately in the direction in which the trench 22 extends (the y direction). That is, the contact region 31 is arranged every other overlapping area 40 in the y direction. The contact overlapping ranges 40a and the non-contact overlapping ranges 40b are also configured to be alternately arranged in the direction (x direction) in which the electric field reduction region 38 extends. That is, the contact regions 31 are arranged in every other overlapping range 40 in the x direction.

[0030] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 16 than to the upper electrode 14. When a voltage equal to or greater than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the area adjacent to the gate insulating film 24, and the semiconductor device 10 is turned on. When the voltage applied to the gate electrode 26 is reduced to a level below the gate threshold, the channel disappears and the semiconductor device 10 is turned off.

[0031] When the semiconductor device 10 is in an off state, the potential of the bottom electrode 16 is much higher than the potential of the top electrode 14. In this state, the drift region 34 has a potential close to that of the bottom electrode 16. As described above, the bottom region 36 has a potential substantially equal to that of the top electrode 14. Therefore, a high reverse voltage is applied to the pn junction at the interface between the drift region 34 and the bottom region 36. As a result, a depletion layer spreads over a wide area from each bottom region 36 into the drift region 34. This suppresses electric field concentration near the bottom end of the trench 22, ensuring the breakdown voltage of the semiconductor device 10.

[0032] Next, the operation when the semiconductor device 10 is turned off will be described in detail. When the semiconductor device 10 is turned off and the potential of the lower electrode 16 rises, holes flow from the bottom region 36 through the electric field reduction region 38, the body region 32, and the contact region 31 to the upper electrode 14. This flow of holes maintains the potential of the bottom region 36 at a low potential. In the contact overlap region 40a, the path that holes take from the bottom region 36 to the upper electrode 14 via the contact region 31 is short. As described above, the contact overlap region 40a and the non-contact overlap region 40b are alternately arranged in the x direction and the y direction. Therefore, the contact overlap region 40a (i.e., the contact region 31) is arranged approximately evenly distributed on the upper surface of the semiconductor substrate 12. Therefore, even in the non-contact overlap region 40b, the path from the bottom region 36 to the upper electrode 14 via the contact region 31 is not very long. Therefore, holes are quickly discharged from the bottom region 36 to the upper electrode 14 throughout the entire bottom region 36. This suppresses the rise in potential of the bottom region 36 that accompanies the rise in potential of the lower electrode 16, and maintains the potential of the bottom region 36 at approximately the same potential as the potential of the upper electrode 14. As a result, a depletion layer quickly spreads around the bottom region 36, effectively suppressing electric field concentration near the bottom end of the trench 22.

[0033] In the semiconductor device 10, the source region 30 is exposed on the upper surface 12a of the semiconductor substrate 12 in the non-contact overlapping range 40b. The contact overlapping range 40a and the non-contact overlapping range 40b are alternately arranged in the x direction and the y direction, so that the non-contact overlapping range 40b (i.e., the area of ​​the source region 30) can be secured, and the contact resistance between the source region 30 and the upper electrode 14 can be reduced.

[0034] In Example 1, the contact overlapping ranges 40a and the non-contact overlapping ranges 40b are alternately arranged in both the x and y directions. However, the contact overlapping ranges 40a and the non-contact overlapping ranges 40b do not have to be alternately arranged in the x direction. As long as they are alternately arranged at least in the y direction, it is possible to both suppress the electric field concentration near the bottom end of the trench 22 and reduce the contact resistance of the source region 30. The same applies to the other examples described below.

[0035] Example 2 Next, a semiconductor device 100 of Example 2 will be described with reference to FIGS. 4 and 5. As shown in FIG. 4, in the semiconductor device 100 of Example 2, the direction in which each electric field relaxation region 138 extends is different from that of Example 1. Each electric field relaxation region 138 extends long in the m direction intersecting with each trench 22. The m direction is a direction inclined at a predetermined angle with respect to the direction (x direction) perpendicular to the direction in which each trench 22 extends (y direction). As shown in FIG. 5, other internal configurations of the semiconductor substrate 12 (such as the source region 30, body region 32, and drift region 34) are the same as those of Example 1.

[0036] In Example 2, similarly to Example 1, the contact overlapping ranges 140a and the non-contact overlapping ranges 140b are configured to be alternately arranged in the direction in which the trenches 22 extend (y direction). That is, a contact region 31 is arranged every other overlapping range 140 in the y direction. The contact overlapping ranges 140a and the non-contact overlapping ranges 140b are also configured to be alternately arranged in the direction in which the electric field reduction region 138 extends (m direction). That is, a contact region 31 is arranged every other overlapping range 140 in the m direction. Note that in Example 2, the contact overlapping ranges 140a and the non-contact overlapping ranges 140b are not alternately arranged in the x direction. In the x direction, either the contact overlapping range 140a or the non-contact overlapping range 140b is arranged contiguously with respect to each overlapping range 140.

[0037] In this embodiment, the contact overlapping range 140a and the non-contact overlapping range 140b are arranged alternately in the y direction and the m direction, so that it is possible to suppress electric field concentration near the bottom end of the trench 22 and reduce the contact resistance of the source region 30 at the same time.

[0038] Example 3 Next, a semiconductor device 200 of Example 3 will be described with reference to Figures 6 to 9. As shown in Figure 6, in the semiconductor device 200 of Example 3, the semiconductor substrate 12 has, in addition to the electric field buffer region 138 of Example 2 (hereinafter referred to as the first electric field buffer region 138), a plurality of p-type second electric field buffer regions 238 extending in a direction (n direction) different from the first electric field buffer region 138. The n direction is a direction intersecting the direction (y direction) in which each trench 22 extends and the direction (m direction) in which the first electric field buffer region 138 extends, and is inclined at a predetermined angle with respect to the x direction orthogonal to the y direction.

[0039] As shown in Fig. 6, when the semiconductor substrate 12 is viewed from above, the first electric field relief region 138 and the second electric field relief region 238 intersect in a range where they overlap with the trench 22. As shown in Fig. 7, each first electric field relief region 138 and each second electric field relief region 238 are connected in a range where they contact the side surface of the trench 22. Each first electric field relief region 138 and each second electric field relief region 238 contacts the bottom region 36 in a range where they are connected to each other. As shown in Fig. 8, in a cross section where the first electric field relief region 138 and the second electric field relief region 238 are not connected, the drift region 34 contacts the side surface of each trench 22 below the body region 32.

[0040] In Example 3, similarly to Examples 1 and 2, in a plurality of overlapping regions 240 where the inter-trench semiconductor region and the second electric field reduction region 238 overlap, the contact overlapping region 240a and the non-contact overlapping region 240b are configured to be arranged alternately in the direction (y direction) in which the trench 22 extends. That is, a contact region 31 is arranged for every other overlapping region 240 in the y direction. Also, as shown in FIGS. 6 and 9, in Example 3, the contact overlapping region 240a is configured to be arranged at an interval with respect to each overlapping region 240 (that is, not arranged contiguous) in the direction (n direction) in which the second electric field reduction region 238 extends.

[0041] In the semiconductor device 200 of Example 3, the plurality of first electric field relief regions 138 and the plurality of second electric field relief regions 238 are provided so as to extend in mutually different directions (the m-direction and the n-direction). Therefore, even if the intervals between the respective first electric field relief regions 138 and the respective second electric field relief regions 238 are widened, holes can efficiently flow from the bottom region 36 to the contact region 31 via the respective electric field relief regions 138, 238, thereby ensuring the breakdown voltage of the semiconductor device 200. Furthermore, because the intervals between the respective electric field relief regions 138, 238 can be widened, the drift region 34 can be disposed over a wide range in the inter-trench semiconductor region, thereby reducing the on-resistance.

[0042] In the range where each electric field relaxation region 138, 238 is provided, the n-type drift region 34 is not in contact with the gate insulating film 24, making it difficult for current to flow through the channel formed in the body region 32. However, in this embodiment, the first electric field relaxation region 138 and the second electric field relaxation region 238 intersect in the range where they overlap with the trench 22, allowing electrons to flow from the channel formed in the body region 32 to a wide range of the drift region 34. This prevents an increase in on-resistance.

[0043] Example 4 Next, a semiconductor device 300 according to a fourth embodiment will be described with reference to FIG. 10 . FIG. 10 is a cross section corresponding to FIG. 2 of the first embodiment. In the fourth embodiment, an n-type upper drift region 42 is provided between the body region 32 and the electric field relaxation region 38. The upper drift region 42 contacts the body region 32 from below and contacts the gate insulating film 24 below the body region 32. The upper drift region 42 is separated from the source region 30 by the body region 32. The lower end of the upper drift region 42 is located above the lower ends of the trenches 22. The electric field relaxation region 38 is provided below the upper drift region 42. The electric field relaxation region 38 contacts the upper drift region 42 from below. Although not shown, the upper drift region 42 is connected to the drift region 34 in a cross section where the electric field relaxation region 38 is not provided (a cross section corresponding to FIG. 3 of the first embodiment).

[0044] In the semiconductor device 300 of Example 4, the upper drift region 42 functions as a current path even in the area where the electric field relaxation region 38 is provided. That is, the channel formed in the body region 32 located above the electric field relaxation region 38 (the channel formed in the cross section of FIG. 2) can be effectively utilized. This allows the channel resistance to be reduced.

[0045] Example 5 Next, a semiconductor device 400 according to a fifth embodiment will be described with reference to FIG. 11. FIG. 11 is a cross section corresponding to FIG. 2 of the first embodiment. In the fifth embodiment, the thickness (length in the z direction) of each bottom region 36 is shorter than that of the first embodiment. In the fifth embodiment, the lower end of each bottom region 36 is located higher than the lower end of each electric field relaxation region 38. That is, within the range where the electric field relaxation region 38 is provided, each bottom region 36 is not in contact with the drift region 34, and is surrounded by the electric field relaxation region 38.

[0046] In the semiconductor device 400 of Example 5, the thickness of the bottom region 36 is thinner than that of Example 1. Because the distance that the bottom region 36 protrudes into the drift region 34 is short, electrons that flow through the inter-trench semiconductor region can flow into a wider range of the drift region 34, thereby reducing the on-resistance.

[0047] (Reference example) Next, a semiconductor device 500 of the reference example will be described with reference to FIG. 12 . The semiconductor device 500 of the reference example differs from the semiconductor device 10 of Example 1 in that it does not have a bottom region 36. The other configurations are similar to those of Example 1. The semiconductor device 500 of the reference example does not have a bottom region 36. However, each electric field relief region 38 extends below the lower end of the trench 22. Because multiple electric field relief regions 38 are provided at intervals in the direction in which each trench 22 extends (the y direction), when the semiconductor device 500 is turned off, a depletion layer extending from each electric field relief region 38 into the drift region 34 can suppress electric field concentration near the lower end of the trench 22. Furthermore, since the semiconductor device 500 does not have a bottom region 36, the manufacturing process can be reduced.

[0048] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

Claims

1. a semiconductor substrate (12); a plurality of trenches (22) provided on an upper surface (12a) of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction on the upper surface intersecting the first direction; a gate insulating film (24) covering the inner surface of each trench; a gate electrode (26) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; It is equipped with The semiconductor substrate is an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches; a p-type body region (32) below the source region and in contact with the gate insulating film in each of the trenches; an n-type drift region (34) in contact with the gate insulating film in each trench below the body region and separated from the source region by the body region; a plurality of p-type field relief regions (38, 138), each of which is disposed below the body region, each of which is connected to the body region, each of which extends in the second direction, and each of which is spaced apart in the first direction; a plurality of p-type contact regions (31), each of which is exposed on the upper surface of the semiconductor substrate and contacts the body region; It has a semiconductor region located between the plurality of trenches is an inter-trench semiconductor region; When the semiconductor substrate is viewed from above in a plan view, there are a plurality of overlapping ranges (40, 140) in which each of the inter-trench semiconductor regions and each of the electric field relaxation regions overlap, In each of the overlapping areas, the body region and the electric field reduction region are connected to each other, The plurality of overlapping ranges include a plurality of contact overlapping ranges (40a, 140a) in which the contact regions are provided and a plurality of non-contact overlapping ranges (40b, 140b) in which the contact regions are not provided, the contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the first direction; Semiconductor device.

2. a semiconductor substrate (12); a plurality of trenches (22) provided on an upper surface (12a) of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction on the upper surface intersecting the first direction; a gate insulating film (24) covering the inner surface of each trench; a gate electrode (26) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; It is equipped with The semiconductor substrate is an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches; a p-type body region (32) below the source region and in contact with the gate insulating film in each of the trenches; an n-type drift region (34) in contact with the gate insulating film in each trench below the body region and separated from the source region by the body region; a plurality of p-type field relief regions (38, 138), each of which is disposed below the body region, each of which is connected to the body region, each of which extends in the second direction, and each of which is spaced apart in the first direction; a plurality of p-type contact regions (31), each of which is exposed on the upper surface of the semiconductor substrate and contacts the body region; It has a semiconductor region located between the plurality of trenches is an inter-trench semiconductor region; the source region and the body region are disposed in each of the inter-trench semiconductor regions; When the semiconductor substrate is viewed from above in a plan view, there are a plurality of overlapping ranges (40, 140) in which each of the inter-trench semiconductor regions and each of the electric field relaxation regions overlap, The plurality of overlapping ranges include a plurality of contact overlapping ranges (40a, 140a) in which the contact regions are provided and a plurality of non-contact overlapping ranges (40b, 140b) in which the contact regions are not provided, the contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the second direction; Semiconductor device.

3. 3. The semiconductor device according to claim 1, wherein the plurality of electric field relaxation regions extend below a bottom end of the trench.

4. 3. The semiconductor device according to claim 2, wherein the semiconductor substrate further comprises a plurality of p-type bottom regions (36) extending in the first direction so as to contact the gate insulating film at the bottom surface of the corresponding trench, contacting the drift region, and contacting each of the electric field relaxation regions.

Images