Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device comprising a semiconductor substrate having a chemical oxygen concentration of at least 1×1016 atoms / cm3. The semiconductor device comprises a buffer region of a first conductivity type that includes bulk donors and increase donors and that has a higher doping concentration than a drift region. For over the entirety of a first range from the lower edge to the deepest peak of the buffer region, the concentration of thermal donors is 10% or lower of the concentration of the increase donors at the same depth position.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] BACKGROUND ART Techniques for forming semiconductor devices such as transistors on a semiconductor substrate are known (see, for example, Patent Documents 1 and 2). Patent Document 1: U.S. Patent Application Publication No. 2020 / 0194550 Patent Document 2: U.S. Patent Application Publication No. 2016 / 0329401 Problem to be Solved

[0003] In semiconductor devices, it is desirable to precisely control the doping concentration in the semiconductor substrate.

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device having an upper surface and a lower surface, including bulk donors and thermal donors, and having an oxygen chemical concentration of 1×10 16 atoms / cm 3 The present invention provides a semiconductor device including a semiconductor substrate as described above. The semiconductor device may include a drift region of a first conductivity type provided in the semiconductor substrate, the drift region including the bulk donor and the thermal donor. Any of the semiconductor devices may include a buffer region of the first conductivity type provided between the drift region and the lower surface of the semiconductor substrate, the buffer region including the bulk donor and the augmented donor, and having a doping concentration higher than that of the drift region. In any of the semiconductor devices, the buffer region may have one or more doping concentration peaks in the depth direction of the semiconductor substrate. In any of the semiconductor devices, the one or more doping concentration peaks may include a deepest peak located farthest from the lower surface of the semiconductor substrate. In any of the semiconductor devices, the augmented donor may include the thermal donor. In any of the semiconductor devices, the concentration of the thermal donor may be 10% or less of the concentration of the augmented donor at the same depth position throughout a first range from the lower end of the buffer region to the deepest peak.

[0005] In any of the above semiconductor devices, the increased donors may include C1Oi-H donors.

[0006] In any of the above semiconductor devices, the concentration of the thermal donors may be 1% or more of the concentration of the enhanced donors at the same depth position throughout the first range.

[0007] In any of the above semiconductor devices, the oxygen chemical concentration of the semiconductor substrate is 1×10 17 atoms / cm 3 That's it, 5 x 10 17 atoms / cm 3 It may be the following:

[0008] In any of the above semiconductor devices, the concentration of the thermal donors in the drift region may be 0.0001 times or less the oxygen chemical concentration.

[0009] In any of the above semiconductor devices, the doping concentration of the drift region may be 1.5 times or less the concentration of the bulk donors.

[0010] In any of the above semiconductor devices, the concentration of the thermal donor at the apex position of the deepest peak may be 0.1 times or less the doping concentration.

[0011] In any of the semiconductor devices described above, the buffer region may include a maximum peak where the doping concentration is greatest among the doping concentration peaks other than the deepest peak, and in any of the semiconductor devices described above, the concentration of the thermal donor at the apex position of the maximum peak may be 0.01 times or less the doping concentration.

[0012] In any of the semiconductor devices described above, the buffer region may include a shallowest peak closest to the bottom surface of the semiconductor substrate, and the concentration of the thermal donors at the apex of the shallowest peak may be 0.001 times or less the doping concentration.

[0013] In any of the above semiconductor devices, the concentration distribution of the thermal donors may have a decreasing portion that decreases toward the upper surface of the semiconductor substrate in a region closer to the upper surface of the semiconductor substrate than the buffer region.

[0014] In any of the above semiconductor devices, the reduced portion may have a region in which the logarithmic gradient of the thermal donor concentration toward the upper surface side of the semiconductor substrate is 0.5 to 10 times the logarithmic gradient of the oxygen chemical concentration.

[0015] In a second aspect of the present invention, a semiconductor device is provided having an upper surface and a lower surface, including a bulk donor, and having an oxygen chemical concentration of 1×10 16 atoms / cm 3 A manufacturing method for a semiconductor device using the semiconductor substrate described above is provided. The semiconductor device may include a drift region of a first conductivity type provided in the semiconductor substrate, the drift region including the bulk donor and the thermal donor. The semiconductor device may include a buffer region of the first conductivity type provided between the drift region and the lower surface of the semiconductor substrate, the buffer region including the bulk donor and the augmented donor, and having a higher doping concentration than the drift region. In any of the semiconductor devices described above, the buffer region may have one or more doping concentration peaks in the depth direction of the semiconductor substrate. In any of the semiconductor devices described above, the one or more doping concentration peaks may include a deepest peak located farthest from the lower surface of the semiconductor substrate. In any of the semiconductor devices described above, the augmented donor may include the thermal donor. The manufacturing method may include annealing the semiconductor substrate so that the concentration of the thermal donor is 10% or less of the concentration of the augmented donor at the same depth position throughout a first range from the lower end of the buffer region to the deepest peak.

[0016] In any of the above manufacturing methods, in each step of annealing the semiconductor substrate, the time for which the temperature of the semiconductor substrate passes through a temperature zone of 400° C. or more and 500° C. or less may be 20 minutes or less per pass.

[0017] In any of the above manufacturing methods, in each step of annealing the semiconductor substrate, the time for which the temperature of the semiconductor substrate passes through a temperature zone of 425° C. or more and 475° C. or less may be 10 minutes or less per pass.

[0018] In any of the above manufacturing methods, in each step of annealing the semiconductor substrate, the cumulative time during which the temperature of the semiconductor substrate passes through a temperature range of 400° C. or more and 500° C. or less may be 120 minutes or less.

[0019] In any of the above manufacturing methods, in each step of annealing the semiconductor substrate, the cumulative time during which the temperature of the semiconductor substrate passes through a temperature zone of 425° C. or more and 475° C. or less may be 60 minutes or less.

[0020] In any of the above manufacturing methods, a metal electrode may be formed above the upper surface of the semiconductor substrate. In any of the above manufacturing methods, a step after forming the metal electrode may be performed at a temperature lower than 400°C.

[0021] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of an area D in FIG. [Figure 3] FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2. [Figure 4] FIG. 4 is a diagram showing a reference example of a doping concentration distribution 210 on the ff line of FIG. [Figure 5] FIG. 2 is a diagram showing a doping concentration distribution 210 according to an example. [Figure 6]10 is a diagram showing an example of an oxygen chemical concentration distribution and a thermal donor concentration distribution in a region on the upper surface 21 side of the buffer region 20 (a region from a depth position Zb to a depth position Zu). FIG. [Figure 7] 2 is a flowchart illustrating an example of a method for manufacturing the semiconductor device 100. FIG. [Figure 8] 10A and 10B are diagrams showing examples of changes in temperature of the semiconductor substrate 10 over time in each annealing stage. [Figure 9] 10 is a flowchart showing a more specific example of the method for manufacturing the semiconductor device 100. FIG. [Figure 10] FIG. 10 is a flowchart showing steps subsequent to the steps in FIG. 9. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0025] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0026] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0027] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0028] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0030] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0031] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. A hydrogen donor may be a donor that is a combination of at least a vacancy (V) and hydrogen (H). Alternatively, an interstitial Si-H, which is a combination of interstitial silicon (Si-i) and hydrogen in a silicon semiconductor, or a CIOi-H, which is a combination of interstitial carbon (Ci), interstitial oxygen (Oi), and hydrogen, also functions as a donor that supplies electrons. In this specification, a VOH defect, CIOi-H, or interstitial Si-H may be referred to as a hydrogen donor.

[0032] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants that are uniformly contained in the ingot that is the base of the semiconductor substrate when it is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3The higher the oxygen concentration, the easier it is to generate hydrogen donors. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of that chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values ​​at room temperature, for example, values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0033] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is used in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system used in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0034] As used herein, chemical concentration refers to the atomic density of an impurity measured regardless of its electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance (CV) measurement. The carrier concentration measured by spreading resistance (SR) measurement may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as the value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is significantly greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0035] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. When the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom notation may be omitted.

[0036] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0037] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method may be lower than the chemical concentration of the element that represents the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0038] FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 1, the positions of each component are shown as projected onto the top surface of a semiconductor substrate 10. In FIG. 1, only some components of the semiconductor device 100 are shown. others The components are omitted.

[0039] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edges 162 facing each other in a top view. In FIG. 1, the X-axis and Y-axis are parallel to either edge 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0040] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0041] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor) and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT).

[0042] In FIG. 1, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0043] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring (described later) may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0044] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, the gate structure having an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0045] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0046] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is indicated by diagonal hatching.

[0047] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. In a top view, the region surrounded by the well region may be the active portion 160.

[0048] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0049] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0050] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0051] The active-side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active-side gate wiring 131 extends in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y-axis direction. When the active section 160 is divided by the active-side gate wiring 131, the transistor sections 70 and the diode sections 80 may be arranged alternately in the X-axis direction in each divided region.

[0052] The semiconductor device 100 may include a temperature sensing section (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0053] In the present example, semiconductor device 100 includes an edge termination structure 90 between active section 160 and edge 162 when viewed from above. Edge termination structure 90 in the present example is disposed between peripheral gate wiring 130 and edge 162. Edge termination structure 90 alleviates electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding active section 160.

[0054] 2 is an enlarged view of region D in FIG. 1. Region D is a region including a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0055] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0056] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0057] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0058] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0059] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width in an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P type and the well region 11 is of P+ type.

[0060] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0061] The gate trench portion 40 in this example may have two straight line portions 39 (parts of the trench that are linear along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0062] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0063] In the transistor section 70, the dummy trench section 30 is provided between each of the linear portions 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the linear portions 39. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have a linear section 29 and an end portion 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both linear dummy trench sections 30 without end portions 31 and dummy trench sections 30 with end portions 31.

[0064] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0065] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0066] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e at one end of each mesa portion in the extension direction, a base region 14-e is also provided at the other end of each mesa portion. Each mesa portion may be provided with at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0067] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0068] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0069] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0070] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0071] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0072] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0073] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0074] Fig. 3 is a diagram showing an example of an ee cross section in Fig. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0075] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described with reference to FIG. 2.

[0076] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0077] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0078] The mesa portion 60 of the transistor portion 70 includes an N+ type emitter region 12 and P type The base region 14 is provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0079] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0080] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0081] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0082] The mesa portion 61 of the diode portion 80 is in contact with the upper surface 21 of the semiconductor substrate 10. P type The mesa portion 61 has a base region 14. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0083] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0084] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as the chemical concentration peaks of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0085] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0086] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as the donor and acceptor in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0087] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the top surface 21 of the semiconductor substrate 10. Each trench extends from the top surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0088] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0089] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and on the inner side of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0090] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0091] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0092] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0093] FIG. 4 is a diagram showing a reference example of a doping concentration distribution 210 along the ff line in FIG. 3. In graphs of concentration distribution such as FIG. 4, the carrier concentration measured by the SR method or the like is taken as the doping concentration. The ff line is a line parallel to the Z axis that passes through the buffer region 20. The horizontal axis in FIG. 4 indicates the depth position (position in the Z axis direction) within the semiconductor substrate 10. In graphs of concentration distribution such as FIG. 4, the bottom end position of the buffer region 20 is taken as the reference position (0) in the Z axis direction, and the distance from the reference position is taken as the position in the Z axis direction. At the bottom end position of the buffer region 20, there is a valley in the doping concentration distribution due to the PN junction between the collector region 22 and the buffer region 20, but this valley is omitted in FIG. 4 and other figures.

[0094] The entire semiconductor substrate 10 contains oxygen. FIG. 4 shows a distribution 210 when a semiconductor device 100 is formed on two semiconductor substrates 10 having different oxygen chemical concentrations. The distribution of the dashed line in FIG. 4 indicates a semiconductor substrate 10 having a relatively high oxygen chemical concentration (for example, 4×10 17 atoms / cm 3 ), and the distribution of the solid line is an example where the oxygen chemical concentration in the semiconductor substrate 10 is relatively low (e.g., 1×10 17 atoms / cm 3 ) are examples. The oxygen chemical concentration of the semiconductor substrate 10 may be compared using the average or maximum oxygen chemical concentration of the entire substrate. In each example, the dose and acceleration energy of the dopant locally implanted into the buffer region 20 are the same. The dopant implanted into the buffer region 20 is, for example, protons, but is not limited to this.

[0095] In either example, buffer region 20 has one or more doping concentration peaks 201. In the example of FIG. 4, buffer region 20 has five doping concentration peaks 201-1 to 201-5. In this specification, of the doping concentration peaks 201 in buffer region 20, the doping concentration peak 201 farthest from lower surface 23 of semiconductor substrate 10 (doping concentration peak 201-5 in FIG. 4) may be referred to as the deepest peak, and the doping concentration peak 201 closest to lower surface 23 (doping concentration peak 201-1 in FIG. 4) may be referred to as the shallowest peak. In addition, the depth position of the apex of doping concentration peak 201-1 is designated Z1, and the depth position of the apex of doping concentration peak 201-5 is designated Z5. In buffer region 20, inter-peak regions 301 are provided between adjacent doping concentration peaks 201. A plurality of inter-peak regions 301 may be provided. In this specification, among the inter-peak regions 301 of the buffer region 20, the inter-peak region 301 farthest from the lower surface 23 of the semiconductor substrate 10 (inter-peak region 301-4 in FIG. 4) is referred to as the deepest inter-peak region, and the inter-peak region 301 closest to the lower surface 23 (inter-peak region 301-5 in FIG. 4) is referred to as the deepest inter-peak region. Inter-peak region 301-1 ) is sometimes referred to as the shallowest inter-peak region.

[0096] The drift region 18 is provided above the buffer region 20. The depth position of the boundary between the buffer region 20 and the drift region 18 is designated Zb. Depth position Zb is the position where the doping concentration first matches the doping concentration (Dd1 or Dd2) of the drift region 18 in the direction from the buffer region 20 toward the drift region 18. No local dopant is implanted into the drift region 18. The doping concentration of the drift region 18 may be substantially constant. Thermal donors are formed throughout the semiconductor substrate 10 due to the influence of heat applied to the semiconductor substrate 10. The distribution of the thermal donors is substantially uniform throughout the semiconductor substrate 10. Therefore, the doping concentration of the drift region 18 is slightly higher than the bulk donor concentration BD. Oxygen contained in the semiconductor substrate 10 forms unstable oxygen complexes as the semiconductor substrate 10 is heated or cooled. The oxygen complexes act as dopants within the semiconductor substrate 10. The oxygen complex is referred to herein as the thermal donor.

[0097] The concentration of thermal donors formed at each location in the semiconductor substrate 10 varies depending on the concentration of oxygen contained in the semiconductor substrate 10 and the conditions for increasing and decreasing the temperature of the semiconductor substrate 10. As shown in Figure 4, in two examples where the oxygen chemical concentration of the semiconductor substrate 10 is different, the concentration of thermal donors formed differs, and the doping concentration varies throughout the semiconductor substrate 10.

[0098] The doping concentration of the drift region 18 in the solid line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively low is denoted as Dd1, and the doping concentration of the drift region 18 in the dashed line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively high is denoted as Dd2. The doping concentration of each drift region 18 may be the average value for the entire drift region 18, or the minimum value.

[0099] The thermal donor concentration in the solid-line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively low is designated as Nth1, and the thermal donor concentration in the dashed-line distribution 210 where the oxygen chemical concentration of the semiconductor substrate 10 is relatively high is designated as Nth2. The difference (Dd1-BD or Dd2-BD) between the doping concentration of the drift region 18 (Dd1 or Dd2) and the bulk donor concentration BD corresponds to the concentration (Nth1 or Nth2) of the thermal donors formed in the respective semiconductor substrates 10. In each example described herein, the difference between the doping concentration of the drift region 18 and the bulk donor concentration BD is designated as the thermal donor concentration. The thermal donor concentration may be the same throughout the semiconductor substrate 10.

[0100] The bulk donor concentration BD may be the minimum value of the bulk donor chemical concentration in the semiconductor substrate 10, the bulk donor chemical concentration at the center position in the depth direction of the semiconductor substrate 10, or the average value of the bulk donor chemical concentration in the drift region 18. A bulk donor is a dopant other than oxygen that is distributed throughout the semiconductor substrate 10. The bulk donor may be, for example, phosphorus, arsenic, or antimony, but is not limited to these. When both P-type bulk acceptors and N-type bulk donors are distributed throughout the semiconductor substrate 10, the bulk donor concentration BD is the net concentration determined by the difference between the bulk donor concentration and the bulk acceptor concentration. The concentrations of the bulk donors and bulk acceptors may be values ​​measured by SIMS or the like.

[0101] The buffer region 20 includes increased donors in addition to bulk donors. Increased donors are donors other than bulk donors. Increased donors include implanted donors formed by locally implanting ions into the buffer region 20 and the thermal donors described above. When hydrogen ions are locally implanted into the buffer region 20, the implanted donors are hydrogen donors. When phosphorus or the like is locally implanted into the buffer region 20, the implanted donors are phosphorus donors.

[0102] The concentration of thermal donors varies depending on the oxygen concentration of the semiconductor substrate 10. Therefore, when the concentration ratio of thermal donors contained in the increased donors is high, the concentration of the increased donors varies depending on the oxygen concentration of the semiconductor substrate 10. Therefore, as shown by the distribution 210 of the dashed and solid lines in FIG. 4, the doping concentration of the buffer region 20 varies depending on the oxygen concentration of the semiconductor substrate 10.

[0103] In the buffer region 20, the range from the bottom end of the buffer region 20 to the deepest peak (doping concentration peak 201-5 in this example) is defined as a first region 200. In the solid line distribution 210, the minimum value of the doping concentration in the first region 200 is defined as Nmin1, and the concentration of the increased donor at that depth position is defined as ID1. In this example, the minimum value Nmin1 of the doping concentration in the first region 200 is the doping concentration Nmin1 in the deepest inter-peak region (inter-peak region 301-4 in this example). The concentration ID1 of the increased donor is the difference (Nmin1-BD) between the doping concentration Nmin1 and the bulk donor concentration BD. In the dashed line distribution 210, the minimum value of the doping concentration in the first region 200 is defined as Nmin2, and the concentration of the increased donor at that depth position is defined as ID2. The depth position at which the doping concentration in the solid line distribution 210 is Nmin1 and the depth position at which the doping concentration in the dashed line distribution 210 is Nmin2 are defined as follows: Nmin2 The depth positions at which the doping concentration ID2 is increased are almost the same. The concentration ID2 of the increased donor is the difference (Nmin2-BD) between the doping concentration Nmin2 and the bulk donor concentration BD. Note that a part of the inter-peak region 301 may have a doping concentration lower than the bulk donor concentration BD. In such a case, the doping concentration of the inter-peak region 301 where the doping concentration is higher than the bulk donor concentration BD and where the doping concentration is minimum may be set as Nmin1.

[0104] The augmented donor concentrations ID1 and ID2 may represent the minimum augmented donor concentrations within the first range 200. Because the thermal donor concentrations Nth1 and Nth2 are approximately constant at each depth position in the buffer region 20, the ratio of the thermal donor concentrations Nth1 and Nth2 to the augmented donor concentrations ID1 and ID2 represents the maximum thermal donor / augmented donor ratio within the first range 200. The average thermal donor concentration in the drift region 18 may be the thermal donor concentration in the buffer region 20, the maximum thermal donor concentration in the drift region 18 may be the thermal donor concentration in the buffer region 20, and the thermal donor concentration at the depth position Zb may be the thermal donor concentration in the buffer region 20.

[0105] In the solid line distribution 210, the concentration of the increased donor, ID1, is 7 × 10 13 / cm 3 and the thermal donor concentration Nth1 is 2 × 10 13 / cm 3 The proportion of thermal donors among the increased donors, Nth1 / ID1, is 29%. In the dashed distribution 210, the concentration of increased donors, ID2, is 1×10 14 / cm 3 and the thermal donor concentration Nth2 is 5×10 13 / cm 3 The proportion of thermal donors among the increased donors is Nth2 / ID2 is 50%. In this way, if the proportion of thermal donors among the increased donors is large, the concentration of increased donors varies greatly depending on the oxygen concentration of the semiconductor substrate 10. This causes fluctuations in characteristics such as the breakdown voltage of the semiconductor device 100. When the breakdown voltage of the example distribution 210 indicated by the solid line is normalized to 1, the breakdown voltage of the example distribution 210 indicated by the dashed line is 1.15.

[0106] FIG. 5 is a diagram showing a doping concentration distribution 210 according to an embodiment. In the example of FIG. 5, the concentration of thermal donors formed in the semiconductor substrate 10 is lower than in the example of FIG. 4. Therefore, the doping concentration and the concentration of increased donors at each depth position are also different from those in the example of FIG. 4. The other structures are similar to those in the example of FIG. 4. In FIG. 5 as well, the oxygen chemical concentration in the semiconductor substrate 10 is relatively high (for example, 4×10 17 atoms / cm 3 An example distribution 210 is shown by the dashed line, and is intended to illustrate a case where the oxygen chemical concentration in the semiconductor substrate 10 is relatively low (e.g., 1×10 17 atoms / cm 3 5, the oxygen chemical concentration in the semiconductor substrate 10 is the same as that in the example of FIG. 4, but the thermal history of the semiconductor substrate 10 is controlled to lower the concentration of thermal donors.

[0107] As described above, the semiconductor substrate 10 includes bulk donors and thermal donors. The bulk donors and thermal donors may be distributed throughout the semiconductor substrate 10. The drift region 18 includes bulk donors and thermal donors. The drift region 18 may not include other donors.

[0108] The buffer region 20 includes bulk donors and boost donors. As described above, boost donors include implanted donors and thermal donors. The implanted donors may be hydrogen donors, phosphorus donors, or other donors. The hydrogen donors may include C1O1-H donors. The hydrogen donors may include VOH defects or interstitial Si-H.

[0109] In this example, in both the solid-line and dashed-line distributions 210, the thermal donor concentration Nth is 10% or less of the augmented donor concentration ID at the same depth throughout the first region 200. In the example of FIG. 5, in the solid-line distribution 210, the minimum doping concentration in the first region 200 is Nmin1, and the augmented donor concentration at that depth is ID1. The augmented donor concentration ID1 is the difference (Nmin1-BD) between the doping concentration Nmin1 and the bulk donor concentration BD. In the dashed-line distribution 210, the minimum doping concentration in the first region 200 is Nmin2, and the augmented donor concentration at that depth is ID2.

[0110] As an example, in the solid line distribution 210, the concentration ID1 of the increased donor is 5 × 10 13 / cm 3 and the thermal donor concentration Nth1 is 3×10 12 / cm 3 The proportion of thermal donors among the increased donors, Nth1 / ID1, is 6%. In the dashed distribution 210, the concentration of increased donors, ID2, is 5×10 13 / cm 3 and the thermal donor concentration Nth2 is 5×10 12 / cm 3 The proportion of thermal donors among the increased donors is Nth2 / ID2is 10%. That is, in all the examples, throughout the first range 200, the concentration Nth of the thermal donor is 10% or less of the concentration ID of the increased donor at the same depth position.

[0111] In this example, by reducing the proportion of thermal donors, it is possible to suppress variations in the concentration of increased donors due to the oxygen concentration in the semiconductor substrate 10. This makes it possible to suppress variations in characteristics such as the breakdown voltage of the semiconductor device 100. In the example of Figure 5, when the breakdown voltage of the example of the distribution 210 indicated by the solid line is set to 1, the breakdown voltage of the example of the distribution 210 indicated by the dashed line is 1.02.

[0112] Throughout the first region 200, the concentration Nth of thermal donors may be 10% or less, 8% or less, 6% or less, or 5% or less of the concentration ID of increased donors at the same depth position. By reducing the proportion of thermal donors, it is possible to suppress variations in the doping concentration of the buffer region 20 and thereby suppress fluctuations in the characteristics of the semiconductor device 100. Throughout the first region 200, the concentration Nth of thermal donors may be 0.1% or more, 0.5% or more, 1% or more, 2% or more, 3% or more, or 5% or more of the concentration ID of increased donors at the same depth position.

[0113] The oxygen chemical concentration of the semiconductor substrate 10 is 1×10 16 atoms / cm 3 That's all. In this example, even if the oxygen chemical concentration of the semiconductor substrate 10 is high, the generation of thermal donors can be suppressed, thereby suppressing fluctuations in the characteristics of the semiconductor device 100, such as the breakdown voltage. Therefore, it is not necessary to prepare a substrate with a low oxygen chemical concentration, and the manufacturing cost of the semiconductor device 100 can be reduced. Furthermore, by using a semiconductor substrate 10 with a high oxygen chemical concentration, it becomes easier to form hydrogen donors, and it becomes easier to increase the doping concentration of the buffer region 20. The oxygen chemical concentration of the semiconductor substrate 10 is 3×10 16 atoms / cm 3 May be greater than or equal to 5 x 10 16 atoms / cm 3 May be greater than or equal to 1 x 10 17 atoms / cm3 The oxygen chemical concentration of the semiconductor substrate 10 may be 1×10 18 atoms / cm 3 may be less than or equal to 5 x 10 17 atoms / cm 3 It may be the following:

[0114] The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 is 0.0001 times (1×10 -4 The oxygen chemical concentration in the drift region 18 may be an average value in the drift region 18, a minimum value, or a value at the center in the depth direction of the drift region 18. This reduces the proportion of thermal donors among the increased donors in the buffer region 20, thereby suppressing fluctuations in the characteristics of the semiconductor device 100. The concentration of thermal donors in the drift region 18 (Nth1 or Nth2) may be 0.00005 times (5×10) the oxygen chemical concentration in the drift region 18. -5 times) or less, and may be 0.00001 times (1 × 10 -5 The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 may be 1×10 times or less of the oxygen chemical concentration in the drift region 18. -8 May be more than 5 x 10 -8 May be more than 1 x 10 -7 It may be more than double.

[0115] The doping concentration (Dd1 or Dd2) of the drift region 18 may be 1.5 times or less the bulk donor concentration BD. This reduces the proportion of thermal donors among the increased donors in the buffer region 20, thereby suppressing fluctuations in the characteristics of the semiconductor device 100. The doping concentration (Dd1 or Dd2) of the drift region 18 may be 1.3 times or less, or even 1.1 times or less, the bulk donor concentration BD. The doping concentration (Dd1 or Dd2) of the drift region 18 is greater than the bulk donor concentration BD.

[0116] The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 may be 0.5 times or less the concentration of bulk donors BD. This reduces the proportion of thermal donors among the increased donors in the buffer region 20, thereby suppressing fluctuations in the characteristics of the semiconductor device 100. The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 may be 0.3 times or less, or even 0.1 times or less, the concentration of bulk donors BD. The concentration of thermal donors (Nth1 or Nth2) in the drift region 18 is greater than 0.

[0117] At depth position Z5 of the apex of the deepest peak (in this example, doping concentration peak 201-5), the thermal donor concentration Nth may be 0.1 times or less the doping concentration Np5. In the solid and dashed line distributions 210, the doping concentration Np5 is approximately the same. This reduces the proportion of thermal donors among the increased donors at the deepest peak of the buffer region 20, thereby suppressing fluctuations in the characteristics of the semiconductor device 100. For example, when the semiconductor substrate 10 is turned off, the variation in the voltage waveform oscillations that occurs when the space charge region (or depletion layer) spreading from the upper surface 21 reaches the buffer region 20 can be suppressed. At depth position Z5, the thermal donor concentration Nth may be 0.05 times or less, or even 0.01 times or less, the doping concentration Np5.

[0118] The buffer region 20 includes a maximum peak (doping concentration peak 201-1 in this example) where the doping concentration is maximum among the doping concentration peaks 201 other than the deepest peak. A peak other than doping concentration 201-1 may be the maximum peak. For example, doping concentration peak 201-2 may be the maximum peak. At depth position Z1 of the apex of the maximum peak, the concentration of thermal donors may be 0.01 times or less the doping concentration Np1. This reduces the proportion of thermal donors among the increased donors at the maximum peak of the buffer region 20, thereby suppressing fluctuations in the characteristics of the semiconductor device 100. At depth position Z1, the concentration of thermal donors may be 0.005 times or less, or even 0.001 times or less, the doping concentration Np1.

[0119] The buffer region 20 includes a shallowest peak (doping concentration peak 201-1 in this example) closest to the bottom surface 23 of the semiconductor substrate 10. At depth position Z1 of the apex of the shallowest peak, the concentration of thermal donors may be 0.001 times or less the doping concentration Np1. This reduces the proportion of thermal donors among the increased donors in the shallowest peak of the buffer region 20, thereby suppressing fluctuations in the characteristics of the semiconductor device 100. At depth position Z1, the concentration of thermal donors may be 0.0005 times or less, or even 0.0001 times or less, the doping concentration Np1.

[0120] 6 is a diagram showing an example of the oxygen chemical concentration distribution and the thermal donor concentration distribution in the region (region from depth position Zb to depth position Zu) on the upper surface 21 side of the buffer region 20. The oxygen chemical concentration may be a value measured by a SIMS method or the like. In this example, depth position Zb is the boundary position between the buffer region 20 and the drift region 18, and depth position Zu is the upper end position of the drift region 18.

[0121] In this example, the thermal donor concentration is not constant in the depth direction. The thermal donor concentration at each depth position in the drift region 18 can be calculated from the difference between the doping concentration and the bulk donor concentration BD. Note that the thermal donor concentration in the buffer region 20 described in FIG. 5 and other figures may be calculated using the average thermal donor concentration in the drift region 18 as shown in FIG. 6, or the thermal donor value at depth position Zb.

[0122] The oxygen chemical concentration distribution in this example has a decreasing portion 220 in which the oxygen chemical concentration decreases toward the upper surface 21 of the semiconductor substrate 10 in the region from the depth position Zb to the depth position Zu. In the decreasing portion 220, the oxygen chemical concentration decreases as the distance from the upper surface 21 decreases. The decreasing portion 220 does not have a region in which the oxygen chemical concentration increases as the distance from the upper surface 21 decreases.

[0123] Oxygen inside the semiconductor substrate 10 may be released to the outside of the semiconductor substrate 10 during the manufacturing process of the semiconductor device 100. As a result, the oxygen chemical concentration decreases significantly near the surface of the semiconductor substrate 10, and even at positions away from the surface of the semiconductor substrate 10, the oxygen chemical concentration may decrease gradually toward the substrate surface. In the semiconductor device 100 of this example, the region where the oxygen chemical concentration decreases toward the underside 23 is ground during the manufacturing process. The decreasing portion 220 may be provided over the entire region from the depth position Zb to the depth position Zu.

[0124] The thermal donor concentration at each depth varies depending on the oxygen chemical concentration at each depth. The thermal donor concentration distribution in this example has a decreasing portion 230 in which the thermal donor concentration decreases toward the upper surface 21 of the semiconductor substrate 10 in the region from depth Zb to depth Zu. In the decreasing portion 230, the thermal donor concentration decreases as the distance from the upper surface 21 decreases. The decreasing portion 230 does not have a region in which the thermal donor concentration increases as the distance from the upper surface 21 decreases. The decreasing portion 230 may be provided in part or the entire region from depth Zb to depth Zu. In the decreasing portion 230, the thermal donor concentration at depth Zu may decrease to less than half, less than one-quarter, less than one-tenth, or even to zero of the thermal donor concentration at depth Zb.

[0125] In this example, the reduced portion 230 has a region 240 in which the logarithmic gradient αth of the thermal donor concentration toward the upper surface 21 of the semiconductor substrate 10 is 0.5 to 10 times the logarithmic gradient αox of the oxygen chemical concentration. This reduces the proportion of thermal donors in the doping concentrations of the drift region 18 and the buffer region 20, thereby suppressing fluctuations in the characteristics of the semiconductor device 100. The depth position of the lower end of the region 240 is defined as Xa, and the depth position of the upper end is defined as Xb. The center position in the depth direction of the semiconductor substrate 10 is defined as Zc. The depth position Xa may be located in the range from Zc to Zb. The depth position Xa may coincide with the depth position Zb. The depth position Xb may be located in the range from Zc to Zb, or may be located in the range from Zc to Zu. The depth position Xb may be located closer to the lower surface 23 than the region where the oxygen chemical concentration changes abruptly. The depth position Xb may be 10 μm or more, 20 μm or more, or 30 μm or more away from the upper surface 21 of the semiconductor substrate 10. The length of the region 240 in the depth direction may be 10 μm or more, or 20 μm or more.

[0126] The oxygen chemical concentration at depth position Xa is Noxa, and the thermal donor concentration is Ntha. The oxygen chemical concentration at depth position Xb is Noxb, and the thermal donor concentration is Nthb. The logarithmic gradient αth of the thermal donor concentration and the logarithmic gradient αox of the oxygen chemical concentration in region 240 are defined by the following equations. αth=|log 10 (Ntha)-log 10 (Nthb)| / |Xa-Xb| αox=|log 10 (Noxa)-log 10 (Noxb)| / |Xa-Xb|

[0127] In region 240, the logarithmic slope α of the thermal donor concentration may be 0.8 times or more, or may be 1 times or more, of the logarithmic slope α of the oxygen chemical concentration. In region 240, the logarithmic slope α of the thermal donor concentration may be 7 times or less, or may be 4 times or less, of the logarithmic slope α of the oxygen chemical concentration.

[0128] FIG. 7 is a flowchart illustrating an example of a method for manufacturing the semiconductor device 100. The manufacturing method includes one or more steps of annealing the semiconductor substrate 10. The manufacturing method includes steps from cutting a semiconductor wafer from a semiconductor ingot to completing the semiconductor device 100. The manufacturing method in the example of FIG. 7 includes a first annealing step S701 and a second annealing step S702, but the manufacturing method may include one annealing step or three or more annealing steps. In each annealing step, the semiconductor substrate 10 is heated to a temperature equal to or higher than room temperature (25° C.). In at least one annealing step, the semiconductor substrate 10 may be heated to a temperature equal to or higher than 400° C.

[0129] As described above, the concentration of thermal donors formed in the semiconductor substrate 10 can be controlled by the thermal history of the semiconductor substrate 10. In the manufacturing method of this example, the semiconductor substrate 10 is annealed so that the concentration Nth of thermal donors is 10% or less of the concentration ID of increased donors at the same depth position over the entire first range 200 shown in FIG.

[0130] FIG. 8 is a diagram showing an example of the change in temperature of the semiconductor substrate 10 over time in each annealing stage. In FIG. 8, the horizontal axis represents time, and the vertical axis represents the temperature (°C) of the semiconductor substrate 10. In each annealing stage, the semiconductor substrate 10 is heated from room temperature (RT=25°C) to a predetermined temperature. In the example of FIG. 8, in both the first annealing stage S701 and the second annealing stage S702, the semiconductor substrate 10 is heated to 500°C or higher.

[0131] In a semiconductor substrate 10 made of silicon or the like, thermal donors are likely to be formed when the temperature of the semiconductor substrate 10 is near 450°C. Therefore, the formation of thermal donors can be suppressed by controlling the time the semiconductor substrate 10 passes through a predetermined first temperature zone in each annealing step. In the example of FIG. 8 , the lower limit temperature of the first temperature zone is 400°C, and the upper limit temperature is 500°C. In each step of annealing the semiconductor substrate 10, the time for the semiconductor substrate 10 to pass through the first temperature zone, in which the temperature is between 400°C and 500°C, may be 20 minutes or less per pass. In the example of FIG. 8 , the time for passing through the first temperature zone during the temperature rise process in the first annealing step S701 is T11, the time for passing through the first temperature zone during the temperature fall process is T21, the time for passing through the first temperature zone during the temperature rise process in the second annealing step S702 is T31, and the time for passing through the first temperature zone during the temperature fall process is T41. Each of T11, T21, T31, and T41 may be 20 minutes or less. This makes it possible to suppress the formation of thermal donors in the semiconductor substrate 10 when passing through the first temperature zone. Each of T11, T21, T31, and T41 may be 10 minutes or less, or may be 5 minutes or less. Furthermore, the average time of T11, T21, T31, and T41 may be 10 minutes or less, or may be 5 minutes or less.

[0132] In each step of annealing the semiconductor substrate 10, the cumulative time for the temperature of the semiconductor substrate 10 to pass through the first temperature zone (400°C or higher and 500°C or lower) throughout all steps from the start to the end of the manufacturing process of the semiconductor device 100 may be 120 minutes or less. In the example of FIG. 8, the total of T11, T21, T31, and T41 is 120 minutes or less. This makes it possible to suppress the total number of thermal donors formed in the semiconductor substrate 10. The cumulative time for passing through the first temperature zone may be 60 minutes or less, or may be 40 minutes or less.

[0133] The second temperature range is a temperature range of 425°C or higher and 475°C or lower. Thermal donors are more likely to be formed in the semiconductor substrate 10 in the second temperature range. In each step of annealing the semiconductor substrate 10, the time for the semiconductor substrate 10 to pass through the second temperature range of 425°C or higher and 475°C or lower may be 10 minutes or less per pass. In the example of FIG. 8 , the time for passing through the second temperature range during the temperature increase process in the first annealing step S701 is T12, the time for passing through the second temperature range during the temperature decrease process is T22, the time for passing through the second temperature range during the temperature increase process in the second annealing step S702 is T32, and the time for passing through the second temperature range during the temperature decrease process is T42. Each of T12, T22, T32, and T42 may be 10 minutes or less. This can suppress the formation of thermal donors in the semiconductor substrate 10 when passing through the second temperature range. Each of T12, T22, T32, and T42 may be 5 minutes or less, or may be 3 minutes or less. Also, the average time of T12, T22, T32, and T42 may be 5 minutes or less, or may be 3 minutes or less.

[0134] In each step of annealing the semiconductor substrate 10, the cumulative time for the temperature of the semiconductor substrate 10 to pass through the second temperature zone (425°C or higher and 475°C or lower) throughout all steps from the start to the end of the manufacturing process of the semiconductor device 100 may be 60 minutes or less. In the example of FIG. 8, the total of T12, T22, T32, and T42 is 60 minutes or less. This makes it possible to suppress the total number of thermal donors formed in the semiconductor substrate 10. The cumulative time for passing through the second temperature zone may be 30 minutes or less, or may be 20 minutes or less.

[0135] FIG. 9 is a flowchart showing a more specific example of a method for manufacturing the semiconductor device 100. In the example of FIG. 9, some steps of the manufacturing method are omitted. In this example, an interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10 (S901). Steps prior to S901 may include multiple steps of heating the semiconductor substrate 10 to a temperature higher than room temperature (25°C). In S901, the semiconductor substrate 10 may be heated to a temperature of 400°C or higher and 900°C or lower. The time during which the temperature of the semiconductor substrate 10 passes through the first temperature zone and the second temperature zone, as described with reference to FIGS. 7 and 8, includes the time in all steps during which the temperature of the semiconductor substrate 10 passes through the first temperature zone and the second temperature zone.

[0136] After the interlayer insulating film 38 is formed, a contact hole 54 is formed in the interlayer insulating film 38. After the contact hole 54 is formed, a barrier metal may be formed inside the contact hole 54 (S902). In S902, the semiconductor substrate 10 may be heated to a temperature of 400° C. or more and 700° C. or less. The barrier metal may include a film of at least one of titanium and titanium nitride.

[0137] After forming the barrier metal, a metal electrode (emitter electrode 52 in this example) is formed above the upper surface 21 of the semiconductor substrate 10 by sputtering (S903). After forming the emitter electrode 52, the semiconductor substrate 10 is placed in an annealing furnace or the like and annealed (S904). Unless otherwise specified, when the semiconductor substrate 10 is heated, the entire semiconductor substrate 10 is heated in an annealing furnace or the like. In S904, the semiconductor substrate 10 may be heated to a temperature of less than 400°C.

[0138] After forming the emitter electrode 52, a protective film is formed on the emitter electrode 52 (S905). The protective film is made of, for example, polyimide. After forming the protective film, the semiconductor substrate 10 is heated to a cure temperature of the protective film (S906). In S906, the semiconductor substrate 10 may be heated to a temperature less than 400°C.

[0139] After the protective film is formed, the semiconductor substrate 10 is thinned (S907) according to the breakdown voltage that the semiconductor device 100 should have. In S907, the thickness of the semiconductor substrate 10 is adjusted by grinding the lower surface 23 of the semiconductor substrate 10.

[0140] After thinning the semiconductor substrate 10, the collector region 22 is formed on the lower surface 23 of the semiconductor substrate 10 (S908), and the cathode region 82 is formed (S909). Either S908 or S909 can be performed first. In S908 and S909, dopant ions are implanted into the respective regions.

[0141] After the dopant ions are implanted into the collector region 22 and the cathode region 82, the semiconductor substrate 10 is annealed to activate the dopants (S910). In S910, the semiconductor substrate 10 may be locally heated by laser annealing or the like.

[0142] Fig. 10 is a flowchart showing a process subsequent to the process of Fig. 9. After forming the collector region 22 and the cathode region 82, the buffer region 20 is formed (S911). In S911, dopant ions such as protons are implanted into the buffer region 20.

[0143] After implanting the dopant ions into the buffer region 20, the semiconductor substrate 10 is annealed to activate the dopants (S912). In S912, the semiconductor substrate 10 may be heated to a temperature below 400°C.

[0144] After forming the buffer region 20, the semiconductor substrate 10 may be irradiated with charged particles such as helium to form lifetime killers (S913). Lifetime killers are recombination centers such as lattice defects, which combine with carriers in the semiconductor substrate 10 to shorten the carrier lifetime. For example, the top surface 21 side of the diode section 80 may be irradiated with charged particles such as helium. After irradiation with charged particles such as helium, the semiconductor substrate 10 is annealed (S914). In S914, the semiconductor substrate 10 may be heated to a temperature less than 400°C.

[0145] After forming the lifetime killer, the collector electrode 24 is formed by sputtering (S915). After forming the collector electrode 24, the semiconductor substrate 10 is annealed (S916). In S916, the semiconductor substrate 10 may be heated to a temperature less than 300°C. After forming the collector electrode 24, the semiconductor wafer may be diced into individual semiconductor chips.

[0146] In the manufacturing method of this example, the steps after forming the emitter electrode 52 (steps after S905) are performed at a temperature below 400°C. This makes it possible to suppress the formation of thermal donors in the semiconductor substrate 10. The steps after forming the emitter electrode 52 may be performed at a temperature of 390°C or lower, or may be performed at a temperature of 380°C or lower. In the manufacturing method of this example, in S901 and S902, the semiconductor substrate 10 is heated to a temperature of 400°C or higher. The temperature of the semiconductor substrate 10 in S901 and S902 may satisfy the conditions described with reference to FIGS. 7 and 8.

[0147] The annealing conditions in the manufacturing method may be determined based on the oxygen chemical concentration of the semiconductor substrate 10 used. For each oxygen chemical concentration of the semiconductor substrate 10, the change in the thermal donor concentration when at least one of the annealing time, temperature rise rate, temperature fall rate, and annealing temperature is changed may be measured in advance. Based on the measurement results, the concentration of thermal donors formed in the semiconductor substrate 10 can be controlled by adjusting at least one of the annealing time, temperature rise rate, temperature fall rate, and annealing temperature in each annealing stage.

[0148] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0149] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0150] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 Gate conductive portion, 52 emitter electrode, 54 contact hole, 60, 61 mesa portion, 70 transistor portion, 80 diode portion, 81 extension region, 82 cathode region, 90 edge termination structure portion, 100 semiconductor device, 130 peripheral gate wiring, 131 active side gate wiring, 160 active portion, 162 edge, 164 gate pad, 200 first region, 201 doping concentration peak, 210 distribution, 220 decreasing portion, 230 decreasing portion, 240 region

Claims

1. having a top surface and a bottom surface, including bulk donors and thermal donors, and an oxygen chemical concentration of 1×10 １６ atoms / cm ３ A semiconductor device including the above semiconductor substrate, a drift region of a first conductivity type provided in the semiconductor substrate and including the bulk donors and the thermal donors; a buffer region of the first conductivity type disposed between the drift region and the lower surface of the semiconductor substrate, the buffer region including the bulk donors and the increased donors, and having a doping concentration higher than that of the drift region; Equipped with the buffer region has one or more doping concentration peaks in a depth direction of the semiconductor substrate; the one or more doping concentration peaks include a deepest peak located furthest from the bottom surface of the semiconductor substrate; the augmented donor comprises the thermal donor; Over the entire first range from the bottom of the buffer region to the deepest peak, the concentration of the thermal donor is 10% or less of the concentration of the enhanced donor at the same depth position. Semiconductor device.

2. The boost donor comprises a CiOi-H donor. The semiconductor device according to claim 1 .

3. Over the entire first range, the concentration of the thermal donor is 0.1% or more of the concentration of the enhanced donor at the same depth position. The semiconductor device according to claim 1 .

4. The oxygen chemical concentration of the semiconductor substrate is 1×10 １７ atoms / cm ３ That's it, 5 x 10 １７ atoms / cm ３ is The semiconductor device according to claim 1 .

5. The concentration of the thermal donors in the drift region is 0.0001 times or less the oxygen chemical concentration. The semiconductor device according to claim 1 .

6. The doping concentration of the drift region is 1.5 times or less than the concentration of the bulk donors. The semiconductor device according to claim 1 .

7. At the apex position of the deepest peak, the concentration of the thermal donor is 0.1 times or less the doping concentration. The semiconductor device according to claim 1 .

8. the buffer region includes a maximum peak at which the doping concentration is maximum among the doping concentration peaks other than the deepest peak, At the apex of the maximum peak, the concentration of the thermal donor is 0.01 times or less the doping concentration. The semiconductor device according to claim 1 .

9. the buffer region includes a shallowest peak closest to the bottom surface of the semiconductor substrate; At the apex position of the shallowest peak, the concentration of the thermal donor is 0.001 times or less the doping concentration. The semiconductor device according to claim 1 .

10. In a region of the semiconductor substrate closer to the upper surface than the buffer region, the concentration distribution of the thermal donors has a decreasing portion that decreases toward the upper surface of the semiconductor substrate. The semiconductor device according to claim 1 .

11. The reduced portion has a region where the logarithmic gradient of the thermal donor concentration toward the upper surface side of the semiconductor substrate is 0.5 to 10 times the logarithmic gradient of the oxygen chemical concentration. The semiconductor device according to claim 10.

12. a bulk donor having an oxygen chemical concentration of 1×10 １６ atoms / cm ３ A manufacturing method for manufacturing a semiconductor device using the above semiconductor substrate, The semiconductor device includes: a drift region of a first conductivity type provided in the semiconductor substrate and including the bulk donors and thermal donors; a buffer region of the first conductivity type disposed between the drift region and the lower surface of the semiconductor substrate, the buffer region including the bulk donors and the increased donors, and having a doping concentration higher than that of the drift region; Equipped with the buffer region has one or more doping concentration peaks in a depth direction of the semiconductor substrate; the one or more doping concentration peaks include a deepest peak located furthest from the bottom surface of the semiconductor substrate; the augmented donor comprises the thermal donor; A method for manufacturing a semiconductor device, comprising annealing the semiconductor substrate so that the concentration of the thermal donors is 10% or less of the concentration of the enhanced donors at the same depth position over the entire first range from the bottom end of the buffer region to the deepest peak.

13. In each step of annealing the semiconductor substrate, the time for which the temperature of the semiconductor substrate passes through a temperature zone of 400° C. or more and 500° C. or less is 20 minutes or less per pass. The method for manufacturing a semiconductor device according to claim 12.

14. In each step of annealing the semiconductor substrate, the time for which the temperature of the semiconductor substrate passes through a temperature zone of 425° C. or more and 475° C. or less is 10 minutes or less per pass. The method for manufacturing a semiconductor device according to claim 12.

15. In each step of annealing the semiconductor substrate, the cumulative time during which the temperature of the semiconductor substrate passes through a temperature range of 400° C. or more and 500° C. or less is 120 minutes or less. The method for manufacturing a semiconductor device according to any one of claims 12 to 14.

16. In each step of annealing the semiconductor substrate, the cumulative time during which the temperature of the semiconductor substrate passes through a temperature range of 425° C. or more and 475° C. or less is 60 minutes or less. The method for manufacturing a semiconductor device according to any one of claims 12 to 14.

17. forming a metal electrode above the top surface of the semiconductor substrate; The process after forming the metal electrode is carried out at a temperature of less than 400°C. The method for manufacturing a semiconductor device according to any one of claims 12 to 14.

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